2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
5 * This code was derived from the Intel e1000e Linux driver.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "pch_gbe_phy.h"
22 #include <linux/module.h>
23 #include <linux/net_tstamp.h>
24 #include <linux/ptp_classify.h>
25 #include <linux/gpio.h>
27 #define DRV_VERSION "1.01"
28 const char pch_driver_version[] = DRV_VERSION;
30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
31 #define PCH_GBE_MAR_ENTRIES 16
32 #define PCH_GBE_SHORT_PKT 64
33 #define DSC_INIT16 0xC000
34 #define PCH_GBE_DMA_ALIGN 0
35 #define PCH_GBE_DMA_PADDING 2
36 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */
37 #define PCH_GBE_PCI_BAR 1
38 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
40 /* Macros for ML7223 */
41 #define PCI_VENDOR_ID_ROHM 0x10db
42 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
44 /* Macros for ML7831 */
45 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
47 #define PCH_GBE_TX_WEIGHT 64
48 #define PCH_GBE_RX_WEIGHT 64
49 #define PCH_GBE_RX_BUFFER_WRITE 16
51 /* Initialize the wake-on-LAN settings */
52 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
54 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
55 PCH_GBE_CHIP_TYPE_INTERNAL | \
56 PCH_GBE_RGMII_MODE_RGMII \
59 /* Ethertype field values */
60 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
61 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
62 #define PCH_GBE_FRAME_SIZE_2048 2048
63 #define PCH_GBE_FRAME_SIZE_4096 4096
64 #define PCH_GBE_FRAME_SIZE_8192 8192
66 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
67 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
68 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
69 #define PCH_GBE_DESC_UNUSED(R) \
70 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
71 (R)->next_to_clean - (R)->next_to_use - 1)
73 /* Pause packet value */
74 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
75 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
76 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
77 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
80 /* This defines the bits that are set in the Interrupt Mask
81 * Set/Read Register. Each bit is documented below:
82 * o RXT0 = Receiver Timer Interrupt (ring 0)
83 * o TXDW = Transmit Descriptor Written Back
84 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
85 * o RXSEQ = Receive Sequence Error
86 * o LSC = Link Status Change
88 #define PCH_GBE_INT_ENABLE_MASK ( \
89 PCH_GBE_INT_RX_DMA_CMPLT | \
90 PCH_GBE_INT_RX_DSC_EMP | \
91 PCH_GBE_INT_RX_FIFO_ERR | \
92 PCH_GBE_INT_WOL_DET | \
93 PCH_GBE_INT_TX_CMPLT \
96 #define PCH_GBE_INT_DISABLE_ALL 0
98 /* Macros for ieee1588 */
99 /* 0x40 Time Synchronization Channel Control Register Bits */
100 #define MASTER_MODE (1<<0)
101 #define SLAVE_MODE (0)
102 #define V2_MODE (1<<31)
103 #define CAP_MODE0 (0)
104 #define CAP_MODE2 (1<<17)
106 /* 0x44 Time Synchronization Channel Event Register Bits */
107 #define TX_SNAPSHOT_LOCKED (1<<0)
108 #define RX_SNAPSHOT_LOCKED (1<<1)
110 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
111 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
113 #define MINNOW_PHY_RESET_GPIO 13
115 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
116 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
118 static void pch_gbe_set_multi(struct net_device *netdev);
120 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
122 u8 *data = skb->data;
127 if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
130 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
132 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
135 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
136 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
138 memcpy(&lo, &hi[1], sizeof(lo));
140 return (uid_hi == *hi &&
146 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
148 struct skb_shared_hwtstamps *shhwtstamps;
149 struct pci_dev *pdev;
154 if (!adapter->hwts_rx_en)
157 /* Get ieee1588's dev information */
158 pdev = adapter->ptp_pdev;
160 val = pch_ch_event_read(pdev);
162 if (!(val & RX_SNAPSHOT_LOCKED))
165 lo = pch_src_uuid_lo_read(pdev);
166 hi = pch_src_uuid_hi_read(pdev);
169 seq = (hi >> 16) & 0xffff;
171 if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
174 ns = pch_rx_snap_read(pdev);
176 shhwtstamps = skb_hwtstamps(skb);
177 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
178 shhwtstamps->hwtstamp = ns_to_ktime(ns);
180 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
184 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
186 struct skb_shared_hwtstamps shhwtstamps;
187 struct pci_dev *pdev;
188 struct skb_shared_info *shtx;
192 shtx = skb_shinfo(skb);
193 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
196 shtx->tx_flags |= SKBTX_IN_PROGRESS;
198 /* Get ieee1588's dev information */
199 pdev = adapter->ptp_pdev;
202 * This really stinks, but we have to poll for the Tx time stamp.
204 for (cnt = 0; cnt < 100; cnt++) {
205 val = pch_ch_event_read(pdev);
206 if (val & TX_SNAPSHOT_LOCKED)
210 if (!(val & TX_SNAPSHOT_LOCKED)) {
211 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
215 ns = pch_tx_snap_read(pdev);
217 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
218 shhwtstamps.hwtstamp = ns_to_ktime(ns);
219 skb_tstamp_tx(skb, &shhwtstamps);
221 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
224 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
226 struct hwtstamp_config cfg;
227 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
228 struct pci_dev *pdev;
231 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
234 if (cfg.flags) /* reserved for future extensions */
237 /* Get ieee1588's dev information */
238 pdev = adapter->ptp_pdev;
240 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
243 switch (cfg.rx_filter) {
244 case HWTSTAMP_FILTER_NONE:
245 adapter->hwts_rx_en = 0;
247 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
248 adapter->hwts_rx_en = 0;
249 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
251 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
252 adapter->hwts_rx_en = 1;
253 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
255 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
256 adapter->hwts_rx_en = 1;
257 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
258 strcpy(station, PTP_L4_MULTICAST_SA);
259 pch_set_station_address(station, pdev);
261 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
262 adapter->hwts_rx_en = 1;
263 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
264 strcpy(station, PTP_L2_MULTICAST_SA);
265 pch_set_station_address(station, pdev);
271 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
273 /* Clear out any old time stamps. */
274 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
276 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
279 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
281 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
285 * pch_gbe_mac_read_mac_addr - Read MAC address
286 * @hw: Pointer to the HW structure
290 static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
292 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
295 adr1a = ioread32(&hw->reg->mac_adr[0].high);
296 adr1b = ioread32(&hw->reg->mac_adr[0].low);
298 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
299 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
300 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
301 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
302 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
303 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
305 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
310 * pch_gbe_wait_clr_bit - Wait to clear a bit
311 * @reg: Pointer of register
314 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
320 while ((ioread32(reg) & bit) && --tmp)
323 pr_err("Error: busy bit is not cleared\n");
327 * pch_gbe_mac_mar_set - Set MAC address register
328 * @hw: Pointer to the HW structure
329 * @addr: Pointer to the MAC address
330 * @index: MAC address array register
332 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
334 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
335 u32 mar_low, mar_high, adrmask;
337 netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
340 * HW expects these in little endian so we reverse the byte order
341 * from network order (big endian) to little endian
343 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
344 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
345 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
346 /* Stop the MAC Address of index. */
347 adrmask = ioread32(&hw->reg->ADDR_MASK);
348 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
350 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
351 /* Set the MAC address to the MAC address 1A/1B register */
352 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
353 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
354 /* Start the MAC address of index */
355 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
357 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
361 * pch_gbe_mac_reset_hw - Reset hardware
362 * @hw: Pointer to the HW structure
364 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
366 /* Read the MAC address. and store to the private data */
367 pch_gbe_mac_read_mac_addr(hw);
368 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
369 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
370 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
371 /* Setup the receive addresses */
372 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
376 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
379 /* Disables Receive MAC */
380 rctl = ioread32(&hw->reg->MAC_RX_EN);
381 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
384 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
387 /* Enables Receive MAC */
388 rctl = ioread32(&hw->reg->MAC_RX_EN);
389 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
393 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
394 * @hw: Pointer to the HW structure
395 * @mar_count: Receive address registers
397 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
401 /* Setup the receive address */
402 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
404 /* Zero out the other receive addresses */
405 for (i = 1; i < mar_count; i++) {
406 iowrite32(0, &hw->reg->mac_adr[i].high);
407 iowrite32(0, &hw->reg->mac_adr[i].low);
409 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
411 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
415 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
416 * @hw: Pointer to the HW structure
419 * Negative value: Failed.
421 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
423 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
424 struct pch_gbe_mac_info *mac = &hw->mac;
427 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
429 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
432 case PCH_GBE_FC_NONE:
433 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
434 mac->tx_fc_enable = false;
436 case PCH_GBE_FC_RX_PAUSE:
437 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
438 mac->tx_fc_enable = false;
440 case PCH_GBE_FC_TX_PAUSE:
441 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
442 mac->tx_fc_enable = true;
444 case PCH_GBE_FC_FULL:
445 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
446 mac->tx_fc_enable = true;
449 netdev_err(adapter->netdev,
450 "Flow control param set incorrectly\n");
453 if (mac->link_duplex == DUPLEX_HALF)
454 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
455 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
456 netdev_dbg(adapter->netdev,
457 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
458 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
463 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
464 * @hw: Pointer to the HW structure
465 * @wu_evt: Wake up event
467 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
469 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
472 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
473 wu_evt, ioread32(&hw->reg->ADDR_MASK));
476 /* Set Wake-On-Lan address mask */
477 addr_mask = ioread32(&hw->reg->ADDR_MASK);
478 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
480 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
481 iowrite32(0, &hw->reg->WOL_ST);
482 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
483 iowrite32(0x02, &hw->reg->TCPIP_ACC);
484 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
486 iowrite32(0, &hw->reg->WOL_CTRL);
487 iowrite32(0, &hw->reg->WOL_ST);
493 * pch_gbe_mac_ctrl_miim - Control MIIM interface
494 * @hw: Pointer to the HW structure
495 * @addr: Address of PHY
496 * @dir: Operetion. (Write or Read)
497 * @reg: Access register of PHY
500 * Returns: Read date.
502 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
505 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
510 spin_lock_irqsave(&hw->miim_lock, flags);
512 for (i = 100; i; --i) {
513 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
518 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
519 spin_unlock_irqrestore(&hw->miim_lock, flags);
520 return 0; /* No way to indicate timeout error */
522 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
523 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
524 dir | data), &hw->reg->MIIM);
525 for (i = 0; i < 100; i++) {
527 data_out = ioread32(&hw->reg->MIIM);
528 if ((data_out & PCH_GBE_MIIM_OPER_READY))
531 spin_unlock_irqrestore(&hw->miim_lock, flags);
533 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
534 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
535 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
536 return (u16) data_out;
540 * pch_gbe_mac_set_pause_packet - Set pause packet
541 * @hw: Pointer to the HW structure
543 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
545 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
546 unsigned long tmp2, tmp3;
548 /* Set Pause packet */
549 tmp2 = hw->mac.addr[1];
550 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
551 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
553 tmp3 = hw->mac.addr[5];
554 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
555 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
556 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
558 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
559 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
560 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
561 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
562 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
564 /* Transmit Pause Packet */
565 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
567 netdev_dbg(adapter->netdev,
568 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
569 ioread32(&hw->reg->PAUSE_PKT1),
570 ioread32(&hw->reg->PAUSE_PKT2),
571 ioread32(&hw->reg->PAUSE_PKT3),
572 ioread32(&hw->reg->PAUSE_PKT4),
573 ioread32(&hw->reg->PAUSE_PKT5));
580 * pch_gbe_alloc_queues - Allocate memory for all rings
581 * @adapter: Board private structure to initialize
584 * Negative value: Failed
586 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
588 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
589 sizeof(*adapter->tx_ring), GFP_KERNEL);
590 if (!adapter->tx_ring)
593 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
594 sizeof(*adapter->rx_ring), GFP_KERNEL);
595 if (!adapter->rx_ring)
601 * pch_gbe_init_stats - Initialize status
602 * @adapter: Board private structure to initialize
604 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
606 memset(&adapter->stats, 0, sizeof(adapter->stats));
611 * pch_gbe_init_phy - Initialize PHY
612 * @adapter: Board private structure to initialize
615 * Negative value: Failed
617 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
619 struct net_device *netdev = adapter->netdev;
623 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
624 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
625 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
626 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
627 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
628 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
629 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
632 adapter->hw.phy.addr = adapter->mii.phy_id;
633 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
634 if (addr == PCH_GBE_PHY_REGS_LEN)
636 /* Selected the phy and isolate the rest */
637 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
638 if (addr != adapter->mii.phy_id) {
639 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
642 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
643 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
644 bmcr & ~BMCR_ISOLATE);
649 adapter->mii.phy_id_mask = 0x1F;
650 adapter->mii.reg_num_mask = 0x1F;
651 adapter->mii.dev = adapter->netdev;
652 adapter->mii.mdio_read = pch_gbe_mdio_read;
653 adapter->mii.mdio_write = pch_gbe_mdio_write;
654 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
659 * pch_gbe_mdio_read - The read function for mii
660 * @netdev: Network interface device structure
662 * @reg: Access location
665 * Negative value: Failed
667 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
669 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
670 struct pch_gbe_hw *hw = &adapter->hw;
672 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
677 * pch_gbe_mdio_write - The write function for mii
678 * @netdev: Network interface device structure
679 * @addr: Phy ID (not used)
680 * @reg: Access location
683 static void pch_gbe_mdio_write(struct net_device *netdev,
684 int addr, int reg, int data)
686 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
687 struct pch_gbe_hw *hw = &adapter->hw;
689 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
693 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
694 * @work: Pointer of board private structure
696 static void pch_gbe_reset_task(struct work_struct *work)
698 struct pch_gbe_adapter *adapter;
699 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
702 pch_gbe_reinit_locked(adapter);
707 * pch_gbe_reinit_locked- Re-initialization
708 * @adapter: Board private structure
710 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
712 pch_gbe_down(adapter);
717 * pch_gbe_reset - Reset GbE
718 * @adapter: Board private structure
720 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
722 struct net_device *netdev = adapter->netdev;
723 struct pch_gbe_hw *hw = &adapter->hw;
726 pch_gbe_mac_reset_hw(hw);
727 /* reprogram multicast address register after reset */
728 pch_gbe_set_multi(netdev);
729 /* Setup the receive address. */
730 pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
732 ret_val = pch_gbe_phy_get_id(hw);
734 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
737 pch_gbe_phy_init_setting(hw);
738 /* Setup Mac interface option RGMII */
739 pch_gbe_phy_set_rgmii(hw);
743 * pch_gbe_free_irq - Free an interrupt
744 * @adapter: Board private structure
746 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
748 struct net_device *netdev = adapter->netdev;
750 free_irq(adapter->irq, netdev);
751 pci_free_irq_vectors(adapter->pdev);
755 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
756 * @adapter: Board private structure
758 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
760 struct pch_gbe_hw *hw = &adapter->hw;
762 atomic_inc(&adapter->irq_sem);
763 iowrite32(0, &hw->reg->INT_EN);
764 ioread32(&hw->reg->INT_ST);
765 synchronize_irq(adapter->irq);
767 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
768 ioread32(&hw->reg->INT_EN));
772 * pch_gbe_irq_enable - Enable default interrupt generation settings
773 * @adapter: Board private structure
775 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
777 struct pch_gbe_hw *hw = &adapter->hw;
779 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
780 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
781 ioread32(&hw->reg->INT_ST);
782 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
783 ioread32(&hw->reg->INT_EN));
789 * pch_gbe_setup_tctl - configure the Transmit control registers
790 * @adapter: Board private structure
792 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
794 struct pch_gbe_hw *hw = &adapter->hw;
797 tx_mode = PCH_GBE_TM_LONG_PKT |
798 PCH_GBE_TM_ST_AND_FD |
799 PCH_GBE_TM_SHORT_PKT |
800 PCH_GBE_TM_TH_TX_STRT_8 |
801 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
803 iowrite32(tx_mode, &hw->reg->TX_MODE);
805 tcpip = ioread32(&hw->reg->TCPIP_ACC);
806 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
807 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
812 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
813 * @adapter: Board private structure
815 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
817 struct pch_gbe_hw *hw = &adapter->hw;
818 u32 tdba, tdlen, dctrl;
820 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n",
821 (unsigned long long)adapter->tx_ring->dma,
822 adapter->tx_ring->size);
824 /* Setup the HW Tx Head and Tail descriptor pointers */
825 tdba = adapter->tx_ring->dma;
826 tdlen = adapter->tx_ring->size - 0x10;
827 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
828 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
829 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
831 /* Enables Transmission DMA */
832 dctrl = ioread32(&hw->reg->DMA_CTRL);
833 dctrl |= PCH_GBE_TX_DMA_EN;
834 iowrite32(dctrl, &hw->reg->DMA_CTRL);
838 * pch_gbe_setup_rctl - Configure the receive control registers
839 * @adapter: Board private structure
841 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
843 struct pch_gbe_hw *hw = &adapter->hw;
846 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
847 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
849 iowrite32(rx_mode, &hw->reg->RX_MODE);
851 tcpip = ioread32(&hw->reg->TCPIP_ACC);
853 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
854 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
855 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
860 * pch_gbe_configure_rx - Configure Receive Unit after Reset
861 * @adapter: Board private structure
863 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
865 struct pch_gbe_hw *hw = &adapter->hw;
866 u32 rdba, rdlen, rxdma;
868 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n",
869 (unsigned long long)adapter->rx_ring->dma,
870 adapter->rx_ring->size);
872 pch_gbe_mac_force_mac_fc(hw);
874 pch_gbe_disable_mac_rx(hw);
876 /* Disables Receive DMA */
877 rxdma = ioread32(&hw->reg->DMA_CTRL);
878 rxdma &= ~PCH_GBE_RX_DMA_EN;
879 iowrite32(rxdma, &hw->reg->DMA_CTRL);
881 netdev_dbg(adapter->netdev,
882 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
883 ioread32(&hw->reg->MAC_RX_EN),
884 ioread32(&hw->reg->DMA_CTRL));
886 /* Setup the HW Rx Head and Tail Descriptor Pointers and
887 * the Base and Length of the Rx Descriptor Ring */
888 rdba = adapter->rx_ring->dma;
889 rdlen = adapter->rx_ring->size - 0x10;
890 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
891 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
892 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
896 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
897 * @adapter: Board private structure
898 * @buffer_info: Buffer information structure
900 static void pch_gbe_unmap_and_free_tx_resource(
901 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
903 if (buffer_info->mapped) {
904 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
905 buffer_info->length, DMA_TO_DEVICE);
906 buffer_info->mapped = false;
908 if (buffer_info->skb) {
909 dev_kfree_skb_any(buffer_info->skb);
910 buffer_info->skb = NULL;
915 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
916 * @adapter: Board private structure
917 * @buffer_info: Buffer information structure
919 static void pch_gbe_unmap_and_free_rx_resource(
920 struct pch_gbe_adapter *adapter,
921 struct pch_gbe_buffer *buffer_info)
923 if (buffer_info->mapped) {
924 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
925 buffer_info->length, DMA_FROM_DEVICE);
926 buffer_info->mapped = false;
928 if (buffer_info->skb) {
929 dev_kfree_skb_any(buffer_info->skb);
930 buffer_info->skb = NULL;
935 * pch_gbe_clean_tx_ring - Free Tx Buffers
936 * @adapter: Board private structure
937 * @tx_ring: Ring to be cleaned
939 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
940 struct pch_gbe_tx_ring *tx_ring)
942 struct pch_gbe_hw *hw = &adapter->hw;
943 struct pch_gbe_buffer *buffer_info;
947 /* Free all the Tx ring sk_buffs */
948 for (i = 0; i < tx_ring->count; i++) {
949 buffer_info = &tx_ring->buffer_info[i];
950 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
952 netdev_dbg(adapter->netdev,
953 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
955 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
956 memset(tx_ring->buffer_info, 0, size);
958 /* Zero out the descriptor ring */
959 memset(tx_ring->desc, 0, tx_ring->size);
960 tx_ring->next_to_use = 0;
961 tx_ring->next_to_clean = 0;
962 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
963 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
967 * pch_gbe_clean_rx_ring - Free Rx Buffers
968 * @adapter: Board private structure
969 * @rx_ring: Ring to free buffers from
972 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
973 struct pch_gbe_rx_ring *rx_ring)
975 struct pch_gbe_hw *hw = &adapter->hw;
976 struct pch_gbe_buffer *buffer_info;
980 /* Free all the Rx ring sk_buffs */
981 for (i = 0; i < rx_ring->count; i++) {
982 buffer_info = &rx_ring->buffer_info[i];
983 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
985 netdev_dbg(adapter->netdev,
986 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
987 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
988 memset(rx_ring->buffer_info, 0, size);
990 /* Zero out the descriptor ring */
991 memset(rx_ring->desc, 0, rx_ring->size);
992 rx_ring->next_to_clean = 0;
993 rx_ring->next_to_use = 0;
994 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
995 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
998 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1001 struct pch_gbe_hw *hw = &adapter->hw;
1002 unsigned long rgmii = 0;
1004 /* Set the RGMII control. */
1007 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1008 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1011 rgmii = (PCH_GBE_RGMII_RATE_25M |
1012 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1015 rgmii = (PCH_GBE_RGMII_RATE_125M |
1016 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1019 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1021 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1024 struct net_device *netdev = adapter->netdev;
1025 struct pch_gbe_hw *hw = &adapter->hw;
1026 unsigned long mode = 0;
1028 /* Set the communication mode */
1031 mode = PCH_GBE_MODE_MII_ETHER;
1032 netdev->tx_queue_len = 10;
1035 mode = PCH_GBE_MODE_MII_ETHER;
1036 netdev->tx_queue_len = 100;
1039 mode = PCH_GBE_MODE_GMII_ETHER;
1042 if (duplex == DUPLEX_FULL)
1043 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1045 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1046 iowrite32(mode, &hw->reg->MODE);
1050 * pch_gbe_watchdog - Watchdog process
1051 * @data: Board private structure
1053 static void pch_gbe_watchdog(struct timer_list *t)
1055 struct pch_gbe_adapter *adapter = from_timer(adapter, t,
1057 struct net_device *netdev = adapter->netdev;
1058 struct pch_gbe_hw *hw = &adapter->hw;
1060 netdev_dbg(netdev, "right now = %ld\n", jiffies);
1062 pch_gbe_update_stats(adapter);
1063 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1064 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1065 netdev->tx_queue_len = adapter->tx_queue_len;
1066 /* mii library handles link maintenance tasks */
1067 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1068 netdev_err(netdev, "ethtool get setting Error\n");
1069 mod_timer(&adapter->watchdog_timer,
1070 round_jiffies(jiffies +
1071 PCH_GBE_WATCHDOG_PERIOD));
1074 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1075 hw->mac.link_duplex = cmd.duplex;
1076 /* Set the RGMII control. */
1077 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1078 hw->mac.link_duplex);
1079 /* Set the communication mode */
1080 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1081 hw->mac.link_duplex);
1083 "Link is Up %d Mbps %s-Duplex\n",
1085 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1086 netif_carrier_on(netdev);
1087 netif_wake_queue(netdev);
1088 } else if ((!mii_link_ok(&adapter->mii)) &&
1089 (netif_carrier_ok(netdev))) {
1090 netdev_dbg(netdev, "NIC Link is Down\n");
1091 hw->mac.link_speed = SPEED_10;
1092 hw->mac.link_duplex = DUPLEX_HALF;
1093 netif_carrier_off(netdev);
1094 netif_stop_queue(netdev);
1096 mod_timer(&adapter->watchdog_timer,
1097 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1101 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1102 * @adapter: Board private structure
1103 * @tx_ring: Tx descriptor ring structure
1104 * @skb: Sockt buffer structure
1106 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1107 struct pch_gbe_tx_ring *tx_ring,
1108 struct sk_buff *skb)
1110 struct pch_gbe_hw *hw = &adapter->hw;
1111 struct pch_gbe_tx_desc *tx_desc;
1112 struct pch_gbe_buffer *buffer_info;
1113 struct sk_buff *tmp_skb;
1114 unsigned int frame_ctrl;
1115 unsigned int ring_num;
1117 /*-- Set frame control --*/
1119 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1120 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1121 if (skb->ip_summed == CHECKSUM_NONE)
1122 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1124 /* Performs checksum processing */
1126 * It is because the hardware accelerator does not support a checksum,
1127 * when the received data size is less than 64 bytes.
1129 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1130 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1131 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1132 if (skb->protocol == htons(ETH_P_IP)) {
1133 struct iphdr *iph = ip_hdr(skb);
1134 unsigned int offset;
1135 offset = skb_transport_offset(skb);
1136 if (iph->protocol == IPPROTO_TCP) {
1138 tcp_hdr(skb)->check = 0;
1139 skb->csum = skb_checksum(skb, offset,
1140 skb->len - offset, 0);
1141 tcp_hdr(skb)->check =
1142 csum_tcpudp_magic(iph->saddr,
1147 } else if (iph->protocol == IPPROTO_UDP) {
1149 udp_hdr(skb)->check = 0;
1151 skb_checksum(skb, offset,
1152 skb->len - offset, 0);
1153 udp_hdr(skb)->check =
1154 csum_tcpudp_magic(iph->saddr,
1163 ring_num = tx_ring->next_to_use;
1164 if (unlikely((ring_num + 1) == tx_ring->count))
1165 tx_ring->next_to_use = 0;
1167 tx_ring->next_to_use = ring_num + 1;
1170 buffer_info = &tx_ring->buffer_info[ring_num];
1171 tmp_skb = buffer_info->skb;
1173 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1174 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1175 tmp_skb->data[ETH_HLEN] = 0x00;
1176 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1177 tmp_skb->len = skb->len;
1178 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1179 (skb->len - ETH_HLEN));
1180 /*-- Set Buffer information --*/
1181 buffer_info->length = tmp_skb->len;
1182 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1183 buffer_info->length,
1185 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1186 netdev_err(adapter->netdev, "TX DMA map failed\n");
1187 buffer_info->dma = 0;
1188 buffer_info->time_stamp = 0;
1189 tx_ring->next_to_use = ring_num;
1192 buffer_info->mapped = true;
1193 buffer_info->time_stamp = jiffies;
1195 /*-- Set Tx descriptor --*/
1196 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1197 tx_desc->buffer_addr = (buffer_info->dma);
1198 tx_desc->length = (tmp_skb->len);
1199 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1200 tx_desc->tx_frame_ctrl = (frame_ctrl);
1201 tx_desc->gbec_status = (DSC_INIT16);
1203 if (unlikely(++ring_num == tx_ring->count))
1206 /* Update software pointer of TX descriptor */
1207 iowrite32(tx_ring->dma +
1208 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1209 &hw->reg->TX_DSC_SW_P);
1211 pch_tx_timestamp(adapter, skb);
1213 dev_kfree_skb_any(skb);
1217 * pch_gbe_update_stats - Update the board statistics counters
1218 * @adapter: Board private structure
1220 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1222 struct net_device *netdev = adapter->netdev;
1223 struct pci_dev *pdev = adapter->pdev;
1224 struct pch_gbe_hw_stats *stats = &adapter->stats;
1225 unsigned long flags;
1228 * Prevent stats update while adapter is being reset, or if the pci
1229 * connection is down.
1231 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1234 spin_lock_irqsave(&adapter->stats_lock, flags);
1236 /* Update device status "adapter->stats" */
1237 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1238 stats->tx_errors = stats->tx_length_errors +
1239 stats->tx_aborted_errors +
1240 stats->tx_carrier_errors + stats->tx_timeout_count;
1242 /* Update network device status "adapter->net_stats" */
1243 netdev->stats.rx_packets = stats->rx_packets;
1244 netdev->stats.rx_bytes = stats->rx_bytes;
1245 netdev->stats.rx_dropped = stats->rx_dropped;
1246 netdev->stats.tx_packets = stats->tx_packets;
1247 netdev->stats.tx_bytes = stats->tx_bytes;
1248 netdev->stats.tx_dropped = stats->tx_dropped;
1249 /* Fill out the OS statistics structure */
1250 netdev->stats.multicast = stats->multicast;
1251 netdev->stats.collisions = stats->collisions;
1253 netdev->stats.rx_errors = stats->rx_errors;
1254 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1255 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1257 netdev->stats.tx_errors = stats->tx_errors;
1258 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1259 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1261 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1264 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1268 /* Disable Receive DMA */
1269 rxdma = ioread32(&hw->reg->DMA_CTRL);
1270 rxdma &= ~PCH_GBE_RX_DMA_EN;
1271 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1274 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1278 /* Enables Receive DMA */
1279 rxdma = ioread32(&hw->reg->DMA_CTRL);
1280 rxdma |= PCH_GBE_RX_DMA_EN;
1281 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1285 * pch_gbe_intr - Interrupt Handler
1286 * @irq: Interrupt number
1287 * @data: Pointer to a network interface device structure
1289 * - IRQ_HANDLED: Our interrupt
1290 * - IRQ_NONE: Not our interrupt
1292 static irqreturn_t pch_gbe_intr(int irq, void *data)
1294 struct net_device *netdev = data;
1295 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1296 struct pch_gbe_hw *hw = &adapter->hw;
1300 /* Check request status */
1301 int_st = ioread32(&hw->reg->INT_ST);
1302 int_st = int_st & ioread32(&hw->reg->INT_EN);
1303 /* When request status is no interruption factor */
1304 if (unlikely(!int_st))
1305 return IRQ_NONE; /* Not our interrupt. End processing. */
1306 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1307 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1308 adapter->stats.intr_rx_frame_err_count++;
1309 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1310 if (!adapter->rx_stop_flag) {
1311 adapter->stats.intr_rx_fifo_err_count++;
1312 netdev_dbg(netdev, "Rx fifo over run\n");
1313 adapter->rx_stop_flag = true;
1314 int_en = ioread32(&hw->reg->INT_EN);
1315 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1317 pch_gbe_disable_dma_rx(&adapter->hw);
1318 int_st |= ioread32(&hw->reg->INT_ST);
1319 int_st = int_st & ioread32(&hw->reg->INT_EN);
1321 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1322 adapter->stats.intr_rx_dma_err_count++;
1323 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1324 adapter->stats.intr_tx_fifo_err_count++;
1325 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1326 adapter->stats.intr_tx_dma_err_count++;
1327 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1328 adapter->stats.intr_tcpip_err_count++;
1329 /* When Rx descriptor is empty */
1330 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1331 adapter->stats.intr_rx_dsc_empty_count++;
1332 netdev_dbg(netdev, "Rx descriptor is empty\n");
1333 int_en = ioread32(&hw->reg->INT_EN);
1334 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1335 if (hw->mac.tx_fc_enable) {
1336 /* Set Pause packet */
1337 pch_gbe_mac_set_pause_packet(hw);
1341 /* When request status is Receive interruption */
1342 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1343 (adapter->rx_stop_flag)) {
1344 if (likely(napi_schedule_prep(&adapter->napi))) {
1345 /* Enable only Rx Descriptor empty */
1346 atomic_inc(&adapter->irq_sem);
1347 int_en = ioread32(&hw->reg->INT_EN);
1349 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1350 iowrite32(int_en, &hw->reg->INT_EN);
1351 /* Start polling for NAPI */
1352 __napi_schedule(&adapter->napi);
1355 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n",
1356 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1361 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1362 * @adapter: Board private structure
1363 * @rx_ring: Rx descriptor ring
1364 * @cleaned_count: Cleaned count
1367 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1368 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1370 struct net_device *netdev = adapter->netdev;
1371 struct pci_dev *pdev = adapter->pdev;
1372 struct pch_gbe_hw *hw = &adapter->hw;
1373 struct pch_gbe_rx_desc *rx_desc;
1374 struct pch_gbe_buffer *buffer_info;
1375 struct sk_buff *skb;
1379 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1380 i = rx_ring->next_to_use;
1382 while ((cleaned_count--)) {
1383 buffer_info = &rx_ring->buffer_info[i];
1384 skb = netdev_alloc_skb(netdev, bufsz);
1385 if (unlikely(!skb)) {
1386 /* Better luck next round */
1387 adapter->stats.rx_alloc_buff_failed++;
1391 skb_reserve(skb, NET_IP_ALIGN);
1392 buffer_info->skb = skb;
1394 buffer_info->dma = dma_map_single(&pdev->dev,
1395 buffer_info->rx_buffer,
1396 buffer_info->length,
1398 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1400 buffer_info->skb = NULL;
1401 buffer_info->dma = 0;
1402 adapter->stats.rx_alloc_buff_failed++;
1403 break; /* while !buffer_info->skb */
1405 buffer_info->mapped = true;
1406 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1407 rx_desc->buffer_addr = (buffer_info->dma);
1408 rx_desc->gbec_status = DSC_INIT16;
1411 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1412 i, (unsigned long long)buffer_info->dma,
1413 buffer_info->length);
1415 if (unlikely(++i == rx_ring->count))
1418 if (likely(rx_ring->next_to_use != i)) {
1419 rx_ring->next_to_use = i;
1420 if (unlikely(i-- == 0))
1421 i = (rx_ring->count - 1);
1422 iowrite32(rx_ring->dma +
1423 (int)sizeof(struct pch_gbe_rx_desc) * i,
1424 &hw->reg->RX_DSC_SW_P);
1430 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1431 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1433 struct pci_dev *pdev = adapter->pdev;
1434 struct pch_gbe_buffer *buffer_info;
1439 bufsz = adapter->rx_buffer_len;
1441 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1442 rx_ring->rx_buff_pool =
1443 dma_alloc_coherent(&pdev->dev, size,
1444 &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1445 if (!rx_ring->rx_buff_pool)
1448 rx_ring->rx_buff_pool_size = size;
1449 for (i = 0; i < rx_ring->count; i++) {
1450 buffer_info = &rx_ring->buffer_info[i];
1451 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1452 buffer_info->length = bufsz;
1458 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1459 * @adapter: Board private structure
1460 * @tx_ring: Tx descriptor ring
1462 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1463 struct pch_gbe_tx_ring *tx_ring)
1465 struct pch_gbe_buffer *buffer_info;
1466 struct sk_buff *skb;
1469 struct pch_gbe_tx_desc *tx_desc;
1472 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1474 for (i = 0; i < tx_ring->count; i++) {
1475 buffer_info = &tx_ring->buffer_info[i];
1476 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1477 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1478 buffer_info->skb = skb;
1479 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1480 tx_desc->gbec_status = (DSC_INIT16);
1486 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1487 * @adapter: Board private structure
1488 * @tx_ring: Tx descriptor ring
1490 * true: Cleaned the descriptor
1491 * false: Not cleaned the descriptor
1494 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1495 struct pch_gbe_tx_ring *tx_ring)
1497 struct pch_gbe_tx_desc *tx_desc;
1498 struct pch_gbe_buffer *buffer_info;
1499 struct sk_buff *skb;
1501 unsigned int cleaned_count = 0;
1502 bool cleaned = false;
1505 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1506 tx_ring->next_to_clean);
1508 i = tx_ring->next_to_clean;
1509 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1510 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n",
1511 tx_desc->gbec_status, tx_desc->dma_status);
1513 unused = PCH_GBE_DESC_UNUSED(tx_ring);
1514 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1515 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1516 { /* current marked clean, tx queue filling up, do extra clean */
1518 if (unused < 8) { /* tx queue nearly full */
1519 netdev_dbg(adapter->netdev,
1520 "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1521 tx_ring->next_to_clean, tx_ring->next_to_use,
1525 /* current marked clean, scan for more that need cleaning. */
1527 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1529 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1530 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1531 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
1533 if (j < PCH_GBE_TX_WEIGHT) {
1534 netdev_dbg(adapter->netdev,
1535 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1536 unused, j, i, k, tx_ring->next_to_use,
1537 tx_desc->gbec_status);
1538 i = k; /*found one to clean, usu gbec_status==2000.*/
1542 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1543 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1544 tx_desc->gbec_status);
1545 buffer_info = &tx_ring->buffer_info[i];
1546 skb = buffer_info->skb;
1549 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1550 adapter->stats.tx_aborted_errors++;
1551 netdev_err(adapter->netdev, "Transfer Abort Error\n");
1552 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1554 adapter->stats.tx_carrier_errors++;
1555 netdev_err(adapter->netdev,
1556 "Transfer Carrier Sense Error\n");
1557 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1559 adapter->stats.tx_aborted_errors++;
1560 netdev_err(adapter->netdev,
1561 "Transfer Collision Abort Error\n");
1562 } else if ((tx_desc->gbec_status &
1563 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1564 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1565 adapter->stats.collisions++;
1566 adapter->stats.tx_packets++;
1567 adapter->stats.tx_bytes += skb->len;
1568 netdev_dbg(adapter->netdev, "Transfer Collision\n");
1569 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1571 adapter->stats.tx_packets++;
1572 adapter->stats.tx_bytes += skb->len;
1574 if (buffer_info->mapped) {
1575 netdev_dbg(adapter->netdev,
1576 "unmap buffer_info->dma : %d\n", i);
1577 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1578 buffer_info->length, DMA_TO_DEVICE);
1579 buffer_info->mapped = false;
1581 if (buffer_info->skb) {
1582 netdev_dbg(adapter->netdev,
1583 "trim buffer_info->skb : %d\n", i);
1584 skb_trim(buffer_info->skb, 0);
1586 tx_desc->gbec_status = DSC_INIT16;
1587 if (unlikely(++i == tx_ring->count))
1589 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1591 /* weight of a sort for tx, to avoid endless transmit cleanup */
1592 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1597 netdev_dbg(adapter->netdev,
1598 "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1600 if (cleaned_count > 0) { /*skip this if nothing cleaned*/
1601 /* Recover from running out of Tx resources in xmit_frame */
1602 netif_tx_lock(adapter->netdev);
1603 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1605 netif_wake_queue(adapter->netdev);
1606 adapter->stats.tx_restart_count++;
1607 netdev_dbg(adapter->netdev, "Tx wake queue\n");
1610 tx_ring->next_to_clean = i;
1612 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1613 tx_ring->next_to_clean);
1614 netif_tx_unlock(adapter->netdev);
1620 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1621 * @adapter: Board private structure
1622 * @rx_ring: Rx descriptor ring
1623 * @work_done: Completed count
1624 * @work_to_do: Request count
1626 * true: Cleaned the descriptor
1627 * false: Not cleaned the descriptor
1630 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1631 struct pch_gbe_rx_ring *rx_ring,
1632 int *work_done, int work_to_do)
1634 struct net_device *netdev = adapter->netdev;
1635 struct pci_dev *pdev = adapter->pdev;
1636 struct pch_gbe_buffer *buffer_info;
1637 struct pch_gbe_rx_desc *rx_desc;
1640 unsigned int cleaned_count = 0;
1641 bool cleaned = false;
1642 struct sk_buff *skb;
1647 i = rx_ring->next_to_clean;
1649 while (*work_done < work_to_do) {
1650 /* Check Rx descriptor status */
1651 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1652 if (rx_desc->gbec_status == DSC_INIT16)
1657 dma_status = rx_desc->dma_status;
1658 gbec_status = rx_desc->gbec_status;
1659 tcp_ip_status = rx_desc->tcp_ip_status;
1660 rx_desc->gbec_status = DSC_INIT16;
1661 buffer_info = &rx_ring->buffer_info[i];
1662 skb = buffer_info->skb;
1663 buffer_info->skb = NULL;
1666 dma_unmap_single(&pdev->dev, buffer_info->dma,
1667 buffer_info->length, DMA_FROM_DEVICE);
1668 buffer_info->mapped = false;
1671 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n",
1672 i, dma_status, gbec_status, tcp_ip_status,
1675 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1676 adapter->stats.rx_frame_errors++;
1677 netdev_err(netdev, "Receive Not Octal Error\n");
1678 } else if (unlikely(gbec_status &
1679 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1680 adapter->stats.rx_frame_errors++;
1681 netdev_err(netdev, "Receive Nibble Error\n");
1682 } else if (unlikely(gbec_status &
1683 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1684 adapter->stats.rx_crc_errors++;
1685 netdev_err(netdev, "Receive CRC Error\n");
1687 /* get receive length */
1688 /* length convert[-3], length includes FCS length */
1689 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1690 if (rx_desc->rx_words_eob & 0x02)
1691 length = length - 4;
1693 * buffer_info->rx_buffer: [Header:14][payload]
1694 * skb->data: [Reserve:2][Header:14][payload]
1696 memcpy(skb->data, buffer_info->rx_buffer, length);
1698 /* update status of driver */
1699 adapter->stats.rx_bytes += length;
1700 adapter->stats.rx_packets++;
1701 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1702 adapter->stats.multicast++;
1703 /* Write meta date of skb */
1704 skb_put(skb, length);
1706 pch_rx_timestamp(adapter, skb);
1708 skb->protocol = eth_type_trans(skb, netdev);
1709 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1710 skb->ip_summed = CHECKSUM_UNNECESSARY;
1712 skb->ip_summed = CHECKSUM_NONE;
1714 napi_gro_receive(&adapter->napi, skb);
1717 "Receive skb->ip_summed: %d length: %d\n",
1718 skb->ip_summed, length);
1720 /* return some buffers to hardware, one at a time is too slow */
1721 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1722 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1726 if (++i == rx_ring->count)
1729 rx_ring->next_to_clean = i;
1731 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1736 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1737 * @adapter: Board private structure
1738 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1741 * Negative value: Failed
1743 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1744 struct pch_gbe_tx_ring *tx_ring)
1746 struct pci_dev *pdev = adapter->pdev;
1747 struct pch_gbe_tx_desc *tx_desc;
1751 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1752 tx_ring->buffer_info = vzalloc(size);
1753 if (!tx_ring->buffer_info)
1756 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1758 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1759 &tx_ring->dma, GFP_KERNEL);
1760 if (!tx_ring->desc) {
1761 vfree(tx_ring->buffer_info);
1765 tx_ring->next_to_use = 0;
1766 tx_ring->next_to_clean = 0;
1768 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1769 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1770 tx_desc->gbec_status = DSC_INIT16;
1772 netdev_dbg(adapter->netdev,
1773 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1774 tx_ring->desc, (unsigned long long)tx_ring->dma,
1775 tx_ring->next_to_clean, tx_ring->next_to_use);
1780 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1781 * @adapter: Board private structure
1782 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1785 * Negative value: Failed
1787 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1788 struct pch_gbe_rx_ring *rx_ring)
1790 struct pci_dev *pdev = adapter->pdev;
1791 struct pch_gbe_rx_desc *rx_desc;
1795 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1796 rx_ring->buffer_info = vzalloc(size);
1797 if (!rx_ring->buffer_info)
1800 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1801 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1802 &rx_ring->dma, GFP_KERNEL);
1803 if (!rx_ring->desc) {
1804 vfree(rx_ring->buffer_info);
1807 rx_ring->next_to_clean = 0;
1808 rx_ring->next_to_use = 0;
1809 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1810 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1811 rx_desc->gbec_status = DSC_INIT16;
1813 netdev_dbg(adapter->netdev,
1814 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1815 rx_ring->desc, (unsigned long long)rx_ring->dma,
1816 rx_ring->next_to_clean, rx_ring->next_to_use);
1821 * pch_gbe_free_tx_resources - Free Tx Resources
1822 * @adapter: Board private structure
1823 * @tx_ring: Tx descriptor ring for a specific queue
1825 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1826 struct pch_gbe_tx_ring *tx_ring)
1828 struct pci_dev *pdev = adapter->pdev;
1830 pch_gbe_clean_tx_ring(adapter, tx_ring);
1831 vfree(tx_ring->buffer_info);
1832 tx_ring->buffer_info = NULL;
1833 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1834 tx_ring->desc = NULL;
1838 * pch_gbe_free_rx_resources - Free Rx Resources
1839 * @adapter: Board private structure
1840 * @rx_ring: Ring to clean the resources from
1842 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1843 struct pch_gbe_rx_ring *rx_ring)
1845 struct pci_dev *pdev = adapter->pdev;
1847 pch_gbe_clean_rx_ring(adapter, rx_ring);
1848 vfree(rx_ring->buffer_info);
1849 rx_ring->buffer_info = NULL;
1850 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1851 rx_ring->desc = NULL;
1855 * pch_gbe_request_irq - Allocate an interrupt line
1856 * @adapter: Board private structure
1859 * Negative value: Failed
1861 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1863 struct net_device *netdev = adapter->netdev;
1866 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1870 adapter->irq = pci_irq_vector(adapter->pdev, 0);
1872 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED,
1873 netdev->name, netdev);
1875 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1877 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n",
1878 pci_dev_msi_enabled(adapter->pdev), err);
1883 * pch_gbe_up - Up GbE network device
1884 * @adapter: Board private structure
1887 * Negative value: Failed
1889 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1891 struct net_device *netdev = adapter->netdev;
1892 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1893 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1896 /* Ensure we have a valid MAC */
1897 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1898 netdev_err(netdev, "Error: Invalid MAC address\n");
1902 /* hardware has been reset, we need to reload some things */
1903 pch_gbe_set_multi(netdev);
1905 pch_gbe_setup_tctl(adapter);
1906 pch_gbe_configure_tx(adapter);
1907 pch_gbe_setup_rctl(adapter);
1908 pch_gbe_configure_rx(adapter);
1910 err = pch_gbe_request_irq(adapter);
1913 "Error: can't bring device up - irq request failed\n");
1916 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1919 "Error: can't bring device up - alloc rx buffers pool failed\n");
1922 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1923 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1924 adapter->tx_queue_len = netdev->tx_queue_len;
1925 pch_gbe_enable_dma_rx(&adapter->hw);
1926 pch_gbe_enable_mac_rx(&adapter->hw);
1928 mod_timer(&adapter->watchdog_timer, jiffies);
1930 napi_enable(&adapter->napi);
1931 pch_gbe_irq_enable(adapter);
1932 netif_start_queue(adapter->netdev);
1937 pch_gbe_free_irq(adapter);
1943 * pch_gbe_down - Down GbE network device
1944 * @adapter: Board private structure
1946 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1948 struct net_device *netdev = adapter->netdev;
1949 struct pci_dev *pdev = adapter->pdev;
1950 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1952 /* signal that we're down so the interrupt handler does not
1953 * reschedule our watchdog timer */
1954 napi_disable(&adapter->napi);
1955 atomic_set(&adapter->irq_sem, 0);
1957 pch_gbe_irq_disable(adapter);
1958 pch_gbe_free_irq(adapter);
1960 del_timer_sync(&adapter->watchdog_timer);
1962 netdev->tx_queue_len = adapter->tx_queue_len;
1963 netif_carrier_off(netdev);
1964 netif_stop_queue(netdev);
1966 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1967 pch_gbe_reset(adapter);
1968 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1969 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1971 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
1972 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
1973 rx_ring->rx_buff_pool_logic = 0;
1974 rx_ring->rx_buff_pool_size = 0;
1975 rx_ring->rx_buff_pool = NULL;
1979 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1980 * @adapter: Board private structure to initialize
1983 * Negative value: Failed
1985 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1987 struct pch_gbe_hw *hw = &adapter->hw;
1988 struct net_device *netdev = adapter->netdev;
1990 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1991 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1992 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1993 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
1995 if (pch_gbe_alloc_queues(adapter)) {
1996 netdev_err(netdev, "Unable to allocate memory for queues\n");
1999 spin_lock_init(&adapter->hw.miim_lock);
2000 spin_lock_init(&adapter->stats_lock);
2001 spin_lock_init(&adapter->ethtool_lock);
2002 atomic_set(&adapter->irq_sem, 0);
2003 pch_gbe_irq_disable(adapter);
2005 pch_gbe_init_stats(adapter);
2008 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
2009 (u32) adapter->rx_buffer_len,
2010 hw->mac.min_frame_size, hw->mac.max_frame_size);
2015 * pch_gbe_open - Called when a network interface is made active
2016 * @netdev: Network interface device structure
2019 * Negative value: Failed
2021 static int pch_gbe_open(struct net_device *netdev)
2023 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2024 struct pch_gbe_hw *hw = &adapter->hw;
2027 /* allocate transmit descriptors */
2028 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2031 /* allocate receive descriptors */
2032 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2035 pch_gbe_phy_power_up(hw);
2036 err = pch_gbe_up(adapter);
2039 netdev_dbg(netdev, "Success End\n");
2043 if (!adapter->wake_up_evt)
2044 pch_gbe_phy_power_down(hw);
2045 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2047 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2049 pch_gbe_reset(adapter);
2050 netdev_err(netdev, "Error End\n");
2055 * pch_gbe_stop - Disables a network interface
2056 * @netdev: Network interface device structure
2060 static int pch_gbe_stop(struct net_device *netdev)
2062 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2063 struct pch_gbe_hw *hw = &adapter->hw;
2065 pch_gbe_down(adapter);
2066 if (!adapter->wake_up_evt)
2067 pch_gbe_phy_power_down(hw);
2068 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2069 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2074 * pch_gbe_xmit_frame - Packet transmitting start
2075 * @skb: Socket buffer structure
2076 * @netdev: Network interface device structure
2078 * - NETDEV_TX_OK: Normal end
2079 * - NETDEV_TX_BUSY: Error end
2081 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2083 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2084 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2086 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2087 netif_stop_queue(netdev);
2089 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2090 tx_ring->next_to_use, tx_ring->next_to_clean);
2091 return NETDEV_TX_BUSY;
2094 /* CRC,ITAG no support */
2095 pch_gbe_tx_queue(adapter, tx_ring, skb);
2096 return NETDEV_TX_OK;
2100 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2101 * @netdev: Network interface device structure
2103 static void pch_gbe_set_multi(struct net_device *netdev)
2105 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2106 struct pch_gbe_hw *hw = &adapter->hw;
2107 struct netdev_hw_addr *ha;
2111 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2113 /* By default enable address & multicast filtering */
2114 rctl = ioread32(&hw->reg->RX_MODE);
2115 rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN;
2117 /* Promiscuous mode disables all hardware address filtering */
2118 if (netdev->flags & IFF_PROMISC)
2119 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2121 /* If we want to monitor more multicast addresses than the hardware can
2122 * support then disable hardware multicast filtering.
2124 mc_count = netdev_mc_count(netdev);
2125 if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES)
2126 rctl &= ~PCH_GBE_MLT_FIL_EN;
2128 iowrite32(rctl, &hw->reg->RX_MODE);
2130 /* If we're not using multicast filtering then there's no point
2131 * configuring the unused MAC address registers.
2133 if (!(rctl & PCH_GBE_MLT_FIL_EN))
2136 /* Load the first set of multicast addresses into MAC address registers
2137 * for use by hardware filtering.
2140 netdev_for_each_mc_addr(ha, netdev)
2141 pch_gbe_mac_mar_set(hw, ha->addr, i++);
2143 /* If there are spare MAC registers, mask & clear them */
2144 for (; i < PCH_GBE_MAR_ENTRIES; i++) {
2145 /* Clear MAC address mask */
2146 adrmask = ioread32(&hw->reg->ADDR_MASK);
2147 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK);
2149 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
2150 /* Clear MAC address */
2151 iowrite32(0, &hw->reg->mac_adr[i].high);
2152 iowrite32(0, &hw->reg->mac_adr[i].low);
2156 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2157 ioread32(&hw->reg->RX_MODE), mc_count);
2161 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2162 * @netdev: Network interface device structure
2163 * @addr: Pointer to an address structure
2166 * -EADDRNOTAVAIL: Failed
2168 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2170 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2171 struct sockaddr *skaddr = addr;
2174 if (!is_valid_ether_addr(skaddr->sa_data)) {
2175 ret_val = -EADDRNOTAVAIL;
2177 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2178 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2179 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2182 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2183 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2184 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2185 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2186 ioread32(&adapter->hw.reg->mac_adr[0].high),
2187 ioread32(&adapter->hw.reg->mac_adr[0].low));
2192 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2193 * @netdev: Network interface device structure
2194 * @new_mtu: New value for maximum frame size
2199 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2201 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2202 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2203 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2206 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2207 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2208 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2209 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2210 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2211 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2213 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2215 if (netif_running(netdev)) {
2216 pch_gbe_down(adapter);
2217 err = pch_gbe_up(adapter);
2219 adapter->rx_buffer_len = old_rx_buffer_len;
2220 pch_gbe_up(adapter);
2223 netdev->mtu = new_mtu;
2224 adapter->hw.mac.max_frame_size = max_frame;
2227 pch_gbe_reset(adapter);
2228 netdev->mtu = new_mtu;
2229 adapter->hw.mac.max_frame_size = max_frame;
2233 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2234 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2235 adapter->hw.mac.max_frame_size);
2240 * pch_gbe_set_features - Reset device after features changed
2241 * @netdev: Network interface device structure
2242 * @features: New features
2244 * 0: HW state updated successfully
2246 static int pch_gbe_set_features(struct net_device *netdev,
2247 netdev_features_t features)
2249 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2250 netdev_features_t changed = features ^ netdev->features;
2252 if (!(changed & NETIF_F_RXCSUM))
2255 if (netif_running(netdev))
2256 pch_gbe_reinit_locked(adapter);
2258 pch_gbe_reset(adapter);
2264 * pch_gbe_ioctl - Controls register through a MII interface
2265 * @netdev: Network interface device structure
2266 * @ifr: Pointer to ifr structure
2267 * @cmd: Control command
2270 * Negative value: Failed
2272 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2274 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2276 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2278 if (cmd == SIOCSHWTSTAMP)
2279 return hwtstamp_ioctl(netdev, ifr, cmd);
2281 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2285 * pch_gbe_tx_timeout - Respond to a Tx Hang
2286 * @netdev: Network interface device structure
2288 static void pch_gbe_tx_timeout(struct net_device *netdev)
2290 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2292 /* Do the reset outside of interrupt context */
2293 adapter->stats.tx_timeout_count++;
2294 schedule_work(&adapter->reset_task);
2298 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2299 * @napi: Pointer of polling device struct
2300 * @budget: The maximum number of a packet
2302 * false: Exit the polling mode
2303 * true: Continue the polling mode
2305 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2307 struct pch_gbe_adapter *adapter =
2308 container_of(napi, struct pch_gbe_adapter, napi);
2310 bool poll_end_flag = false;
2311 bool cleaned = false;
2313 netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2315 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2316 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2320 /* If no Tx and not enough Rx work done,
2321 * exit the polling mode
2323 if (work_done < budget)
2324 poll_end_flag = true;
2326 if (poll_end_flag) {
2327 napi_complete_done(napi, work_done);
2328 pch_gbe_irq_enable(adapter);
2331 if (adapter->rx_stop_flag) {
2332 adapter->rx_stop_flag = false;
2333 pch_gbe_enable_dma_rx(&adapter->hw);
2336 netdev_dbg(adapter->netdev,
2337 "poll_end_flag : %d work_done : %d budget : %d\n",
2338 poll_end_flag, work_done, budget);
2343 #ifdef CONFIG_NET_POLL_CONTROLLER
2345 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2346 * @netdev: Network interface device structure
2348 static void pch_gbe_netpoll(struct net_device *netdev)
2350 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2352 disable_irq(adapter->irq);
2353 pch_gbe_intr(adapter->irq, netdev);
2354 enable_irq(adapter->irq);
2358 static const struct net_device_ops pch_gbe_netdev_ops = {
2359 .ndo_open = pch_gbe_open,
2360 .ndo_stop = pch_gbe_stop,
2361 .ndo_start_xmit = pch_gbe_xmit_frame,
2362 .ndo_set_mac_address = pch_gbe_set_mac,
2363 .ndo_tx_timeout = pch_gbe_tx_timeout,
2364 .ndo_change_mtu = pch_gbe_change_mtu,
2365 .ndo_set_features = pch_gbe_set_features,
2366 .ndo_do_ioctl = pch_gbe_ioctl,
2367 .ndo_set_rx_mode = pch_gbe_set_multi,
2368 #ifdef CONFIG_NET_POLL_CONTROLLER
2369 .ndo_poll_controller = pch_gbe_netpoll,
2373 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2374 pci_channel_state_t state)
2376 struct net_device *netdev = pci_get_drvdata(pdev);
2377 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2379 netif_device_detach(netdev);
2380 if (netif_running(netdev))
2381 pch_gbe_down(adapter);
2382 pci_disable_device(pdev);
2383 /* Request a slot slot reset. */
2384 return PCI_ERS_RESULT_NEED_RESET;
2387 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2389 struct net_device *netdev = pci_get_drvdata(pdev);
2390 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2391 struct pch_gbe_hw *hw = &adapter->hw;
2393 if (pci_enable_device(pdev)) {
2394 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2395 return PCI_ERS_RESULT_DISCONNECT;
2397 pci_set_master(pdev);
2398 pci_enable_wake(pdev, PCI_D0, 0);
2399 pch_gbe_phy_power_up(hw);
2400 pch_gbe_reset(adapter);
2401 /* Clear wake up status */
2402 pch_gbe_mac_set_wol_event(hw, 0);
2404 return PCI_ERS_RESULT_RECOVERED;
2407 static void pch_gbe_io_resume(struct pci_dev *pdev)
2409 struct net_device *netdev = pci_get_drvdata(pdev);
2410 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2412 if (netif_running(netdev)) {
2413 if (pch_gbe_up(adapter)) {
2415 "can't bring device back up after reset\n");
2419 netif_device_attach(netdev);
2422 static int __pch_gbe_suspend(struct pci_dev *pdev)
2424 struct net_device *netdev = pci_get_drvdata(pdev);
2425 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2426 struct pch_gbe_hw *hw = &adapter->hw;
2427 u32 wufc = adapter->wake_up_evt;
2430 netif_device_detach(netdev);
2431 if (netif_running(netdev))
2432 pch_gbe_down(adapter);
2434 pch_gbe_set_multi(netdev);
2435 pch_gbe_setup_rctl(adapter);
2436 pch_gbe_configure_rx(adapter);
2437 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2438 hw->mac.link_duplex);
2439 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2440 hw->mac.link_duplex);
2441 pch_gbe_mac_set_wol_event(hw, wufc);
2442 pci_disable_device(pdev);
2444 pch_gbe_phy_power_down(hw);
2445 pch_gbe_mac_set_wol_event(hw, wufc);
2446 pci_disable_device(pdev);
2452 static int pch_gbe_suspend(struct device *device)
2454 struct pci_dev *pdev = to_pci_dev(device);
2456 return __pch_gbe_suspend(pdev);
2459 static int pch_gbe_resume(struct device *device)
2461 struct pci_dev *pdev = to_pci_dev(device);
2462 struct net_device *netdev = pci_get_drvdata(pdev);
2463 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2464 struct pch_gbe_hw *hw = &adapter->hw;
2467 err = pci_enable_device(pdev);
2469 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2472 pci_set_master(pdev);
2473 pch_gbe_phy_power_up(hw);
2474 pch_gbe_reset(adapter);
2475 /* Clear wake on lan control and status */
2476 pch_gbe_mac_set_wol_event(hw, 0);
2478 if (netif_running(netdev))
2479 pch_gbe_up(adapter);
2480 netif_device_attach(netdev);
2484 #endif /* CONFIG_PM */
2486 static void pch_gbe_shutdown(struct pci_dev *pdev)
2488 __pch_gbe_suspend(pdev);
2489 if (system_state == SYSTEM_POWER_OFF) {
2490 pci_wake_from_d3(pdev, true);
2491 pci_set_power_state(pdev, PCI_D3hot);
2495 static void pch_gbe_remove(struct pci_dev *pdev)
2497 struct net_device *netdev = pci_get_drvdata(pdev);
2498 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2500 cancel_work_sync(&adapter->reset_task);
2501 unregister_netdev(netdev);
2503 pch_gbe_phy_hw_reset(&adapter->hw);
2505 free_netdev(netdev);
2508 static int pch_gbe_probe(struct pci_dev *pdev,
2509 const struct pci_device_id *pci_id)
2511 struct net_device *netdev;
2512 struct pch_gbe_adapter *adapter;
2515 ret = pcim_enable_device(pdev);
2519 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2520 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2521 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2523 ret = pci_set_consistent_dma_mask(pdev,
2526 dev_err(&pdev->dev, "ERR: No usable DMA "
2527 "configuration, aborting\n");
2533 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2536 "ERR: Can't reserve PCI I/O and memory resources\n");
2539 pci_set_master(pdev);
2541 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2544 SET_NETDEV_DEV(netdev, &pdev->dev);
2546 pci_set_drvdata(pdev, netdev);
2547 adapter = netdev_priv(netdev);
2548 adapter->netdev = netdev;
2549 adapter->pdev = pdev;
2550 adapter->hw.back = adapter;
2551 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2552 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2553 if (adapter->pdata && adapter->pdata->platform_init)
2554 adapter->pdata->platform_init(pdev);
2557 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
2558 adapter->pdev->bus->number,
2561 netdev->netdev_ops = &pch_gbe_netdev_ops;
2562 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2563 netif_napi_add(netdev, &adapter->napi,
2564 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2565 netdev->hw_features = NETIF_F_RXCSUM |
2566 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2567 netdev->features = netdev->hw_features;
2568 pch_gbe_set_ethtool_ops(netdev);
2570 /* MTU range: 46 - 10300 */
2571 netdev->min_mtu = ETH_ZLEN - ETH_HLEN;
2572 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE -
2573 (ETH_HLEN + ETH_FCS_LEN);
2575 pch_gbe_mac_load_mac_addr(&adapter->hw);
2576 pch_gbe_mac_reset_hw(&adapter->hw);
2578 /* setup the private structure */
2579 ret = pch_gbe_sw_init(adapter);
2581 goto err_free_netdev;
2583 /* Initialize PHY */
2584 ret = pch_gbe_init_phy(adapter);
2586 dev_err(&pdev->dev, "PHY initialize error\n");
2587 goto err_free_adapter;
2590 /* Read the MAC address. and store to the private data */
2591 ret = pch_gbe_mac_read_mac_addr(&adapter->hw);
2593 dev_err(&pdev->dev, "MAC address Read Error\n");
2594 goto err_free_adapter;
2597 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2598 if (!is_valid_ether_addr(netdev->dev_addr)) {
2600 * If the MAC is invalid (or just missing), display a warning
2601 * but do not abort setting up the device. pch_gbe_up will
2602 * prevent the interface from being brought up until a valid MAC
2605 dev_err(&pdev->dev, "Invalid MAC address, "
2606 "interface disabled.\n");
2608 timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0);
2610 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2612 pch_gbe_check_options(adapter);
2614 /* initialize the wol settings based on the eeprom settings */
2615 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2616 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2618 /* reset the hardware with the new settings */
2619 pch_gbe_reset(adapter);
2621 ret = register_netdev(netdev);
2623 goto err_free_adapter;
2624 /* tell the stack to leave us alone until pch_gbe_open() is called */
2625 netif_carrier_off(netdev);
2626 netif_stop_queue(netdev);
2628 dev_dbg(&pdev->dev, "PCH Network Connection\n");
2630 /* Disable hibernation on certain platforms */
2631 if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2632 pch_gbe_phy_disable_hibernate(&adapter->hw);
2634 device_set_wakeup_enable(&pdev->dev, 1);
2638 pch_gbe_phy_hw_reset(&adapter->hw);
2640 free_netdev(netdev);
2644 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2645 * ensure it is awake for probe and init. Request the line and reset the PHY.
2647 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2649 unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2650 unsigned gpio = MINNOW_PHY_RESET_GPIO;
2653 ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2654 "minnow_phy_reset");
2657 "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2661 gpio_set_value(gpio, 0);
2662 usleep_range(1250, 1500);
2663 gpio_set_value(gpio, 1);
2664 usleep_range(1250, 1500);
2669 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2670 .phy_tx_clk_delay = true,
2671 .phy_disable_hibernate = true,
2672 .platform_init = pch_gbe_minnow_platform_init,
2675 static const struct pci_device_id pch_gbe_pcidev_id[] = {
2676 {.vendor = PCI_VENDOR_ID_INTEL,
2677 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2678 .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2679 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2680 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2681 .class_mask = (0xFFFF00),
2682 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2684 {.vendor = PCI_VENDOR_ID_INTEL,
2685 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2686 .subvendor = PCI_ANY_ID,
2687 .subdevice = PCI_ANY_ID,
2688 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2689 .class_mask = (0xFFFF00)
2691 {.vendor = PCI_VENDOR_ID_ROHM,
2692 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2693 .subvendor = PCI_ANY_ID,
2694 .subdevice = PCI_ANY_ID,
2695 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2696 .class_mask = (0xFFFF00)
2698 {.vendor = PCI_VENDOR_ID_ROHM,
2699 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2700 .subvendor = PCI_ANY_ID,
2701 .subdevice = PCI_ANY_ID,
2702 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2703 .class_mask = (0xFFFF00)
2705 /* required last entry */
2710 static const struct dev_pm_ops pch_gbe_pm_ops = {
2711 .suspend = pch_gbe_suspend,
2712 .resume = pch_gbe_resume,
2713 .freeze = pch_gbe_suspend,
2714 .thaw = pch_gbe_resume,
2715 .poweroff = pch_gbe_suspend,
2716 .restore = pch_gbe_resume,
2720 static const struct pci_error_handlers pch_gbe_err_handler = {
2721 .error_detected = pch_gbe_io_error_detected,
2722 .slot_reset = pch_gbe_io_slot_reset,
2723 .resume = pch_gbe_io_resume
2726 static struct pci_driver pch_gbe_driver = {
2727 .name = KBUILD_MODNAME,
2728 .id_table = pch_gbe_pcidev_id,
2729 .probe = pch_gbe_probe,
2730 .remove = pch_gbe_remove,
2732 .driver.pm = &pch_gbe_pm_ops,
2734 .shutdown = pch_gbe_shutdown,
2735 .err_handler = &pch_gbe_err_handler
2737 module_pci_driver(pch_gbe_driver);
2739 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2740 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2741 MODULE_LICENSE("GPL");
2742 MODULE_VERSION(DRV_VERSION);
2743 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2745 /* pch_gbe_main.c */