1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. */
4 #ifndef MLX5_IFC_DR_STE_V1_H
5 #define MLX5_IFC_DR_STE_V1_H
7 enum mlx5_ifc_ste_v1_modify_hdr_offset {
8 MLX5_MODIFY_HEADER_V1_QW_OFFSET = 0x20,
11 struct mlx5_ifc_ste_single_action_flow_tag_v1_bits {
16 struct mlx5_ifc_ste_single_action_modify_list_v1_bits {
18 u8 num_of_modify_actions[0x8];
19 u8 modify_actions_ptr[0x10];
22 struct mlx5_ifc_ste_single_action_remove_header_v1_bits {
24 u8 reserved_at_8[0x2];
26 u8 reserved_at_10[0x2];
28 u8 reserved_at_18[0x4];
34 struct mlx5_ifc_ste_single_action_remove_header_size_v1_bits {
36 u8 reserved_at_8[0x2];
38 u8 outer_l4_remove[0x1];
39 u8 reserved_at_11[0x1];
41 u8 reserved_at_18[0x1];
45 struct mlx5_ifc_ste_double_action_copy_v1_bits {
47 u8 destination_dw_offset[0x8];
48 u8 reserved_at_10[0x2];
49 u8 destination_left_shifter[0x6];
50 u8 reserved_at_17[0x2];
51 u8 destination_length[0x6];
53 u8 reserved_at_20[0x8];
54 u8 source_dw_offset[0x8];
55 u8 reserved_at_30[0x2];
56 u8 source_right_shifter[0x6];
57 u8 reserved_at_38[0x8];
60 struct mlx5_ifc_ste_double_action_set_v1_bits {
62 u8 destination_dw_offset[0x8];
63 u8 reserved_at_10[0x2];
64 u8 destination_left_shifter[0x6];
65 u8 reserved_at_18[0x2];
66 u8 destination_length[0x6];
71 struct mlx5_ifc_ste_double_action_add_v1_bits {
73 u8 destination_dw_offset[0x8];
74 u8 reserved_at_10[0x2];
75 u8 destination_left_shifter[0x6];
76 u8 reserved_at_18[0x2];
77 u8 destination_length[0x6];
82 struct mlx5_ifc_ste_double_action_insert_with_inline_v1_bits {
84 u8 reserved_at_8[0x2];
87 u8 reserved_at_17[0x9];
92 struct mlx5_ifc_ste_double_action_insert_with_ptr_v1_bits {
94 u8 reserved_at_8[0x2];
103 struct mlx5_ifc_ste_double_action_accelerated_modify_action_list_v1_bits {
105 u8 modify_actions_pattern_pointer[0x18];
107 u8 number_of_modify_actions[0x8];
108 u8 modify_actions_argument_pointer[0x18];
111 struct mlx5_ifc_ste_match_bwc_v1_bits {
112 u8 entry_format[0x8];
115 u8 miss_address_63_48[0x10];
116 u8 match_definer_ctx_idx[0x8];
117 u8 miss_address_39_32[0x8];
119 u8 miss_address_31_6[0x1a];
120 u8 reserved_at_5a[0x1];
121 u8 match_polarity[0x1];
123 u8 reserved_at_5d[0x3];
125 u8 next_table_base_63_48[0x10];
126 u8 hash_definer_ctx_idx[0x8];
127 u8 next_table_base_39_32_size[0x8];
129 u8 next_table_base_31_5_size[0x1b];
131 u8 hash_after_actions[0x1];
132 u8 reserved_at_9e[0x2];
135 u8 next_entry_format[0x1];
142 struct mlx5_ifc_ste_mask_and_match_v1_bits {
143 u8 entry_format[0x8];
146 u8 miss_address_63_48[0x10];
147 u8 match_definer_ctx_idx[0x8];
148 u8 miss_address_39_32[0x8];
150 u8 miss_address_31_6[0x1a];
151 u8 reserved_at_5a[0x1];
152 u8 match_polarity[0x1];
154 u8 reserved_at_5d[0x3];
156 u8 next_table_base_63_48[0x10];
157 u8 hash_definer_ctx_idx[0x8];
158 u8 next_table_base_39_32_size[0x8];
160 u8 next_table_base_31_5_size[0x1b];
162 u8 hash_after_actions[0x1];
163 u8 reserved_at_9e[0x2];
168 struct mlx5_ifc_ste_match_ranges_v1_bits {
169 u8 entry_format[0x8];
172 u8 miss_address_63_48[0x10];
173 u8 match_definer_ctx_idx[0x8];
174 u8 miss_address_39_32[0x8];
176 u8 miss_address_31_6[0x1a];
177 u8 reserved_at_5a[0x1];
178 u8 match_polarity[0x1];
180 u8 reserved_at_5d[0x3];
182 u8 next_table_base_63_48[0x10];
183 u8 hash_definer_ctx_idx[0x8];
184 u8 next_table_base_39_32_size[0x8];
186 u8 next_table_base_31_5_size[0x1b];
188 u8 hash_after_actions[0x1];
189 u8 reserved_at_9e[0x2];
193 u8 max_value_0[0x20];
194 u8 min_value_0[0x20];
195 u8 max_value_1[0x20];
196 u8 min_value_1[0x20];
197 u8 max_value_2[0x20];
198 u8 min_value_2[0x20];
199 u8 max_value_3[0x20];
200 u8 min_value_3[0x20];
203 struct mlx5_ifc_ste_eth_l2_src_v1_bits {
204 u8 reserved_at_0[0x1];
206 u8 functional_loopback[0x1];
207 u8 ip_fragmented[0x1];
209 u8 encapsulation_type[0x2];
213 u8 first_vlan_qualifier[0x2];
214 u8 first_priority[0x3];
216 u8 first_vlan_id[0xc];
221 u8 l3_ethertype[0x10];
223 u8 reserved_at_60[0x6];
225 u8 reserved_at_67[0x3];
226 u8 force_loopback[0x1];
230 u8 second_vlan_qualifier[0x2];
232 u8 second_priority[0x3];
234 u8 second_vlan_id[0xc];
237 struct mlx5_ifc_ste_eth_l2_dst_v1_bits {
238 u8 reserved_at_0[0x1];
240 u8 functional_lb[0x1];
241 u8 ip_fragmented[0x1];
243 u8 encapsulation_type[0x2];
247 u8 first_vlan_qualifier[0x2];
248 u8 first_priority[0x3];
250 u8 first_vlan_id[0xc];
255 u8 l3_ethertype[0x10];
257 u8 reserved_at_60[0x6];
259 u8 reserved_at_67[0x3];
264 u8 second_vlan_qualifier[0x2];
265 u8 second_priority[0x3];
267 u8 second_vlan_id[0xc];
270 struct mlx5_ifc_ste_eth_l2_src_dst_v1_bits {
276 u8 reserved_at_50[0x2];
277 u8 functional_lb[0x1];
278 u8 reserved_at_53[0x5];
281 u8 reserved_at_5c[0x2];
282 u8 first_vlan_qualifier[0x2];
284 u8 first_priority[0x3];
286 u8 first_vlan_id[0xc];
290 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_v1_bits {
291 u8 source_address[0x20];
293 u8 destination_address[0x20];
295 u8 source_port[0x10];
296 u8 destination_port[0x10];
298 u8 reserved_at_60[0x4];
316 struct mlx5_ifc_ste_eth_l2_tnl_v1_bits {
317 u8 l2_tunneling_network_id[0x20];
322 u8 l3_ethertype[0x10];
324 u8 reserved_at_60[0x3];
325 u8 ip_fragmented[0x1];
326 u8 reserved_at_64[0x2];
328 u8 reserved_at_68[0x2];
331 u8 first_vlan_qualifier[0x2];
332 u8 first_priority[0x3];
334 u8 first_vlan_id[0xc];
337 struct mlx5_ifc_ste_eth_l3_ipv4_misc_v1_bits {
338 u8 identification[0x10];
340 u8 fragment_offset[0xd];
342 u8 total_length[0x10];
347 u8 time_to_live[0x8];
348 u8 reserved_at_50[0x10];
350 u8 reserved_at_60[0x1c];
351 u8 voq_internal_prio[0x4];
354 struct mlx5_ifc_ste_eth_l4_v1_bits {
355 u8 ipv6_version[0x4];
356 u8 reserved_at_4[0x4];
359 u8 ipv6_hop_limit[0x8];
365 u8 first_fragment[0x1];
366 u8 reserved_at_41[0xb];
369 u8 tcp_data_offset[0x4];
382 u8 ipv6_paylen[0x10];
385 struct mlx5_ifc_ste_eth_l4_misc_v1_bits {
386 u8 window_size[0x10];
387 u8 urgent_pointer[0x10];
397 struct mlx5_ifc_ste_mpls_v1_bits {
398 u8 reserved_at_0[0x15];
401 u8 mpls4_qualifier[0x1];
403 u8 mpls3_qualifier[0x1];
405 u8 mpls2_qualifier[0x1];
407 u8 mpls1_qualifier[0x1];
409 u8 mpls0_qualifier[0x1];
411 u8 mpls0_label[0x14];
416 u8 mpls1_label[0x20];
418 u8 mpls2_label[0x20];
421 struct mlx5_ifc_ste_gre_v1_bits {
422 u8 gre_c_present[0x1];
423 u8 reserved_at_1[0x1];
424 u8 gre_k_present[0x1];
425 u8 gre_s_present[0x1];
426 u8 strict_src_route[0x1];
430 u8 gre_protocol[0x10];
432 u8 reserved_at_20[0x20];
437 u8 reserved_at_60[0x20];
440 struct mlx5_ifc_ste_src_gvmi_qp_v1_bits {
441 u8 loopback_synd[0x8];
442 u8 reserved_at_8[0x7];
443 u8 functional_lb[0x1];
444 u8 source_gvmi[0x10];
447 u8 reserved_at_21[0x1];
448 u8 source_is_requestor[0x1];
449 u8 reserved_at_23[0x5];
452 u8 reserved_at_40[0x20];
454 u8 reserved_at_60[0x20];
457 struct mlx5_ifc_ste_icmp_v1_bits {
458 u8 icmp_payload_data[0x20];
460 u8 icmp_header_data[0x20];
464 u8 reserved_at_50[0x10];
466 u8 reserved_at_60[0x20];
469 #endif /* MLX5_IFC_DR_STE_V1_H */