2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
61 #include "fpga/core.h"
62 #include "en_accel/ipsec.h"
63 #include "lib/clock.h"
64 #include "lib/vxlan.h"
65 #include "lib/geneve.h"
66 #include "lib/devcom.h"
67 #include "lib/pci_vsc.h"
68 #include "diag/fw_tracer.h"
70 #include "lib/hv_vhca.h"
71 #include "diag/rsc_dump.h"
72 #include "sf/vhca_event.h"
73 #include "sf/dev/dev.h"
77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
79 MODULE_LICENSE("Dual BSD/GPL");
81 unsigned int mlx5_core_debug_mask;
82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
86 module_param_named(prof_sel, prof_sel, uint, 0444);
87 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89 static u32 sw_owner_id[4];
90 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
91 static DEFINE_IDA(sw_vhca_ida);
94 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
95 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
98 #define LOG_MAX_SUPPORTED_QPS 0xff
100 static struct mlx5_profile profile[] = {
103 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
106 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
112 .mask = MLX5_PROF_MASK_QP_SIZE |
113 MLX5_PROF_MASK_MR_CACHE,
114 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
115 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
182 .mask = MLX5_PROF_MASK_QP_SIZE,
183 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
188 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
191 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
192 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
197 fw_initializing = ioread32be(&dev->iseg->initializing);
198 if (!(fw_initializing >> 31))
200 if (time_after(jiffies, end) ||
201 test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
205 if (warn_time_mili && time_after(jiffies, warn)) {
206 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n",
207 jiffies_to_msecs(end - warn) / 1000, fw_initializing);
208 warn = jiffies + msecs_to_jiffies(warn_time_mili);
210 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
216 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
218 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
220 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
221 int remaining_size = driver_ver_sz;
224 if (!MLX5_CAP_GEN(dev, driver_version))
227 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
229 strncpy(string, "Linux", remaining_size);
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235 strncat(string, KBUILD_MODNAME, remaining_size);
237 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
238 strncat(string, ",", remaining_size);
240 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
242 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
243 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
244 LINUX_VERSION_SUBLEVEL);
247 MLX5_SET(set_driver_version_in, in, opcode,
248 MLX5_CMD_OP_SET_DRIVER_VERSION);
250 mlx5_cmd_exec_in(dev, set_driver_version, in);
253 static int set_dma_caps(struct pci_dev *pdev)
257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
259 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
262 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
267 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
271 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
273 struct pci_dev *pdev = dev->pdev;
276 mutex_lock(&dev->pci_status_mutex);
277 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
278 err = pci_enable_device(pdev);
280 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
282 mutex_unlock(&dev->pci_status_mutex);
287 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
289 struct pci_dev *pdev = dev->pdev;
291 mutex_lock(&dev->pci_status_mutex);
292 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
293 pci_disable_device(pdev);
294 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
296 mutex_unlock(&dev->pci_status_mutex);
299 static int request_bar(struct pci_dev *pdev)
303 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
304 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
308 err = pci_request_regions(pdev, KBUILD_MODNAME);
310 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
315 static void release_bar(struct pci_dev *pdev)
317 pci_release_regions(pdev);
320 struct mlx5_reg_host_endianness {
325 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
341 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
346 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
348 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
349 dev->mlx5e_res.uplink_netdev = netdev;
350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
355 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
357 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
358 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
359 dev->mlx5e_res.uplink_netdev);
360 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
362 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
364 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
365 enum mlx5_cap_type cap_type,
366 enum mlx5_cap_mode cap_mode)
368 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
369 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
370 void *out, *hca_caps;
371 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
374 memset(in, 0, sizeof(in));
375 out = kzalloc(out_sz, GFP_KERNEL);
379 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
380 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
381 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
384 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
385 cap_type, cap_mode, err);
389 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
392 case HCA_CAP_OPMOD_GET_MAX:
393 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
394 MLX5_UN_SZ_BYTES(hca_cap_union));
396 case HCA_CAP_OPMOD_GET_CUR:
397 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
398 MLX5_UN_SZ_BYTES(hca_cap_union));
402 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
412 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
416 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
419 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
422 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
424 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
425 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
426 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
429 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
435 if (!MLX5_CAP_GEN(dev, atomic))
438 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
444 supported_atomic_req_8B_endianness_mode_1);
446 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
449 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
451 /* Set requestor to host endianness */
452 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
453 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
455 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
458 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
464 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
465 !MLX5_CAP_GEN(dev, pg))
468 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
472 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
473 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
474 MLX5_ST_SZ_BYTES(odp_cap));
476 #define ODP_CAP_SET_MAX(dev, field) \
478 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
481 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
485 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
486 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
490 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
491 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
492 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
493 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
494 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
495 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
496 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
497 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
498 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
503 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
506 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
508 struct devlink *devlink = priv_to_devlink(dev);
509 union devlink_param_value val;
512 err = devl_param_driverinit_value_get(devlink,
513 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
517 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
521 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
523 struct devlink *devlink = priv_to_devlink(dev);
524 union devlink_param_value val;
527 err = devl_param_driverinit_value_get(devlink,
528 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
534 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
535 return MLX5_CAP_GEN(dev, roce);
537 EXPORT_SYMBOL(mlx5_is_roce_on);
539 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
544 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
547 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
551 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
552 !(dev->priv.sw_vhca_id > 0))
555 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
557 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
558 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
559 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
561 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
564 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
566 struct mlx5_profile *prof = &dev->profile;
571 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
575 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
577 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
578 MLX5_ST_SZ_BYTES(cmd_hca_cap));
580 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
581 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
583 /* we limit the size of the pkey table to 128 entries for now */
584 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
585 to_fw_pkey_sz(dev, 128));
587 /* Check log_max_qp from HCA caps to set in current profile */
588 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
589 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
590 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
591 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
593 MLX5_CAP_GEN_MAX(dev, log_max_qp));
594 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
596 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
597 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
600 /* disable cmdif checksum */
601 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
603 /* Enable 4K UAR only when HCA supports it and page size is bigger
606 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
607 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
609 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
611 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
612 MLX5_SET(cmd_hca_cap,
615 cache_line_size() >= 128 ? 1 : 0);
617 if (MLX5_CAP_GEN_MAX(dev, dct))
618 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
620 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
621 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
623 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
624 MLX5_SET(cmd_hca_cap,
627 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
629 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
630 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
632 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
633 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
635 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
637 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
638 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
639 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
641 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
642 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
643 mlx5_is_roce_on(dev));
645 max_uc_list = max_uc_list_get_devlink_param(dev);
647 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
650 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
653 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
655 * In case RoCE cap is writable in FW and user/devlink requested to change the
656 * cap, we are yet to query the final state of the above cap.
657 * Hence, the need for this function.
661 * 1) RoCE cap is read only in FW and already disabled
663 * 2) RoCE cap is writable in FW and user/devlink requested it off.
665 * In any other case, return False.
667 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
669 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
670 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
673 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
678 if (is_roce_fw_disabled(dev))
681 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
685 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
686 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
689 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
690 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
691 MLX5_ST_SZ_BYTES(roce_cap));
692 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
694 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
698 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
704 if (!MLX5_CAP_GEN(dev, port_selection_cap))
707 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
711 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
712 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
715 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
716 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
717 MLX5_ST_SZ_BYTES(port_selection_cap));
718 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
720 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
725 static int set_hca_cap(struct mlx5_core_dev *dev)
727 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
731 set_ctx = kzalloc(set_sz, GFP_KERNEL);
735 err = handle_hca_cap(dev, set_ctx);
737 mlx5_core_err(dev, "handle_hca_cap failed\n");
741 memset(set_ctx, 0, set_sz);
742 err = handle_hca_cap_atomic(dev, set_ctx);
744 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
748 memset(set_ctx, 0, set_sz);
749 err = handle_hca_cap_odp(dev, set_ctx);
751 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
755 memset(set_ctx, 0, set_sz);
756 err = handle_hca_cap_roce(dev, set_ctx);
758 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
762 memset(set_ctx, 0, set_sz);
763 err = handle_hca_cap_2(dev, set_ctx);
765 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
769 memset(set_ctx, 0, set_sz);
770 err = handle_hca_cap_port_selection(dev, set_ctx);
772 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
781 static int set_hca_ctrl(struct mlx5_core_dev *dev)
783 struct mlx5_reg_host_endianness he_in;
784 struct mlx5_reg_host_endianness he_out;
787 if (!mlx5_core_is_pf(dev))
790 memset(&he_in, 0, sizeof(he_in));
791 he_in.he = MLX5_SET_HOST_ENDIANNESS;
792 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
793 &he_out, sizeof(he_out),
794 MLX5_REG_HOST_ENDIANNESS, 0, 1);
798 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
802 /* Disable local_lb by default */
803 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
804 ret = mlx5_nic_vport_update_local_lb(dev, false);
809 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
811 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
813 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
814 MLX5_SET(enable_hca_in, in, function_id, func_id);
815 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
816 dev->caps.embedded_cpu);
817 return mlx5_cmd_exec_in(dev, enable_hca, in);
820 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
822 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
824 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
825 MLX5_SET(disable_hca_in, in, function_id, func_id);
826 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
827 dev->caps.embedded_cpu);
828 return mlx5_cmd_exec_in(dev, disable_hca, in);
831 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
833 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
834 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
838 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
839 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
841 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
842 u8 status = MLX5_GET(query_issi_out, query_out, status);
844 if (!status || syndrome == MLX5_DRIVER_SYND) {
845 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
846 err, status, syndrome);
850 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
855 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
857 if (sup_issi & (1 << 1)) {
858 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
860 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
861 MLX5_SET(set_issi_in, set_in, current_issi, 1);
862 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
864 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
872 } else if (sup_issi & (1 << 0) || !sup_issi) {
879 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
880 const struct pci_device_id *id)
884 mutex_init(&dev->pci_status_mutex);
885 pci_set_drvdata(dev->pdev, dev);
887 dev->bar_addr = pci_resource_start(pdev, 0);
889 err = mlx5_pci_enable_device(dev);
891 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
895 err = request_bar(pdev);
897 mlx5_core_err(dev, "error requesting BARs, aborting\n");
901 pci_set_master(pdev);
903 err = set_dma_caps(pdev);
905 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
909 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
910 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
911 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
912 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
914 dev->iseg_base = dev->bar_addr;
915 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
918 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
922 mlx5_pci_vsc_init(dev);
923 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
927 release_bar(dev->pdev);
929 mlx5_pci_disable_device(dev);
933 static void mlx5_pci_close(struct mlx5_core_dev *dev)
935 /* health work might still be active, and it needs pci bar in
936 * order to know the NIC state. Therefore, drain the health WQ
937 * before removing the pci bars
939 mlx5_drain_health_wq(dev);
941 release_bar(dev->pdev);
942 mlx5_pci_disable_device(dev);
945 static int mlx5_init_once(struct mlx5_core_dev *dev)
949 dev->priv.devcom = mlx5_devcom_register_device(dev);
950 if (IS_ERR(dev->priv.devcom))
951 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
954 err = mlx5_query_board_id(dev);
956 mlx5_core_err(dev, "query board id failed\n");
960 err = mlx5_irq_table_init(dev);
962 mlx5_core_err(dev, "failed to initialize irq table\n");
966 err = mlx5_eq_table_init(dev);
968 mlx5_core_err(dev, "failed to initialize eq\n");
969 goto err_irq_cleanup;
972 err = mlx5_events_init(dev);
974 mlx5_core_err(dev, "failed to initialize events\n");
978 err = mlx5_fw_reset_init(dev);
980 mlx5_core_err(dev, "failed to initialize fw reset events\n");
981 goto err_events_cleanup;
984 mlx5_cq_debugfs_init(dev);
986 mlx5_init_reserved_gids(dev);
988 mlx5_init_clock(dev);
990 dev->vxlan = mlx5_vxlan_create(dev);
991 dev->geneve = mlx5_geneve_create(dev);
993 err = mlx5_init_rl_table(dev);
995 mlx5_core_err(dev, "Failed to init rate limiting\n");
996 goto err_tables_cleanup;
999 err = mlx5_mpfs_init(dev);
1001 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1002 goto err_rl_cleanup;
1005 err = mlx5_sriov_init(dev);
1007 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1008 goto err_mpfs_cleanup;
1011 err = mlx5_eswitch_init(dev);
1013 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1014 goto err_sriov_cleanup;
1017 err = mlx5_fpga_init(dev);
1019 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1020 goto err_eswitch_cleanup;
1023 err = mlx5_vhca_event_init(dev);
1025 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1026 goto err_fpga_cleanup;
1029 err = mlx5_sf_hw_table_init(dev);
1031 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1032 goto err_sf_hw_table_cleanup;
1035 err = mlx5_sf_table_init(dev);
1037 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1038 goto err_sf_table_cleanup;
1041 err = mlx5_fs_core_alloc(dev);
1043 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1047 dev->dm = mlx5_dm_create(dev);
1048 if (IS_ERR(dev->dm))
1049 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
1051 dev->tracer = mlx5_fw_tracer_create(dev);
1052 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1053 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1058 mlx5_sf_table_cleanup(dev);
1059 err_sf_table_cleanup:
1060 mlx5_sf_hw_table_cleanup(dev);
1061 err_sf_hw_table_cleanup:
1062 mlx5_vhca_event_cleanup(dev);
1064 mlx5_fpga_cleanup(dev);
1065 err_eswitch_cleanup:
1066 mlx5_eswitch_cleanup(dev->priv.eswitch);
1068 mlx5_sriov_cleanup(dev);
1070 mlx5_mpfs_cleanup(dev);
1072 mlx5_cleanup_rl_table(dev);
1074 mlx5_geneve_destroy(dev->geneve);
1075 mlx5_vxlan_destroy(dev->vxlan);
1076 mlx5_cleanup_clock(dev);
1077 mlx5_cleanup_reserved_gids(dev);
1078 mlx5_cq_debugfs_cleanup(dev);
1079 mlx5_fw_reset_cleanup(dev);
1081 mlx5_events_cleanup(dev);
1083 mlx5_eq_table_cleanup(dev);
1085 mlx5_irq_table_cleanup(dev);
1087 mlx5_devcom_unregister_device(dev->priv.devcom);
1092 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1094 mlx5_rsc_dump_destroy(dev);
1095 mlx5_hv_vhca_destroy(dev->hv_vhca);
1096 mlx5_fw_tracer_destroy(dev->tracer);
1097 mlx5_dm_cleanup(dev);
1098 mlx5_fs_core_free(dev);
1099 mlx5_sf_table_cleanup(dev);
1100 mlx5_sf_hw_table_cleanup(dev);
1101 mlx5_vhca_event_cleanup(dev);
1102 mlx5_fpga_cleanup(dev);
1103 mlx5_eswitch_cleanup(dev->priv.eswitch);
1104 mlx5_sriov_cleanup(dev);
1105 mlx5_mpfs_cleanup(dev);
1106 mlx5_cleanup_rl_table(dev);
1107 mlx5_geneve_destroy(dev->geneve);
1108 mlx5_vxlan_destroy(dev->vxlan);
1109 mlx5_cleanup_clock(dev);
1110 mlx5_cleanup_reserved_gids(dev);
1111 mlx5_cq_debugfs_cleanup(dev);
1112 mlx5_fw_reset_cleanup(dev);
1113 mlx5_events_cleanup(dev);
1114 mlx5_eq_table_cleanup(dev);
1115 mlx5_irq_table_cleanup(dev);
1116 mlx5_devcom_unregister_device(dev->priv.devcom);
1119 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1123 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1124 fw_rev_min(dev), fw_rev_sub(dev));
1126 /* Only PFs hold the relevant PCIe information for this query */
1127 if (mlx5_core_is_pf(dev))
1128 pcie_print_link_status(dev->pdev);
1130 /* wait for firmware to accept initialization segments configurations
1132 err = wait_fw_init(dev, timeout,
1133 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1135 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1140 err = mlx5_cmd_init(dev);
1142 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1146 mlx5_tout_query_iseg(dev);
1148 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1150 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1151 mlx5_tout_ms(dev, FW_INIT));
1152 goto err_cmd_cleanup;
1155 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1157 mlx5_start_health_poll(dev);
1159 err = mlx5_core_enable_hca(dev, 0);
1161 mlx5_core_err(dev, "enable hca failed\n");
1162 goto stop_health_poll;
1165 err = mlx5_core_set_issi(dev);
1167 mlx5_core_err(dev, "failed to set issi\n");
1168 goto err_disable_hca;
1171 err = mlx5_satisfy_startup_pages(dev, 1);
1173 mlx5_core_err(dev, "failed to allocate boot pages\n");
1174 goto err_disable_hca;
1177 err = mlx5_tout_query_dtor(dev);
1179 mlx5_core_err(dev, "failed to read dtor\n");
1180 goto reclaim_boot_pages;
1183 err = set_hca_ctrl(dev);
1185 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1186 goto reclaim_boot_pages;
1189 err = set_hca_cap(dev);
1191 mlx5_core_err(dev, "set_hca_cap failed\n");
1192 goto reclaim_boot_pages;
1195 err = mlx5_satisfy_startup_pages(dev, 0);
1197 mlx5_core_err(dev, "failed to allocate init pages\n");
1198 goto reclaim_boot_pages;
1201 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1203 mlx5_core_err(dev, "init hca failed\n");
1204 goto reclaim_boot_pages;
1207 mlx5_set_driver_version(dev);
1209 err = mlx5_query_hca_caps(dev);
1211 mlx5_core_err(dev, "query hca failed\n");
1212 goto reclaim_boot_pages;
1214 mlx5_start_health_fw_log_up(dev);
1219 mlx5_reclaim_startup_pages(dev);
1221 mlx5_core_disable_hca(dev, 0);
1223 mlx5_stop_health_poll(dev, boot);
1225 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1226 mlx5_cmd_cleanup(dev);
1231 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1235 err = mlx5_cmd_teardown_hca(dev);
1237 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1240 mlx5_reclaim_startup_pages(dev);
1241 mlx5_core_disable_hca(dev, 0);
1242 mlx5_stop_health_poll(dev, boot);
1243 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1244 mlx5_cmd_cleanup(dev);
1249 static int mlx5_load(struct mlx5_core_dev *dev)
1253 dev->priv.uar = mlx5_get_uars_page(dev);
1254 if (IS_ERR(dev->priv.uar)) {
1255 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1256 err = PTR_ERR(dev->priv.uar);
1260 mlx5_events_start(dev);
1261 mlx5_pagealloc_start(dev);
1263 err = mlx5_irq_table_create(dev);
1265 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1269 err = mlx5_eq_table_create(dev);
1271 mlx5_core_err(dev, "Failed to create EQs\n");
1275 err = mlx5_fw_tracer_init(dev->tracer);
1277 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1278 mlx5_fw_tracer_destroy(dev->tracer);
1282 mlx5_fw_reset_events_start(dev);
1283 mlx5_hv_vhca_init(dev->hv_vhca);
1285 err = mlx5_rsc_dump_init(dev);
1287 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1288 mlx5_rsc_dump_destroy(dev);
1289 dev->rsc_dump = NULL;
1292 err = mlx5_fpga_device_start(dev);
1294 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1295 goto err_fpga_start;
1298 err = mlx5_fs_core_init(dev);
1300 mlx5_core_err(dev, "Failed to init flow steering\n");
1304 err = mlx5_core_set_hca_defaults(dev);
1306 mlx5_core_err(dev, "Failed to set hca defaults\n");
1310 mlx5_vhca_event_start(dev);
1312 err = mlx5_sf_hw_table_create(dev);
1314 mlx5_core_err(dev, "sf table create failed %d\n", err);
1318 err = mlx5_ec_init(dev);
1320 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1324 mlx5_lag_add_mdev(dev);
1325 err = mlx5_sriov_attach(dev);
1327 mlx5_core_err(dev, "sriov init failed %d\n", err);
1331 mlx5_sf_dev_table_create(dev);
1333 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1340 mlx5_sf_dev_table_destroy(dev);
1341 mlx5_sriov_detach(dev);
1343 mlx5_lag_remove_mdev(dev);
1344 mlx5_ec_cleanup(dev);
1346 mlx5_sf_hw_table_destroy(dev);
1348 mlx5_vhca_event_stop(dev);
1350 mlx5_fs_core_cleanup(dev);
1352 mlx5_fpga_device_stop(dev);
1354 mlx5_rsc_dump_cleanup(dev);
1355 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1356 mlx5_fw_reset_events_stop(dev);
1357 mlx5_fw_tracer_cleanup(dev->tracer);
1358 mlx5_eq_table_destroy(dev);
1360 mlx5_irq_table_destroy(dev);
1362 mlx5_pagealloc_stop(dev);
1363 mlx5_events_stop(dev);
1364 mlx5_put_uars_page(dev, dev->priv.uar);
1368 static void mlx5_unload(struct mlx5_core_dev *dev)
1370 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1371 mlx5_sf_dev_table_destroy(dev);
1372 mlx5_eswitch_disable(dev->priv.eswitch);
1373 mlx5_sriov_detach(dev);
1374 mlx5_lag_remove_mdev(dev);
1375 mlx5_ec_cleanup(dev);
1376 mlx5_sf_hw_table_destroy(dev);
1377 mlx5_vhca_event_stop(dev);
1378 mlx5_fs_core_cleanup(dev);
1379 mlx5_fpga_device_stop(dev);
1380 mlx5_rsc_dump_cleanup(dev);
1381 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1382 mlx5_fw_reset_events_stop(dev);
1383 mlx5_fw_tracer_cleanup(dev->tracer);
1384 mlx5_eq_table_destroy(dev);
1385 mlx5_irq_table_destroy(dev);
1386 mlx5_pagealloc_stop(dev);
1387 mlx5_events_stop(dev);
1388 mlx5_put_uars_page(dev, dev->priv.uar);
1391 int mlx5_init_one(struct mlx5_core_dev *dev)
1393 struct devlink *devlink = priv_to_devlink(dev);
1397 mutex_lock(&dev->intf_state_mutex);
1398 dev->state = MLX5_DEVICE_STATE_UP;
1400 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1404 err = mlx5_init_once(dev);
1406 mlx5_core_err(dev, "sw objs init failed\n");
1407 goto function_teardown;
1410 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1412 goto err_devlink_params_reg;
1414 err = mlx5_load(dev);
1418 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1420 err = mlx5_register_device(dev);
1424 mutex_unlock(&dev->intf_state_mutex);
1425 devl_unlock(devlink);
1429 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1432 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1433 err_devlink_params_reg:
1434 mlx5_cleanup_once(dev);
1436 mlx5_function_teardown(dev, true);
1438 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1439 mutex_unlock(&dev->intf_state_mutex);
1440 devl_unlock(devlink);
1444 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1446 struct devlink *devlink = priv_to_devlink(dev);
1449 mutex_lock(&dev->intf_state_mutex);
1451 mlx5_unregister_device(dev);
1453 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1454 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1456 mlx5_cleanup_once(dev);
1460 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1462 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1463 mlx5_cleanup_once(dev);
1464 mlx5_function_teardown(dev, true);
1466 mutex_unlock(&dev->intf_state_mutex);
1467 devl_unlock(devlink);
1470 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1475 devl_assert_locked(priv_to_devlink(dev));
1476 mutex_lock(&dev->intf_state_mutex);
1477 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1478 mlx5_core_warn(dev, "interface is up, NOP\n");
1481 /* remove any previous indication of internal error */
1482 dev->state = MLX5_DEVICE_STATE_UP;
1485 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1487 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1488 err = mlx5_function_setup(dev, false, timeout);
1492 err = mlx5_load(dev);
1496 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1498 err = mlx5_attach_device(dev);
1502 mutex_unlock(&dev->intf_state_mutex);
1506 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1509 mlx5_function_teardown(dev, false);
1511 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1513 mutex_unlock(&dev->intf_state_mutex);
1517 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1519 struct devlink *devlink = priv_to_devlink(dev);
1523 ret = mlx5_load_one_devl_locked(dev, recovery);
1524 devl_unlock(devlink);
1528 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1530 devl_assert_locked(priv_to_devlink(dev));
1531 mutex_lock(&dev->intf_state_mutex);
1533 mlx5_detach_device(dev, suspend);
1535 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1536 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1541 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1543 mlx5_function_teardown(dev, false);
1545 mutex_unlock(&dev->intf_state_mutex);
1548 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1550 struct devlink *devlink = priv_to_devlink(dev);
1553 mlx5_unload_one_devl_locked(dev, suspend);
1554 devl_unlock(devlink);
1557 static const int types[] = {
1560 MLX5_CAP_ETHERNET_OFFLOADS,
1561 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1565 MLX5_CAP_IPOIB_OFFLOADS,
1566 MLX5_CAP_FLOW_TABLE,
1567 MLX5_CAP_ESWITCH_FLOW_TABLE,
1569 MLX5_CAP_VECTOR_CALC,
1575 MLX5_CAP_VDPA_EMULATION,
1577 MLX5_CAP_PORT_SELECTION,
1578 MLX5_CAP_DEV_SHAMPO,
1580 MLX5_CAP_ADV_VIRTUALIZATION,
1584 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1589 for (i = 0; i < ARRAY_SIZE(types); i++) {
1591 kfree(dev->caps.hca[type]);
1595 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1597 struct mlx5_hca_cap *cap;
1601 for (i = 0; i < ARRAY_SIZE(types); i++) {
1602 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1606 dev->caps.hca[type] = cap;
1612 mlx5_hca_caps_free(dev);
1616 static int vhca_id_show(struct seq_file *file, void *priv)
1618 struct mlx5_core_dev *dev = file->private;
1620 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1624 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1626 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1628 struct mlx5_priv *priv = &dev->priv;
1631 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1632 lockdep_register_key(&dev->lock_key);
1633 mutex_init(&dev->intf_state_mutex);
1634 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1635 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1637 mutex_init(&priv->bfregs.reg_head.lock);
1638 mutex_init(&priv->bfregs.wc_head.lock);
1639 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1640 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1642 mutex_init(&priv->alloc_mutex);
1643 mutex_init(&priv->pgdir_mutex);
1644 INIT_LIST_HEAD(&priv->pgdir_list);
1646 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1647 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1649 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1650 INIT_LIST_HEAD(&priv->traps);
1652 err = mlx5_tout_init(dev);
1654 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1655 goto err_timeout_init;
1658 err = mlx5_health_init(dev);
1660 goto err_health_init;
1662 err = mlx5_pagealloc_init(dev);
1664 goto err_pagealloc_init;
1666 err = mlx5_adev_init(dev);
1670 err = mlx5_hca_caps_alloc(dev);
1674 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1675 * unique id per function which uses mlx5_core.
1676 * Those values are supplied to FW as part of the init HCA command to
1677 * be used by both driver and FW when it's applicable.
1679 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1682 if (dev->priv.sw_vhca_id < 0)
1683 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1684 dev->priv.sw_vhca_id);
1689 mlx5_adev_cleanup(dev);
1691 mlx5_pagealloc_cleanup(dev);
1693 mlx5_health_cleanup(dev);
1695 mlx5_tout_cleanup(dev);
1697 debugfs_remove(dev->priv.dbg.dbg_root);
1698 mutex_destroy(&priv->pgdir_mutex);
1699 mutex_destroy(&priv->alloc_mutex);
1700 mutex_destroy(&priv->bfregs.wc_head.lock);
1701 mutex_destroy(&priv->bfregs.reg_head.lock);
1702 mutex_destroy(&dev->intf_state_mutex);
1703 lockdep_unregister_key(&dev->lock_key);
1707 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1709 struct mlx5_priv *priv = &dev->priv;
1711 if (priv->sw_vhca_id > 0)
1712 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1714 mlx5_hca_caps_free(dev);
1715 mlx5_adev_cleanup(dev);
1716 mlx5_pagealloc_cleanup(dev);
1717 mlx5_health_cleanup(dev);
1718 mlx5_tout_cleanup(dev);
1719 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1720 mutex_destroy(&priv->pgdir_mutex);
1721 mutex_destroy(&priv->alloc_mutex);
1722 mutex_destroy(&priv->bfregs.wc_head.lock);
1723 mutex_destroy(&priv->bfregs.reg_head.lock);
1724 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1725 mutex_destroy(&dev->intf_state_mutex);
1726 lockdep_unregister_key(&dev->lock_key);
1729 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1731 struct mlx5_core_dev *dev;
1732 struct devlink *devlink;
1735 devlink = mlx5_devlink_alloc(&pdev->dev);
1737 dev_err(&pdev->dev, "devlink alloc failed\n");
1741 dev = devlink_priv(devlink);
1742 dev->device = &pdev->dev;
1745 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1746 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1748 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1749 if (dev->priv.adev_idx < 0) {
1750 err = dev->priv.adev_idx;
1754 err = mlx5_mdev_init(dev, prof_sel);
1758 err = mlx5_pci_init(dev, pdev, id);
1760 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1765 err = mlx5_init_one(dev);
1767 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1772 err = mlx5_crdump_enable(dev);
1774 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1776 err = mlx5_thermal_init(dev);
1778 dev_err(&pdev->dev, "mlx5_thermal_init failed with error code %d\n", err);
1780 pci_save_state(pdev);
1781 devlink_register(devlink);
1785 mlx5_pci_close(dev);
1787 mlx5_mdev_uninit(dev);
1789 mlx5_adev_idx_free(dev->priv.adev_idx);
1791 mlx5_devlink_free(devlink);
1796 static void remove_one(struct pci_dev *pdev)
1798 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1799 struct devlink *devlink = priv_to_devlink(dev);
1801 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1802 /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain
1803 * fw_reset before unregistering the devlink.
1805 mlx5_drain_fw_reset(dev);
1806 devlink_unregister(devlink);
1807 mlx5_sriov_disable(pdev);
1808 mlx5_thermal_uninit(dev);
1809 mlx5_crdump_disable(dev);
1810 mlx5_drain_health_wq(dev);
1811 mlx5_uninit_one(dev);
1812 mlx5_pci_close(dev);
1813 mlx5_mdev_uninit(dev);
1814 mlx5_adev_idx_free(dev->priv.adev_idx);
1815 mlx5_devlink_free(devlink);
1818 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1819 struct mlx5_core_dev *__dev = (dev); \
1820 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1821 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1822 __dev->pci_status, ##__VA_ARGS__); \
1825 static const char *result2str(enum pci_ers_result result)
1827 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1828 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1829 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1833 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1834 pci_channel_state_t state)
1836 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1837 enum pci_ers_result res;
1839 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1841 mlx5_enter_error_state(dev, false);
1842 mlx5_error_sw_reset(dev);
1843 mlx5_unload_one(dev, true);
1844 mlx5_drain_health_wq(dev);
1845 mlx5_pci_disable_device(dev);
1847 res = state == pci_channel_io_perm_failure ?
1848 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1850 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
1851 __func__, dev->state, dev->pci_status, res, result2str(res));
1855 /* wait for the device to show vital signs by waiting
1856 * for the health counter to start counting.
1858 static int wait_vital(struct pci_dev *pdev)
1860 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1861 struct mlx5_core_health *health = &dev->priv.health;
1862 const int niter = 100;
1867 for (i = 0; i < niter; i++) {
1868 count = ioread32be(health->health_counter);
1869 if (count && count != 0xffffffff) {
1870 if (last_count && last_count != count) {
1872 "wait vital counter value 0x%x after %d iterations\n",
1884 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1886 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1887 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1890 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
1891 __func__, dev->state, dev->pci_status);
1893 err = mlx5_pci_enable_device(dev);
1895 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1900 pci_set_master(pdev);
1901 pci_restore_state(pdev);
1902 pci_save_state(pdev);
1904 err = wait_vital(pdev);
1906 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1911 res = PCI_ERS_RESULT_RECOVERED;
1913 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
1914 __func__, dev->state, dev->pci_status, err, res, result2str(res));
1918 static void mlx5_pci_resume(struct pci_dev *pdev)
1920 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1923 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1925 err = mlx5_load_one(dev, false);
1928 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
1929 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
1931 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1932 !err ? "recovered" : "Failed");
1935 static const struct pci_error_handlers mlx5_err_handler = {
1936 .error_detected = mlx5_pci_err_detected,
1937 .slot_reset = mlx5_pci_slot_reset,
1938 .resume = mlx5_pci_resume
1941 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1943 bool fast_teardown = false, force_teardown = false;
1946 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1947 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1949 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1950 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1952 if (!fast_teardown && !force_teardown)
1955 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1956 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1960 /* Panic tear down fw command will stop the PCI bus communication
1961 * with the HCA, so the health poll is no longer needed.
1963 mlx5_drain_health_wq(dev);
1964 mlx5_stop_health_poll(dev, false);
1966 ret = mlx5_cmd_fast_teardown_hca(dev);
1970 ret = mlx5_cmd_force_teardown_hca(dev);
1974 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1975 mlx5_start_health_poll(dev);
1979 mlx5_enter_error_state(dev, true);
1981 /* Some platforms requiring freeing the IRQ's in the shutdown
1982 * flow. If they aren't freed they can't be allocated after
1983 * kexec. There is no need to cleanup the mlx5_core software
1986 mlx5_core_eq_free_irqs(dev);
1991 static void shutdown(struct pci_dev *pdev)
1993 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1996 mlx5_core_info(dev, "Shutdown was called\n");
1997 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1998 err = mlx5_try_fast_unload(dev);
2000 mlx5_unload_one(dev, false);
2001 mlx5_pci_disable_device(dev);
2004 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2006 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2008 mlx5_unload_one(dev, true);
2013 static int mlx5_resume(struct pci_dev *pdev)
2015 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2017 return mlx5_load_one(dev, false);
2020 static const struct pci_device_id mlx5_core_pci_table[] = {
2021 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2022 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2023 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2024 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2025 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2026 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2027 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2028 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2029 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2030 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2031 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2032 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2033 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2034 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2035 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2036 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2037 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2038 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2039 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2040 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2041 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2042 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2046 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2048 void mlx5_disable_device(struct mlx5_core_dev *dev)
2050 mlx5_error_sw_reset(dev);
2051 mlx5_unload_one_devl_locked(dev, false);
2054 int mlx5_recover_device(struct mlx5_core_dev *dev)
2056 if (!mlx5_core_is_sf(dev)) {
2057 mlx5_pci_disable_device(dev);
2058 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2062 return mlx5_load_one_devl_locked(dev, true);
2065 static struct pci_driver mlx5_core_driver = {
2066 .name = KBUILD_MODNAME,
2067 .id_table = mlx5_core_pci_table,
2069 .remove = remove_one,
2070 .suspend = mlx5_suspend,
2071 .resume = mlx5_resume,
2072 .shutdown = shutdown,
2073 .err_handler = &mlx5_err_handler,
2074 .sriov_configure = mlx5_core_sriov_configure,
2075 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2076 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2080 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2081 * mlx5_core is its driver.
2082 * @pdev: The associated PCI device.
2084 * Upon return the interface state lock stay held to let caller uses it safely.
2085 * Caller must ensure to use the returned mlx5 device for a narrow window
2086 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2088 * Return: Pointer to the associated mlx5_core_dev or NULL.
2090 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2092 struct mlx5_core_dev *mdev;
2094 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2098 mutex_lock(&mdev->intf_state_mutex);
2099 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2100 mutex_unlock(&mdev->intf_state_mutex);
2106 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2109 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2110 * @mdev: The mlx5 core device.
2112 * Upon return the interface state lock is unlocked and caller should not
2113 * access the mdev any more.
2115 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2117 mutex_unlock(&mdev->intf_state_mutex);
2119 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2121 static void mlx5_core_verify_params(void)
2123 if (prof_sel >= ARRAY_SIZE(profile)) {
2124 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2126 ARRAY_SIZE(profile) - 1,
2128 prof_sel = MLX5_DEFAULT_PROF;
2132 static int __init mlx5_init(void)
2136 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2137 "mlx5_core name not in sync with kernel module name");
2139 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2141 mlx5_core_verify_params();
2142 mlx5_register_debugfs();
2148 err = mlx5_sf_driver_register();
2152 err = pci_register_driver(&mlx5_core_driver);
2159 mlx5_sf_driver_unregister();
2163 mlx5_unregister_debugfs();
2167 static void __exit mlx5_cleanup(void)
2169 pci_unregister_driver(&mlx5_core_driver);
2170 mlx5_sf_driver_unregister();
2172 mlx5_unregister_debugfs();
2175 module_init(mlx5_init);
2176 module_exit(mlx5_cleanup);