2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "en_accel/tls.h"
36 #include "en_accel/en_accel.h"
38 static unsigned int stats_grps_num(struct mlx5e_priv *priv)
40 return !priv->profile->stats_grps_num ? 0 :
41 priv->profile->stats_grps_num(priv);
44 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv)
46 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
47 const unsigned int num_stats_grps = stats_grps_num(priv);
48 unsigned int total = 0;
51 for (i = 0; i < num_stats_grps; i++)
52 total += stats_grps[i]->get_num_stats(priv);
57 void mlx5e_stats_update(struct mlx5e_priv *priv)
59 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
60 const unsigned int num_stats_grps = stats_grps_num(priv);
63 for (i = num_stats_grps - 1; i >= 0; i--)
64 if (stats_grps[i]->update_stats)
65 stats_grps[i]->update_stats(priv);
68 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx)
70 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
71 const unsigned int num_stats_grps = stats_grps_num(priv);
74 for (i = 0; i < num_stats_grps; i++)
75 idx = stats_grps[i]->fill_stats(priv, data, idx);
78 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data)
80 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
81 const unsigned int num_stats_grps = stats_grps_num(priv);
84 for (i = 0; i < num_stats_grps; i++)
85 idx = stats_grps[i]->fill_strings(priv, data, idx);
88 /* Concrete NIC Stats */
90 static const struct counter_desc sw_stats_desc[] = {
91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) },
102 #ifdef CONFIG_MLX5_EN_TLS
103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_packets) },
104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_bytes) },
105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ctx) },
106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_packets) },
108 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_bytes) },
109 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
110 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_skip_no_sync_data) },
111 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_no_sync_data) },
112 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_bypass_req) },
115 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
116 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
117 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_ecn_mark) },
118 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
119 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
120 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
121 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
122 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail) },
123 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail_slow) },
124 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
125 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
126 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) },
127 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) },
128 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_mpwqe) },
129 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_inlnw) },
130 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_nops) },
131 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
132 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) },
133 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) },
134 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
135 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
136 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
137 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
138 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
139 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
140 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
141 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) },
142 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
143 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
144 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_xmit) },
145 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_mpwqe) },
146 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_inlnw) },
147 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_nops) },
148 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_full) },
149 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_err) },
150 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_cqes) },
151 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
152 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) },
153 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) },
154 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_oversize_pkts_sw_drop) },
155 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
156 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
157 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
158 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
159 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
160 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
161 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
162 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
163 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
164 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) },
165 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_recover) },
166 #ifdef CONFIG_MLX5_EN_TLS
167 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_packets) },
168 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_bytes) },
169 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_ctx) },
170 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_del) },
171 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_pkt) },
172 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_start) },
173 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_end) },
174 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_skip) },
175 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_ok) },
176 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_skip) },
177 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_err) },
179 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) },
180 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
181 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
182 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
183 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_force_irq) },
184 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
185 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_packets) },
186 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_bytes) },
187 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_complete) },
188 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary) },
189 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary_inner) },
190 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_none) },
191 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_ecn_mark) },
192 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_removed_vlan_packets) },
193 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_drop) },
194 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_redirect) },
195 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_wqe_err) },
196 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_cqes) },
197 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_strides) },
198 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_oversize_pkts_sw_drop) },
199 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_buff_alloc_err) },
200 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_blks) },
201 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_pkts) },
202 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_congst_umr) },
203 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_arfs_err) },
204 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_xmit) },
205 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_mpwqe) },
206 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_inlnw) },
207 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_full) },
208 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_err) },
209 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_cqes) },
212 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
214 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(sw)
216 return NUM_SW_COUNTERS;
219 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(sw)
223 for (i = 0; i < NUM_SW_COUNTERS; i++)
224 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
228 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(sw)
232 for (i = 0; i < NUM_SW_COUNTERS; i++)
233 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
237 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw)
239 struct mlx5e_sw_stats *s = &priv->stats.sw;
242 memset(s, 0, sizeof(*s));
244 for (i = 0; i < priv->max_nch; i++) {
245 struct mlx5e_channel_stats *channel_stats =
246 &priv->channel_stats[i];
247 struct mlx5e_xdpsq_stats *xdpsq_red_stats = &channel_stats->xdpsq;
248 struct mlx5e_xdpsq_stats *xdpsq_stats = &channel_stats->rq_xdpsq;
249 struct mlx5e_xdpsq_stats *xsksq_stats = &channel_stats->xsksq;
250 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
251 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
252 struct mlx5e_ch_stats *ch_stats = &channel_stats->ch;
255 s->rx_packets += rq_stats->packets;
256 s->rx_bytes += rq_stats->bytes;
257 s->rx_lro_packets += rq_stats->lro_packets;
258 s->rx_lro_bytes += rq_stats->lro_bytes;
259 s->rx_ecn_mark += rq_stats->ecn_mark;
260 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
261 s->rx_csum_none += rq_stats->csum_none;
262 s->rx_csum_complete += rq_stats->csum_complete;
263 s->rx_csum_complete_tail += rq_stats->csum_complete_tail;
264 s->rx_csum_complete_tail_slow += rq_stats->csum_complete_tail_slow;
265 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
266 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
267 s->rx_xdp_drop += rq_stats->xdp_drop;
268 s->rx_xdp_redirect += rq_stats->xdp_redirect;
269 s->rx_xdp_tx_xmit += xdpsq_stats->xmit;
270 s->rx_xdp_tx_mpwqe += xdpsq_stats->mpwqe;
271 s->rx_xdp_tx_inlnw += xdpsq_stats->inlnw;
272 s->rx_xdp_tx_nops += xdpsq_stats->nops;
273 s->rx_xdp_tx_full += xdpsq_stats->full;
274 s->rx_xdp_tx_err += xdpsq_stats->err;
275 s->rx_xdp_tx_cqe += xdpsq_stats->cqes;
276 s->rx_wqe_err += rq_stats->wqe_err;
277 s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes;
278 s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides;
279 s->rx_oversize_pkts_sw_drop += rq_stats->oversize_pkts_sw_drop;
280 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
281 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
282 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
283 s->rx_cache_reuse += rq_stats->cache_reuse;
284 s->rx_cache_full += rq_stats->cache_full;
285 s->rx_cache_empty += rq_stats->cache_empty;
286 s->rx_cache_busy += rq_stats->cache_busy;
287 s->rx_cache_waive += rq_stats->cache_waive;
288 s->rx_congst_umr += rq_stats->congst_umr;
289 s->rx_arfs_err += rq_stats->arfs_err;
290 s->rx_recover += rq_stats->recover;
291 #ifdef CONFIG_MLX5_EN_TLS
292 s->rx_tls_decrypted_packets += rq_stats->tls_decrypted_packets;
293 s->rx_tls_decrypted_bytes += rq_stats->tls_decrypted_bytes;
294 s->rx_tls_ctx += rq_stats->tls_ctx;
295 s->rx_tls_del += rq_stats->tls_del;
296 s->rx_tls_resync_req_pkt += rq_stats->tls_resync_req_pkt;
297 s->rx_tls_resync_req_start += rq_stats->tls_resync_req_start;
298 s->rx_tls_resync_req_end += rq_stats->tls_resync_req_end;
299 s->rx_tls_resync_req_skip += rq_stats->tls_resync_req_skip;
300 s->rx_tls_resync_res_ok += rq_stats->tls_resync_res_ok;
301 s->rx_tls_resync_res_skip += rq_stats->tls_resync_res_skip;
302 s->rx_tls_err += rq_stats->tls_err;
304 s->ch_events += ch_stats->events;
305 s->ch_poll += ch_stats->poll;
306 s->ch_arm += ch_stats->arm;
307 s->ch_aff_change += ch_stats->aff_change;
308 s->ch_force_irq += ch_stats->force_irq;
309 s->ch_eq_rearm += ch_stats->eq_rearm;
311 s->tx_xdp_xmit += xdpsq_red_stats->xmit;
312 s->tx_xdp_mpwqe += xdpsq_red_stats->mpwqe;
313 s->tx_xdp_inlnw += xdpsq_red_stats->inlnw;
314 s->tx_xdp_nops += xdpsq_red_stats->nops;
315 s->tx_xdp_full += xdpsq_red_stats->full;
316 s->tx_xdp_err += xdpsq_red_stats->err;
317 s->tx_xdp_cqes += xdpsq_red_stats->cqes;
318 /* AF_XDP zero-copy */
319 s->rx_xsk_packets += xskrq_stats->packets;
320 s->rx_xsk_bytes += xskrq_stats->bytes;
321 s->rx_xsk_csum_complete += xskrq_stats->csum_complete;
322 s->rx_xsk_csum_unnecessary += xskrq_stats->csum_unnecessary;
323 s->rx_xsk_csum_unnecessary_inner += xskrq_stats->csum_unnecessary_inner;
324 s->rx_xsk_csum_none += xskrq_stats->csum_none;
325 s->rx_xsk_ecn_mark += xskrq_stats->ecn_mark;
326 s->rx_xsk_removed_vlan_packets += xskrq_stats->removed_vlan_packets;
327 s->rx_xsk_xdp_drop += xskrq_stats->xdp_drop;
328 s->rx_xsk_xdp_redirect += xskrq_stats->xdp_redirect;
329 s->rx_xsk_wqe_err += xskrq_stats->wqe_err;
330 s->rx_xsk_mpwqe_filler_cqes += xskrq_stats->mpwqe_filler_cqes;
331 s->rx_xsk_mpwqe_filler_strides += xskrq_stats->mpwqe_filler_strides;
332 s->rx_xsk_oversize_pkts_sw_drop += xskrq_stats->oversize_pkts_sw_drop;
333 s->rx_xsk_buff_alloc_err += xskrq_stats->buff_alloc_err;
334 s->rx_xsk_cqe_compress_blks += xskrq_stats->cqe_compress_blks;
335 s->rx_xsk_cqe_compress_pkts += xskrq_stats->cqe_compress_pkts;
336 s->rx_xsk_congst_umr += xskrq_stats->congst_umr;
337 s->rx_xsk_arfs_err += xskrq_stats->arfs_err;
338 s->tx_xsk_xmit += xsksq_stats->xmit;
339 s->tx_xsk_mpwqe += xsksq_stats->mpwqe;
340 s->tx_xsk_inlnw += xsksq_stats->inlnw;
341 s->tx_xsk_full += xsksq_stats->full;
342 s->tx_xsk_err += xsksq_stats->err;
343 s->tx_xsk_cqes += xsksq_stats->cqes;
345 for (j = 0; j < priv->max_opened_tc; j++) {
346 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
348 s->tx_packets += sq_stats->packets;
349 s->tx_bytes += sq_stats->bytes;
350 s->tx_tso_packets += sq_stats->tso_packets;
351 s->tx_tso_bytes += sq_stats->tso_bytes;
352 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
353 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
354 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
355 s->tx_nop += sq_stats->nop;
356 s->tx_queue_stopped += sq_stats->stopped;
357 s->tx_queue_wake += sq_stats->wake;
358 s->tx_queue_dropped += sq_stats->dropped;
359 s->tx_cqe_err += sq_stats->cqe_err;
360 s->tx_recover += sq_stats->recover;
361 s->tx_xmit_more += sq_stats->xmit_more;
362 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
363 s->tx_csum_none += sq_stats->csum_none;
364 s->tx_csum_partial += sq_stats->csum_partial;
365 #ifdef CONFIG_MLX5_EN_TLS
366 s->tx_tls_encrypted_packets += sq_stats->tls_encrypted_packets;
367 s->tx_tls_encrypted_bytes += sq_stats->tls_encrypted_bytes;
368 s->tx_tls_ctx += sq_stats->tls_ctx;
369 s->tx_tls_ooo += sq_stats->tls_ooo;
370 s->tx_tls_dump_bytes += sq_stats->tls_dump_bytes;
371 s->tx_tls_dump_packets += sq_stats->tls_dump_packets;
372 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
373 s->tx_tls_skip_no_sync_data += sq_stats->tls_skip_no_sync_data;
374 s->tx_tls_drop_no_sync_data += sq_stats->tls_drop_no_sync_data;
375 s->tx_tls_drop_bypass_req += sq_stats->tls_drop_bypass_req;
377 s->tx_cqes += sq_stats->cqes;
379 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
385 static const struct counter_desc q_stats_desc[] = {
386 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
389 static const struct counter_desc drop_rq_stats_desc[] = {
390 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
393 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
394 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
396 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qcnt)
401 num_stats += NUM_Q_COUNTERS;
403 if (priv->drop_rq_q_counter)
404 num_stats += NUM_DROP_RQ_COUNTERS;
409 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qcnt)
413 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
414 strcpy(data + (idx++) * ETH_GSTRING_LEN,
415 q_stats_desc[i].format);
417 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
418 strcpy(data + (idx++) * ETH_GSTRING_LEN,
419 drop_rq_stats_desc[i].format);
424 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qcnt)
428 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
429 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
431 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
432 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
433 drop_rq_stats_desc, i);
437 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qcnt)
439 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
440 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {};
441 u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {};
444 MLX5_SET(query_q_counter_in, in, opcode, MLX5_CMD_OP_QUERY_Q_COUNTER);
446 if (priv->q_counter) {
447 MLX5_SET(query_q_counter_in, in, counter_set_id,
449 ret = mlx5_cmd_exec_inout(priv->mdev, query_q_counter, in, out);
451 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
455 if (priv->drop_rq_q_counter) {
456 MLX5_SET(query_q_counter_in, in, counter_set_id,
457 priv->drop_rq_q_counter);
458 ret = mlx5_cmd_exec_inout(priv->mdev, query_q_counter, in, out);
460 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out,
465 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
466 static const struct counter_desc vnic_env_stats_steer_desc[] = {
467 { "rx_steer_missed_packets",
468 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
471 static const struct counter_desc vnic_env_stats_dev_oob_desc[] = {
472 { "dev_internal_queue_oob",
473 VNIC_ENV_OFF(vport_env.internal_rq_out_of_buffer) },
476 #define NUM_VNIC_ENV_STEER_COUNTERS(dev) \
477 (MLX5_CAP_GEN(dev, nic_receive_steering_discard) ? \
478 ARRAY_SIZE(vnic_env_stats_steer_desc) : 0)
479 #define NUM_VNIC_ENV_DEV_OOB_COUNTERS(dev) \
480 (MLX5_CAP_GEN(dev, vnic_env_int_rq_oob) ? \
481 ARRAY_SIZE(vnic_env_stats_dev_oob_desc) : 0)
483 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vnic_env)
485 return NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev) +
486 NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev);
489 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vnic_env)
493 for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
494 strcpy(data + (idx++) * ETH_GSTRING_LEN,
495 vnic_env_stats_steer_desc[i].format);
497 for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
498 strcpy(data + (idx++) * ETH_GSTRING_LEN,
499 vnic_env_stats_dev_oob_desc[i].format);
503 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vnic_env)
507 for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
508 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
509 vnic_env_stats_steer_desc, i);
511 for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
512 data[idx++] = MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
513 vnic_env_stats_dev_oob_desc, i);
517 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vnic_env)
519 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
520 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
521 struct mlx5_core_dev *mdev = priv->mdev;
523 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
526 MLX5_SET(query_vnic_env_in, in, opcode, MLX5_CMD_OP_QUERY_VNIC_ENV);
527 mlx5_cmd_exec_inout(mdev, query_vnic_env, in, out);
530 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
531 static const struct counter_desc vport_stats_desc[] = {
532 { "rx_vport_unicast_packets",
533 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
534 { "rx_vport_unicast_bytes",
535 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
536 { "tx_vport_unicast_packets",
537 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
538 { "tx_vport_unicast_bytes",
539 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
540 { "rx_vport_multicast_packets",
541 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
542 { "rx_vport_multicast_bytes",
543 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
544 { "tx_vport_multicast_packets",
545 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
546 { "tx_vport_multicast_bytes",
547 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
548 { "rx_vport_broadcast_packets",
549 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
550 { "rx_vport_broadcast_bytes",
551 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
552 { "tx_vport_broadcast_packets",
553 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
554 { "tx_vport_broadcast_bytes",
555 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
556 { "rx_vport_rdma_unicast_packets",
557 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
558 { "rx_vport_rdma_unicast_bytes",
559 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
560 { "tx_vport_rdma_unicast_packets",
561 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
562 { "tx_vport_rdma_unicast_bytes",
563 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
564 { "rx_vport_rdma_multicast_packets",
565 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
566 { "rx_vport_rdma_multicast_bytes",
567 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
568 { "tx_vport_rdma_multicast_packets",
569 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
570 { "tx_vport_rdma_multicast_bytes",
571 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
574 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
576 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vport)
578 return NUM_VPORT_COUNTERS;
581 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vport)
585 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
586 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
590 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport)
594 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
595 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
596 vport_stats_desc, i);
600 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport)
602 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
603 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {};
604 struct mlx5_core_dev *mdev = priv->mdev;
606 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
607 mlx5_cmd_exec_inout(mdev, query_vport_counter, in, out);
610 #define PPORT_802_3_OFF(c) \
611 MLX5_BYTE_OFF(ppcnt_reg, \
612 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
613 static const struct counter_desc pport_802_3_stats_desc[] = {
614 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
615 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
616 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
617 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
618 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
619 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
620 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
621 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
622 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
623 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
624 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
625 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
626 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
627 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
628 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
629 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
630 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
631 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
634 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
636 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(802_3)
638 return NUM_PPORT_802_3_COUNTERS;
641 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(802_3)
645 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
646 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
650 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(802_3)
654 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
655 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
656 pport_802_3_stats_desc, i);
660 #define MLX5_BASIC_PPCNT_SUPPORTED(mdev) \
661 (MLX5_CAP_GEN(mdev, pcam_reg) ? MLX5_CAP_PCAM_REG(mdev, ppcnt) : 1)
663 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(802_3)
665 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
666 struct mlx5_core_dev *mdev = priv->mdev;
667 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
668 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
671 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
674 MLX5_SET(ppcnt_reg, in, local_port, 1);
675 out = pstats->IEEE_802_3_counters;
676 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
677 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
680 #define PPORT_2863_OFF(c) \
681 MLX5_BYTE_OFF(ppcnt_reg, \
682 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
683 static const struct counter_desc pport_2863_stats_desc[] = {
684 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
685 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
686 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
689 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
691 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2863)
693 return NUM_PPORT_2863_COUNTERS;
696 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2863)
700 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
701 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
705 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2863)
709 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
710 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
711 pport_2863_stats_desc, i);
715 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2863)
717 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
718 struct mlx5_core_dev *mdev = priv->mdev;
719 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
720 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
723 MLX5_SET(ppcnt_reg, in, local_port, 1);
724 out = pstats->RFC_2863_counters;
725 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
726 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
729 #define PPORT_2819_OFF(c) \
730 MLX5_BYTE_OFF(ppcnt_reg, \
731 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
732 static const struct counter_desc pport_2819_stats_desc[] = {
733 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
734 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
735 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
736 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
737 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
738 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
739 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
740 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
741 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
742 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
743 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
744 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
745 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
748 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
750 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2819)
752 return NUM_PPORT_2819_COUNTERS;
755 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2819)
759 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
760 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
764 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2819)
768 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
769 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
770 pport_2819_stats_desc, i);
774 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2819)
776 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
777 struct mlx5_core_dev *mdev = priv->mdev;
778 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
779 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
782 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
785 MLX5_SET(ppcnt_reg, in, local_port, 1);
786 out = pstats->RFC_2819_counters;
787 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
788 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
791 #define PPORT_PHY_STATISTICAL_OFF(c) \
792 MLX5_BYTE_OFF(ppcnt_reg, \
793 counter_set.phys_layer_statistical_cntrs.c##_high)
794 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
795 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
796 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
799 static const struct counter_desc
800 pport_phy_statistical_err_lanes_stats_desc[] = {
801 { "rx_err_lane_0_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane0) },
802 { "rx_err_lane_1_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane1) },
803 { "rx_err_lane_2_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane2) },
804 { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) },
807 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \
808 ARRAY_SIZE(pport_phy_statistical_stats_desc)
809 #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \
810 ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc)
812 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy)
814 struct mlx5_core_dev *mdev = priv->mdev;
817 /* "1" for link_down_events special counter */
820 num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ?
821 NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0;
823 num_stats += MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters) ?
824 NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0;
829 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy)
831 struct mlx5_core_dev *mdev = priv->mdev;
834 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
836 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
839 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
840 strcpy(data + (idx++) * ETH_GSTRING_LEN,
841 pport_phy_statistical_stats_desc[i].format);
843 if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters))
844 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++)
845 strcpy(data + (idx++) * ETH_GSTRING_LEN,
846 pport_phy_statistical_err_lanes_stats_desc[i].format);
851 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy)
853 struct mlx5_core_dev *mdev = priv->mdev;
856 /* link_down_events_phy has special handling since it is not stored in __be64 format */
857 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
858 counter_set.phys_layer_cntrs.link_down_events);
860 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
863 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
865 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
866 pport_phy_statistical_stats_desc, i);
868 if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters))
869 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++)
871 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
872 pport_phy_statistical_err_lanes_stats_desc,
877 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)
879 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
880 struct mlx5_core_dev *mdev = priv->mdev;
881 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
882 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
885 MLX5_SET(ppcnt_reg, in, local_port, 1);
886 out = pstats->phy_counters;
887 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
888 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
890 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
893 out = pstats->phy_statistical_counters;
894 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
895 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
898 #define PPORT_ETH_EXT_OFF(c) \
899 MLX5_BYTE_OFF(ppcnt_reg, \
900 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
901 static const struct counter_desc pport_eth_ext_stats_desc[] = {
902 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
905 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
907 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(eth_ext)
909 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
910 return NUM_PPORT_ETH_EXT_COUNTERS;
915 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(eth_ext)
919 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
920 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
921 strcpy(data + (idx++) * ETH_GSTRING_LEN,
922 pport_eth_ext_stats_desc[i].format);
926 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(eth_ext)
930 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
931 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
933 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
934 pport_eth_ext_stats_desc, i);
938 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(eth_ext)
940 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
941 struct mlx5_core_dev *mdev = priv->mdev;
942 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
943 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
946 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
949 MLX5_SET(ppcnt_reg, in, local_port, 1);
950 out = pstats->eth_ext_counters;
951 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
952 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
955 #define PCIE_PERF_OFF(c) \
956 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
957 static const struct counter_desc pcie_perf_stats_desc[] = {
958 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
959 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
962 #define PCIE_PERF_OFF64(c) \
963 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
964 static const struct counter_desc pcie_perf_stats_desc64[] = {
965 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
968 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
969 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
970 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
971 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
972 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
975 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
976 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
977 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
979 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pcie)
983 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
984 num_stats += NUM_PCIE_PERF_COUNTERS;
986 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
987 num_stats += NUM_PCIE_PERF_COUNTERS64;
989 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
990 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
995 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pcie)
999 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1000 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1001 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1002 pcie_perf_stats_desc[i].format);
1004 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1005 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1006 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1007 pcie_perf_stats_desc64[i].format);
1009 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1010 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1011 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1012 pcie_perf_stall_stats_desc[i].format);
1016 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie)
1020 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1021 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1023 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
1024 pcie_perf_stats_desc, i);
1026 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1027 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1029 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
1030 pcie_perf_stats_desc64, i);
1032 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1033 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1035 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
1036 pcie_perf_stall_stats_desc, i);
1040 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie)
1042 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
1043 struct mlx5_core_dev *mdev = priv->mdev;
1044 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
1045 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
1048 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
1051 out = pcie_stats->pcie_perf_counters;
1052 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
1053 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
1056 #define PPORT_PER_TC_PRIO_OFF(c) \
1057 MLX5_BYTE_OFF(ppcnt_reg, \
1058 counter_set.eth_per_tc_prio_grp_data_layout.c##_high)
1060 static const struct counter_desc pport_per_tc_prio_stats_desc[] = {
1061 { "rx_prio%d_buf_discard", PPORT_PER_TC_PRIO_OFF(no_buffer_discard_uc) },
1064 #define NUM_PPORT_PER_TC_PRIO_COUNTERS ARRAY_SIZE(pport_per_tc_prio_stats_desc)
1066 #define PPORT_PER_TC_CONGEST_PRIO_OFF(c) \
1067 MLX5_BYTE_OFF(ppcnt_reg, \
1068 counter_set.eth_per_tc_congest_prio_grp_data_layout.c##_high)
1070 static const struct counter_desc pport_per_tc_congest_prio_stats_desc[] = {
1071 { "rx_prio%d_cong_discard", PPORT_PER_TC_CONGEST_PRIO_OFF(wred_discard) },
1072 { "rx_prio%d_marked", PPORT_PER_TC_CONGEST_PRIO_OFF(ecn_marked_tc) },
1075 #define NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS \
1076 ARRAY_SIZE(pport_per_tc_congest_prio_stats_desc)
1078 static int mlx5e_grp_per_tc_prio_get_num_stats(struct mlx5e_priv *priv)
1080 struct mlx5_core_dev *mdev = priv->mdev;
1082 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1085 return NUM_PPORT_PER_TC_PRIO_COUNTERS * NUM_PPORT_PRIO;
1088 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_port_buff_congest)
1090 struct mlx5_core_dev *mdev = priv->mdev;
1093 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1096 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1097 for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1098 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1099 pport_per_tc_prio_stats_desc[i].format, prio);
1100 for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS; i++)
1101 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1102 pport_per_tc_congest_prio_stats_desc[i].format, prio);
1108 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_port_buff_congest)
1110 struct mlx5e_pport_stats *pport = &priv->stats.pport;
1111 struct mlx5_core_dev *mdev = priv->mdev;
1114 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1117 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1118 for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1120 MLX5E_READ_CTR64_BE(&pport->per_tc_prio_counters[prio],
1121 pport_per_tc_prio_stats_desc, i);
1122 for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS ; i++)
1124 MLX5E_READ_CTR64_BE(&pport->per_tc_congest_prio_counters[prio],
1125 pport_per_tc_congest_prio_stats_desc, i);
1131 static void mlx5e_grp_per_tc_prio_update_stats(struct mlx5e_priv *priv)
1133 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1134 struct mlx5_core_dev *mdev = priv->mdev;
1135 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1136 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1140 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1143 MLX5_SET(ppcnt_reg, in, pnat, 2);
1144 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP);
1145 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1146 out = pstats->per_tc_prio_counters[prio];
1147 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1148 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1152 static int mlx5e_grp_per_tc_congest_prio_get_num_stats(struct mlx5e_priv *priv)
1154 struct mlx5_core_dev *mdev = priv->mdev;
1156 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1159 return NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS * NUM_PPORT_PRIO;
1162 static void mlx5e_grp_per_tc_congest_prio_update_stats(struct mlx5e_priv *priv)
1164 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1165 struct mlx5_core_dev *mdev = priv->mdev;
1166 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1167 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1171 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1174 MLX5_SET(ppcnt_reg, in, pnat, 2);
1175 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP);
1176 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1177 out = pstats->per_tc_congest_prio_counters[prio];
1178 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1179 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1183 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_port_buff_congest)
1185 return mlx5e_grp_per_tc_prio_get_num_stats(priv) +
1186 mlx5e_grp_per_tc_congest_prio_get_num_stats(priv);
1189 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_port_buff_congest)
1191 mlx5e_grp_per_tc_prio_update_stats(priv);
1192 mlx5e_grp_per_tc_congest_prio_update_stats(priv);
1195 #define PPORT_PER_PRIO_OFF(c) \
1196 MLX5_BYTE_OFF(ppcnt_reg, \
1197 counter_set.eth_per_prio_grp_data_layout.c##_high)
1198 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
1199 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
1200 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
1201 { "rx_prio%d_discards", PPORT_PER_PRIO_OFF(rx_discards) },
1202 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
1203 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
1206 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
1208 static int mlx5e_grp_per_prio_traffic_get_num_stats(void)
1210 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
1213 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
1219 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1220 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1221 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1222 pport_per_prio_traffic_stats_desc[i].format, prio);
1228 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
1234 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1235 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1237 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
1238 pport_per_prio_traffic_stats_desc, i);
1244 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
1245 /* %s is "global" or "prio{i}" */
1246 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
1247 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
1248 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
1249 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
1250 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
1253 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
1254 { "tx_pause_storm_warning_events", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
1255 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
1258 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
1259 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
1260 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
1261 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1263 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
1265 struct mlx5_core_dev *mdev = priv->mdev;
1270 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1273 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
1275 return err ? 0 : pfc_en_tx | pfc_en_rx;
1278 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
1280 struct mlx5_core_dev *mdev = priv->mdev;
1285 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1288 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1290 return err ? false : rx_pause | tx_pause;
1293 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
1295 return (mlx5e_query_global_pause_combined(priv) +
1296 hweight8(mlx5e_query_pfc_combined(priv))) *
1297 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
1298 NUM_PPORT_PFC_STALL_COUNTERS(priv);
1301 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
1305 unsigned long pfc_combined;
1308 pfc_combined = mlx5e_query_pfc_combined(priv);
1309 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
1310 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1311 char pfc_string[ETH_GSTRING_LEN];
1313 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
1314 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1315 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
1319 if (mlx5e_query_global_pause_combined(priv)) {
1320 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1321 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1322 pport_per_prio_pfc_stats_desc[i].format, "global");
1326 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1327 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1328 pport_pfc_stall_stats_desc[i].format);
1333 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
1337 unsigned long pfc_combined;
1340 pfc_combined = mlx5e_query_pfc_combined(priv);
1341 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
1342 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1344 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
1345 pport_per_prio_pfc_stats_desc, i);
1349 if (mlx5e_query_global_pause_combined(priv)) {
1350 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1352 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1353 pport_per_prio_pfc_stats_desc, i);
1357 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1358 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1359 pport_pfc_stall_stats_desc, i);
1364 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_prio)
1366 return mlx5e_grp_per_prio_traffic_get_num_stats() +
1367 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
1370 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_prio)
1372 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
1373 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
1377 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_prio)
1379 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
1380 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
1384 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_prio)
1386 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1387 struct mlx5_core_dev *mdev = priv->mdev;
1388 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1389 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1393 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
1396 MLX5_SET(ppcnt_reg, in, local_port, 1);
1397 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1398 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1399 out = pstats->per_prio_counters[prio];
1400 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1401 mlx5_core_access_reg(mdev, in, sz, out, sz,
1402 MLX5_REG_PPCNT, 0, 0);
1406 static const struct counter_desc mlx5e_pme_status_desc[] = {
1407 { "module_unplug", sizeof(u64) * MLX5_MODULE_STATUS_UNPLUGGED },
1410 static const struct counter_desc mlx5e_pme_error_desc[] = {
1411 { "module_bus_stuck", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BUS_STUCK },
1412 { "module_high_temp", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE },
1413 { "module_bad_shorted", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BAD_CABLE },
1416 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1417 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1419 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pme)
1421 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1424 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pme)
1428 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1429 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1431 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1432 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1437 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pme)
1439 struct mlx5_pme_stats pme_stats;
1442 mlx5_get_pme_stats(priv->mdev, &pme_stats);
1444 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1445 data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.status_counters,
1446 mlx5e_pme_status_desc, i);
1448 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1449 data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.error_counters,
1450 mlx5e_pme_error_desc, i);
1455 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pme) { return; }
1457 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(tls)
1459 return mlx5e_tls_get_count(priv);
1462 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(tls)
1464 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1467 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(tls)
1469 return idx + mlx5e_tls_get_stats(priv, data + idx);
1472 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(tls) { return; }
1474 static const struct counter_desc rq_stats_desc[] = {
1475 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1476 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1477 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1478 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail) },
1479 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) },
1480 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1481 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1482 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1483 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1484 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) },
1485 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1486 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
1487 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, ecn_mark) },
1488 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1489 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1490 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
1491 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
1492 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
1493 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1494 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1495 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1496 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1497 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1498 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1499 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1500 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
1501 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
1502 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) },
1503 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, recover) },
1504 #ifdef CONFIG_MLX5_EN_TLS
1505 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_packets) },
1506 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_bytes) },
1507 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_ctx) },
1508 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_del) },
1509 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_pkt) },
1510 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_start) },
1511 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_end) },
1512 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_skip) },
1513 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_ok) },
1514 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_skip) },
1515 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_err) },
1519 static const struct counter_desc sq_stats_desc[] = {
1520 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1521 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1522 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1523 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1524 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1525 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1526 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1527 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
1528 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1529 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1530 #ifdef CONFIG_MLX5_EN_TLS
1531 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_packets) },
1532 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_bytes) },
1533 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_ctx) },
1534 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_ooo) },
1535 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_packets) },
1536 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_bytes) },
1537 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_resync_bytes) },
1538 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_skip_no_sync_data) },
1539 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_no_sync_data) },
1540 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_bypass_req) },
1542 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1543 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1544 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1545 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
1546 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
1547 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) },
1548 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1549 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1552 static const struct counter_desc rq_xdpsq_stats_desc[] = {
1553 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1554 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
1555 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
1556 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) },
1557 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1558 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1559 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1562 static const struct counter_desc xdpsq_stats_desc[] = {
1563 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1564 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
1565 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
1566 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) },
1567 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1568 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1569 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1572 static const struct counter_desc xskrq_stats_desc[] = {
1573 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, packets) },
1574 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, bytes) },
1575 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_complete) },
1576 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1577 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1578 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_none) },
1579 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, ecn_mark) },
1580 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1581 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_drop) },
1582 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_redirect) },
1583 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, wqe_err) },
1584 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
1585 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
1586 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
1587 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1588 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1589 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1590 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, congst_umr) },
1591 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, arfs_err) },
1594 static const struct counter_desc xsksq_stats_desc[] = {
1595 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1596 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
1597 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
1598 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1599 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1600 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1603 static const struct counter_desc ch_stats_desc[] = {
1604 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) },
1605 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) },
1606 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) },
1607 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) },
1608 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, force_irq) },
1609 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1612 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1613 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
1614 #define NUM_XDPSQ_STATS ARRAY_SIZE(xdpsq_stats_desc)
1615 #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc)
1616 #define NUM_XSKRQ_STATS ARRAY_SIZE(xskrq_stats_desc)
1617 #define NUM_XSKSQ_STATS ARRAY_SIZE(xsksq_stats_desc)
1618 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1620 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(channels)
1622 int max_nch = priv->max_nch;
1624 return (NUM_RQ_STATS * max_nch) +
1625 (NUM_CH_STATS * max_nch) +
1626 (NUM_SQ_STATS * max_nch * priv->max_opened_tc) +
1627 (NUM_RQ_XDPSQ_STATS * max_nch) +
1628 (NUM_XDPSQ_STATS * max_nch) +
1629 (NUM_XSKRQ_STATS * max_nch * priv->xsk.ever_used) +
1630 (NUM_XSKSQ_STATS * max_nch * priv->xsk.ever_used);
1633 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(channels)
1635 bool is_xsk = priv->xsk.ever_used;
1636 int max_nch = priv->max_nch;
1639 for (i = 0; i < max_nch; i++)
1640 for (j = 0; j < NUM_CH_STATS; j++)
1641 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1642 ch_stats_desc[j].format, i);
1644 for (i = 0; i < max_nch; i++) {
1645 for (j = 0; j < NUM_RQ_STATS; j++)
1646 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1647 rq_stats_desc[j].format, i);
1648 for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
1649 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1650 xskrq_stats_desc[j].format, i);
1651 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1652 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1653 rq_xdpsq_stats_desc[j].format, i);
1656 for (tc = 0; tc < priv->max_opened_tc; tc++)
1657 for (i = 0; i < max_nch; i++)
1658 for (j = 0; j < NUM_SQ_STATS; j++)
1659 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1660 sq_stats_desc[j].format,
1663 for (i = 0; i < max_nch; i++) {
1664 for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
1665 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1666 xsksq_stats_desc[j].format, i);
1667 for (j = 0; j < NUM_XDPSQ_STATS; j++)
1668 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1669 xdpsq_stats_desc[j].format, i);
1675 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(channels)
1677 bool is_xsk = priv->xsk.ever_used;
1678 int max_nch = priv->max_nch;
1681 for (i = 0; i < max_nch; i++)
1682 for (j = 0; j < NUM_CH_STATS; j++)
1684 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch,
1687 for (i = 0; i < max_nch; i++) {
1688 for (j = 0; j < NUM_RQ_STATS; j++)
1690 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq,
1692 for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
1694 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xskrq,
1695 xskrq_stats_desc, j);
1696 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1698 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq_xdpsq,
1699 rq_xdpsq_stats_desc, j);
1702 for (tc = 0; tc < priv->max_opened_tc; tc++)
1703 for (i = 0; i < max_nch; i++)
1704 for (j = 0; j < NUM_SQ_STATS; j++)
1706 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc],
1709 for (i = 0; i < max_nch; i++) {
1710 for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
1712 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xsksq,
1713 xsksq_stats_desc, j);
1714 for (j = 0; j < NUM_XDPSQ_STATS; j++)
1716 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xdpsq,
1717 xdpsq_stats_desc, j);
1723 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(channels) { return; }
1725 MLX5E_DEFINE_STATS_GRP(sw, 0);
1726 MLX5E_DEFINE_STATS_GRP(qcnt, MLX5E_NDO_UPDATE_STATS);
1727 MLX5E_DEFINE_STATS_GRP(vnic_env, 0);
1728 MLX5E_DEFINE_STATS_GRP(vport, MLX5E_NDO_UPDATE_STATS);
1729 MLX5E_DEFINE_STATS_GRP(802_3, MLX5E_NDO_UPDATE_STATS);
1730 MLX5E_DEFINE_STATS_GRP(2863, 0);
1731 MLX5E_DEFINE_STATS_GRP(2819, 0);
1732 MLX5E_DEFINE_STATS_GRP(phy, 0);
1733 MLX5E_DEFINE_STATS_GRP(pcie, 0);
1734 MLX5E_DEFINE_STATS_GRP(per_prio, 0);
1735 MLX5E_DEFINE_STATS_GRP(pme, 0);
1736 MLX5E_DEFINE_STATS_GRP(channels, 0);
1737 MLX5E_DEFINE_STATS_GRP(per_port_buff_congest, 0);
1738 MLX5E_DEFINE_STATS_GRP(eth_ext, 0);
1739 static MLX5E_DEFINE_STATS_GRP(tls, 0);
1741 /* The stats groups order is opposite to the update_stats() order calls */
1742 mlx5e_stats_grp_t mlx5e_nic_stats_grps[] = {
1743 &MLX5E_STATS_GRP(sw),
1744 &MLX5E_STATS_GRP(qcnt),
1745 &MLX5E_STATS_GRP(vnic_env),
1746 &MLX5E_STATS_GRP(vport),
1747 &MLX5E_STATS_GRP(802_3),
1748 &MLX5E_STATS_GRP(2863),
1749 &MLX5E_STATS_GRP(2819),
1750 &MLX5E_STATS_GRP(phy),
1751 &MLX5E_STATS_GRP(eth_ext),
1752 &MLX5E_STATS_GRP(pcie),
1753 &MLX5E_STATS_GRP(per_prio),
1754 &MLX5E_STATS_GRP(pme),
1755 #ifdef CONFIG_MLX5_EN_IPSEC
1756 &MLX5E_STATS_GRP(ipsec_sw),
1757 &MLX5E_STATS_GRP(ipsec_hw),
1759 &MLX5E_STATS_GRP(tls),
1760 &MLX5E_STATS_GRP(channels),
1761 &MLX5E_STATS_GRP(per_port_buff_congest),
1764 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv)
1766 return ARRAY_SIZE(mlx5e_nic_stats_grps);