drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67
  68 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  69 {
  70         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  71                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  72                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  73         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  74         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  75
  76         if (!striding_rq_umr)
  77                 return false;
  78         if (!inline_umr) {
  79                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  80                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  81                 return false;
  82         }
  83         return true;
  84 }
  85
  86 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  87                                struct mlx5e_params *params)
  88 {
  89         params->log_rq_mtu_frames = is_kdump_kernel() ?
  90                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  91                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  92
  93         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  94                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  96                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  97                        BIT(params->log_rq_mtu_frames),
  98                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
  99                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 100 }
 101
 102 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 103                                 struct mlx5e_params *params)
 104 {
 105         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 106                 return false;
 107
 108         if (MLX5_IPSEC_DEV(mdev))
 109                 return false;
 110
 111         if (params->xdp_prog) {
 112                 /* XSK params are not considered here. If striding RQ is in use,
 113                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 114                  * be called with the known XSK params.
 115                  */
 116                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 117                         return false;
 118         }
 119
 120         return true;
 121 }
 122
 123 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 124 {
 125         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 126                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 127                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 128                 MLX5_WQ_TYPE_CYCLIC;
 129 }
 130
 131 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 132 {
 133         struct mlx5_core_dev *mdev = priv->mdev;
 134         u8 port_state;
 135
 136         port_state = mlx5_query_vport_state(mdev,
 137                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 138                                             0);
 139
 140         if (port_state == VPORT_STATE_UP) {
 141                 netdev_info(priv->netdev, "Link up\n");
 142                 netif_carrier_on(priv->netdev);
 143         } else {
 144                 netdev_info(priv->netdev, "Link down\n");
 145                 netif_carrier_off(priv->netdev);
 146         }
 147 }
 148
 149 static void mlx5e_update_carrier_work(struct work_struct *work)
 150 {
 151         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 152                                                update_carrier_work);
 153
 154         mutex_lock(&priv->state_lock);
 155         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 156                 if (priv->profile->update_carrier)
 157                         priv->profile->update_carrier(priv);
 158         mutex_unlock(&priv->state_lock);
 159 }
 160
 161 static void mlx5e_update_stats_work(struct work_struct *work)
 162 {
 163         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 164                                                update_stats_work);
 165
 166         mutex_lock(&priv->state_lock);
 167         priv->profile->update_stats(priv);
 168         mutex_unlock(&priv->state_lock);
 169 }
 170
 171 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 172 {
 173         if (!priv->profile->update_stats)
 174                 return;
 175
 176         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 177                 return;
 178
 179         queue_work(priv->wq, &priv->update_stats_work);
 180 }
 181
 182 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 183 {
 184         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 185         struct mlx5_eqe   *eqe = data;
 186
 187         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 188                 return NOTIFY_DONE;
 189
 190         switch (eqe->sub_type) {
 191         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 192         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 193                 queue_work(priv->wq, &priv->update_carrier_work);
 194                 break;
 195         default:
 196                 return NOTIFY_DONE;
 197         }
 198
 199         return NOTIFY_OK;
 200 }
 201
 202 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 203 {
 204         priv->events_nb.notifier_call = async_event;
 205         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 206 }
 207
 208 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 209 {
 210         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 211 }
 212
 213 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 214                                        struct mlx5e_icosq *sq,
 215                                        struct mlx5e_umr_wqe *wqe)
 216 {
 217         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 218         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 219         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 220
 221         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 222                                       ds_cnt);
 223         cseg->umr_mkey  = rq->mkey_be;
 224
 225         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 226         ucseg->xlt_octowords =
 227                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 228         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 229 }
 230
 231 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 232                                      struct mlx5e_channel *c)
 233 {
 234         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 235
 236         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 237                                                   sizeof(*rq->mpwqe.info)),
 238                                        GFP_KERNEL, cpu_to_node(c->cpu));
 239         if (!rq->mpwqe.info)
 240                 return -ENOMEM;
 241
 242         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 243
 244         return 0;
 245 }
 246
 247 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 248                                  u64 npages, u8 page_shift,
 249                                  struct mlx5_core_mkey *umr_mkey,
 250                                  dma_addr_t filler_addr)
 251 {
 252         struct mlx5_mtt *mtt;
 253         int inlen;
 254         void *mkc;
 255         u32 *in;
 256         int err;
 257         int i;
 258
 259         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 260
 261         in = kvzalloc(inlen, GFP_KERNEL);
 262         if (!in)
 263                 return -ENOMEM;
 264
 265         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 266
 267         MLX5_SET(mkc, mkc, free, 1);
 268         MLX5_SET(mkc, mkc, umr_en, 1);
 269         MLX5_SET(mkc, mkc, lw, 1);
 270         MLX5_SET(mkc, mkc, lr, 1);
 271         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 272         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 273         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 274         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 275         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 276         MLX5_SET(mkc, mkc, translations_octword_size,
 277                  MLX5_MTT_OCTW(npages));
 278         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 279         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 280                  MLX5_MTT_OCTW(npages));
 281
 282         /* Initialize the mkey with all MTTs pointing to a default
 283          * page (filler_addr). When the channels are activated, UMR
 284          * WQEs will redirect the RX WQEs to the actual memory from
 285          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 286          * to the default page.
 287          */
 288         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 289         for (i = 0 ; i < npages ; i++)
 290                 mtt[i].ptag = cpu_to_be64(filler_addr);
 291
 292         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 293
 294         kvfree(in);
 295         return err;
 296 }
 297
 298 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 299 {
 300         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 301
 302         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 303                                      rq->wqe_overflow.addr);
 304 }
 305
 306 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 307 {
 308         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 309 }
 310
 311 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 312 {
 313         struct mlx5e_wqe_frag_info next_frag = {};
 314         struct mlx5e_wqe_frag_info *prev = NULL;
 315         int i;
 316
 317         next_frag.di = &rq->wqe.di[0];
 318
 319         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 320                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 321                 struct mlx5e_wqe_frag_info *frag =
 322                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 323                 int f;
 324
 325                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 326                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 327                                 next_frag.di++;
 328                                 next_frag.offset = 0;
 329                                 if (prev)
 330                                         prev->last_in_page = true;
 331                         }
 332                         *frag = next_frag;
 333
 334                         /* prepare next */
 335                         next_frag.offset += frag_info[f].frag_stride;
 336                         prev = frag;
 337                 }
 338         }
 339
 340         if (prev)
 341                 prev->last_in_page = true;
 342 }
 343
 344 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 345                               int wq_sz, int cpu)
 346 {
 347         int len = wq_sz << rq->wqe.info.log_num_frags;
 348
 349         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 350                                    GFP_KERNEL, cpu_to_node(cpu));
 351         if (!rq->wqe.di)
 352                 return -ENOMEM;
 353
 354         mlx5e_init_frags_partition(rq);
 355
 356         return 0;
 357 }
 358
 359 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 360 {
 361         kvfree(rq->wqe.di);
 362 }
 363
 364 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 365 {
 366         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 367
 368         mlx5e_reporter_rq_cqe_err(rq);
 369 }
 370
 371 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 372 {
 373         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 374         if (!rq->wqe_overflow.page)
 375                 return -ENOMEM;
 376
 377         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 378                                              PAGE_SIZE, rq->buff.map_dir);
 379         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 380                 __free_page(rq->wqe_overflow.page);
 381                 return -ENOMEM;
 382         }
 383         return 0;
 384 }
 385
 386 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 387 {
 388          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 389                         rq->buff.map_dir);
 390          __free_page(rq->wqe_overflow.page);
 391 }
 392
 393 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 394                           struct mlx5e_params *params,
 395                           struct mlx5e_xsk_param *xsk,
 396                           struct xsk_buff_pool *xsk_pool,
 397                           struct mlx5e_rq_param *rqp,
 398                           struct mlx5e_rq *rq)
 399 {
 400         struct page_pool_params pp_params = { 0 };
 401         struct mlx5_core_dev *mdev = c->mdev;
 402         void *rqc = rqp->rqc;
 403         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 404         u32 rq_xdp_ix;
 405         u32 pool_size;
 406         int wq_sz;
 407         int err;
 408         int i;
 409
 410         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 411
 412         rq->wq_type = params->rq_wq_type;
 413         rq->pdev    = c->pdev;
 414         rq->netdev  = c->netdev;
 415         rq->tstamp  = c->tstamp;
 416         rq->clock   = &mdev->clock;
 417         rq->channel = c;
 418         rq->ix      = c->ix;
 419         rq->mdev    = mdev;
 420         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 421         rq->xdpsq   = &c->rq_xdpsq;
 422         rq->xsk_pool = xsk_pool;
 423
 424         if (rq->xsk_pool)
 425                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 426         else
 427                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 428         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 429
 430         if (params->xdp_prog)
 431                 bpf_prog_inc(params->xdp_prog);
 432         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 433
 434         rq_xdp_ix = rq->ix;
 435         if (xsk)
 436                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 437         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 438         if (err < 0)
 439                 goto err_rq_xdp_prog;
 440
 441         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 442         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 443         pool_size = 1 << params->log_rq_mtu_frames;
 444
 445         switch (rq->wq_type) {
 446         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 447                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 448                                         &rq->wq_ctrl);
 449                 if (err)
 450                         goto err_rq_xdp;
 451
 452                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 453                 if (err)
 454                         goto err_rq_wq_destroy;
 455
 456                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 457
 458                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 459
 460                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 461                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 462
 463                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 464                 rq->mpwqe.num_strides =
 465                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 466
 467                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 468
 469                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 470                 if (err)
 471                         goto err_rq_drop_page;
 472                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 473
 474                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 475                 if (err)
 476                         goto err_rq_mkey;
 477                 break;
 478         default: /* MLX5_WQ_TYPE_CYCLIC */
 479                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 480                                          &rq->wq_ctrl);
 481                 if (err)
 482                         goto err_rq_xdp;
 483
 484                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 485
 486                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 487
 488                 rq->wqe.info = rqp->frags_info;
 489                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 490
 491                 rq->wqe.frags =
 492                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 493                                         (wq_sz << rq->wqe.info.log_num_frags)),
 494                                       GFP_KERNEL, cpu_to_node(c->cpu));
 495                 if (!rq->wqe.frags) {
 496                         err = -ENOMEM;
 497                         goto err_rq_wq_destroy;
 498                 }
 499
 500                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 501                 if (err)
 502                         goto err_rq_frags;
 503
 504                 rq->mkey_be = c->mkey_be;
 505         }
 506
 507         err = mlx5e_rq_set_handlers(rq, params, xsk);
 508         if (err)
 509                 goto err_free_by_rq_type;
 510
 511         if (xsk) {
 512                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 513                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 514                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 515         } else {
 516                 /* Create a page_pool and register it with rxq */
 517                 pp_params.order     = 0;
 518                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 519                 pp_params.pool_size = pool_size;
 520                 pp_params.nid       = cpu_to_node(c->cpu);
 521                 pp_params.dev       = c->pdev;
 522                 pp_params.dma_dir   = rq->buff.map_dir;
 523
 524                 /* page_pool can be used even when there is no rq->xdp_prog,
 525                  * given page_pool does not handle DMA mapping there is no
 526                  * required state to clear. And page_pool gracefully handle
 527                  * elevated refcnt.
 528                  */
 529                 rq->page_pool = page_pool_create(&pp_params);
 530                 if (IS_ERR(rq->page_pool)) {
 531                         err = PTR_ERR(rq->page_pool);
 532                         rq->page_pool = NULL;
 533                         goto err_free_by_rq_type;
 534                 }
 535                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 536                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 537         }
 538         if (err)
 539                 goto err_free_by_rq_type;
 540
 541         for (i = 0; i < wq_sz; i++) {
 542                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 543                         struct mlx5e_rx_wqe_ll *wqe =
 544                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 545                         u32 byte_count =
 546                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 547                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 548
 549                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 550                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 551                         wqe->data[0].lkey = rq->mkey_be;
 552                 } else {
 553                         struct mlx5e_rx_wqe_cyc *wqe =
 554                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 555                         int f;
 556
 557                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 558                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 559                                         MLX5_HW_START_PADDING;
 560
 561                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 562                                 wqe->data[f].lkey = rq->mkey_be;
 563                         }
 564                         /* check if num_frags is not a pow of two */
 565                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 566                                 wqe->data[f].byte_count = 0;
 567                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 568                                 wqe->data[f].addr = 0;
 569                         }
 570                 }
 571         }
 572
 573         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 574
 575         switch (params->rx_cq_moderation.cq_period_mode) {
 576         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 577                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 578                 break;
 579         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 580         default:
 581                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 582         }
 583
 584         rq->page_cache.head = 0;
 585         rq->page_cache.tail = 0;
 586
 587         return 0;
 588
 589 err_free_by_rq_type:
 590         switch (rq->wq_type) {
 591         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 592                 kvfree(rq->mpwqe.info);
 593 err_rq_mkey:
 594                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 595 err_rq_drop_page:
 596                 mlx5e_free_mpwqe_rq_drop_page(rq);
 597                 break;
 598         default: /* MLX5_WQ_TYPE_CYCLIC */
 599                 mlx5e_free_di_list(rq);
 600 err_rq_frags:
 601                 kvfree(rq->wqe.frags);
 602         }
 603 err_rq_wq_destroy:
 604         mlx5_wq_destroy(&rq->wq_ctrl);
 605 err_rq_xdp:
 606         xdp_rxq_info_unreg(&rq->xdp_rxq);
 607 err_rq_xdp_prog:
 608         if (params->xdp_prog)
 609                 bpf_prog_put(params->xdp_prog);
 610
 611         return err;
 612 }
 613
 614 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 615 {
 616         struct mlx5e_channel *c = rq->channel;
 617         struct bpf_prog *old_prog = NULL;
 618         int i;
 619
 620         /* drop_rq has neither channel nor xdp_prog. */
 621         if (c)
 622                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 623                                                      lockdep_is_held(&c->priv->state_lock));
 624         if (old_prog)
 625                 bpf_prog_put(old_prog);
 626
 627         switch (rq->wq_type) {
 628         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 629                 kvfree(rq->mpwqe.info);
 630                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 631                 mlx5e_free_mpwqe_rq_drop_page(rq);
 632                 break;
 633         default: /* MLX5_WQ_TYPE_CYCLIC */
 634                 kvfree(rq->wqe.frags);
 635                 mlx5e_free_di_list(rq);
 636         }
 637
 638         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 639              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 640                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 641
 642                 /* With AF_XDP, page_cache is not used, so this loop is not
 643                  * entered, and it's safe to call mlx5e_page_release_dynamic
 644                  * directly.
 645                  */
 646                 mlx5e_page_release_dynamic(rq, dma_info, false);
 647         }
 648
 649         xdp_rxq_info_unreg(&rq->xdp_rxq);
 650         page_pool_destroy(rq->page_pool);
 651         mlx5_wq_destroy(&rq->wq_ctrl);
 652 }
 653
 654 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 655                            struct mlx5e_rq_param *param)
 656 {
 657         struct mlx5_core_dev *mdev = rq->mdev;
 658
 659         void *in;
 660         void *rqc;
 661         void *wq;
 662         int inlen;
 663         int err;
 664
 665         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 666                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 667         in = kvzalloc(inlen, GFP_KERNEL);
 668         if (!in)
 669                 return -ENOMEM;
 670
 671         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 672         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 673
 674         memcpy(rqc, param->rqc, sizeof(param->rqc));
 675
 676         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 677         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 678         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 679                                                 MLX5_ADAPTER_PAGE_SHIFT);
 680         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 681
 682         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 683                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 684
 685         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 686
 687         kvfree(in);
 688
 689         return err;
 690 }
 691
 692 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 693 {
 694         struct mlx5_core_dev *mdev = rq->mdev;
 695
 696         void *in;
 697         void *rqc;
 698         int inlen;
 699         int err;
 700
 701         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 702         in = kvzalloc(inlen, GFP_KERNEL);
 703         if (!in)
 704                 return -ENOMEM;
 705
 706         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 707                 mlx5e_rqwq_reset(rq);
 708
 709         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 710
 711         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 712         MLX5_SET(rqc, rqc, state, next_state);
 713
 714         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 715
 716         kvfree(in);
 717
 718         return err;
 719 }
 720
 721 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 722 {
 723         struct mlx5e_channel *c = rq->channel;
 724         struct mlx5e_priv *priv = c->priv;
 725         struct mlx5_core_dev *mdev = priv->mdev;
 726
 727         void *in;
 728         void *rqc;
 729         int inlen;
 730         int err;
 731
 732         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 733         in = kvzalloc(inlen, GFP_KERNEL);
 734         if (!in)
 735                 return -ENOMEM;
 736
 737         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 738
 739         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 740         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 741                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 742         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 743         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 744
 745         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 746
 747         kvfree(in);
 748
 749         return err;
 750 }
 751
 752 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 753 {
 754         struct mlx5e_channel *c = rq->channel;
 755         struct mlx5_core_dev *mdev = c->mdev;
 756         void *in;
 757         void *rqc;
 758         int inlen;
 759         int err;
 760
 761         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 762         in = kvzalloc(inlen, GFP_KERNEL);
 763         if (!in)
 764                 return -ENOMEM;
 765
 766         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 767
 768         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 769         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 770                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 771         MLX5_SET(rqc, rqc, vsd, vsd);
 772         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 773
 774         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 775
 776         kvfree(in);
 777
 778         return err;
 779 }
 780
 781 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 782 {
 783         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 784 }
 785
 786 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 787 {
 788         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 789         struct mlx5e_channel *c = rq->channel;
 790
 791         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 792
 793         do {
 794                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 795                         return 0;
 796
 797                 msleep(20);
 798         } while (time_before(jiffies, exp_time));
 799
 800         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 801                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 802
 803         mlx5e_reporter_rx_timeout(rq);
 804         return -ETIMEDOUT;
 805 }
 806
 807 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 808 {
 809         struct mlx5_wq_ll *wq;
 810         u16 head;
 811         int i;
 812
 813         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 814                 return;
 815
 816         wq = &rq->mpwqe.wq;
 817         head = wq->head;
 818
 819         /* Outstanding UMR WQEs (in progress) start at wq->head */
 820         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 821                 rq->dealloc_wqe(rq, head);
 822                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 823         }
 824
 825         rq->mpwqe.actual_wq_head = wq->head;
 826         rq->mpwqe.umr_in_progress = 0;
 827         rq->mpwqe.umr_completed = 0;
 828 }
 829
 830 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 831 {
 832         __be16 wqe_ix_be;
 833         u16 wqe_ix;
 834
 835         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 836                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 837
 838                 mlx5e_free_rx_in_progress_descs(rq);
 839
 840                 while (!mlx5_wq_ll_is_empty(wq)) {
 841                         struct mlx5e_rx_wqe_ll *wqe;
 842
 843                         wqe_ix_be = *wq->tail_next;
 844                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 845                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 846                         rq->dealloc_wqe(rq, wqe_ix);
 847                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 848                                        &wqe->next.next_wqe_index);
 849                 }
 850         } else {
 851                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 852
 853                 while (!mlx5_wq_cyc_is_empty(wq)) {
 854                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 855                         rq->dealloc_wqe(rq, wqe_ix);
 856                         mlx5_wq_cyc_pop(wq);
 857                 }
 858         }
 859
 860 }
 861
 862 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 863                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 864                   struct xsk_buff_pool *xsk_pool, struct mlx5e_rq *rq)
 865 {
 866         int err;
 867
 868         err = mlx5e_alloc_rq(c, params, xsk, xsk_pool, param, rq);
 869         if (err)
 870                 return err;
 871
 872         err = mlx5e_create_rq(rq, param);
 873         if (err)
 874                 goto err_free_rq;
 875
 876         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 877         if (err)
 878                 goto err_destroy_rq;
 879
 880         if (mlx5e_is_tls_on(c->priv) && !mlx5_accel_is_ktls_device(c->mdev))
 881                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &c->rq.state); /* must be FPGA */
 882
 883         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 884                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 885
 886         if (params->rx_dim_enabled)
 887                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 888
 889         /* We disable csum_complete when XDP is enabled since
 890          * XDP programs might manipulate packets which will render
 891          * skb->checksum incorrect.
 892          */
 893         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 894                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 895
 896         /* For CQE compression on striding RQ, use stride index provided by
 897          * HW if capability is supported.
 898          */
 899         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 900             MLX5_CAP_GEN(c->mdev, mini_cqe_resp_stride_index))
 901                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &c->rq.state);
 902
 903         return 0;
 904
 905 err_destroy_rq:
 906         mlx5e_destroy_rq(rq);
 907 err_free_rq:
 908         mlx5e_free_rq(rq);
 909
 910         return err;
 911 }
 912
 913 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 914 {
 915         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 916         mlx5e_trigger_irq(&rq->channel->icosq);
 917 }
 918
 919 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 920 {
 921         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 922         synchronize_rcu(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 923 }
 924
 925 void mlx5e_close_rq(struct mlx5e_rq *rq)
 926 {
 927         cancel_work_sync(&rq->dim.work);
 928         cancel_work_sync(&rq->channel->icosq.recover_work);
 929         cancel_work_sync(&rq->recover_work);
 930         mlx5e_destroy_rq(rq);
 931         mlx5e_free_rx_descs(rq);
 932         mlx5e_free_rq(rq);
 933 }
 934
 935 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 936 {
 937         kvfree(sq->db.xdpi_fifo.xi);
 938         kvfree(sq->db.wqe_info);
 939 }
 940
 941 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 942 {
 943         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 944         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 945         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 946
 947         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 948                                       GFP_KERNEL, numa);
 949         if (!xdpi_fifo->xi)
 950                 return -ENOMEM;
 951
 952         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 953         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 954         xdpi_fifo->mask = dsegs_per_wq - 1;
 955
 956         return 0;
 957 }
 958
 959 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 960 {
 961         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 962         int err;
 963
 964         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 965                                         GFP_KERNEL, numa);
 966         if (!sq->db.wqe_info)
 967                 return -ENOMEM;
 968
 969         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 970         if (err) {
 971                 mlx5e_free_xdpsq_db(sq);
 972                 return err;
 973         }
 974
 975         return 0;
 976 }
 977
 978 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 979                              struct mlx5e_params *params,
 980                              struct xsk_buff_pool *xsk_pool,
 981                              struct mlx5e_sq_param *param,
 982                              struct mlx5e_xdpsq *sq,
 983                              bool is_redirect)
 984 {
 985         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 986         struct mlx5_core_dev *mdev = c->mdev;
 987         struct mlx5_wq_cyc *wq = &sq->wq;
 988         int err;
 989
 990         sq->pdev      = c->pdev;
 991         sq->mkey_be   = c->mkey_be;
 992         sq->channel   = c;
 993         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 994         sq->min_inline_mode = params->tx_min_inline_mode;
 995         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 996         sq->xsk_pool  = xsk_pool;
 997
 998         sq->stats = sq->xsk_pool ?
 999                 &c->priv->channel_stats[c->ix].xsksq :
1000                 is_redirect ?
1001                         &c->priv->channel_stats[c->ix].xdpsq :
1002                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1003
1004         param->wq.db_numa_node = cpu_to_node(c->cpu);
1005         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1006         if (err)
1007                 return err;
1008         wq->db = &wq->db[MLX5_SND_DBR];
1009
1010         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1011         if (err)
1012                 goto err_sq_wq_destroy;
1013
1014         return 0;
1015
1016 err_sq_wq_destroy:
1017         mlx5_wq_destroy(&sq->wq_ctrl);
1018
1019         return err;
1020 }
1021
1022 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1023 {
1024         mlx5e_free_xdpsq_db(sq);
1025         mlx5_wq_destroy(&sq->wq_ctrl);
1026 }
1027
1028 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1029 {
1030         kvfree(sq->db.wqe_info);
1031 }
1032
1033 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1034 {
1035         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1036         size_t size;
1037
1038         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1039         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1040         if (!sq->db.wqe_info)
1041                 return -ENOMEM;
1042
1043         return 0;
1044 }
1045
1046 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1047 {
1048         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1049                                               recover_work);
1050
1051         mlx5e_reporter_icosq_cqe_err(sq);
1052 }
1053
1054 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1055                              struct mlx5e_sq_param *param,
1056                              struct mlx5e_icosq *sq)
1057 {
1058         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1059         struct mlx5_core_dev *mdev = c->mdev;
1060         struct mlx5_wq_cyc *wq = &sq->wq;
1061         int err;
1062
1063         sq->channel   = c;
1064         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1065
1066         param->wq.db_numa_node = cpu_to_node(c->cpu);
1067         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1068         if (err)
1069                 return err;
1070         wq->db = &wq->db[MLX5_SND_DBR];
1071
1072         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1073         if (err)
1074                 goto err_sq_wq_destroy;
1075
1076         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1077
1078         return 0;
1079
1080 err_sq_wq_destroy:
1081         mlx5_wq_destroy(&sq->wq_ctrl);
1082
1083         return err;
1084 }
1085
1086 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1087 {
1088         mlx5e_free_icosq_db(sq);
1089         mlx5_wq_destroy(&sq->wq_ctrl);
1090 }
1091
1092 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1093 {
1094         kvfree(sq->db.wqe_info);
1095         kvfree(sq->db.skb_fifo);
1096         kvfree(sq->db.dma_fifo);
1097 }
1098
1099 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1100 {
1101         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1102         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1103
1104         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1105                                                    sizeof(*sq->db.dma_fifo)),
1106                                         GFP_KERNEL, numa);
1107         sq->db.skb_fifo = kvzalloc_node(array_size(df_sz,
1108                                                    sizeof(*sq->db.skb_fifo)),
1109                                         GFP_KERNEL, numa);
1110         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1111                                                    sizeof(*sq->db.wqe_info)),
1112                                         GFP_KERNEL, numa);
1113         if (!sq->db.dma_fifo || !sq->db.skb_fifo || !sq->db.wqe_info) {
1114                 mlx5e_free_txqsq_db(sq);
1115                 return -ENOMEM;
1116         }
1117
1118         sq->dma_fifo_mask = df_sz - 1;
1119         sq->skb_fifo_mask = df_sz - 1;
1120
1121         return 0;
1122 }
1123
1124 static int mlx5e_calc_sq_stop_room(struct mlx5e_txqsq *sq, u8 log_sq_size)
1125 {
1126         int sq_size = 1 << log_sq_size;
1127
1128         sq->stop_room  = mlx5e_tls_get_stop_room(sq);
1129         sq->stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
1130         if (test_bit(MLX5E_SQ_STATE_MPWQE, &sq->state))
1131                 /* A MPWQE can take up to the maximum-sized WQE + all the normal
1132                  * stop room can be taken if a new packet breaks the active
1133                  * MPWQE session and allocates its WQEs right away.
1134                  */
1135                 sq->stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
1136
1137         if (WARN_ON(sq->stop_room >= sq_size)) {
1138                 netdev_err(sq->channel->netdev, "Stop room %hu is bigger than the SQ size %d\n",
1139                            sq->stop_room, sq_size);
1140                 return -ENOSPC;
1141         }
1142
1143         return 0;
1144 }
1145
1146 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1147 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1148                              int txq_ix,
1149                              struct mlx5e_params *params,
1150                              struct mlx5e_sq_param *param,
1151                              struct mlx5e_txqsq *sq,
1152                              int tc)
1153 {
1154         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1155         struct mlx5_core_dev *mdev = c->mdev;
1156         struct mlx5_wq_cyc *wq = &sq->wq;
1157         int err;
1158
1159         sq->pdev      = c->pdev;
1160         sq->tstamp    = c->tstamp;
1161         sq->clock     = &mdev->clock;
1162         sq->mkey_be   = c->mkey_be;
1163         sq->channel   = c;
1164         sq->ch_ix     = c->ix;
1165         sq->txq_ix    = txq_ix;
1166         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1167         sq->min_inline_mode = params->tx_min_inline_mode;
1168         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1169         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1170         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1171         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1172                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1173         if (MLX5_IPSEC_DEV(c->priv->mdev))
1174                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1175         if (mlx5_accel_is_tls_device(c->priv->mdev))
1176                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1177         if (param->is_mpw)
1178                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1179         err = mlx5e_calc_sq_stop_room(sq, params->log_sq_size);
1180         if (err)
1181                 return err;
1182
1183         param->wq.db_numa_node = cpu_to_node(c->cpu);
1184         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1185         if (err)
1186                 return err;
1187         wq->db    = &wq->db[MLX5_SND_DBR];
1188
1189         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1190         if (err)
1191                 goto err_sq_wq_destroy;
1192
1193         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1194         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1195
1196         return 0;
1197
1198 err_sq_wq_destroy:
1199         mlx5_wq_destroy(&sq->wq_ctrl);
1200
1201         return err;
1202 }
1203
1204 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1205 {
1206         mlx5e_free_txqsq_db(sq);
1207         mlx5_wq_destroy(&sq->wq_ctrl);
1208 }
1209
1210 struct mlx5e_create_sq_param {
1211         struct mlx5_wq_ctrl        *wq_ctrl;
1212         u32                         cqn;
1213         u32                         tisn;
1214         u8                          tis_lst_sz;
1215         u8                          min_inline_mode;
1216 };
1217
1218 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1219                            struct mlx5e_sq_param *param,
1220                            struct mlx5e_create_sq_param *csp,
1221                            u32 *sqn)
1222 {
1223         void *in;
1224         void *sqc;
1225         void *wq;
1226         int inlen;
1227         int err;
1228
1229         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1230                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1231         in = kvzalloc(inlen, GFP_KERNEL);
1232         if (!in)
1233                 return -ENOMEM;
1234
1235         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1236         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1237
1238         memcpy(sqc, param->sqc, sizeof(param->sqc));
1239         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1240         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1241         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1242
1243         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1244                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1245
1246         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1247         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1248
1249         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1250         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1251         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1252                                           MLX5_ADAPTER_PAGE_SHIFT);
1253         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1254
1255         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1256                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1257
1258         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1259
1260         kvfree(in);
1261
1262         return err;
1263 }
1264
1265 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1266                     struct mlx5e_modify_sq_param *p)
1267 {
1268         void *in;
1269         void *sqc;
1270         int inlen;
1271         int err;
1272
1273         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1274         in = kvzalloc(inlen, GFP_KERNEL);
1275         if (!in)
1276                 return -ENOMEM;
1277
1278         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1279
1280         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1281         MLX5_SET(sqc, sqc, state, p->next_state);
1282         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1283                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1284                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1285         }
1286
1287         err = mlx5_core_modify_sq(mdev, sqn, in);
1288
1289         kvfree(in);
1290
1291         return err;
1292 }
1293
1294 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1295 {
1296         mlx5_core_destroy_sq(mdev, sqn);
1297 }
1298
1299 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1300                                struct mlx5e_sq_param *param,
1301                                struct mlx5e_create_sq_param *csp,
1302                                u32 *sqn)
1303 {
1304         struct mlx5e_modify_sq_param msp = {0};
1305         int err;
1306
1307         err = mlx5e_create_sq(mdev, param, csp, sqn);
1308         if (err)
1309                 return err;
1310
1311         msp.curr_state = MLX5_SQC_STATE_RST;
1312         msp.next_state = MLX5_SQC_STATE_RDY;
1313         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1314         if (err)
1315                 mlx5e_destroy_sq(mdev, *sqn);
1316
1317         return err;
1318 }
1319
1320 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1321                                 struct mlx5e_txqsq *sq, u32 rate);
1322
1323 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1324                             u32 tisn,
1325                             int txq_ix,
1326                             struct mlx5e_params *params,
1327                             struct mlx5e_sq_param *param,
1328                             struct mlx5e_txqsq *sq,
1329                             int tc)
1330 {
1331         struct mlx5e_create_sq_param csp = {};
1332         u32 tx_rate;
1333         int err;
1334
1335         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1336         if (err)
1337                 return err;
1338
1339         csp.tisn            = tisn;
1340         csp.tis_lst_sz      = 1;
1341         csp.cqn             = sq->cq.mcq.cqn;
1342         csp.wq_ctrl         = &sq->wq_ctrl;
1343         csp.min_inline_mode = sq->min_inline_mode;
1344         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1345         if (err)
1346                 goto err_free_txqsq;
1347
1348         tx_rate = c->priv->tx_rates[sq->txq_ix];
1349         if (tx_rate)
1350                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1351
1352         if (params->tx_dim_enabled)
1353                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1354
1355         return 0;
1356
1357 err_free_txqsq:
1358         mlx5e_free_txqsq(sq);
1359
1360         return err;
1361 }
1362
1363 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1364 {
1365         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1366         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1367         netdev_tx_reset_queue(sq->txq);
1368         netif_tx_start_queue(sq->txq);
1369 }
1370
1371 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1372 {
1373         __netif_tx_lock_bh(txq);
1374         netif_tx_stop_queue(txq);
1375         __netif_tx_unlock_bh(txq);
1376 }
1377
1378 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1379 {
1380         struct mlx5_wq_cyc *wq = &sq->wq;
1381
1382         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1383         synchronize_rcu(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1384
1385         mlx5e_tx_disable_queue(sq->txq);
1386
1387         /* last doorbell out, godspeed .. */
1388         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1389                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1390                 struct mlx5e_tx_wqe *nop;
1391
1392                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1393                         .num_wqebbs = 1,
1394                 };
1395
1396                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1397                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1398         }
1399 }
1400
1401 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1402 {
1403         struct mlx5e_channel *c = sq->channel;
1404         struct mlx5_core_dev *mdev = c->mdev;
1405         struct mlx5_rate_limit rl = {0};
1406
1407         cancel_work_sync(&sq->dim.work);
1408         cancel_work_sync(&sq->recover_work);
1409         mlx5e_destroy_sq(mdev, sq->sqn);
1410         if (sq->rate_limit) {
1411                 rl.rate = sq->rate_limit;
1412                 mlx5_rl_remove_rate(mdev, &rl);
1413         }
1414         mlx5e_free_txqsq_descs(sq);
1415         mlx5e_free_txqsq(sq);
1416 }
1417
1418 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1419 {
1420         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1421                                               recover_work);
1422
1423         mlx5e_reporter_tx_err_cqe(sq);
1424 }
1425
1426 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1427                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1428 {
1429         struct mlx5e_create_sq_param csp = {};
1430         int err;
1431
1432         err = mlx5e_alloc_icosq(c, param, sq);
1433         if (err)
1434                 return err;
1435
1436         csp.cqn             = sq->cq.mcq.cqn;
1437         csp.wq_ctrl         = &sq->wq_ctrl;
1438         csp.min_inline_mode = params->tx_min_inline_mode;
1439         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1440         if (err)
1441                 goto err_free_icosq;
1442
1443         return 0;
1444
1445 err_free_icosq:
1446         mlx5e_free_icosq(sq);
1447
1448         return err;
1449 }
1450
1451 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1452 {
1453         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1454 }
1455
1456 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1457 {
1458         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1459         synchronize_rcu(); /* Sync with NAPI. */
1460 }
1461
1462 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1463 {
1464         struct mlx5e_channel *c = sq->channel;
1465
1466         mlx5e_destroy_sq(c->mdev, sq->sqn);
1467         mlx5e_free_icosq_descs(sq);
1468         mlx5e_free_icosq(sq);
1469 }
1470
1471 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1472                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1473                      struct mlx5e_xdpsq *sq, bool is_redirect)
1474 {
1475         struct mlx5e_create_sq_param csp = {};
1476         int err;
1477
1478         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1479         if (err)
1480                 return err;
1481
1482         csp.tis_lst_sz      = 1;
1483         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1484         csp.cqn             = sq->cq.mcq.cqn;
1485         csp.wq_ctrl         = &sq->wq_ctrl;
1486         csp.min_inline_mode = sq->min_inline_mode;
1487         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1488         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1489         if (err)
1490                 goto err_free_xdpsq;
1491
1492         mlx5e_set_xmit_fp(sq, param->is_mpw);
1493
1494         if (!param->is_mpw) {
1495                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1496                 unsigned int inline_hdr_sz = 0;
1497                 int i;
1498
1499                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1500                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1501                         ds_cnt++;
1502                 }
1503
1504                 /* Pre initialize fixed WQE fields */
1505                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1506                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1507                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1508                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1509                         struct mlx5_wqe_data_seg *dseg;
1510
1511                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1512                                 .num_wqebbs = 1,
1513                                 .num_pkts   = 1,
1514                         };
1515
1516                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1517                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1518
1519                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1520                         dseg->lkey = sq->mkey_be;
1521                 }
1522         }
1523
1524         return 0;
1525
1526 err_free_xdpsq:
1527         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1528         mlx5e_free_xdpsq(sq);
1529
1530         return err;
1531 }
1532
1533 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1534 {
1535         struct mlx5e_channel *c = sq->channel;
1536
1537         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1538         synchronize_rcu(); /* Sync with NAPI. */
1539
1540         mlx5e_destroy_sq(c->mdev, sq->sqn);
1541         mlx5e_free_xdpsq_descs(sq);
1542         mlx5e_free_xdpsq(sq);
1543 }
1544
1545 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1546                                  struct mlx5e_cq_param *param,
1547                                  struct mlx5e_cq *cq)
1548 {
1549         struct mlx5_core_cq *mcq = &cq->mcq;
1550         int eqn_not_used;
1551         unsigned int irqn;
1552         int err;
1553         u32 i;
1554
1555         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1556         if (err)
1557                 return err;
1558
1559         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1560                                &cq->wq_ctrl);
1561         if (err)
1562                 return err;
1563
1564         mcq->cqe_sz     = 64;
1565         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1566         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1567         *mcq->set_ci_db = 0;
1568         *mcq->arm_db    = 0;
1569         mcq->vector     = param->eq_ix;
1570         mcq->comp       = mlx5e_completion_event;
1571         mcq->event      = mlx5e_cq_error_event;
1572         mcq->irqn       = irqn;
1573
1574         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1575                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1576
1577                 cqe->op_own = 0xf1;
1578         }
1579
1580         cq->mdev = mdev;
1581
1582         return 0;
1583 }
1584
1585 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1586                           struct mlx5e_cq_param *param,
1587                           struct mlx5e_cq *cq)
1588 {
1589         struct mlx5_core_dev *mdev = c->priv->mdev;
1590         int err;
1591
1592         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1593         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1594         param->eq_ix   = c->ix;
1595
1596         err = mlx5e_alloc_cq_common(mdev, param, cq);
1597
1598         cq->napi    = &c->napi;
1599         cq->channel = c;
1600
1601         return err;
1602 }
1603
1604 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1605 {
1606         mlx5_wq_destroy(&cq->wq_ctrl);
1607 }
1608
1609 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1610 {
1611         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1612         struct mlx5_core_dev *mdev = cq->mdev;
1613         struct mlx5_core_cq *mcq = &cq->mcq;
1614
1615         void *in;
1616         void *cqc;
1617         int inlen;
1618         unsigned int irqn_not_used;
1619         int eqn;
1620         int err;
1621
1622         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1623         if (err)
1624                 return err;
1625
1626         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1627                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1628         in = kvzalloc(inlen, GFP_KERNEL);
1629         if (!in)
1630                 return -ENOMEM;
1631
1632         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1633
1634         memcpy(cqc, param->cqc, sizeof(param->cqc));
1635
1636         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1637                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1638
1639         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1640         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1641         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1642         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1643                                             MLX5_ADAPTER_PAGE_SHIFT);
1644         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1645
1646         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1647
1648         kvfree(in);
1649
1650         if (err)
1651                 return err;
1652
1653         mlx5e_cq_arm(cq);
1654
1655         return 0;
1656 }
1657
1658 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1659 {
1660         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1661 }
1662
1663 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1664                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1665 {
1666         struct mlx5_core_dev *mdev = c->mdev;
1667         int err;
1668
1669         err = mlx5e_alloc_cq(c, param, cq);
1670         if (err)
1671                 return err;
1672
1673         err = mlx5e_create_cq(cq, param);
1674         if (err)
1675                 goto err_free_cq;
1676
1677         if (MLX5_CAP_GEN(mdev, cq_moderation))
1678                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1679         return 0;
1680
1681 err_free_cq:
1682         mlx5e_free_cq(cq);
1683
1684         return err;
1685 }
1686
1687 void mlx5e_close_cq(struct mlx5e_cq *cq)
1688 {
1689         mlx5e_destroy_cq(cq);
1690         mlx5e_free_cq(cq);
1691 }
1692
1693 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1694                              struct mlx5e_params *params,
1695                              struct mlx5e_channel_param *cparam)
1696 {
1697         int err;
1698         int tc;
1699
1700         for (tc = 0; tc < c->num_tc; tc++) {
1701                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1702                                     &cparam->txq_sq.cqp, &c->sq[tc].cq);
1703                 if (err)
1704                         goto err_close_tx_cqs;
1705         }
1706
1707         return 0;
1708
1709 err_close_tx_cqs:
1710         for (tc--; tc >= 0; tc--)
1711                 mlx5e_close_cq(&c->sq[tc].cq);
1712
1713         return err;
1714 }
1715
1716 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1717 {
1718         int tc;
1719
1720         for (tc = 0; tc < c->num_tc; tc++)
1721                 mlx5e_close_cq(&c->sq[tc].cq);
1722 }
1723
1724 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1725                           struct mlx5e_params *params,
1726                           struct mlx5e_channel_param *cparam)
1727 {
1728         int err, tc;
1729
1730         for (tc = 0; tc < params->num_tc; tc++) {
1731                 int txq_ix = c->ix + tc * params->num_channels;
1732
1733                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1734                                        params, &cparam->txq_sq, &c->sq[tc], tc);
1735                 if (err)
1736                         goto err_close_sqs;
1737         }
1738
1739         return 0;
1740
1741 err_close_sqs:
1742         for (tc--; tc >= 0; tc--)
1743                 mlx5e_close_txqsq(&c->sq[tc]);
1744
1745         return err;
1746 }
1747
1748 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1749 {
1750         int tc;
1751
1752         for (tc = 0; tc < c->num_tc; tc++)
1753                 mlx5e_close_txqsq(&c->sq[tc]);
1754 }
1755
1756 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1757                                 struct mlx5e_txqsq *sq, u32 rate)
1758 {
1759         struct mlx5e_priv *priv = netdev_priv(dev);
1760         struct mlx5_core_dev *mdev = priv->mdev;
1761         struct mlx5e_modify_sq_param msp = {0};
1762         struct mlx5_rate_limit rl = {0};
1763         u16 rl_index = 0;
1764         int err;
1765
1766         if (rate == sq->rate_limit)
1767                 /* nothing to do */
1768                 return 0;
1769
1770         if (sq->rate_limit) {
1771                 rl.rate = sq->rate_limit;
1772                 /* remove current rl index to free space to next ones */
1773                 mlx5_rl_remove_rate(mdev, &rl);
1774         }
1775
1776         sq->rate_limit = 0;
1777
1778         if (rate) {
1779                 rl.rate = rate;
1780                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1781                 if (err) {
1782                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1783                                    rate, err);
1784                         return err;
1785                 }
1786         }
1787
1788         msp.curr_state = MLX5_SQC_STATE_RDY;
1789         msp.next_state = MLX5_SQC_STATE_RDY;
1790         msp.rl_index   = rl_index;
1791         msp.rl_update  = true;
1792         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1793         if (err) {
1794                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1795                            rate, err);
1796                 /* remove the rate from the table */
1797                 if (rate)
1798                         mlx5_rl_remove_rate(mdev, &rl);
1799                 return err;
1800         }
1801
1802         sq->rate_limit = rate;
1803         return 0;
1804 }
1805
1806 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1807 {
1808         struct mlx5e_priv *priv = netdev_priv(dev);
1809         struct mlx5_core_dev *mdev = priv->mdev;
1810         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1811         int err = 0;
1812
1813         if (!mlx5_rl_is_supported(mdev)) {
1814                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1815                 return -EINVAL;
1816         }
1817
1818         /* rate is given in Mb/sec, HW config is in Kb/sec */
1819         rate = rate << 10;
1820
1821         /* Check whether rate in valid range, 0 is always valid */
1822         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1823                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1824                 return -ERANGE;
1825         }
1826
1827         mutex_lock(&priv->state_lock);
1828         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1829                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1830         if (!err)
1831                 priv->tx_rates[index] = rate;
1832         mutex_unlock(&priv->state_lock);
1833
1834         return err;
1835 }
1836
1837 static int mlx5e_open_queues(struct mlx5e_channel *c,
1838                              struct mlx5e_params *params,
1839                              struct mlx5e_channel_param *cparam)
1840 {
1841         struct dim_cq_moder icocq_moder = {0, 0};
1842         int err;
1843
1844         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq.cqp, &c->async_icosq.cq);
1845         if (err)
1846                 return err;
1847
1848         err = mlx5e_open_cq(c, icocq_moder, &cparam->async_icosq.cqp, &c->icosq.cq);
1849         if (err)
1850                 goto err_close_async_icosq_cq;
1851
1852         err = mlx5e_open_tx_cqs(c, params, cparam);
1853         if (err)
1854                 goto err_close_icosq_cq;
1855
1856         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &c->xdpsq.cq);
1857         if (err)
1858                 goto err_close_tx_cqs;
1859
1860         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rq.cqp, &c->rq.cq);
1861         if (err)
1862                 goto err_close_xdp_tx_cqs;
1863
1864         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1865                                      &cparam->xdp_sq.cqp, &c->rq_xdpsq.cq) : 0;
1866         if (err)
1867                 goto err_close_rx_cq;
1868
1869         napi_enable(&c->napi);
1870
1871         spin_lock_init(&c->async_icosq_lock);
1872
1873         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1874         if (err)
1875                 goto err_disable_napi;
1876
1877         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1878         if (err)
1879                 goto err_close_async_icosq;
1880
1881         err = mlx5e_open_sqs(c, params, cparam);
1882         if (err)
1883                 goto err_close_icosq;
1884
1885         if (c->xdp) {
1886                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1887                                        &c->rq_xdpsq, false);
1888                 if (err)
1889                         goto err_close_sqs;
1890         }
1891
1892         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1893         if (err)
1894                 goto err_close_xdp_sq;
1895
1896         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1897         if (err)
1898                 goto err_close_rq;
1899
1900         return 0;
1901
1902 err_close_rq:
1903         mlx5e_close_rq(&c->rq);
1904
1905 err_close_xdp_sq:
1906         if (c->xdp)
1907                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1908
1909 err_close_sqs:
1910         mlx5e_close_sqs(c);
1911
1912 err_close_icosq:
1913         mlx5e_close_icosq(&c->icosq);
1914
1915 err_close_async_icosq:
1916         mlx5e_close_icosq(&c->async_icosq);
1917
1918 err_disable_napi:
1919         napi_disable(&c->napi);
1920
1921         if (c->xdp)
1922                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1923
1924 err_close_rx_cq:
1925         mlx5e_close_cq(&c->rq.cq);
1926
1927 err_close_xdp_tx_cqs:
1928         mlx5e_close_cq(&c->xdpsq.cq);
1929
1930 err_close_tx_cqs:
1931         mlx5e_close_tx_cqs(c);
1932
1933 err_close_icosq_cq:
1934         mlx5e_close_cq(&c->icosq.cq);
1935
1936 err_close_async_icosq_cq:
1937         mlx5e_close_cq(&c->async_icosq.cq);
1938
1939         return err;
1940 }
1941
1942 static void mlx5e_close_queues(struct mlx5e_channel *c)
1943 {
1944         mlx5e_close_xdpsq(&c->xdpsq);
1945         mlx5e_close_rq(&c->rq);
1946         if (c->xdp)
1947                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1948         mlx5e_close_sqs(c);
1949         mlx5e_close_icosq(&c->icosq);
1950         mlx5e_close_icosq(&c->async_icosq);
1951         napi_disable(&c->napi);
1952         if (c->xdp)
1953                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1954         mlx5e_close_cq(&c->rq.cq);
1955         mlx5e_close_cq(&c->xdpsq.cq);
1956         mlx5e_close_tx_cqs(c);
1957         mlx5e_close_cq(&c->icosq.cq);
1958         mlx5e_close_cq(&c->async_icosq.cq);
1959 }
1960
1961 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1962 {
1963         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1964
1965         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1966 }
1967
1968 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1969                               struct mlx5e_params *params,
1970                               struct mlx5e_channel_param *cparam,
1971                               struct xsk_buff_pool *xsk_pool,
1972                               struct mlx5e_channel **cp)
1973 {
1974         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1975         struct net_device *netdev = priv->netdev;
1976         struct mlx5e_xsk_param xsk;
1977         struct mlx5e_channel *c;
1978         unsigned int irq;
1979         int err;
1980         int eqn;
1981
1982         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1983         if (err)
1984                 return err;
1985
1986         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1987         if (!c)
1988                 return -ENOMEM;
1989
1990         c->priv     = priv;
1991         c->mdev     = priv->mdev;
1992         c->tstamp   = &priv->tstamp;
1993         c->ix       = ix;
1994         c->cpu      = cpu;
1995         c->pdev     = mlx5_core_dma_dev(priv->mdev);
1996         c->netdev   = priv->netdev;
1997         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1998         c->num_tc   = params->num_tc;
1999         c->xdp      = !!params->xdp_prog;
2000         c->stats    = &priv->channel_stats[ix].ch;
2001         c->irq_desc = irq_to_desc(irq);
2002         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2003
2004         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2005
2006         err = mlx5e_open_queues(c, params, cparam);
2007         if (unlikely(err))
2008                 goto err_napi_del;
2009
2010         if (xsk_pool) {
2011                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2012                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2013                 if (unlikely(err))
2014                         goto err_close_queues;
2015         }
2016
2017         *cp = c;
2018
2019         return 0;
2020
2021 err_close_queues:
2022         mlx5e_close_queues(c);
2023
2024 err_napi_del:
2025         netif_napi_del(&c->napi);
2026
2027         kvfree(c);
2028
2029         return err;
2030 }
2031
2032 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2033 {
2034         int tc;
2035
2036         for (tc = 0; tc < c->num_tc; tc++)
2037                 mlx5e_activate_txqsq(&c->sq[tc]);
2038         mlx5e_activate_icosq(&c->icosq);
2039         mlx5e_activate_icosq(&c->async_icosq);
2040         mlx5e_activate_rq(&c->rq);
2041
2042         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2043                 mlx5e_activate_xsk(c);
2044 }
2045
2046 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2047 {
2048         int tc;
2049
2050         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2051                 mlx5e_deactivate_xsk(c);
2052
2053         mlx5e_deactivate_rq(&c->rq);
2054         mlx5e_deactivate_icosq(&c->async_icosq);
2055         mlx5e_deactivate_icosq(&c->icosq);
2056         for (tc = 0; tc < c->num_tc; tc++)
2057                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2058 }
2059
2060 static void mlx5e_close_channel(struct mlx5e_channel *c)
2061 {
2062         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2063                 mlx5e_close_xsk(c);
2064         mlx5e_close_queues(c);
2065         netif_napi_del(&c->napi);
2066
2067         kvfree(c);
2068 }
2069
2070 #define DEFAULT_FRAG_SIZE (2048)
2071
2072 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2073                                       struct mlx5e_params *params,
2074                                       struct mlx5e_xsk_param *xsk,
2075                                       struct mlx5e_rq_frags_info *info)
2076 {
2077         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2078         int frag_size_max = DEFAULT_FRAG_SIZE;
2079         u32 buf_size = 0;
2080         int i;
2081
2082 #ifdef CONFIG_MLX5_EN_IPSEC
2083         if (MLX5_IPSEC_DEV(mdev))
2084                 byte_count += MLX5E_METADATA_ETHER_LEN;
2085 #endif
2086
2087         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2088                 int frag_stride;
2089
2090                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2091                 frag_stride = roundup_pow_of_two(frag_stride);
2092
2093                 info->arr[0].frag_size = byte_count;
2094                 info->arr[0].frag_stride = frag_stride;
2095                 info->num_frags = 1;
2096                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2097                 goto out;
2098         }
2099
2100         if (byte_count > PAGE_SIZE +
2101             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2102                 frag_size_max = PAGE_SIZE;
2103
2104         i = 0;
2105         while (buf_size < byte_count) {
2106                 int frag_size = byte_count - buf_size;
2107
2108                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2109                         frag_size = min(frag_size, frag_size_max);
2110
2111                 info->arr[i].frag_size = frag_size;
2112                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2113
2114                 buf_size += frag_size;
2115                 i++;
2116         }
2117         info->num_frags = i;
2118         /* number of different wqes sharing a page */
2119         info->wqe_bulk = 1 + (info->num_frags % 2);
2120
2121 out:
2122         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2123         info->log_num_frags = order_base_2(info->num_frags);
2124 }
2125
2126 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2127 {
2128         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2129
2130         switch (wq_type) {
2131         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2132                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2133                 break;
2134         default: /* MLX5_WQ_TYPE_CYCLIC */
2135                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2136         }
2137
2138         return order_base_2(sz);
2139 }
2140
2141 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2142 {
2143         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2144
2145         return MLX5_GET(wq, wq, log_wq_sz);
2146 }
2147
2148 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2149                           struct mlx5e_params *params,
2150                           struct mlx5e_xsk_param *xsk,
2151                           struct mlx5e_rq_param *param)
2152 {
2153         struct mlx5_core_dev *mdev = priv->mdev;
2154         void *rqc = param->rqc;
2155         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2156         int ndsegs = 1;
2157
2158         switch (params->rq_wq_type) {
2159         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2160                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2161                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2162                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2163                 MLX5_SET(wq, wq, log_wqe_stride_size,
2164                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2165                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2166                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2167                 break;
2168         default: /* MLX5_WQ_TYPE_CYCLIC */
2169                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2170                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2171                 ndsegs = param->frags_info.num_frags;
2172         }
2173
2174         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2175         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2176         MLX5_SET(wq, wq, log_wq_stride,
2177                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2178         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2179         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2180         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2181         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2182
2183         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2184         mlx5e_build_rx_cq_param(priv, params, xsk, &param->cqp);
2185 }
2186
2187 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2188                                       struct mlx5e_rq_param *param)
2189 {
2190         struct mlx5_core_dev *mdev = priv->mdev;
2191         void *rqc = param->rqc;
2192         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2193
2194         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2195         MLX5_SET(wq, wq, log_wq_stride,
2196                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2197         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2198
2199         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2200 }
2201
2202 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2203                                  struct mlx5e_sq_param *param)
2204 {
2205         void *sqc = param->sqc;
2206         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2207
2208         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2209         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2210
2211         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(priv->mdev));
2212 }
2213
2214 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2215                                  struct mlx5e_params *params,
2216                                  struct mlx5e_sq_param *param)
2217 {
2218         void *sqc = param->sqc;
2219         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2220         bool allow_swp;
2221
2222         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2223                     !!MLX5_IPSEC_DEV(priv->mdev);
2224         mlx5e_build_sq_param_common(priv, param);
2225         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2226         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2227         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE);
2228         mlx5e_build_tx_cq_param(priv, params, &param->cqp);
2229 }
2230
2231 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2232                                         struct mlx5e_cq_param *param)
2233 {
2234         void *cqc = param->cqc;
2235
2236         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2237         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2238                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2239 }
2240
2241 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2242                              struct mlx5e_params *params,
2243                              struct mlx5e_xsk_param *xsk,
2244                              struct mlx5e_cq_param *param)
2245 {
2246         struct mlx5_core_dev *mdev = priv->mdev;
2247         bool hw_stridx = false;
2248         void *cqc = param->cqc;
2249         u8 log_cq_size;
2250
2251         switch (params->rq_wq_type) {
2252         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2253                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2254                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2255                 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index);
2256                 break;
2257         default: /* MLX5_WQ_TYPE_CYCLIC */
2258                 log_cq_size = params->log_rq_mtu_frames;
2259         }
2260
2261         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2262         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2263                 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ?
2264                          MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM);
2265                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2266         }
2267
2268         mlx5e_build_common_cq_param(priv, param);
2269         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2270 }
2271
2272 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2273                              struct mlx5e_params *params,
2274                              struct mlx5e_cq_param *param)
2275 {
2276         void *cqc = param->cqc;
2277
2278         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2279
2280         mlx5e_build_common_cq_param(priv, param);
2281         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2282 }
2283
2284 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2285                               u8 log_wq_size,
2286                               struct mlx5e_cq_param *param)
2287 {
2288         void *cqc = param->cqc;
2289
2290         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2291
2292         mlx5e_build_common_cq_param(priv, param);
2293
2294         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2295 }
2296
2297 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2298                              u8 log_wq_size,
2299                              struct mlx5e_sq_param *param)
2300 {
2301         void *sqc = param->sqc;
2302         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2303
2304         mlx5e_build_sq_param_common(priv, param);
2305
2306         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2307         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2308         mlx5e_build_ico_cq_param(priv, log_wq_size, &param->cqp);
2309 }
2310
2311 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2312                              struct mlx5e_params *params,
2313                              struct mlx5e_sq_param *param)
2314 {
2315         void *sqc = param->sqc;
2316         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2317
2318         mlx5e_build_sq_param_common(priv, param);
2319         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2320         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2321         mlx5e_build_tx_cq_param(priv, params, &param->cqp);
2322 }
2323
2324 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2325                                       struct mlx5e_rq_param *rqp)
2326 {
2327         switch (params->rq_wq_type) {
2328         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2329                 return order_base_2(MLX5E_UMR_WQEBBS) +
2330                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2331         default: /* MLX5_WQ_TYPE_CYCLIC */
2332                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2333         }
2334 }
2335
2336 static u8 mlx5e_build_async_icosq_log_wq_sz(struct net_device *netdev)
2337 {
2338         if (netdev->hw_features & NETIF_F_HW_TLS_RX)
2339                 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2340
2341         return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2342 }
2343
2344 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2345                                       struct mlx5e_params *params,
2346                                       struct mlx5e_channel_param *cparam)
2347 {
2348         u8 icosq_log_wq_sz, async_icosq_log_wq_sz;
2349
2350         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2351
2352         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2353         async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(priv->netdev);
2354
2355         mlx5e_build_sq_param(priv, params, &cparam->txq_sq);
2356         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2357         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2358         mlx5e_build_icosq_param(priv, async_icosq_log_wq_sz, &cparam->async_icosq);
2359 }
2360
2361 int mlx5e_open_channels(struct mlx5e_priv *priv,
2362                         struct mlx5e_channels *chs)
2363 {
2364         struct mlx5e_channel_param *cparam;
2365         int err = -ENOMEM;
2366         int i;
2367
2368         chs->num = chs->params.num_channels;
2369
2370         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2371         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2372         if (!chs->c || !cparam)
2373                 goto err_free;
2374
2375         mlx5e_build_channel_param(priv, &chs->params, cparam);
2376         for (i = 0; i < chs->num; i++) {
2377                 struct xsk_buff_pool *xsk_pool = NULL;
2378
2379                 if (chs->params.xdp_prog)
2380                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2381
2382                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2383                 if (err)
2384                         goto err_close_channels;
2385         }
2386
2387         mlx5e_health_channels_update(priv);
2388         kvfree(cparam);
2389         return 0;
2390
2391 err_close_channels:
2392         for (i--; i >= 0; i--)
2393                 mlx5e_close_channel(chs->c[i]);
2394
2395 err_free:
2396         kfree(chs->c);
2397         kvfree(cparam);
2398         chs->num = 0;
2399         return err;
2400 }
2401
2402 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2403 {
2404         int i;
2405
2406         for (i = 0; i < chs->num; i++)
2407                 mlx5e_activate_channel(chs->c[i]);
2408 }
2409
2410 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2411
2412 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2413 {
2414         int err = 0;
2415         int i;
2416
2417         for (i = 0; i < chs->num; i++) {
2418                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2419
2420                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2421
2422                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2423                  * doesn't provide any Fill Ring entries at the setup stage.
2424                  */
2425         }
2426
2427         return err ? -ETIMEDOUT : 0;
2428 }
2429
2430 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2431 {
2432         int i;
2433
2434         for (i = 0; i < chs->num; i++)
2435                 mlx5e_deactivate_channel(chs->c[i]);
2436 }
2437
2438 void mlx5e_close_channels(struct mlx5e_channels *chs)
2439 {
2440         int i;
2441
2442         for (i = 0; i < chs->num; i++)
2443                 mlx5e_close_channel(chs->c[i]);
2444
2445         kfree(chs->c);
2446         chs->num = 0;
2447 }
2448
2449 static int
2450 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2451 {
2452         struct mlx5_core_dev *mdev = priv->mdev;
2453         void *rqtc;
2454         int inlen;
2455         int err;
2456         u32 *in;
2457         int i;
2458
2459         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2460         in = kvzalloc(inlen, GFP_KERNEL);
2461         if (!in)
2462                 return -ENOMEM;
2463
2464         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2465
2466         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2467         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2468
2469         for (i = 0; i < sz; i++)
2470                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2471
2472         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2473         if (!err)
2474                 rqt->enabled = true;
2475
2476         kvfree(in);
2477         return err;
2478 }
2479
2480 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2481 {
2482         rqt->enabled = false;
2483         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2484 }
2485
2486 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2487 {
2488         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2489         int err;
2490
2491         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2492         if (err)
2493                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2494         return err;
2495 }
2496
2497 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2498 {
2499         int err;
2500         int ix;
2501
2502         for (ix = 0; ix < priv->max_nch; ix++) {
2503                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2504                 if (unlikely(err))
2505                         goto err_destroy_rqts;
2506         }
2507
2508         return 0;
2509
2510 err_destroy_rqts:
2511         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2512         for (ix--; ix >= 0; ix--)
2513                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2514
2515         return err;
2516 }
2517
2518 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2519 {
2520         int i;
2521
2522         for (i = 0; i < priv->max_nch; i++)
2523                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2524 }
2525
2526 static int mlx5e_rx_hash_fn(int hfunc)
2527 {
2528         return (hfunc == ETH_RSS_HASH_TOP) ?
2529                MLX5_RX_HASH_FN_TOEPLITZ :
2530                MLX5_RX_HASH_FN_INVERTED_XOR8;
2531 }
2532
2533 int mlx5e_bits_invert(unsigned long a, int size)
2534 {
2535         int inv = 0;
2536         int i;
2537
2538         for (i = 0; i < size; i++)
2539                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2540
2541         return inv;
2542 }
2543
2544 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2545                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2546 {
2547         int i;
2548
2549         for (i = 0; i < sz; i++) {
2550                 u32 rqn;
2551
2552                 if (rrp.is_rss) {
2553                         int ix = i;
2554
2555                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2556                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2557
2558                         ix = priv->rss_params.indirection_rqt[ix];
2559                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2560                 } else {
2561                         rqn = rrp.rqn;
2562                 }
2563                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2564         }
2565 }
2566
2567 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2568                        struct mlx5e_redirect_rqt_param rrp)
2569 {
2570         struct mlx5_core_dev *mdev = priv->mdev;
2571         void *rqtc;
2572         int inlen;
2573         u32 *in;
2574         int err;
2575
2576         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2577         in = kvzalloc(inlen, GFP_KERNEL);
2578         if (!in)
2579                 return -ENOMEM;
2580
2581         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2582
2583         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2584         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2585         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2586         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2587
2588         kvfree(in);
2589         return err;
2590 }
2591
2592 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2593                                 struct mlx5e_redirect_rqt_param rrp)
2594 {
2595         if (!rrp.is_rss)
2596                 return rrp.rqn;
2597
2598         if (ix >= rrp.rss.channels->num)
2599                 return priv->drop_rq.rqn;
2600
2601         return rrp.rss.channels->c[ix]->rq.rqn;
2602 }
2603
2604 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2605                                 struct mlx5e_redirect_rqt_param rrp)
2606 {
2607         u32 rqtn;
2608         int ix;
2609
2610         if (priv->indir_rqt.enabled) {
2611                 /* RSS RQ table */
2612                 rqtn = priv->indir_rqt.rqtn;
2613                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2614         }
2615
2616         for (ix = 0; ix < priv->max_nch; ix++) {
2617                 struct mlx5e_redirect_rqt_param direct_rrp = {
2618                         .is_rss = false,
2619                         {
2620                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2621                         },
2622                 };
2623
2624                 /* Direct RQ Tables */
2625                 if (!priv->direct_tir[ix].rqt.enabled)
2626                         continue;
2627
2628                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2629                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2630         }
2631 }
2632
2633 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2634                                             struct mlx5e_channels *chs)
2635 {
2636         struct mlx5e_redirect_rqt_param rrp = {
2637                 .is_rss        = true,
2638                 {
2639                         .rss = {
2640                                 .channels  = chs,
2641                                 .hfunc     = priv->rss_params.hfunc,
2642                         }
2643                 },
2644         };
2645
2646         mlx5e_redirect_rqts(priv, rrp);
2647 }
2648
2649 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2650 {
2651         struct mlx5e_redirect_rqt_param drop_rrp = {
2652                 .is_rss = false,
2653                 {
2654                         .rqn = priv->drop_rq.rqn,
2655                 },
2656         };
2657
2658         mlx5e_redirect_rqts(priv, drop_rrp);
2659 }
2660
2661 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2662         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2663                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2664                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2665         },
2666         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2667                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2668                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2669         },
2670         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2671                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2672                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2673         },
2674         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2675                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2676                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2677         },
2678         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2679                                      .l4_prot_type = 0,
2680                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2681         },
2682         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2683                                      .l4_prot_type = 0,
2684                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2685         },
2686         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2687                                       .l4_prot_type = 0,
2688                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2689         },
2690         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2691                                       .l4_prot_type = 0,
2692                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2693         },
2694         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2695                             .l4_prot_type = 0,
2696                             .rx_hash_fields = MLX5_HASH_IP,
2697         },
2698         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2699                             .l4_prot_type = 0,
2700                             .rx_hash_fields = MLX5_HASH_IP,
2701         },
2702 };
2703
2704 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2705 {
2706         return tirc_default_config[tt];
2707 }
2708
2709 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2710 {
2711         if (!params->lro_en)
2712                 return;
2713
2714 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2715
2716         MLX5_SET(tirc, tirc, lro_enable_mask,
2717                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2718                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2719         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2720                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2721         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2722 }
2723
2724 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2725                                     const struct mlx5e_tirc_config *ttconfig,
2726                                     void *tirc, bool inner)
2727 {
2728         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2729                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2730
2731         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2732         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2733                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2734                                              rx_hash_toeplitz_key);
2735                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2736                                                rx_hash_toeplitz_key);
2737
2738                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2739                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2740         }
2741         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2742                  ttconfig->l3_prot_type);
2743         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2744                  ttconfig->l4_prot_type);
2745         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2746                  ttconfig->rx_hash_fields);
2747 }
2748
2749 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2750                                         enum mlx5e_traffic_types tt,
2751                                         u32 rx_hash_fields)
2752 {
2753         *ttconfig                = tirc_default_config[tt];
2754         ttconfig->rx_hash_fields = rx_hash_fields;
2755 }
2756
2757 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2758 {
2759         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2760         struct mlx5e_rss_params *rss = &priv->rss_params;
2761         struct mlx5_core_dev *mdev = priv->mdev;
2762         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2763         struct mlx5e_tirc_config ttconfig;
2764         int tt;
2765
2766         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2767
2768         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2769                 memset(tirc, 0, ctxlen);
2770                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2771                                             rss->rx_hash_fields[tt]);
2772                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2773                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2774         }
2775
2776         /* Verify inner tirs resources allocated */
2777         if (!priv->inner_indir_tir[0].tirn)
2778                 return;
2779
2780         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2781                 memset(tirc, 0, ctxlen);
2782                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2783                                             rss->rx_hash_fields[tt]);
2784                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2785                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2786         }
2787 }
2788
2789 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2790 {
2791         struct mlx5_core_dev *mdev = priv->mdev;
2792
2793         void *in;
2794         void *tirc;
2795         int inlen;
2796         int err;
2797         int tt;
2798         int ix;
2799
2800         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2801         in = kvzalloc(inlen, GFP_KERNEL);
2802         if (!in)
2803                 return -ENOMEM;
2804
2805         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2806         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2807
2808         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2809
2810         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2811                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2812                 if (err)
2813                         goto free_in;
2814         }
2815
2816         for (ix = 0; ix < priv->max_nch; ix++) {
2817                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2818                 if (err)
2819                         goto free_in;
2820         }
2821
2822 free_in:
2823         kvfree(in);
2824
2825         return err;
2826 }
2827
2828 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2829
2830 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2831                          struct mlx5e_params *params, u16 mtu)
2832 {
2833         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2834         int err;
2835
2836         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2837         if (err)
2838                 return err;
2839
2840         /* Update vport context MTU */
2841         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2842         return 0;
2843 }
2844
2845 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2846                             struct mlx5e_params *params, u16 *mtu)
2847 {
2848         u16 hw_mtu = 0;
2849         int err;
2850
2851         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2852         if (err || !hw_mtu) /* fallback to port oper mtu */
2853                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2854
2855         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2856 }
2857
2858 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2859 {
2860         struct mlx5e_params *params = &priv->channels.params;
2861         struct net_device *netdev = priv->netdev;
2862         struct mlx5_core_dev *mdev = priv->mdev;
2863         u16 mtu;
2864         int err;
2865
2866         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2867         if (err)
2868                 return err;
2869
2870         mlx5e_query_mtu(mdev, params, &mtu);
2871         if (mtu != params->sw_mtu)
2872                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2873                             __func__, mtu, params->sw_mtu);
2874
2875         params->sw_mtu = mtu;
2876         return 0;
2877 }
2878
2879 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2880
2881 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2882 {
2883         struct mlx5e_params *params = &priv->channels.params;
2884         struct net_device *netdev   = priv->netdev;
2885         struct mlx5_core_dev *mdev  = priv->mdev;
2886         u16 max_mtu;
2887
2888         /* MTU range: 68 - hw-specific max */
2889         netdev->min_mtu = ETH_MIN_MTU;
2890
2891         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2892         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2893                                 ETH_MAX_MTU);
2894 }
2895
2896 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2897 {
2898         int tc;
2899
2900         netdev_reset_tc(netdev);
2901
2902         if (ntc == 1)
2903                 return;
2904
2905         netdev_set_num_tc(netdev, ntc);
2906
2907         /* Map netdev TCs to offset 0
2908          * We have our own UP to TXQ mapping for QoS
2909          */
2910         for (tc = 0; tc < ntc; tc++)
2911                 netdev_set_tc_queue(netdev, tc, nch, 0);
2912 }
2913
2914 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2915 {
2916         struct net_device *netdev = priv->netdev;
2917         int num_txqs, num_rxqs, nch, ntc;
2918         int old_num_txqs, old_ntc;
2919         int err;
2920
2921         old_num_txqs = netdev->real_num_tx_queues;
2922         old_ntc = netdev->num_tc;
2923
2924         nch = priv->channels.params.num_channels;
2925         ntc = priv->channels.params.num_tc;
2926         num_txqs = nch * ntc;
2927         num_rxqs = nch * priv->profile->rq_groups;
2928
2929         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2930
2931         err = netif_set_real_num_tx_queues(netdev, num_txqs);
2932         if (err) {
2933                 netdev_warn(netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2934                 goto err_tcs;
2935         }
2936         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2937         if (err) {
2938                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2939                 goto err_txqs;
2940         }
2941
2942         return 0;
2943
2944 err_txqs:
2945         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2946          * one of nch and ntc is changed in this function. That means, the call
2947          * to netif_set_real_num_tx_queues below should not fail, because it
2948          * decreases the number of TX queues.
2949          */
2950         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2951
2952 err_tcs:
2953         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2954         return err;
2955 }
2956
2957 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2958                                            struct mlx5e_params *params)
2959 {
2960         struct mlx5_core_dev *mdev = priv->mdev;
2961         int num_comp_vectors, ix, irq;
2962
2963         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2964
2965         for (ix = 0; ix < params->num_channels; ix++) {
2966                 cpumask_clear(priv->scratchpad.cpumask);
2967
2968                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2969                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2970
2971                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2972                 }
2973
2974                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2975         }
2976 }
2977
2978 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2979 {
2980         u16 count = priv->channels.params.num_channels;
2981         int err;
2982
2983         err = mlx5e_update_netdev_queues(priv);
2984         if (err)
2985                 return err;
2986
2987         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2988
2989         if (!netif_is_rxfh_configured(priv->netdev))
2990                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2991                                               MLX5E_INDIR_RQT_SIZE, count);
2992
2993         return 0;
2994 }
2995
2996 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2997
2998 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2999 {
3000         int i, ch;
3001
3002         ch = priv->channels.num;
3003
3004         for (i = 0; i < ch; i++) {
3005                 int tc;
3006
3007                 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
3008                         struct mlx5e_channel *c = priv->channels.c[i];
3009                         struct mlx5e_txqsq *sq = &c->sq[tc];
3010
3011                         priv->txq2sq[sq->txq_ix] = sq;
3012                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
3013                 }
3014         }
3015 }
3016
3017 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
3018 {
3019         mlx5e_build_txq_maps(priv);
3020         mlx5e_activate_channels(&priv->channels);
3021         mlx5e_xdp_tx_enable(priv);
3022         netif_tx_start_all_queues(priv->netdev);
3023
3024         if (mlx5e_is_vport_rep(priv))
3025                 mlx5e_add_sqs_fwd_rules(priv);
3026
3027         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
3028         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
3029
3030         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
3031 }
3032
3033 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
3034 {
3035         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
3036
3037         mlx5e_redirect_rqts_to_drop(priv);
3038
3039         if (mlx5e_is_vport_rep(priv))
3040                 mlx5e_remove_sqs_fwd_rules(priv);
3041
3042         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
3043          * polling for inactive tx queues.
3044          */
3045         netif_tx_stop_all_queues(priv->netdev);
3046         netif_tx_disable(priv->netdev);
3047         mlx5e_xdp_tx_disable(priv);
3048         mlx5e_deactivate_channels(&priv->channels);
3049 }
3050
3051 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3052                                       struct mlx5e_channels *new_chs,
3053                                       mlx5e_fp_preactivate preactivate,
3054                                       void *context)
3055 {
3056         struct net_device *netdev = priv->netdev;
3057         struct mlx5e_channels old_chs;
3058         int carrier_ok;
3059         int err = 0;
3060
3061         carrier_ok = netif_carrier_ok(netdev);
3062         netif_carrier_off(netdev);
3063
3064         mlx5e_deactivate_priv_channels(priv);
3065
3066         old_chs = priv->channels;
3067         priv->channels = *new_chs;
3068
3069         /* New channels are ready to roll, call the preactivate hook if needed
3070          * to modify HW settings or update kernel parameters.
3071          */
3072         if (preactivate) {
3073                 err = preactivate(priv, context);
3074                 if (err) {
3075                         priv->channels = old_chs;
3076                         goto out;
3077                 }
3078         }
3079
3080         mlx5e_close_channels(&old_chs);
3081         priv->profile->update_rx(priv);
3082
3083 out:
3084         mlx5e_activate_priv_channels(priv);
3085
3086         /* return carrier back if needed */
3087         if (carrier_ok)
3088                 netif_carrier_on(netdev);
3089
3090         return err;
3091 }
3092
3093 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3094                                struct mlx5e_channels *new_chs,
3095                                mlx5e_fp_preactivate preactivate,
3096                                void *context)
3097 {
3098         int err;
3099
3100         err = mlx5e_open_channels(priv, new_chs);
3101         if (err)
3102                 return err;
3103
3104         err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3105         if (err)
3106                 goto err_close;
3107
3108         return 0;
3109
3110 err_close:
3111         mlx5e_close_channels(new_chs);
3112
3113         return err;
3114 }
3115
3116 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3117 {
3118         struct mlx5e_channels new_channels = {};
3119
3120         new_channels.params = priv->channels.params;
3121         return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
3122 }
3123
3124 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3125 {
3126         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3127         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3128 }
3129
3130 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3131                                      enum mlx5_port_status state)
3132 {
3133         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3134         int vport_admin_state;
3135
3136         mlx5_set_port_admin_status(mdev, state);
3137
3138         if (!MLX5_ESWITCH_MANAGER(mdev) ||  mlx5_eswitch_mode(esw) == MLX5_ESWITCH_OFFLOADS)
3139                 return;
3140
3141         if (state == MLX5_PORT_UP)
3142                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3143         else
3144                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3145
3146         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3147 }
3148
3149 int mlx5e_open_locked(struct net_device *netdev)
3150 {
3151         struct mlx5e_priv *priv = netdev_priv(netdev);
3152         int err;
3153
3154         set_bit(MLX5E_STATE_OPENED, &priv->state);
3155
3156         err = mlx5e_open_channels(priv, &priv->channels);
3157         if (err)
3158                 goto err_clear_state_opened_flag;
3159
3160         priv->profile->update_rx(priv);
3161         mlx5e_activate_priv_channels(priv);
3162         if (priv->profile->update_carrier)
3163                 priv->profile->update_carrier(priv);
3164
3165         mlx5e_queue_update_stats(priv);
3166         return 0;
3167
3168 err_clear_state_opened_flag:
3169         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3170         return err;
3171 }
3172
3173 int mlx5e_open(struct net_device *netdev)
3174 {
3175         struct mlx5e_priv *priv = netdev_priv(netdev);
3176         int err;
3177
3178         mutex_lock(&priv->state_lock);
3179         err = mlx5e_open_locked(netdev);
3180         if (!err)
3181                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3182         mutex_unlock(&priv->state_lock);
3183
3184         return err;
3185 }
3186
3187 int mlx5e_close_locked(struct net_device *netdev)
3188 {
3189         struct mlx5e_priv *priv = netdev_priv(netdev);
3190
3191         /* May already be CLOSED in case a previous configuration operation
3192          * (e.g RX/TX queue size change) that involves close&open failed.
3193          */
3194         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3195                 return 0;
3196
3197         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3198
3199         netif_carrier_off(priv->netdev);
3200         mlx5e_deactivate_priv_channels(priv);
3201         mlx5e_close_channels(&priv->channels);
3202
3203         return 0;
3204 }
3205
3206 int mlx5e_close(struct net_device *netdev)
3207 {
3208         struct mlx5e_priv *priv = netdev_priv(netdev);
3209         int err;
3210
3211         if (!netif_device_present(netdev))
3212                 return -ENODEV;
3213
3214         mutex_lock(&priv->state_lock);
3215         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3216         err = mlx5e_close_locked(netdev);
3217         mutex_unlock(&priv->state_lock);
3218
3219         return err;
3220 }
3221
3222 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3223                                struct mlx5e_rq *rq,
3224                                struct mlx5e_rq_param *param)
3225 {
3226         void *rqc = param->rqc;
3227         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3228         int err;
3229
3230         param->wq.db_numa_node = param->wq.buf_numa_node;
3231
3232         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3233                                  &rq->wq_ctrl);
3234         if (err)
3235                 return err;
3236
3237         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3238         xdp_rxq_info_unused(&rq->xdp_rxq);
3239
3240         rq->mdev = mdev;
3241
3242         return 0;
3243 }
3244
3245 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3246                                struct mlx5e_cq *cq,
3247                                struct mlx5e_cq_param *param)
3248 {
3249         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3250         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3251
3252         return mlx5e_alloc_cq_common(mdev, param, cq);
3253 }
3254
3255 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3256                        struct mlx5e_rq *drop_rq)
3257 {
3258         struct mlx5_core_dev *mdev = priv->mdev;
3259         struct mlx5e_cq_param cq_param = {};
3260         struct mlx5e_rq_param rq_param = {};
3261         struct mlx5e_cq *cq = &drop_rq->cq;
3262         int err;
3263
3264         mlx5e_build_drop_rq_param(priv, &rq_param);
3265
3266         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3267         if (err)
3268                 return err;
3269
3270         err = mlx5e_create_cq(cq, &cq_param);
3271         if (err)
3272                 goto err_free_cq;
3273
3274         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3275         if (err)
3276                 goto err_destroy_cq;
3277
3278         err = mlx5e_create_rq(drop_rq, &rq_param);
3279         if (err)
3280                 goto err_free_rq;
3281
3282         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3283         if (err)
3284                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3285
3286         return 0;
3287
3288 err_free_rq:
3289         mlx5e_free_rq(drop_rq);
3290
3291 err_destroy_cq:
3292         mlx5e_destroy_cq(cq);
3293
3294 err_free_cq:
3295         mlx5e_free_cq(cq);
3296
3297         return err;
3298 }
3299
3300 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3301 {
3302         mlx5e_destroy_rq(drop_rq);
3303         mlx5e_free_rq(drop_rq);
3304         mlx5e_destroy_cq(&drop_rq->cq);
3305         mlx5e_free_cq(&drop_rq->cq);
3306 }
3307
3308 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3309 {
3310         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3311
3312         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3313
3314         if (MLX5_GET(tisc, tisc, tls_en))
3315                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3316
3317         if (mlx5_lag_is_lacp_owner(mdev))
3318                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3319
3320         return mlx5_core_create_tis(mdev, in, tisn);
3321 }
3322
3323 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3324 {
3325         mlx5_core_destroy_tis(mdev, tisn);
3326 }
3327
3328 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3329 {
3330         int tc, i;
3331
3332         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3333                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3334                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3335 }
3336
3337 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3338 {
3339         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3340 }
3341
3342 int mlx5e_create_tises(struct mlx5e_priv *priv)
3343 {
3344         int tc, i;
3345         int err;
3346
3347         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3348                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3349                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3350                         void *tisc;
3351
3352                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3353
3354                         MLX5_SET(tisc, tisc, prio, tc << 1);
3355
3356                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3357                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3358
3359                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3360                         if (err)
3361                                 goto err_close_tises;
3362                 }
3363         }
3364
3365         return 0;
3366
3367 err_close_tises:
3368         for (; i >= 0; i--) {
3369                 for (tc--; tc >= 0; tc--)
3370                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3371                 tc = priv->profile->max_tc;
3372         }
3373
3374         return err;
3375 }
3376
3377 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3378 {
3379         mlx5e_destroy_tises(priv);
3380 }
3381
3382 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3383                                              u32 rqtn, u32 *tirc)
3384 {
3385         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3386         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3387         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3388         MLX5_SET(tirc, tirc, tunneled_offload_en,
3389                  priv->channels.params.tunneled_offload_en);
3390
3391         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3392 }
3393
3394 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3395                                       enum mlx5e_traffic_types tt,
3396                                       u32 *tirc)
3397 {
3398         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3399         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3400                                        &tirc_default_config[tt], tirc, false);
3401 }
3402
3403 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3404 {
3405         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3406         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3407 }
3408
3409 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3410                                             enum mlx5e_traffic_types tt,
3411                                             u32 *tirc)
3412 {
3413         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3414         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3415                                        &tirc_default_config[tt], tirc, true);
3416 }
3417
3418 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3419 {
3420         struct mlx5e_tir *tir;
3421         void *tirc;
3422         int inlen;
3423         int i = 0;
3424         int err;
3425         u32 *in;
3426         int tt;
3427
3428         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3429         in = kvzalloc(inlen, GFP_KERNEL);
3430         if (!in)
3431                 return -ENOMEM;
3432
3433         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3434                 memset(in, 0, inlen);
3435                 tir = &priv->indir_tir[tt];
3436                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3437                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3438                 err = mlx5e_create_tir(priv->mdev, tir, in);
3439                 if (err) {
3440                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3441                         goto err_destroy_inner_tirs;
3442                 }
3443         }
3444
3445         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3446                 goto out;
3447
3448         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3449                 memset(in, 0, inlen);
3450                 tir = &priv->inner_indir_tir[i];
3451                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3452                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3453                 err = mlx5e_create_tir(priv->mdev, tir, in);
3454                 if (err) {
3455                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3456                         goto err_destroy_inner_tirs;
3457                 }
3458         }
3459
3460 out:
3461         kvfree(in);
3462
3463         return 0;
3464
3465 err_destroy_inner_tirs:
3466         for (i--; i >= 0; i--)
3467                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3468
3469         for (tt--; tt >= 0; tt--)
3470                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3471
3472         kvfree(in);
3473
3474         return err;
3475 }
3476
3477 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3478 {
3479         struct mlx5e_tir *tir;
3480         void *tirc;
3481         int inlen;
3482         int err = 0;
3483         u32 *in;
3484         int ix;
3485
3486         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3487         in = kvzalloc(inlen, GFP_KERNEL);
3488         if (!in)
3489                 return -ENOMEM;
3490
3491         for (ix = 0; ix < priv->max_nch; ix++) {
3492                 memset(in, 0, inlen);
3493                 tir = &tirs[ix];
3494                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3495                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3496                 err = mlx5e_create_tir(priv->mdev, tir, in);
3497                 if (unlikely(err))
3498                         goto err_destroy_ch_tirs;
3499         }
3500
3501         goto out;
3502
3503 err_destroy_ch_tirs:
3504         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3505         for (ix--; ix >= 0; ix--)
3506                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3507
3508 out:
3509         kvfree(in);
3510
3511         return err;
3512 }
3513
3514 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3515 {
3516         int i;
3517
3518         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3519                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3520
3521         /* Verify inner tirs resources allocated */
3522         if (!priv->inner_indir_tir[0].tirn)
3523                 return;
3524
3525         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3526                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3527 }
3528
3529 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3530 {
3531         int i;
3532
3533         for (i = 0; i < priv->max_nch; i++)
3534                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3535 }
3536
3537 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3538 {
3539         int err = 0;
3540         int i;
3541
3542         for (i = 0; i < chs->num; i++) {
3543                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3544                 if (err)
3545                         return err;
3546         }
3547
3548         return 0;
3549 }
3550
3551 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3552 {
3553         int err = 0;
3554         int i;
3555
3556         for (i = 0; i < chs->num; i++) {
3557                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3558                 if (err)
3559                         return err;
3560         }
3561
3562         return 0;
3563 }
3564
3565 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3566                                  struct tc_mqprio_qopt *mqprio)
3567 {
3568         struct mlx5e_channels new_channels = {};
3569         u8 tc = mqprio->num_tc;
3570         int err = 0;
3571
3572         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3573
3574         if (tc && tc != MLX5E_MAX_NUM_TC)
3575                 return -EINVAL;
3576
3577         mutex_lock(&priv->state_lock);
3578
3579         new_channels.params = priv->channels.params;
3580         new_channels.params.num_tc = tc ? tc : 1;
3581
3582         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3583                 priv->channels.params = new_channels.params;
3584                 goto out;
3585         }
3586
3587         err = mlx5e_safe_switch_channels(priv, &new_channels,
3588                                          mlx5e_num_channels_changed_ctx, NULL);
3589         if (err)
3590                 goto out;
3591
3592         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3593                                     new_channels.params.num_tc);
3594 out:
3595         mutex_unlock(&priv->state_lock);
3596         return err;
3597 }
3598
3599 static LIST_HEAD(mlx5e_block_cb_list);
3600
3601 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3602                           void *type_data)
3603 {
3604         struct mlx5e_priv *priv = netdev_priv(dev);
3605
3606         switch (type) {
3607         case TC_SETUP_BLOCK: {
3608                 struct flow_block_offload *f = type_data;
3609
3610                 f->unlocked_driver_cb = true;
3611                 return flow_block_cb_setup_simple(type_data,
3612                                                   &mlx5e_block_cb_list,
3613                                                   mlx5e_setup_tc_block_cb,
3614                                                   priv, priv, true);
3615         }
3616         case TC_SETUP_QDISC_MQPRIO:
3617                 return mlx5e_setup_tc_mqprio(priv, type_data);
3618         default:
3619                 return -EOPNOTSUPP;
3620         }
3621 }
3622
3623 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3624 {
3625         int i;
3626
3627         for (i = 0; i < priv->max_nch; i++) {
3628                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3629                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3630                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3631                 int j;
3632
3633                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3634                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3635                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3636
3637                 for (j = 0; j < priv->max_opened_tc; j++) {
3638                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3639
3640                         s->tx_packets    += sq_stats->packets;
3641                         s->tx_bytes      += sq_stats->bytes;
3642                         s->tx_dropped    += sq_stats->dropped;
3643                 }
3644         }
3645 }
3646
3647 void
3648 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3649 {
3650         struct mlx5e_priv *priv = netdev_priv(dev);
3651         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3652
3653         /* In switchdev mode, monitor counters doesn't monitor
3654          * rx/tx stats of 802_3. The update stats mechanism
3655          * should keep the 802_3 layout counters updated
3656          */
3657         if (!mlx5e_monitor_counter_supported(priv) ||
3658             mlx5e_is_uplink_rep(priv)) {
3659                 /* update HW stats in background for next time */
3660                 mlx5e_queue_update_stats(priv);
3661         }
3662
3663         if (mlx5e_is_uplink_rep(priv)) {
3664                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3665                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3666                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3667                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3668         } else {
3669                 mlx5e_fold_sw_stats64(priv, stats);
3670         }
3671
3672         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3673
3674         stats->rx_length_errors =
3675                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3676                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3677                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3678         stats->rx_crc_errors =
3679                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3680         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3681         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3682         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3683                            stats->rx_frame_errors;
3684         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3685 }
3686
3687 static void mlx5e_set_rx_mode(struct net_device *dev)
3688 {
3689         struct mlx5e_priv *priv = netdev_priv(dev);
3690
3691         queue_work(priv->wq, &priv->set_rx_mode_work);
3692 }
3693
3694 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3695 {
3696         struct mlx5e_priv *priv = netdev_priv(netdev);
3697         struct sockaddr *saddr = addr;
3698
3699         if (!is_valid_ether_addr(saddr->sa_data))
3700                 return -EADDRNOTAVAIL;
3701
3702         netif_addr_lock_bh(netdev);
3703         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3704         netif_addr_unlock_bh(netdev);
3705
3706         queue_work(priv->wq, &priv->set_rx_mode_work);
3707
3708         return 0;
3709 }
3710
3711 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3712         do {                                            \
3713                 if (enable)                             \
3714                         *features |= feature;           \
3715                 else                                    \
3716                         *features &= ~feature;          \
3717         } while (0)
3718
3719 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3720
3721 static int set_feature_lro(struct net_device *netdev, bool enable)
3722 {
3723         struct mlx5e_priv *priv = netdev_priv(netdev);
3724         struct mlx5_core_dev *mdev = priv->mdev;
3725         struct mlx5e_channels new_channels = {};
3726         struct mlx5e_params *old_params;
3727         int err = 0;
3728         bool reset;
3729
3730         mutex_lock(&priv->state_lock);
3731
3732         if (enable && priv->xsk.refcnt) {
3733                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3734                             priv->xsk.refcnt);
3735                 err = -EINVAL;
3736                 goto out;
3737         }
3738
3739         old_params = &priv->channels.params;
3740         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3741                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3742                 err = -EINVAL;
3743                 goto out;
3744         }
3745
3746         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3747
3748         new_channels.params = *old_params;
3749         new_channels.params.lro_en = enable;
3750
3751         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3752                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3753                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3754                         reset = false;
3755         }
3756
3757         if (!reset) {
3758                 *old_params = new_channels.params;
3759                 err = mlx5e_modify_tirs_lro(priv);
3760                 goto out;
3761         }
3762
3763         err = mlx5e_safe_switch_channels(priv, &new_channels,
3764                                          mlx5e_modify_tirs_lro_ctx, NULL);
3765 out:
3766         mutex_unlock(&priv->state_lock);
3767         return err;
3768 }
3769
3770 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3771 {
3772         struct mlx5e_priv *priv = netdev_priv(netdev);
3773
3774         if (enable)
3775                 mlx5e_enable_cvlan_filter(priv);
3776         else
3777                 mlx5e_disable_cvlan_filter(priv);
3778
3779         return 0;
3780 }
3781
3782 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3783 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3784 {
3785         struct mlx5e_priv *priv = netdev_priv(netdev);
3786
3787         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3788                 netdev_err(netdev,
3789                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3790                 return -EINVAL;
3791         }
3792
3793         return 0;
3794 }
3795 #endif
3796
3797 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3798 {
3799         struct mlx5e_priv *priv = netdev_priv(netdev);
3800         struct mlx5_core_dev *mdev = priv->mdev;
3801
3802         return mlx5_set_port_fcs(mdev, !enable);
3803 }
3804
3805 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3806 {
3807         struct mlx5e_priv *priv = netdev_priv(netdev);
3808         int err;
3809
3810         mutex_lock(&priv->state_lock);
3811
3812         priv->channels.params.scatter_fcs_en = enable;
3813         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3814         if (err)
3815                 priv->channels.params.scatter_fcs_en = !enable;
3816
3817         mutex_unlock(&priv->state_lock);
3818
3819         return err;
3820 }
3821
3822 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3823 {
3824         struct mlx5e_priv *priv = netdev_priv(netdev);
3825         int err = 0;
3826
3827         mutex_lock(&priv->state_lock);
3828
3829         priv->channels.params.vlan_strip_disable = !enable;
3830         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3831                 goto unlock;
3832
3833         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3834         if (err)
3835                 priv->channels.params.vlan_strip_disable = enable;
3836
3837 unlock:
3838         mutex_unlock(&priv->state_lock);
3839
3840         return err;
3841 }
3842
3843 #ifdef CONFIG_MLX5_EN_ARFS
3844 static int set_feature_arfs(struct net_device *netdev, bool enable)
3845 {
3846         struct mlx5e_priv *priv = netdev_priv(netdev);
3847         int err;
3848
3849         if (enable)
3850                 err = mlx5e_arfs_enable(priv);
3851         else
3852                 err = mlx5e_arfs_disable(priv);
3853
3854         return err;
3855 }
3856 #endif
3857
3858 static int mlx5e_handle_feature(struct net_device *netdev,
3859                                 netdev_features_t *features,
3860                                 netdev_features_t wanted_features,
3861                                 netdev_features_t feature,
3862                                 mlx5e_feature_handler feature_handler)
3863 {
3864         netdev_features_t changes = wanted_features ^ netdev->features;
3865         bool enable = !!(wanted_features & feature);
3866         int err;
3867
3868         if (!(changes & feature))
3869                 return 0;
3870
3871         err = feature_handler(netdev, enable);
3872         if (err) {
3873                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3874                            enable ? "Enable" : "Disable", &feature, err);
3875                 return err;
3876         }
3877
3878         MLX5E_SET_FEATURE(features, feature, enable);
3879         return 0;
3880 }
3881
3882 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3883 {
3884         netdev_features_t oper_features = netdev->features;
3885         int err = 0;
3886
3887 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3888         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3889
3890         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3891         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3892                                     set_feature_cvlan_filter);
3893 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3894         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3895 #endif
3896         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3897         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3898         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3899 #ifdef CONFIG_MLX5_EN_ARFS
3900         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3901 #endif
3902         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3903
3904         if (err) {
3905                 netdev->features = oper_features;
3906                 return -EINVAL;
3907         }
3908
3909         return 0;
3910 }
3911
3912 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3913                                             netdev_features_t features)
3914 {
3915         struct mlx5e_priv *priv = netdev_priv(netdev);
3916         struct mlx5e_params *params;
3917
3918         mutex_lock(&priv->state_lock);
3919         params = &priv->channels.params;
3920         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3921                 /* HW strips the outer C-tag header, this is a problem
3922                  * for S-tag traffic.
3923                  */
3924                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3925                 if (!params->vlan_strip_disable)
3926                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3927         }
3928         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3929                 if (features & NETIF_F_LRO) {
3930                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3931                         features &= ~NETIF_F_LRO;
3932                 }
3933         }
3934
3935         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3936                 features &= ~NETIF_F_RXHASH;
3937                 if (netdev->features & NETIF_F_RXHASH)
3938                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3939         }
3940
3941         mutex_unlock(&priv->state_lock);
3942
3943         return features;
3944 }
3945
3946 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3947                                    struct mlx5e_channels *chs,
3948                                    struct mlx5e_params *new_params,
3949                                    struct mlx5_core_dev *mdev)
3950 {
3951         u16 ix;
3952
3953         for (ix = 0; ix < chs->params.num_channels; ix++) {
3954                 struct xsk_buff_pool *xsk_pool =
3955                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3956                 struct mlx5e_xsk_param xsk;
3957
3958                 if (!xsk_pool)
3959                         continue;
3960
3961                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3962
3963                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3964                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3965                         int max_mtu_frame, max_mtu_page, max_mtu;
3966
3967                         /* Two criteria must be met:
3968                          * 1. HW MTU + all headrooms <= XSK frame size.
3969                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3970                          */
3971                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3972                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3973                         max_mtu = min(max_mtu_frame, max_mtu_page);
3974
3975                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3976                                    new_params->sw_mtu, ix, max_mtu);
3977                         return false;
3978                 }
3979         }
3980
3981         return true;
3982 }
3983
3984 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3985                      mlx5e_fp_preactivate preactivate)
3986 {
3987         struct mlx5e_priv *priv = netdev_priv(netdev);
3988         struct mlx5e_channels new_channels = {};
3989         struct mlx5e_params *params;
3990         int err = 0;
3991         bool reset;
3992
3993         mutex_lock(&priv->state_lock);
3994
3995         params = &priv->channels.params;
3996
3997         reset = !params->lro_en;
3998         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3999
4000         new_channels.params = *params;
4001         new_channels.params.sw_mtu = new_mtu;
4002
4003         if (params->xdp_prog &&
4004             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4005                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
4006                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
4007                 err = -EINVAL;
4008                 goto out;
4009         }
4010
4011         if (priv->xsk.refcnt &&
4012             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4013                                     &new_channels.params, priv->mdev)) {
4014                 err = -EINVAL;
4015                 goto out;
4016         }
4017
4018         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4019                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4020                                                               &new_channels.params,
4021                                                               NULL);
4022                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
4023                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
4024
4025                 /* If XSK is active, XSK RQs are linear. */
4026                 is_linear |= priv->xsk.refcnt;
4027
4028                 /* Always reset in linear mode - hw_mtu is used in data path. */
4029                 reset = reset && (is_linear || (ppw_old != ppw_new));
4030         }
4031
4032         if (!reset) {
4033                 params->sw_mtu = new_mtu;
4034                 if (preactivate)
4035                         preactivate(priv, NULL);
4036                 netdev->mtu = params->sw_mtu;
4037                 goto out;
4038         }
4039
4040         err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL);
4041         if (err)
4042                 goto out;
4043
4044         netdev->mtu = new_channels.params.sw_mtu;
4045
4046 out:
4047         mutex_unlock(&priv->state_lock);
4048         return err;
4049 }
4050
4051 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4052 {
4053         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4054 }
4055
4056 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4057 {
4058         struct hwtstamp_config config;
4059         int err;
4060
4061         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4062             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4063                 return -EOPNOTSUPP;
4064
4065         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4066                 return -EFAULT;
4067
4068         /* TX HW timestamp */
4069         switch (config.tx_type) {
4070         case HWTSTAMP_TX_OFF:
4071         case HWTSTAMP_TX_ON:
4072                 break;
4073         default:
4074                 return -ERANGE;
4075         }
4076
4077         mutex_lock(&priv->state_lock);
4078         /* RX HW timestamp */
4079         switch (config.rx_filter) {
4080         case HWTSTAMP_FILTER_NONE:
4081                 /* Reset CQE compression to Admin default */
4082                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4083                 break;
4084         case HWTSTAMP_FILTER_ALL:
4085         case HWTSTAMP_FILTER_SOME:
4086         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4087         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4088         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4089         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4090         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4091         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4092         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4093         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4094         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4095         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4096         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4097         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4098         case HWTSTAMP_FILTER_NTP_ALL:
4099                 /* Disable CQE compression */
4100                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4101                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4102                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4103                 if (err) {
4104                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4105                         mutex_unlock(&priv->state_lock);
4106                         return err;
4107                 }
4108                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4109                 break;
4110         default:
4111                 mutex_unlock(&priv->state_lock);
4112                 return -ERANGE;
4113         }
4114
4115         memcpy(&priv->tstamp, &config, sizeof(config));
4116         mutex_unlock(&priv->state_lock);
4117
4118         /* might need to fix some features */
4119         netdev_update_features(priv->netdev);
4120
4121         return copy_to_user(ifr->ifr_data, &config,
4122                             sizeof(config)) ? -EFAULT : 0;
4123 }
4124
4125 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4126 {
4127         struct hwtstamp_config *cfg = &priv->tstamp;
4128
4129         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4130                 return -EOPNOTSUPP;
4131
4132         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4133 }
4134
4135 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4136 {
4137         struct mlx5e_priv *priv = netdev_priv(dev);
4138
4139         switch (cmd) {
4140         case SIOCSHWTSTAMP:
4141                 return mlx5e_hwstamp_set(priv, ifr);
4142         case SIOCGHWTSTAMP:
4143                 return mlx5e_hwstamp_get(priv, ifr);
4144         default:
4145                 return -EOPNOTSUPP;
4146         }
4147 }
4148
4149 #ifdef CONFIG_MLX5_ESWITCH
4150 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4151 {
4152         struct mlx5e_priv *priv = netdev_priv(dev);
4153         struct mlx5_core_dev *mdev = priv->mdev;
4154
4155         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4156 }
4157
4158 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4159                              __be16 vlan_proto)
4160 {
4161         struct mlx5e_priv *priv = netdev_priv(dev);
4162         struct mlx5_core_dev *mdev = priv->mdev;
4163
4164         if (vlan_proto != htons(ETH_P_8021Q))
4165                 return -EPROTONOSUPPORT;
4166
4167         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4168                                            vlan, qos);
4169 }
4170
4171 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4172 {
4173         struct mlx5e_priv *priv = netdev_priv(dev);
4174         struct mlx5_core_dev *mdev = priv->mdev;
4175
4176         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4177 }
4178
4179 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4180 {
4181         struct mlx5e_priv *priv = netdev_priv(dev);
4182         struct mlx5_core_dev *mdev = priv->mdev;
4183
4184         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4185 }
4186
4187 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4188                       int max_tx_rate)
4189 {
4190         struct mlx5e_priv *priv = netdev_priv(dev);
4191         struct mlx5_core_dev *mdev = priv->mdev;
4192
4193         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4194                                            max_tx_rate, min_tx_rate);
4195 }
4196
4197 static int mlx5_vport_link2ifla(u8 esw_link)
4198 {
4199         switch (esw_link) {
4200         case MLX5_VPORT_ADMIN_STATE_DOWN:
4201                 return IFLA_VF_LINK_STATE_DISABLE;
4202         case MLX5_VPORT_ADMIN_STATE_UP:
4203                 return IFLA_VF_LINK_STATE_ENABLE;
4204         }
4205         return IFLA_VF_LINK_STATE_AUTO;
4206 }
4207
4208 static int mlx5_ifla_link2vport(u8 ifla_link)
4209 {
4210         switch (ifla_link) {
4211         case IFLA_VF_LINK_STATE_DISABLE:
4212                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4213         case IFLA_VF_LINK_STATE_ENABLE:
4214                 return MLX5_VPORT_ADMIN_STATE_UP;
4215         }
4216         return MLX5_VPORT_ADMIN_STATE_AUTO;
4217 }
4218
4219 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4220                                    int link_state)
4221 {
4222         struct mlx5e_priv *priv = netdev_priv(dev);
4223         struct mlx5_core_dev *mdev = priv->mdev;
4224
4225         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4226                                             mlx5_ifla_link2vport(link_state));
4227 }
4228
4229 int mlx5e_get_vf_config(struct net_device *dev,
4230                         int vf, struct ifla_vf_info *ivi)
4231 {
4232         struct mlx5e_priv *priv = netdev_priv(dev);
4233         struct mlx5_core_dev *mdev = priv->mdev;
4234         int err;
4235
4236         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4237         if (err)
4238                 return err;
4239         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4240         return 0;
4241 }
4242
4243 int mlx5e_get_vf_stats(struct net_device *dev,
4244                        int vf, struct ifla_vf_stats *vf_stats)
4245 {
4246         struct mlx5e_priv *priv = netdev_priv(dev);
4247         struct mlx5_core_dev *mdev = priv->mdev;
4248
4249         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4250                                             vf_stats);
4251 }
4252 #endif
4253
4254 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4255                                                            struct sk_buff *skb)
4256 {
4257         switch (skb->inner_protocol) {
4258         case htons(ETH_P_IP):
4259         case htons(ETH_P_IPV6):
4260         case htons(ETH_P_TEB):
4261                 return true;
4262         case htons(ETH_P_MPLS_UC):
4263         case htons(ETH_P_MPLS_MC):
4264                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4265         }
4266         return false;
4267 }
4268
4269 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4270                                                      struct sk_buff *skb,
4271                                                      netdev_features_t features)
4272 {
4273         unsigned int offset = 0;
4274         struct udphdr *udph;
4275         u8 proto;
4276         u16 port;
4277
4278         switch (vlan_get_protocol(skb)) {
4279         case htons(ETH_P_IP):
4280                 proto = ip_hdr(skb)->protocol;
4281                 break;
4282         case htons(ETH_P_IPV6):
4283                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4284                 break;
4285         default:
4286                 goto out;
4287         }
4288
4289         switch (proto) {
4290         case IPPROTO_GRE:
4291                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4292                         return features;
4293                 break;
4294         case IPPROTO_IPIP:
4295         case IPPROTO_IPV6:
4296                 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4297                         return features;
4298                 break;
4299         case IPPROTO_UDP:
4300                 udph = udp_hdr(skb);
4301                 port = be16_to_cpu(udph->dest);
4302
4303                 /* Verify if UDP port is being offloaded by HW */
4304                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4305                         return features;
4306
4307 #if IS_ENABLED(CONFIG_GENEVE)
4308                 /* Support Geneve offload for default UDP port */
4309                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4310                         return features;
4311 #endif
4312         }
4313
4314 out:
4315         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4316         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4317 }
4318
4319 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4320                                        struct net_device *netdev,
4321                                        netdev_features_t features)
4322 {
4323         struct mlx5e_priv *priv = netdev_priv(netdev);
4324
4325         features = vlan_features_check(skb, features);
4326         features = vxlan_features_check(skb, features);
4327
4328 #ifdef CONFIG_MLX5_EN_IPSEC
4329         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4330                 return features;
4331 #endif
4332
4333         /* Validate if the tunneled packet is being offloaded by HW */
4334         if (skb->encapsulation &&
4335             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4336                 return mlx5e_tunnel_features_check(priv, skb, features);
4337
4338         return features;
4339 }
4340
4341 static void mlx5e_tx_timeout_work(struct work_struct *work)
4342 {
4343         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4344                                                tx_timeout_work);
4345         int i;
4346
4347         rtnl_lock();
4348         mutex_lock(&priv->state_lock);
4349
4350         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4351                 goto unlock;
4352
4353         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4354                 struct netdev_queue *dev_queue =
4355                         netdev_get_tx_queue(priv->netdev, i);
4356                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4357
4358                 if (!netif_xmit_stopped(dev_queue))
4359                         continue;
4360
4361                 if (mlx5e_reporter_tx_timeout(sq))
4362                 /* break if tried to reopened channels */
4363                         break;
4364         }
4365
4366 unlock:
4367         mutex_unlock(&priv->state_lock);
4368         rtnl_unlock();
4369 }
4370
4371 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4372 {
4373         struct mlx5e_priv *priv = netdev_priv(dev);
4374
4375         netdev_err(dev, "TX timeout detected\n");
4376         queue_work(priv->wq, &priv->tx_timeout_work);
4377 }
4378
4379 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4380 {
4381         struct net_device *netdev = priv->netdev;
4382         struct mlx5e_channels new_channels = {};
4383
4384         if (priv->channels.params.lro_en) {
4385                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4386                 return -EINVAL;
4387         }
4388
4389         if (MLX5_IPSEC_DEV(priv->mdev)) {
4390                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4391                 return -EINVAL;
4392         }
4393
4394         new_channels.params = priv->channels.params;
4395         new_channels.params.xdp_prog = prog;
4396
4397         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4398          * the XDP program.
4399          */
4400         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4401                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4402                             new_channels.params.sw_mtu,
4403                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4404                 return -EINVAL;
4405         }
4406
4407         return 0;
4408 }
4409
4410 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4411 {
4412         struct bpf_prog *old_prog;
4413
4414         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4415                                        lockdep_is_held(&rq->channel->priv->state_lock));
4416         if (old_prog)
4417                 bpf_prog_put(old_prog);
4418 }
4419
4420 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4421 {
4422         struct mlx5e_priv *priv = netdev_priv(netdev);
4423         struct bpf_prog *old_prog;
4424         bool reset, was_opened;
4425         int err = 0;
4426         int i;
4427
4428         mutex_lock(&priv->state_lock);
4429
4430         if (prog) {
4431                 err = mlx5e_xdp_allowed(priv, prog);
4432                 if (err)
4433                         goto unlock;
4434         }
4435
4436         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4437         /* no need for full reset when exchanging programs */
4438         reset = (!priv->channels.params.xdp_prog || !prog);
4439
4440         if (was_opened && !reset)
4441                 /* num_channels is invariant here, so we can take the
4442                  * batched reference right upfront.
4443                  */
4444                 bpf_prog_add(prog, priv->channels.num);
4445
4446         if (was_opened && reset) {
4447                 struct mlx5e_channels new_channels = {};
4448
4449                 new_channels.params = priv->channels.params;
4450                 new_channels.params.xdp_prog = prog;
4451                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4452                 old_prog = priv->channels.params.xdp_prog;
4453
4454                 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
4455                 if (err)
4456                         goto unlock;
4457         } else {
4458                 /* exchange programs, extra prog reference we got from caller
4459                  * as long as we don't fail from this point onwards.
4460                  */
4461                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4462         }
4463
4464         if (old_prog)
4465                 bpf_prog_put(old_prog);
4466
4467         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4468                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4469
4470         if (!was_opened || reset)
4471                 goto unlock;
4472
4473         /* exchanging programs w/o reset, we update ref counts on behalf
4474          * of the channels RQs here.
4475          */
4476         for (i = 0; i < priv->channels.num; i++) {
4477                 struct mlx5e_channel *c = priv->channels.c[i];
4478
4479                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4480                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
4481                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4482         }
4483
4484 unlock:
4485         mutex_unlock(&priv->state_lock);
4486         return err;
4487 }
4488
4489 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4490 {
4491         switch (xdp->command) {
4492         case XDP_SETUP_PROG:
4493                 return mlx5e_xdp_set(dev, xdp->prog);
4494         case XDP_SETUP_XSK_POOL:
4495                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4496                                             xdp->xsk.queue_id);
4497         default:
4498                 return -EINVAL;
4499         }
4500 }
4501
4502 #ifdef CONFIG_MLX5_ESWITCH
4503 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4504                                 struct net_device *dev, u32 filter_mask,
4505                                 int nlflags)
4506 {
4507         struct mlx5e_priv *priv = netdev_priv(dev);
4508         struct mlx5_core_dev *mdev = priv->mdev;
4509         u8 mode, setting;
4510         int err;
4511
4512         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4513         if (err)
4514                 return err;
4515         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4516         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4517                                        mode,
4518                                        0, 0, nlflags, filter_mask, NULL);
4519 }
4520
4521 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4522                                 u16 flags, struct netlink_ext_ack *extack)
4523 {
4524         struct mlx5e_priv *priv = netdev_priv(dev);
4525         struct mlx5_core_dev *mdev = priv->mdev;
4526         struct nlattr *attr, *br_spec;
4527         u16 mode = BRIDGE_MODE_UNDEF;
4528         u8 setting;
4529         int rem;
4530
4531         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4532         if (!br_spec)
4533                 return -EINVAL;
4534
4535         nla_for_each_nested(attr, br_spec, rem) {
4536                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4537                         continue;
4538
4539                 if (nla_len(attr) < sizeof(mode))
4540                         return -EINVAL;
4541
4542                 mode = nla_get_u16(attr);
4543                 if (mode > BRIDGE_MODE_VEPA)
4544                         return -EINVAL;
4545
4546                 break;
4547         }
4548
4549         if (mode == BRIDGE_MODE_UNDEF)
4550                 return -EINVAL;
4551
4552         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4553         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4554 }
4555 #endif
4556
4557 const struct net_device_ops mlx5e_netdev_ops = {
4558         .ndo_open                = mlx5e_open,
4559         .ndo_stop                = mlx5e_close,
4560         .ndo_start_xmit          = mlx5e_xmit,
4561         .ndo_setup_tc            = mlx5e_setup_tc,
4562         .ndo_select_queue        = mlx5e_select_queue,
4563         .ndo_get_stats64         = mlx5e_get_stats,
4564         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4565         .ndo_set_mac_address     = mlx5e_set_mac,
4566         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4567         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4568         .ndo_set_features        = mlx5e_set_features,
4569         .ndo_fix_features        = mlx5e_fix_features,
4570         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4571         .ndo_do_ioctl            = mlx5e_ioctl,
4572         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4573         .ndo_udp_tunnel_add      = udp_tunnel_nic_add_port,
4574         .ndo_udp_tunnel_del      = udp_tunnel_nic_del_port,
4575         .ndo_features_check      = mlx5e_features_check,
4576         .ndo_tx_timeout          = mlx5e_tx_timeout,
4577         .ndo_bpf                 = mlx5e_xdp,
4578         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4579         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4580 #ifdef CONFIG_MLX5_EN_ARFS
4581         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4582 #endif
4583 #ifdef CONFIG_MLX5_ESWITCH
4584         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4585         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4586
4587         /* SRIOV E-Switch NDOs */
4588         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4589         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4590         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4591         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4592         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4593         .ndo_get_vf_config       = mlx5e_get_vf_config,
4594         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4595         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4596 #endif
4597         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4598 };
4599
4600 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4601 {
4602         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4603                 return -EOPNOTSUPP;
4604         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4605             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4606             !MLX5_CAP_ETH(mdev, csum_cap) ||
4607             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4608             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4609             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4610             MLX5_CAP_FLOWTABLE(mdev,
4611                                flow_table_properties_nic_receive.max_ft_level)
4612                                < 3) {
4613                 mlx5_core_warn(mdev,
4614                                "Not creating net device, some required device capabilities are missing\n");
4615                 return -EOPNOTSUPP;
4616         }
4617         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4618                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4619         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4620                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4621
4622         return 0;
4623 }
4624
4625 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4626                                    int num_channels)
4627 {
4628         int i;
4629
4630         for (i = 0; i < len; i++)
4631                 indirection_rqt[i] = i % num_channels;
4632 }
4633
4634 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4635 {
4636         u32 link_speed = 0;
4637         u32 pci_bw = 0;
4638
4639         mlx5e_port_max_linkspeed(mdev, &link_speed);
4640         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4641         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4642                            link_speed, pci_bw);
4643
4644 #define MLX5E_SLOW_PCI_RATIO (2)
4645
4646         return link_speed && pci_bw &&
4647                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4648 }
4649
4650 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4651 {
4652         struct dim_cq_moder moder;
4653
4654         moder.cq_period_mode = cq_period_mode;
4655         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4656         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4657         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4658                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4659
4660         return moder;
4661 }
4662
4663 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4664 {
4665         struct dim_cq_moder moder;
4666
4667         moder.cq_period_mode = cq_period_mode;
4668         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4669         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4670         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4671                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4672
4673         return moder;
4674 }
4675
4676 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4677 {
4678         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4679                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4680                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4681 }
4682
4683 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4684 {
4685         if (params->tx_dim_enabled) {
4686                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4687
4688                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4689         } else {
4690                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4691         }
4692 }
4693
4694 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4695 {
4696         if (params->rx_dim_enabled) {
4697                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4698
4699                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4700         } else {
4701                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4702         }
4703 }
4704
4705 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4706 {
4707         mlx5e_reset_tx_moderation(params, cq_period_mode);
4708         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4709                         params->tx_cq_moderation.cq_period_mode ==
4710                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4711 }
4712
4713 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4714 {
4715         mlx5e_reset_rx_moderation(params, cq_period_mode);
4716         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4717                         params->rx_cq_moderation.cq_period_mode ==
4718                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4719 }
4720
4721 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4722 {
4723         int i;
4724
4725         /* The supported periods are organized in ascending order */
4726         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4727                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4728                         break;
4729
4730         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4731 }
4732
4733 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4734                            struct mlx5e_params *params)
4735 {
4736         /* Prefer Striding RQ, unless any of the following holds:
4737          * - Striding RQ configuration is not possible/supported.
4738          * - Slow PCI heuristic.
4739          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4740          *
4741          * No XSK params: checking the availability of striding RQ in general.
4742          */
4743         if (!slow_pci_heuristic(mdev) &&
4744             mlx5e_striding_rq_possible(mdev, params) &&
4745             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4746              !mlx5e_rx_is_linear_skb(params, NULL)))
4747                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4748         mlx5e_set_rq_type(mdev, params);
4749         mlx5e_init_rq_type_params(mdev, params);
4750 }
4751
4752 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4753                             u16 num_channels)
4754 {
4755         enum mlx5e_traffic_types tt;
4756
4757         rss_params->hfunc = ETH_RSS_HASH_TOP;
4758         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4759                             sizeof(rss_params->toeplitz_hash_key));
4760         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4761                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4762         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4763                 rss_params->rx_hash_fields[tt] =
4764                         tirc_default_config[tt].rx_hash_fields;
4765 }
4766
4767 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4768                             struct mlx5e_xsk *xsk,
4769                             struct mlx5e_rss_params *rss_params,
4770                             struct mlx5e_params *params,
4771                             u16 mtu)
4772 {
4773         struct mlx5_core_dev *mdev = priv->mdev;
4774         u8 rx_cq_period_mode;
4775
4776         params->sw_mtu = mtu;
4777         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4778         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4779                                      priv->max_nch);
4780         params->num_tc       = 1;
4781
4782         /* SQ */
4783         params->log_sq_size = is_kdump_kernel() ?
4784                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4785                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4786         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE,
4787                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4788
4789         /* XDP SQ */
4790         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4791                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4792
4793         /* set CQE compression */
4794         params->rx_cqe_compress_def = false;
4795         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4796             MLX5_CAP_GEN(mdev, vport_group_manager))
4797                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4798
4799         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4800         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4801
4802         /* RQ */
4803         mlx5e_build_rq_params(mdev, params);
4804
4805         /* HW LRO */
4806         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4807             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4808                 /* No XSK params: checking the availability of striding RQ in general. */
4809                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4810                         params->lro_en = !slow_pci_heuristic(mdev);
4811         }
4812         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4813
4814         /* CQ moderation params */
4815         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4816                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4817                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4818         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4819         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4820         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4821         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4822
4823         /* TX inline */
4824         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4825
4826         /* RSS */
4827         mlx5e_build_rss_params(rss_params, params->num_channels);
4828         params->tunneled_offload_en =
4829                 mlx5e_tunnel_inner_ft_supported(mdev);
4830
4831         /* AF_XDP */
4832         params->xsk = xsk;
4833 }
4834
4835 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4836 {
4837         struct mlx5e_priv *priv = netdev_priv(netdev);
4838
4839         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4840         if (is_zero_ether_addr(netdev->dev_addr) &&
4841             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4842                 eth_hw_addr_random(netdev);
4843                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4844         }
4845 }
4846
4847 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4848                                 unsigned int entry, struct udp_tunnel_info *ti)
4849 {
4850         struct mlx5e_priv *priv = netdev_priv(netdev);
4851
4852         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4853 }
4854
4855 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4856                                   unsigned int entry, struct udp_tunnel_info *ti)
4857 {
4858         struct mlx5e_priv *priv = netdev_priv(netdev);
4859
4860         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4861 }
4862
4863 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4864 {
4865         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4866                 return;
4867
4868         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4869         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4870         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4871                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4872         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4873         /* Don't count the space hard-coded to the IANA port */
4874         priv->nic_info.tables[0].n_entries =
4875                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4876
4877         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4878 }
4879
4880 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4881 {
4882         struct mlx5e_priv *priv = netdev_priv(netdev);
4883         struct mlx5_core_dev *mdev = priv->mdev;
4884         bool fcs_supported;
4885         bool fcs_enabled;
4886
4887         SET_NETDEV_DEV(netdev, mdev->device);
4888
4889         netdev->netdev_ops = &mlx5e_netdev_ops;
4890
4891         mlx5e_dcbnl_build_netdev(netdev);
4892
4893         netdev->watchdog_timeo    = 15 * HZ;
4894
4895         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4896
4897         netdev->vlan_features    |= NETIF_F_SG;
4898         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4899         netdev->vlan_features    |= NETIF_F_GRO;
4900         netdev->vlan_features    |= NETIF_F_TSO;
4901         netdev->vlan_features    |= NETIF_F_TSO6;
4902         netdev->vlan_features    |= NETIF_F_RXCSUM;
4903         netdev->vlan_features    |= NETIF_F_RXHASH;
4904
4905         netdev->mpls_features    |= NETIF_F_SG;
4906         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4907         netdev->mpls_features    |= NETIF_F_TSO;
4908         netdev->mpls_features    |= NETIF_F_TSO6;
4909
4910         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4911         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4912
4913         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4914             mlx5e_check_fragmented_striding_rq_cap(mdev))
4915                 netdev->vlan_features    |= NETIF_F_LRO;
4916
4917         netdev->hw_features       = netdev->vlan_features;
4918         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4919         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4920         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4921         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4922
4923         mlx5e_vxlan_set_netdev_info(priv);
4924
4925         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4926             mlx5e_any_tunnel_proto_supported(mdev)) {
4927                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4928                 netdev->hw_enc_features |= NETIF_F_TSO;
4929                 netdev->hw_enc_features |= NETIF_F_TSO6;
4930                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4931         }
4932
4933         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4934                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4935                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4936                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4937                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4938                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4939                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4940                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4941         }
4942
4943         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4944                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4945                                            NETIF_F_GSO_GRE_CSUM;
4946                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4947                                            NETIF_F_GSO_GRE_CSUM;
4948                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4949                                                 NETIF_F_GSO_GRE_CSUM;
4950         }
4951
4952         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4953                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4954                                        NETIF_F_GSO_IPXIP6;
4955                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4956                                            NETIF_F_GSO_IPXIP6;
4957                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4958                                                 NETIF_F_GSO_IPXIP6;
4959         }
4960
4961         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4962         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4963         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4964         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4965
4966         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4967
4968         if (fcs_supported)
4969                 netdev->hw_features |= NETIF_F_RXALL;
4970
4971         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4972                 netdev->hw_features |= NETIF_F_RXFCS;
4973
4974         netdev->features          = netdev->hw_features;
4975         if (!priv->channels.params.lro_en)
4976                 netdev->features  &= ~NETIF_F_LRO;
4977
4978         if (fcs_enabled)
4979                 netdev->features  &= ~NETIF_F_RXALL;
4980
4981         if (!priv->channels.params.scatter_fcs_en)
4982                 netdev->features  &= ~NETIF_F_RXFCS;
4983
4984         /* prefere CQE compression over rxhash */
4985         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4986                 netdev->features &= ~NETIF_F_RXHASH;
4987
4988 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4989         if (FT_CAP(flow_modify_en) &&
4990             FT_CAP(modify_root) &&
4991             FT_CAP(identified_miss_table_mode) &&
4992             FT_CAP(flow_table_modify)) {
4993 #ifdef CONFIG_MLX5_ESWITCH
4994                 netdev->hw_features      |= NETIF_F_HW_TC;
4995 #endif
4996 #ifdef CONFIG_MLX5_EN_ARFS
4997                 netdev->hw_features      |= NETIF_F_NTUPLE;
4998 #endif
4999         }
5000
5001         netdev->features         |= NETIF_F_HIGHDMA;
5002         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
5003
5004         netdev->priv_flags       |= IFF_UNICAST_FLT;
5005
5006         mlx5e_set_netdev_dev_addr(netdev);
5007         mlx5e_ipsec_build_netdev(priv);
5008         mlx5e_tls_build_netdev(priv);
5009 }
5010
5011 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5012 {
5013         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5014         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5015         struct mlx5_core_dev *mdev = priv->mdev;
5016         int err;
5017
5018         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5019         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5020         if (!err)
5021                 priv->q_counter =
5022                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5023
5024         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5025         if (!err)
5026                 priv->drop_rq_q_counter =
5027                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5028 }
5029
5030 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5031 {
5032         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5033
5034         MLX5_SET(dealloc_q_counter_in, in, opcode,
5035                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5036         if (priv->q_counter) {
5037                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5038                          priv->q_counter);
5039                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5040         }
5041
5042         if (priv->drop_rq_q_counter) {
5043                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5044                          priv->drop_rq_q_counter);
5045                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5046         }
5047 }
5048
5049 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5050                           struct net_device *netdev,
5051                           const struct mlx5e_profile *profile,
5052                           void *ppriv)
5053 {
5054         struct mlx5e_priv *priv = netdev_priv(netdev);
5055         struct mlx5e_rss_params *rss = &priv->rss_params;
5056         int err;
5057
5058         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5059         if (err)
5060                 return err;
5061
5062         mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
5063                                netdev->mtu);
5064
5065         mlx5e_timestamp_init(priv);
5066
5067         err = mlx5e_ipsec_init(priv);
5068         if (err)
5069                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5070         err = mlx5e_tls_init(priv);
5071         if (err)
5072                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5073         mlx5e_build_nic_netdev(netdev);
5074         err = mlx5e_devlink_port_register(priv);
5075         if (err)
5076                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5077         mlx5e_health_create_reporters(priv);
5078
5079         return 0;
5080 }
5081
5082 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5083 {
5084         mlx5e_health_destroy_reporters(priv);
5085         mlx5e_devlink_port_unregister(priv);
5086         mlx5e_tls_cleanup(priv);
5087         mlx5e_ipsec_cleanup(priv);
5088         mlx5e_netdev_cleanup(priv->netdev, priv);
5089 }
5090
5091 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5092 {
5093         struct mlx5_core_dev *mdev = priv->mdev;
5094         int err;
5095
5096         mlx5e_create_q_counters(priv);
5097
5098         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5099         if (err) {
5100                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5101                 goto err_destroy_q_counters;
5102         }
5103
5104         err = mlx5e_create_indirect_rqt(priv);
5105         if (err)
5106                 goto err_close_drop_rq;
5107
5108         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5109         if (err)
5110                 goto err_destroy_indirect_rqts;
5111
5112         err = mlx5e_create_indirect_tirs(priv, true);
5113         if (err)
5114                 goto err_destroy_direct_rqts;
5115
5116         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5117         if (err)
5118                 goto err_destroy_indirect_tirs;
5119
5120         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5121         if (unlikely(err))
5122                 goto err_destroy_direct_tirs;
5123
5124         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5125         if (unlikely(err))
5126                 goto err_destroy_xsk_rqts;
5127
5128         err = mlx5e_create_flow_steering(priv);
5129         if (err) {
5130                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5131                 goto err_destroy_xsk_tirs;
5132         }
5133
5134         err = mlx5e_tc_nic_init(priv);
5135         if (err)
5136                 goto err_destroy_flow_steering;
5137
5138         err = mlx5e_accel_init_rx(priv);
5139         if (err)
5140                 goto err_tc_nic_cleanup;
5141
5142 #ifdef CONFIG_MLX5_EN_ARFS
5143         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5144 #endif
5145
5146         return 0;
5147
5148 err_tc_nic_cleanup:
5149         mlx5e_tc_nic_cleanup(priv);
5150 err_destroy_flow_steering:
5151         mlx5e_destroy_flow_steering(priv);
5152 err_destroy_xsk_tirs:
5153         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5154 err_destroy_xsk_rqts:
5155         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5156 err_destroy_direct_tirs:
5157         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5158 err_destroy_indirect_tirs:
5159         mlx5e_destroy_indirect_tirs(priv);
5160 err_destroy_direct_rqts:
5161         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5162 err_destroy_indirect_rqts:
5163         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5164 err_close_drop_rq:
5165         mlx5e_close_drop_rq(&priv->drop_rq);
5166 err_destroy_q_counters:
5167         mlx5e_destroy_q_counters(priv);
5168         return err;
5169 }
5170
5171 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5172 {
5173         mlx5e_accel_cleanup_rx(priv);
5174         mlx5e_tc_nic_cleanup(priv);
5175         mlx5e_destroy_flow_steering(priv);
5176         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5177         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5178         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5179         mlx5e_destroy_indirect_tirs(priv);
5180         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5181         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5182         mlx5e_close_drop_rq(&priv->drop_rq);
5183         mlx5e_destroy_q_counters(priv);
5184 }
5185
5186 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5187 {
5188         int err;
5189
5190         err = mlx5e_create_tises(priv);
5191         if (err) {
5192                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5193                 return err;
5194         }
5195
5196         mlx5e_dcbnl_initialize(priv);
5197         return 0;
5198 }
5199
5200 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5201 {
5202         struct net_device *netdev = priv->netdev;
5203         struct mlx5_core_dev *mdev = priv->mdev;
5204
5205         mlx5e_init_l2_addr(priv);
5206
5207         /* Marking the link as currently not needed by the Driver */
5208         if (!netif_running(netdev))
5209                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5210
5211         mlx5e_set_netdev_mtu_boundaries(priv);
5212         mlx5e_set_dev_port_mtu(priv);
5213
5214         mlx5_lag_add(mdev, netdev);
5215
5216         mlx5e_enable_async_events(priv);
5217         if (mlx5e_monitor_counter_supported(priv))
5218                 mlx5e_monitor_counter_init(priv);
5219
5220         mlx5e_hv_vhca_stats_create(priv);
5221         if (netdev->reg_state != NETREG_REGISTERED)
5222                 return;
5223         mlx5e_dcbnl_init_app(priv);
5224
5225         queue_work(priv->wq, &priv->set_rx_mode_work);
5226
5227         rtnl_lock();
5228         if (netif_running(netdev))
5229                 mlx5e_open(netdev);
5230         udp_tunnel_nic_reset_ntf(priv->netdev);
5231         netif_device_attach(netdev);
5232         rtnl_unlock();
5233 }
5234
5235 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5236 {
5237         struct mlx5_core_dev *mdev = priv->mdev;
5238
5239         if (priv->netdev->reg_state == NETREG_REGISTERED)
5240                 mlx5e_dcbnl_delete_app(priv);
5241
5242         rtnl_lock();
5243         if (netif_running(priv->netdev))
5244                 mlx5e_close(priv->netdev);
5245         netif_device_detach(priv->netdev);
5246         rtnl_unlock();
5247
5248         queue_work(priv->wq, &priv->set_rx_mode_work);
5249
5250         mlx5e_hv_vhca_stats_destroy(priv);
5251         if (mlx5e_monitor_counter_supported(priv))
5252                 mlx5e_monitor_counter_cleanup(priv);
5253
5254         mlx5e_disable_async_events(priv);
5255         mlx5_lag_remove(mdev);
5256         mlx5_vxlan_reset_to_default(mdev->vxlan);
5257 }
5258
5259 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5260 {
5261         return mlx5e_refresh_tirs(priv, false, false);
5262 }
5263
5264 static const struct mlx5e_profile mlx5e_nic_profile = {
5265         .init              = mlx5e_nic_init,
5266         .cleanup           = mlx5e_nic_cleanup,
5267         .init_rx           = mlx5e_init_nic_rx,
5268         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5269         .init_tx           = mlx5e_init_nic_tx,
5270         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5271         .enable            = mlx5e_nic_enable,
5272         .disable           = mlx5e_nic_disable,
5273         .update_rx         = mlx5e_update_nic_rx,
5274         .update_stats      = mlx5e_stats_update_ndo_stats,
5275         .update_carrier    = mlx5e_update_carrier,
5276         .rx_handlers       = &mlx5e_rx_handlers_nic,
5277         .max_tc            = MLX5E_MAX_NUM_TC,
5278         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5279         .stats_grps        = mlx5e_nic_stats_grps,
5280         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5281 };
5282
5283 /* mlx5e generic netdev management API (move to en_common.c) */
5284
5285 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5286 int mlx5e_netdev_init(struct net_device *netdev,
5287                       struct mlx5e_priv *priv,
5288                       struct mlx5_core_dev *mdev,
5289                       const struct mlx5e_profile *profile,
5290                       void *ppriv)
5291 {
5292         /* priv init */
5293         priv->mdev        = mdev;
5294         priv->netdev      = netdev;
5295         priv->profile     = profile;
5296         priv->ppriv       = ppriv;
5297         priv->msglevel    = MLX5E_MSG_LEVEL;
5298         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5299         priv->max_opened_tc = 1;
5300
5301         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5302                 return -ENOMEM;
5303
5304         mutex_init(&priv->state_lock);
5305         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5306         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5307         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5308         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5309
5310         priv->wq = create_singlethread_workqueue("mlx5e");
5311         if (!priv->wq)
5312                 goto err_free_cpumask;
5313
5314         /* netdev init */
5315         netif_carrier_off(netdev);
5316
5317         return 0;
5318
5319 err_free_cpumask:
5320         free_cpumask_var(priv->scratchpad.cpumask);
5321
5322         return -ENOMEM;
5323 }
5324
5325 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5326 {
5327         destroy_workqueue(priv->wq);
5328         free_cpumask_var(priv->scratchpad.cpumask);
5329 }
5330
5331 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5332                                        const struct mlx5e_profile *profile,
5333                                        int nch,
5334                                        void *ppriv)
5335 {
5336         struct net_device *netdev;
5337         int err;
5338
5339         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5340                                     nch * profile->max_tc,
5341                                     nch * profile->rq_groups);
5342         if (!netdev) {
5343                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5344                 return NULL;
5345         }
5346
5347         err = profile->init(mdev, netdev, profile, ppriv);
5348         if (err) {
5349                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5350                 goto err_free_netdev;
5351         }
5352
5353         return netdev;
5354
5355 err_free_netdev:
5356         free_netdev(netdev);
5357
5358         return NULL;
5359 }
5360
5361 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5362 {
5363         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5364         const struct mlx5e_profile *profile;
5365         int max_nch;
5366         int err;
5367
5368         profile = priv->profile;
5369         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5370
5371         /* max number of channels may have changed */
5372         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5373         if (priv->channels.params.num_channels > max_nch) {
5374                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5375                 /* Reducing the number of channels - RXFH has to be reset, and
5376                  * mlx5e_num_channels_changed below will build the RQT.
5377                  */
5378                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5379                 priv->channels.params.num_channels = max_nch;
5380         }
5381         /* 1. Set the real number of queues in the kernel the first time.
5382          * 2. Set our default XPS cpumask.
5383          * 3. Build the RQT.
5384          *
5385          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5386          * netdev has been registered by this point (if this function was called
5387          * in the reload or resume flow).
5388          */
5389         if (take_rtnl)
5390                 rtnl_lock();
5391         err = mlx5e_num_channels_changed(priv);
5392         if (take_rtnl)
5393                 rtnl_unlock();
5394         if (err)
5395                 goto out;
5396
5397         err = profile->init_tx(priv);
5398         if (err)
5399                 goto out;
5400
5401         err = profile->init_rx(priv);
5402         if (err)
5403                 goto err_cleanup_tx;
5404
5405         if (profile->enable)
5406                 profile->enable(priv);
5407
5408         return 0;
5409
5410 err_cleanup_tx:
5411         profile->cleanup_tx(priv);
5412
5413 out:
5414         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5415         cancel_work_sync(&priv->update_stats_work);
5416         return err;
5417 }
5418
5419 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5420 {
5421         const struct mlx5e_profile *profile = priv->profile;
5422
5423         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5424
5425         if (profile->disable)
5426                 profile->disable(priv);
5427         flush_workqueue(priv->wq);
5428
5429         profile->cleanup_rx(priv);
5430         profile->cleanup_tx(priv);
5431         cancel_work_sync(&priv->update_stats_work);
5432 }
5433
5434 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5435 {
5436         const struct mlx5e_profile *profile = priv->profile;
5437         struct net_device *netdev = priv->netdev;
5438
5439         if (profile->cleanup)
5440                 profile->cleanup(priv);
5441         free_netdev(netdev);
5442 }
5443
5444 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5445  * hardware contexts and to connect it to the current netdev.
5446  */
5447 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5448 {
5449         struct mlx5e_priv *priv = vpriv;
5450         struct net_device *netdev = priv->netdev;
5451         int err;
5452
5453         if (netif_device_present(netdev))
5454                 return 0;
5455
5456         err = mlx5e_create_mdev_resources(mdev);
5457         if (err)
5458                 return err;
5459
5460         err = mlx5e_attach_netdev(priv);
5461         if (err) {
5462                 mlx5e_destroy_mdev_resources(mdev);
5463                 return err;
5464         }
5465
5466         return 0;
5467 }
5468
5469 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5470 {
5471         struct mlx5e_priv *priv = vpriv;
5472         struct net_device *netdev = priv->netdev;
5473
5474 #ifdef CONFIG_MLX5_ESWITCH
5475         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5476                 return;
5477 #endif
5478
5479         if (!netif_device_present(netdev))
5480                 return;
5481
5482         mlx5e_detach_netdev(priv);
5483         mlx5e_destroy_mdev_resources(mdev);
5484 }
5485
5486 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5487 {
5488         struct net_device *netdev;
5489         void *priv;
5490         int err;
5491         int nch;
5492
5493         err = mlx5e_check_required_hca_cap(mdev);
5494         if (err)
5495                 return NULL;
5496
5497 #ifdef CONFIG_MLX5_ESWITCH
5498         if (MLX5_ESWITCH_MANAGER(mdev) &&
5499             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5500                 mlx5e_rep_register_vport_reps(mdev);
5501                 return mdev;
5502         }
5503 #endif
5504
5505         nch = mlx5e_get_max_num_channels(mdev);
5506         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5507         if (!netdev) {
5508                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5509                 return NULL;
5510         }
5511
5512         dev_net_set(netdev, mlx5_core_net(mdev));
5513         priv = netdev_priv(netdev);
5514
5515         err = mlx5e_attach(mdev, priv);
5516         if (err) {
5517                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5518                 goto err_destroy_netdev;
5519         }
5520
5521         err = register_netdev(netdev);
5522         if (err) {
5523                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5524                 goto err_detach;
5525         }
5526
5527         mlx5e_devlink_port_type_eth_set(priv);
5528
5529         mlx5e_dcbnl_init_app(priv);
5530         return priv;
5531
5532 err_detach:
5533         mlx5e_detach(mdev, priv);
5534 err_destroy_netdev:
5535         mlx5e_destroy_netdev(priv);
5536         return NULL;
5537 }
5538
5539 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5540 {
5541         struct mlx5e_priv *priv;
5542
5543 #ifdef CONFIG_MLX5_ESWITCH
5544         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5545                 mlx5e_rep_unregister_vport_reps(mdev);
5546                 return;
5547         }
5548 #endif
5549         priv = vpriv;
5550         mlx5e_dcbnl_delete_app(priv);
5551         unregister_netdev(priv->netdev);
5552         mlx5e_detach(mdev, vpriv);
5553         mlx5e_destroy_netdev(priv);
5554 }
5555
5556 static struct mlx5_interface mlx5e_interface = {
5557         .add       = mlx5e_add,
5558         .remove    = mlx5e_remove,
5559         .attach    = mlx5e_attach,
5560         .detach    = mlx5e_detach,
5561         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5562 };
5563
5564 void mlx5e_init(void)
5565 {
5566         mlx5e_ipsec_build_inverse_table();
5567         mlx5e_build_ptys2ethtool_map();
5568         mlx5_register_interface(&mlx5e_interface);
5569 }
5570
5571 void mlx5e_cleanup(void)
5572 {
5573         mlx5_unregister_interface(&mlx5e_interface);
5574 }