drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <linux/filter.h>
  41 #include <net/page_pool.h>
  42 #include <net/xdp_sock_drv.h>
  43 #include "eswitch.h"
  44 #include "en.h"
  45 #include "en/txrx.h"
  46 #include "en_tc.h"
  47 #include "en_rep.h"
  48 #include "en_accel/ipsec.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/pool.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 #include "en/devlink.h"
  67 #include "lib/mlx5.h"
  68 #include "en/ptp.h"
  69 #include "qos.h"
  70 #include "en/trap.h"
  71 #include "fpga/ipsec.h"
  72
  73 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  74 {
  75         bool striding_rq_umr, inline_umr;
  76         u16 max_wqe_sz_cap;
  77
  78         striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  79                           MLX5_CAP_ETH(mdev, reg_umr_sq);
  80         max_wqe_sz_cap = mlx5e_get_max_sq_wqebbs(mdev) * MLX5_SEND_WQE_BB;
  81         inline_umr = max_wqe_sz_cap >= MLX5E_UMR_WQE_INLINE_SZ;
  82         if (!striding_rq_umr)
  83                 return false;
  84         if (!inline_umr) {
  85                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  86                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  87                 return false;
  88         }
  89         return true;
  90 }
  91
  92 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  93 {
  94         struct mlx5_core_dev *mdev = priv->mdev;
  95         u8 port_state;
  96         bool up;
  97
  98         port_state = mlx5_query_vport_state(mdev,
  99                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 100                                             0);
 101
 102         up = port_state == VPORT_STATE_UP;
 103         if (up == netif_carrier_ok(priv->netdev))
 104                 netif_carrier_event(priv->netdev);
 105         if (up) {
 106                 netdev_info(priv->netdev, "Link up\n");
 107                 netif_carrier_on(priv->netdev);
 108         } else {
 109                 netdev_info(priv->netdev, "Link down\n");
 110                 netif_carrier_off(priv->netdev);
 111         }
 112 }
 113
 114 static void mlx5e_update_carrier_work(struct work_struct *work)
 115 {
 116         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 117                                                update_carrier_work);
 118
 119         mutex_lock(&priv->state_lock);
 120         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 121                 if (priv->profile->update_carrier)
 122                         priv->profile->update_carrier(priv);
 123         mutex_unlock(&priv->state_lock);
 124 }
 125
 126 static void mlx5e_update_stats_work(struct work_struct *work)
 127 {
 128         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 129                                                update_stats_work);
 130
 131         mutex_lock(&priv->state_lock);
 132         priv->profile->update_stats(priv);
 133         mutex_unlock(&priv->state_lock);
 134 }
 135
 136 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 137 {
 138         if (!priv->profile->update_stats)
 139                 return;
 140
 141         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 142                 return;
 143
 144         queue_work(priv->wq, &priv->update_stats_work);
 145 }
 146
 147 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 148 {
 149         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 150         struct mlx5_eqe   *eqe = data;
 151
 152         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 153                 return NOTIFY_DONE;
 154
 155         switch (eqe->sub_type) {
 156         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 157         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 158                 queue_work(priv->wq, &priv->update_carrier_work);
 159                 break;
 160         default:
 161                 return NOTIFY_DONE;
 162         }
 163
 164         return NOTIFY_OK;
 165 }
 166
 167 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 168 {
 169         priv->events_nb.notifier_call = async_event;
 170         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 171 }
 172
 173 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 174 {
 175         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 176 }
 177
 178 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 179 {
 180         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 181         int err;
 182
 183         switch (event) {
 184         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 185                 err = mlx5e_handle_trap_event(priv, data);
 186                 break;
 187         default:
 188                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 189                 err = -EINVAL;
 190         }
 191         return err;
 192 }
 193
 194 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 195 {
 196         priv->blocking_events_nb.notifier_call = blocking_event;
 197         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 198 }
 199
 200 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 201 {
 202         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 203 }
 204
 205 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 206                                        struct mlx5e_icosq *sq,
 207                                        struct mlx5e_umr_wqe *wqe)
 208 {
 209         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 210         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 211         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 212
 213         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 214                                       ds_cnt);
 215         cseg->umr_mkey  = rq->mkey_be;
 216
 217         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 218         ucseg->xlt_octowords =
 219                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 220         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 221 }
 222
 223 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
 224 {
 225         rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
 226                                          GFP_KERNEL, node);
 227         if (!rq->mpwqe.shampo)
 228                 return -ENOMEM;
 229         return 0;
 230 }
 231
 232 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
 233 {
 234         kvfree(rq->mpwqe.shampo);
 235 }
 236
 237 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
 238 {
 239         struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
 240
 241         shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
 242                                             node);
 243         if (!shampo->bitmap)
 244                 return -ENOMEM;
 245
 246         shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
 247                                                 sizeof(*shampo->info)),
 248                                      GFP_KERNEL, node);
 249         if (!shampo->info) {
 250                 kvfree(shampo->bitmap);
 251                 return -ENOMEM;
 252         }
 253         return 0;
 254 }
 255
 256 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
 257 {
 258         kvfree(rq->mpwqe.shampo->bitmap);
 259         kvfree(rq->mpwqe.shampo->info);
 260 }
 261
 262 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 263 {
 264         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 265
 266         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 267                                                   sizeof(*rq->mpwqe.info)),
 268                                        GFP_KERNEL, node);
 269         if (!rq->mpwqe.info)
 270                 return -ENOMEM;
 271
 272         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 273
 274         return 0;
 275 }
 276
 277 static int mlx5e_create_umr_mtt_mkey(struct mlx5_core_dev *mdev,
 278                                      u64 npages, u8 page_shift, u32 *umr_mkey,
 279                                      dma_addr_t filler_addr)
 280 {
 281         struct mlx5_mtt *mtt;
 282         int inlen;
 283         void *mkc;
 284         u32 *in;
 285         int err;
 286         int i;
 287
 288         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 289
 290         in = kvzalloc(inlen, GFP_KERNEL);
 291         if (!in)
 292                 return -ENOMEM;
 293
 294         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 295
 296         MLX5_SET(mkc, mkc, free, 1);
 297         MLX5_SET(mkc, mkc, umr_en, 1);
 298         MLX5_SET(mkc, mkc, lw, 1);
 299         MLX5_SET(mkc, mkc, lr, 1);
 300         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 301         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 302         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 303         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 304         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 305         MLX5_SET(mkc, mkc, translations_octword_size,
 306                  MLX5_MTT_OCTW(npages));
 307         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 308         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 309                  MLX5_MTT_OCTW(npages));
 310
 311         /* Initialize the mkey with all MTTs pointing to a default
 312          * page (filler_addr). When the channels are activated, UMR
 313          * WQEs will redirect the RX WQEs to the actual memory from
 314          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 315          * to the default page.
 316          */
 317         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 318         for (i = 0 ; i < npages ; i++)
 319                 mtt[i].ptag = cpu_to_be64(filler_addr);
 320
 321         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 322
 323         kvfree(in);
 324         return err;
 325 }
 326
 327 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
 328                                      u64 nentries,
 329                                      u32 *umr_mkey)
 330 {
 331         int inlen;
 332         void *mkc;
 333         u32 *in;
 334         int err;
 335
 336         inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 337
 338         in = kvzalloc(inlen, GFP_KERNEL);
 339         if (!in)
 340                 return -ENOMEM;
 341
 342         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 343
 344         MLX5_SET(mkc, mkc, free, 1);
 345         MLX5_SET(mkc, mkc, umr_en, 1);
 346         MLX5_SET(mkc, mkc, lw, 1);
 347         MLX5_SET(mkc, mkc, lr, 1);
 348         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
 349         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 350         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 351         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 352         MLX5_SET(mkc, mkc, translations_octword_size, nentries);
 353         MLX5_SET(mkc, mkc, length64, 1);
 354         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 355
 356         kvfree(in);
 357         return err;
 358 }
 359
 360 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 361 {
 362         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 363
 364         return mlx5e_create_umr_mtt_mkey(mdev, num_mtts, PAGE_SHIFT,
 365                                          &rq->umr_mkey, rq->wqe_overflow.addr);
 366 }
 367
 368 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
 369                                        struct mlx5e_rq *rq)
 370 {
 371         u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
 372
 373         if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
 374                 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
 375                               max_klm_size, rq->mpwqe.shampo->hd_per_wq);
 376                 return -EINVAL;
 377         }
 378         return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
 379                                          &rq->mpwqe.shampo->mkey);
 380 }
 381
 382 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 383 {
 384         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 385 }
 386
 387 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 388 {
 389         struct mlx5e_wqe_frag_info next_frag = {};
 390         struct mlx5e_wqe_frag_info *prev = NULL;
 391         int i;
 392
 393         next_frag.di = &rq->wqe.di[0];
 394
 395         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 396                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 397                 struct mlx5e_wqe_frag_info *frag =
 398                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 399                 int f;
 400
 401                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 402                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 403                                 next_frag.di++;
 404                                 next_frag.offset = 0;
 405                                 if (prev)
 406                                         prev->last_in_page = true;
 407                         }
 408                         *frag = next_frag;
 409
 410                         /* prepare next */
 411                         next_frag.offset += frag_info[f].frag_stride;
 412                         prev = frag;
 413                 }
 414         }
 415
 416         if (prev)
 417                 prev->last_in_page = true;
 418 }
 419
 420 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 421 {
 422         int len = wq_sz << rq->wqe.info.log_num_frags;
 423
 424         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 425         if (!rq->wqe.di)
 426                 return -ENOMEM;
 427
 428         mlx5e_init_frags_partition(rq);
 429
 430         return 0;
 431 }
 432
 433 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 434 {
 435         kvfree(rq->wqe.di);
 436 }
 437
 438 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 439 {
 440         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 441
 442         mlx5e_reporter_rq_cqe_err(rq);
 443 }
 444
 445 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 446 {
 447         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 448         if (!rq->wqe_overflow.page)
 449                 return -ENOMEM;
 450
 451         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 452                                              PAGE_SIZE, rq->buff.map_dir);
 453         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 454                 __free_page(rq->wqe_overflow.page);
 455                 return -ENOMEM;
 456         }
 457         return 0;
 458 }
 459
 460 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 461 {
 462          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 463                         rq->buff.map_dir);
 464          __free_page(rq->wqe_overflow.page);
 465 }
 466
 467 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 468                              struct mlx5e_rq *rq)
 469 {
 470         struct mlx5_core_dev *mdev = c->mdev;
 471         int err;
 472
 473         rq->wq_type      = params->rq_wq_type;
 474         rq->pdev         = c->pdev;
 475         rq->netdev       = c->netdev;
 476         rq->priv         = c->priv;
 477         rq->tstamp       = c->tstamp;
 478         rq->clock        = &mdev->clock;
 479         rq->icosq        = &c->icosq;
 480         rq->ix           = c->ix;
 481         rq->mdev         = mdev;
 482         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 483         rq->xdpsq        = &c->rq_xdpsq;
 484         rq->stats        = &c->priv->channel_stats[c->ix]->rq;
 485         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 486         err = mlx5e_rq_set_handlers(rq, params, NULL);
 487         if (err)
 488                 return err;
 489
 490         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 491 }
 492
 493 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
 494                                 struct mlx5e_params *params,
 495                                 struct mlx5e_rq_param *rqp,
 496                                 struct mlx5e_rq *rq,
 497                                 u32 *pool_size,
 498                                 int node)
 499 {
 500         void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
 501         int wq_size;
 502         int err;
 503
 504         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 505                 return 0;
 506         err = mlx5e_rq_shampo_hd_alloc(rq, node);
 507         if (err)
 508                 goto out;
 509         rq->mpwqe.shampo->hd_per_wq =
 510                 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
 511         err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
 512         if (err)
 513                 goto err_shampo_hd;
 514         err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
 515         if (err)
 516                 goto err_shampo_info;
 517         rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
 518         if (!rq->hw_gro_data) {
 519                 err = -ENOMEM;
 520                 goto err_hw_gro_data;
 521         }
 522         rq->mpwqe.shampo->key =
 523                 cpu_to_be32(rq->mpwqe.shampo->mkey);
 524         rq->mpwqe.shampo->hd_per_wqe =
 525                 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
 526         wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
 527         *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
 528                      MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
 529         return 0;
 530
 531 err_hw_gro_data:
 532         mlx5e_rq_shampo_hd_info_free(rq);
 533 err_shampo_info:
 534         mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
 535 err_shampo_hd:
 536         mlx5e_rq_shampo_hd_free(rq);
 537 out:
 538         return err;
 539 }
 540
 541 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
 542 {
 543         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 544                 return;
 545
 546         kvfree(rq->hw_gro_data);
 547         mlx5e_rq_shampo_hd_info_free(rq);
 548         mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
 549         mlx5e_rq_shampo_hd_free(rq);
 550 }
 551
 552 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 553                           struct mlx5e_xsk_param *xsk,
 554                           struct mlx5e_rq_param *rqp,
 555                           int node, struct mlx5e_rq *rq)
 556 {
 557         struct page_pool_params pp_params = { 0 };
 558         struct mlx5_core_dev *mdev = rq->mdev;
 559         void *rqc = rqp->rqc;
 560         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 561         u32 pool_size;
 562         int wq_sz;
 563         int err;
 564         int i;
 565
 566         rqp->wq.db_numa_node = node;
 567         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 568
 569         if (params->xdp_prog)
 570                 bpf_prog_inc(params->xdp_prog);
 571         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 572
 573         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 574         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 575         pool_size = 1 << params->log_rq_mtu_frames;
 576
 577         switch (rq->wq_type) {
 578         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 579                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 580                                         &rq->wq_ctrl);
 581                 if (err)
 582                         goto err_rq_xdp_prog;
 583
 584                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 585                 if (err)
 586                         goto err_rq_wq_destroy;
 587
 588                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 589
 590                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 591
 592                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 593                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 594
 595                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 596                 rq->mpwqe.num_strides =
 597                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 598                 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
 599
 600                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 601
 602                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 603                 if (err)
 604                         goto err_rq_drop_page;
 605                 rq->mkey_be = cpu_to_be32(rq->umr_mkey);
 606
 607                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 608                 if (err)
 609                         goto err_rq_mkey;
 610
 611                 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
 612                 if (err)
 613                         goto err_free_by_rq_type;
 614
 615                 break;
 616         default: /* MLX5_WQ_TYPE_CYCLIC */
 617                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 618                                          &rq->wq_ctrl);
 619                 if (err)
 620                         goto err_rq_xdp_prog;
 621
 622                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 623
 624                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 625
 626                 rq->wqe.info = rqp->frags_info;
 627                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 628
 629                 rq->wqe.frags =
 630                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 631                                         (wq_sz << rq->wqe.info.log_num_frags)),
 632                                       GFP_KERNEL, node);
 633                 if (!rq->wqe.frags) {
 634                         err = -ENOMEM;
 635                         goto err_rq_wq_destroy;
 636                 }
 637
 638                 err = mlx5e_init_di_list(rq, wq_sz, node);
 639                 if (err)
 640                         goto err_rq_frags;
 641
 642                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
 643         }
 644
 645         if (xsk) {
 646                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 647                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 648                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 649         } else {
 650                 /* Create a page_pool and register it with rxq */
 651                 pp_params.order     = 0;
 652                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 653                 pp_params.pool_size = pool_size;
 654                 pp_params.nid       = node;
 655                 pp_params.dev       = rq->pdev;
 656                 pp_params.dma_dir   = rq->buff.map_dir;
 657
 658                 /* page_pool can be used even when there is no rq->xdp_prog,
 659                  * given page_pool does not handle DMA mapping there is no
 660                  * required state to clear. And page_pool gracefully handle
 661                  * elevated refcnt.
 662                  */
 663                 rq->page_pool = page_pool_create(&pp_params);
 664                 if (IS_ERR(rq->page_pool)) {
 665                         err = PTR_ERR(rq->page_pool);
 666                         rq->page_pool = NULL;
 667                         goto err_free_shampo;
 668                 }
 669                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 670                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 671                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 672         }
 673         if (err)
 674                 goto err_free_shampo;
 675
 676         for (i = 0; i < wq_sz; i++) {
 677                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 678                         struct mlx5e_rx_wqe_ll *wqe =
 679                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 680                         u32 byte_count =
 681                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 682                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 683                         u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
 684                                        0 : rq->buff.headroom;
 685
 686                         wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
 687                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 688                         wqe->data[0].lkey = rq->mkey_be;
 689                 } else {
 690                         struct mlx5e_rx_wqe_cyc *wqe =
 691                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 692                         int f;
 693
 694                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 695                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 696                                         MLX5_HW_START_PADDING;
 697
 698                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 699                                 wqe->data[f].lkey = rq->mkey_be;
 700                         }
 701                         /* check if num_frags is not a pow of two */
 702                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 703                                 wqe->data[f].byte_count = 0;
 704                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 705                                 wqe->data[f].addr = 0;
 706                         }
 707                 }
 708         }
 709
 710         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 711
 712         switch (params->rx_cq_moderation.cq_period_mode) {
 713         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 714                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 715                 break;
 716         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 717         default:
 718                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 719         }
 720
 721         rq->page_cache.head = 0;
 722         rq->page_cache.tail = 0;
 723
 724         return 0;
 725
 726 err_free_shampo:
 727         mlx5e_rq_free_shampo(rq);
 728 err_free_by_rq_type:
 729         switch (rq->wq_type) {
 730         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 731                 kvfree(rq->mpwqe.info);
 732 err_rq_mkey:
 733                 mlx5_core_destroy_mkey(mdev, rq->umr_mkey);
 734 err_rq_drop_page:
 735                 mlx5e_free_mpwqe_rq_drop_page(rq);
 736                 break;
 737         default: /* MLX5_WQ_TYPE_CYCLIC */
 738                 mlx5e_free_di_list(rq);
 739 err_rq_frags:
 740                 kvfree(rq->wqe.frags);
 741         }
 742 err_rq_wq_destroy:
 743         mlx5_wq_destroy(&rq->wq_ctrl);
 744 err_rq_xdp_prog:
 745         if (params->xdp_prog)
 746                 bpf_prog_put(params->xdp_prog);
 747
 748         return err;
 749 }
 750
 751 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 752 {
 753         struct bpf_prog *old_prog;
 754         int i;
 755
 756         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 757                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 758                                                      lockdep_is_held(&rq->priv->state_lock));
 759                 if (old_prog)
 760                         bpf_prog_put(old_prog);
 761         }
 762
 763         switch (rq->wq_type) {
 764         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 765                 kvfree(rq->mpwqe.info);
 766                 mlx5_core_destroy_mkey(rq->mdev, rq->umr_mkey);
 767                 mlx5e_free_mpwqe_rq_drop_page(rq);
 768                 mlx5e_rq_free_shampo(rq);
 769                 break;
 770         default: /* MLX5_WQ_TYPE_CYCLIC */
 771                 kvfree(rq->wqe.frags);
 772                 mlx5e_free_di_list(rq);
 773         }
 774
 775         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 776              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 777                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 778
 779                 /* With AF_XDP, page_cache is not used, so this loop is not
 780                  * entered, and it's safe to call mlx5e_page_release_dynamic
 781                  * directly.
 782                  */
 783                 mlx5e_page_release_dynamic(rq, dma_info->page, false);
 784         }
 785
 786         xdp_rxq_info_unreg(&rq->xdp_rxq);
 787         page_pool_destroy(rq->page_pool);
 788         mlx5_wq_destroy(&rq->wq_ctrl);
 789 }
 790
 791 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 792 {
 793         struct mlx5_core_dev *mdev = rq->mdev;
 794         u8 ts_format;
 795         void *in;
 796         void *rqc;
 797         void *wq;
 798         int inlen;
 799         int err;
 800
 801         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 802                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 803         in = kvzalloc(inlen, GFP_KERNEL);
 804         if (!in)
 805                 return -ENOMEM;
 806
 807         ts_format = mlx5_is_real_time_rq(mdev) ?
 808                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 809                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 810         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 811         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 812
 813         memcpy(rqc, param->rqc, sizeof(param->rqc));
 814
 815         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 816         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 817         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 818         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 819                                                 MLX5_ADAPTER_PAGE_SHIFT);
 820         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 821
 822         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 823                 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
 824                          order_base_2(rq->mpwqe.shampo->hd_per_wq));
 825                 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
 826         }
 827
 828         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 829                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 830
 831         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 832
 833         kvfree(in);
 834
 835         return err;
 836 }
 837
 838 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 839 {
 840         struct mlx5_core_dev *mdev = rq->mdev;
 841
 842         void *in;
 843         void *rqc;
 844         int inlen;
 845         int err;
 846
 847         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 848         in = kvzalloc(inlen, GFP_KERNEL);
 849         if (!in)
 850                 return -ENOMEM;
 851
 852         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 853                 mlx5e_rqwq_reset(rq);
 854
 855         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 856
 857         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 858         MLX5_SET(rqc, rqc, state, next_state);
 859
 860         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 861
 862         kvfree(in);
 863
 864         return err;
 865 }
 866
 867 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 868 {
 869         struct mlx5_core_dev *mdev = rq->mdev;
 870
 871         void *in;
 872         void *rqc;
 873         int inlen;
 874         int err;
 875
 876         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 877         in = kvzalloc(inlen, GFP_KERNEL);
 878         if (!in)
 879                 return -ENOMEM;
 880
 881         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 882
 883         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 884         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 885                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 886         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 887         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 888
 889         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 890
 891         kvfree(in);
 892
 893         return err;
 894 }
 895
 896 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 897 {
 898         struct mlx5_core_dev *mdev = rq->mdev;
 899         void *in;
 900         void *rqc;
 901         int inlen;
 902         int err;
 903
 904         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 905         in = kvzalloc(inlen, GFP_KERNEL);
 906         if (!in)
 907                 return -ENOMEM;
 908
 909         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 910
 911         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 912         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 913                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 914         MLX5_SET(rqc, rqc, vsd, vsd);
 915         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 916
 917         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 918
 919         kvfree(in);
 920
 921         return err;
 922 }
 923
 924 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 925 {
 926         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 927 }
 928
 929 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 930 {
 931         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 932
 933         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 934
 935         do {
 936                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 937                         return 0;
 938
 939                 msleep(20);
 940         } while (time_before(jiffies, exp_time));
 941
 942         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 943                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 944
 945         mlx5e_reporter_rx_timeout(rq);
 946         return -ETIMEDOUT;
 947 }
 948
 949 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 950 {
 951         struct mlx5_wq_ll *wq;
 952         u16 head;
 953         int i;
 954
 955         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 956                 return;
 957
 958         wq = &rq->mpwqe.wq;
 959         head = wq->head;
 960
 961         /* Outstanding UMR WQEs (in progress) start at wq->head */
 962         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 963                 rq->dealloc_wqe(rq, head);
 964                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 965         }
 966
 967         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 968                 u16 len;
 969
 970                 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
 971                       (rq->mpwqe.shampo->hd_per_wq - 1);
 972                 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
 973                 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
 974         }
 975
 976         rq->mpwqe.actual_wq_head = wq->head;
 977         rq->mpwqe.umr_in_progress = 0;
 978         rq->mpwqe.umr_completed = 0;
 979 }
 980
 981 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 982 {
 983         __be16 wqe_ix_be;
 984         u16 wqe_ix;
 985
 986         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 987                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 988
 989                 mlx5e_free_rx_in_progress_descs(rq);
 990
 991                 while (!mlx5_wq_ll_is_empty(wq)) {
 992                         struct mlx5e_rx_wqe_ll *wqe;
 993
 994                         wqe_ix_be = *wq->tail_next;
 995                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 996                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 997                         rq->dealloc_wqe(rq, wqe_ix);
 998                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 999                                        &wqe->next.next_wqe_index);
1000                 }
1001
1002                 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1003                         mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1004                                                 0, true);
1005         } else {
1006                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1007
1008                 while (!mlx5_wq_cyc_is_empty(wq)) {
1009                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
1010                         rq->dealloc_wqe(rq, wqe_ix);
1011                         mlx5_wq_cyc_pop(wq);
1012                 }
1013         }
1014
1015 }
1016
1017 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1018                   struct mlx5e_xsk_param *xsk, int node,
1019                   struct mlx5e_rq *rq)
1020 {
1021         struct mlx5_core_dev *mdev = rq->mdev;
1022         int err;
1023
1024         if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1025                 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1026
1027         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1028         if (err)
1029                 return err;
1030
1031         err = mlx5e_create_rq(rq, param);
1032         if (err)
1033                 goto err_free_rq;
1034
1035         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1036         if (err)
1037                 goto err_destroy_rq;
1038
1039         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
1040                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
1041
1042         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1043                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1044
1045         if (params->rx_dim_enabled)
1046                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
1047
1048         /* We disable csum_complete when XDP is enabled since
1049          * XDP programs might manipulate packets which will render
1050          * skb->checksum incorrect.
1051          */
1052         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1053                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1054
1055         /* For CQE compression on striding RQ, use stride index provided by
1056          * HW if capability is supported.
1057          */
1058         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1059             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1060                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1061
1062         return 0;
1063
1064 err_destroy_rq:
1065         mlx5e_destroy_rq(rq);
1066 err_free_rq:
1067         mlx5e_free_rq(rq);
1068
1069         return err;
1070 }
1071
1072 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1073 {
1074         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1075         if (rq->icosq) {
1076                 mlx5e_trigger_irq(rq->icosq);
1077         } else {
1078                 local_bh_disable();
1079                 napi_schedule(rq->cq.napi);
1080                 local_bh_enable();
1081         }
1082 }
1083
1084 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1085 {
1086         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1087         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1088 }
1089
1090 void mlx5e_close_rq(struct mlx5e_rq *rq)
1091 {
1092         cancel_work_sync(&rq->dim.work);
1093         cancel_work_sync(&rq->recover_work);
1094         mlx5e_destroy_rq(rq);
1095         mlx5e_free_rx_descs(rq);
1096         mlx5e_free_rq(rq);
1097 }
1098
1099 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1100 {
1101         kvfree(sq->db.xdpi_fifo.xi);
1102         kvfree(sq->db.wqe_info);
1103 }
1104
1105 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1106 {
1107         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1108         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1109         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1110         size_t size;
1111
1112         size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
1113         xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1114         if (!xdpi_fifo->xi)
1115                 return -ENOMEM;
1116
1117         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1118         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1119         xdpi_fifo->mask = dsegs_per_wq - 1;
1120
1121         return 0;
1122 }
1123
1124 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1125 {
1126         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1127         size_t size;
1128         int err;
1129
1130         size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1131         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1132         if (!sq->db.wqe_info)
1133                 return -ENOMEM;
1134
1135         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1136         if (err) {
1137                 mlx5e_free_xdpsq_db(sq);
1138                 return err;
1139         }
1140
1141         return 0;
1142 }
1143
1144 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1145                              struct mlx5e_params *params,
1146                              struct xsk_buff_pool *xsk_pool,
1147                              struct mlx5e_sq_param *param,
1148                              struct mlx5e_xdpsq *sq,
1149                              bool is_redirect)
1150 {
1151         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1152         struct mlx5_core_dev *mdev = c->mdev;
1153         struct mlx5_wq_cyc *wq = &sq->wq;
1154         int err;
1155
1156         sq->pdev      = c->pdev;
1157         sq->mkey_be   = c->mkey_be;
1158         sq->channel   = c;
1159         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1160         sq->min_inline_mode = params->tx_min_inline_mode;
1161         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1162         sq->xsk_pool  = xsk_pool;
1163
1164         sq->stats = sq->xsk_pool ?
1165                 &c->priv->channel_stats[c->ix]->xsksq :
1166                 is_redirect ?
1167                         &c->priv->channel_stats[c->ix]->xdpsq :
1168                         &c->priv->channel_stats[c->ix]->rq_xdpsq;
1169         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1170         sq->stop_room = MLX5E_STOP_ROOM(sq->max_sq_wqebbs);
1171         sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1172
1173         param->wq.db_numa_node = cpu_to_node(c->cpu);
1174         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1175         if (err)
1176                 return err;
1177         wq->db = &wq->db[MLX5_SND_DBR];
1178
1179         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1180         if (err)
1181                 goto err_sq_wq_destroy;
1182
1183         return 0;
1184
1185 err_sq_wq_destroy:
1186         mlx5_wq_destroy(&sq->wq_ctrl);
1187
1188         return err;
1189 }
1190
1191 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1192 {
1193         mlx5e_free_xdpsq_db(sq);
1194         mlx5_wq_destroy(&sq->wq_ctrl);
1195 }
1196
1197 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1198 {
1199         kvfree(sq->db.wqe_info);
1200 }
1201
1202 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1203 {
1204         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1205         size_t size;
1206
1207         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1208         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1209         if (!sq->db.wqe_info)
1210                 return -ENOMEM;
1211
1212         return 0;
1213 }
1214
1215 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1216 {
1217         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1218                                               recover_work);
1219
1220         mlx5e_reporter_icosq_cqe_err(sq);
1221 }
1222
1223 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1224 {
1225         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1226                                               recover_work);
1227
1228         /* Not implemented yet. */
1229
1230         netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1231 }
1232
1233 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1234                              struct mlx5e_sq_param *param,
1235                              struct mlx5e_icosq *sq,
1236                              work_func_t recover_work_func)
1237 {
1238         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1239         struct mlx5_core_dev *mdev = c->mdev;
1240         struct mlx5_wq_cyc *wq = &sq->wq;
1241         int err;
1242
1243         sq->channel   = c;
1244         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1245         sq->reserved_room = param->stop_room;
1246         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1247
1248         param->wq.db_numa_node = cpu_to_node(c->cpu);
1249         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1250         if (err)
1251                 return err;
1252         wq->db = &wq->db[MLX5_SND_DBR];
1253
1254         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1255         if (err)
1256                 goto err_sq_wq_destroy;
1257
1258         INIT_WORK(&sq->recover_work, recover_work_func);
1259
1260         return 0;
1261
1262 err_sq_wq_destroy:
1263         mlx5_wq_destroy(&sq->wq_ctrl);
1264
1265         return err;
1266 }
1267
1268 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1269 {
1270         mlx5e_free_icosq_db(sq);
1271         mlx5_wq_destroy(&sq->wq_ctrl);
1272 }
1273
1274 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1275 {
1276         kvfree(sq->db.wqe_info);
1277         kvfree(sq->db.skb_fifo.fifo);
1278         kvfree(sq->db.dma_fifo);
1279 }
1280
1281 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1282 {
1283         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1284         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1285
1286         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1287                                                    sizeof(*sq->db.dma_fifo)),
1288                                         GFP_KERNEL, numa);
1289         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1290                                                         sizeof(*sq->db.skb_fifo.fifo)),
1291                                         GFP_KERNEL, numa);
1292         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1293                                                    sizeof(*sq->db.wqe_info)),
1294                                         GFP_KERNEL, numa);
1295         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1296                 mlx5e_free_txqsq_db(sq);
1297                 return -ENOMEM;
1298         }
1299
1300         sq->dma_fifo_mask = df_sz - 1;
1301
1302         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1303         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1304         sq->db.skb_fifo.mask = df_sz - 1;
1305
1306         return 0;
1307 }
1308
1309 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1310                              int txq_ix,
1311                              struct mlx5e_params *params,
1312                              struct mlx5e_sq_param *param,
1313                              struct mlx5e_txqsq *sq,
1314                              int tc)
1315 {
1316         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1317         struct mlx5_core_dev *mdev = c->mdev;
1318         struct mlx5_wq_cyc *wq = &sq->wq;
1319         int err;
1320
1321         sq->pdev      = c->pdev;
1322         sq->clock     = &mdev->clock;
1323         sq->mkey_be   = c->mkey_be;
1324         sq->netdev    = c->netdev;
1325         sq->mdev      = c->mdev;
1326         sq->priv      = c->priv;
1327         sq->ch_ix     = c->ix;
1328         sq->txq_ix    = txq_ix;
1329         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1330         sq->min_inline_mode = params->tx_min_inline_mode;
1331         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1332         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1333         sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1334         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1335         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1336                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1337         if (MLX5_IPSEC_DEV(c->priv->mdev))
1338                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1339         if (param->is_mpw)
1340                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1341         sq->stop_room = param->stop_room;
1342         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1343
1344         param->wq.db_numa_node = cpu_to_node(c->cpu);
1345         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1346         if (err)
1347                 return err;
1348         wq->db    = &wq->db[MLX5_SND_DBR];
1349
1350         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1351         if (err)
1352                 goto err_sq_wq_destroy;
1353
1354         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1355         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1356
1357         return 0;
1358
1359 err_sq_wq_destroy:
1360         mlx5_wq_destroy(&sq->wq_ctrl);
1361
1362         return err;
1363 }
1364
1365 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1366 {
1367         mlx5e_free_txqsq_db(sq);
1368         mlx5_wq_destroy(&sq->wq_ctrl);
1369 }
1370
1371 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1372                            struct mlx5e_sq_param *param,
1373                            struct mlx5e_create_sq_param *csp,
1374                            u32 *sqn)
1375 {
1376         u8 ts_format;
1377         void *in;
1378         void *sqc;
1379         void *wq;
1380         int inlen;
1381         int err;
1382
1383         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1384                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1385         in = kvzalloc(inlen, GFP_KERNEL);
1386         if (!in)
1387                 return -ENOMEM;
1388
1389         ts_format = mlx5_is_real_time_sq(mdev) ?
1390                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1391                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1392         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1393         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1394
1395         memcpy(sqc, param->sqc, sizeof(param->sqc));
1396         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1397         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1398         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1399         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1400         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1401
1402
1403         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1404                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1405
1406         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1407         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1408
1409         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1410         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1411         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1412                                           MLX5_ADAPTER_PAGE_SHIFT);
1413         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1414
1415         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1416                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1417
1418         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1419
1420         kvfree(in);
1421
1422         return err;
1423 }
1424
1425 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1426                     struct mlx5e_modify_sq_param *p)
1427 {
1428         u64 bitmask = 0;
1429         void *in;
1430         void *sqc;
1431         int inlen;
1432         int err;
1433
1434         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1435         in = kvzalloc(inlen, GFP_KERNEL);
1436         if (!in)
1437                 return -ENOMEM;
1438
1439         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1440
1441         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1442         MLX5_SET(sqc, sqc, state, p->next_state);
1443         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1444                 bitmask |= 1;
1445                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1446         }
1447         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1448                 bitmask |= 1 << 2;
1449                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1450         }
1451         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1452
1453         err = mlx5_core_modify_sq(mdev, sqn, in);
1454
1455         kvfree(in);
1456
1457         return err;
1458 }
1459
1460 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1461 {
1462         mlx5_core_destroy_sq(mdev, sqn);
1463 }
1464
1465 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1466                         struct mlx5e_sq_param *param,
1467                         struct mlx5e_create_sq_param *csp,
1468                         u16 qos_queue_group_id,
1469                         u32 *sqn)
1470 {
1471         struct mlx5e_modify_sq_param msp = {0};
1472         int err;
1473
1474         err = mlx5e_create_sq(mdev, param, csp, sqn);
1475         if (err)
1476                 return err;
1477
1478         msp.curr_state = MLX5_SQC_STATE_RST;
1479         msp.next_state = MLX5_SQC_STATE_RDY;
1480         if (qos_queue_group_id) {
1481                 msp.qos_update = true;
1482                 msp.qos_queue_group_id = qos_queue_group_id;
1483         }
1484         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1485         if (err)
1486                 mlx5e_destroy_sq(mdev, *sqn);
1487
1488         return err;
1489 }
1490
1491 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1492                                 struct mlx5e_txqsq *sq, u32 rate);
1493
1494 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1495                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1496                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1497                      struct mlx5e_sq_stats *sq_stats)
1498 {
1499         struct mlx5e_create_sq_param csp = {};
1500         u32 tx_rate;
1501         int err;
1502
1503         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1504         if (err)
1505                 return err;
1506
1507         sq->stats = sq_stats;
1508
1509         csp.tisn            = tisn;
1510         csp.tis_lst_sz      = 1;
1511         csp.cqn             = sq->cq.mcq.cqn;
1512         csp.wq_ctrl         = &sq->wq_ctrl;
1513         csp.min_inline_mode = sq->min_inline_mode;
1514         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1515         if (err)
1516                 goto err_free_txqsq;
1517
1518         tx_rate = c->priv->tx_rates[sq->txq_ix];
1519         if (tx_rate)
1520                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1521
1522         if (params->tx_dim_enabled)
1523                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1524
1525         return 0;
1526
1527 err_free_txqsq:
1528         mlx5e_free_txqsq(sq);
1529
1530         return err;
1531 }
1532
1533 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1534 {
1535         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1536         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1537         netdev_tx_reset_queue(sq->txq);
1538         netif_tx_start_queue(sq->txq);
1539 }
1540
1541 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1542 {
1543         __netif_tx_lock_bh(txq);
1544         netif_tx_stop_queue(txq);
1545         __netif_tx_unlock_bh(txq);
1546 }
1547
1548 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1549 {
1550         struct mlx5_wq_cyc *wq = &sq->wq;
1551
1552         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1553         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1554
1555         mlx5e_tx_disable_queue(sq->txq);
1556
1557         /* last doorbell out, godspeed .. */
1558         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1559                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1560                 struct mlx5e_tx_wqe *nop;
1561
1562                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1563                         .num_wqebbs = 1,
1564                 };
1565
1566                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1567                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1568         }
1569 }
1570
1571 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1572 {
1573         struct mlx5_core_dev *mdev = sq->mdev;
1574         struct mlx5_rate_limit rl = {0};
1575
1576         cancel_work_sync(&sq->dim.work);
1577         cancel_work_sync(&sq->recover_work);
1578         mlx5e_destroy_sq(mdev, sq->sqn);
1579         if (sq->rate_limit) {
1580                 rl.rate = sq->rate_limit;
1581                 mlx5_rl_remove_rate(mdev, &rl);
1582         }
1583         mlx5e_free_txqsq_descs(sq);
1584         mlx5e_free_txqsq(sq);
1585 }
1586
1587 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1588 {
1589         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1590                                               recover_work);
1591
1592         mlx5e_reporter_tx_err_cqe(sq);
1593 }
1594
1595 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1596                             struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1597                             work_func_t recover_work_func)
1598 {
1599         struct mlx5e_create_sq_param csp = {};
1600         int err;
1601
1602         err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1603         if (err)
1604                 return err;
1605
1606         csp.cqn             = sq->cq.mcq.cqn;
1607         csp.wq_ctrl         = &sq->wq_ctrl;
1608         csp.min_inline_mode = params->tx_min_inline_mode;
1609         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1610         if (err)
1611                 goto err_free_icosq;
1612
1613         if (param->is_tls) {
1614                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1615                 if (IS_ERR(sq->ktls_resync)) {
1616                         err = PTR_ERR(sq->ktls_resync);
1617                         goto err_destroy_icosq;
1618                 }
1619         }
1620         return 0;
1621
1622 err_destroy_icosq:
1623         mlx5e_destroy_sq(c->mdev, sq->sqn);
1624 err_free_icosq:
1625         mlx5e_free_icosq(sq);
1626
1627         return err;
1628 }
1629
1630 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1631 {
1632         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1633 }
1634
1635 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1636 {
1637         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1638         synchronize_net(); /* Sync with NAPI. */
1639 }
1640
1641 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1642 {
1643         struct mlx5e_channel *c = sq->channel;
1644
1645         if (sq->ktls_resync)
1646                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1647         mlx5e_destroy_sq(c->mdev, sq->sqn);
1648         mlx5e_free_icosq_descs(sq);
1649         mlx5e_free_icosq(sq);
1650 }
1651
1652 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1653                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1654                      struct mlx5e_xdpsq *sq, bool is_redirect)
1655 {
1656         struct mlx5e_create_sq_param csp = {};
1657         int err;
1658
1659         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1660         if (err)
1661                 return err;
1662
1663         csp.tis_lst_sz      = 1;
1664         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1665         csp.cqn             = sq->cq.mcq.cqn;
1666         csp.wq_ctrl         = &sq->wq_ctrl;
1667         csp.min_inline_mode = sq->min_inline_mode;
1668         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1669
1670         /* Don't enable multi buffer on XDP_REDIRECT SQ, as it's not yet
1671          * supported by upstream, and there is no defined trigger to allow
1672          * transmitting redirected multi-buffer frames.
1673          */
1674         if (param->is_xdp_mb && !is_redirect)
1675                 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state);
1676
1677         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1678         if (err)
1679                 goto err_free_xdpsq;
1680
1681         mlx5e_set_xmit_fp(sq, param->is_mpw);
1682
1683         if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1684                 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1685                 unsigned int inline_hdr_sz = 0;
1686                 int i;
1687
1688                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1689                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1690                         ds_cnt++;
1691                 }
1692
1693                 /* Pre initialize fixed WQE fields */
1694                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1695                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1696                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1697                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1698                         struct mlx5_wqe_data_seg *dseg;
1699
1700                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1701                                 .num_wqebbs = 1,
1702                                 .num_pkts   = 1,
1703                         };
1704
1705                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1706                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1707
1708                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1709                         dseg->lkey = sq->mkey_be;
1710                 }
1711         }
1712
1713         return 0;
1714
1715 err_free_xdpsq:
1716         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1717         mlx5e_free_xdpsq(sq);
1718
1719         return err;
1720 }
1721
1722 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1723 {
1724         struct mlx5e_channel *c = sq->channel;
1725
1726         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1727         synchronize_net(); /* Sync with NAPI. */
1728
1729         mlx5e_destroy_sq(c->mdev, sq->sqn);
1730         mlx5e_free_xdpsq_descs(sq);
1731         mlx5e_free_xdpsq(sq);
1732 }
1733
1734 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1735                                  struct mlx5e_cq_param *param,
1736                                  struct mlx5e_cq *cq)
1737 {
1738         struct mlx5_core_dev *mdev = priv->mdev;
1739         struct mlx5_core_cq *mcq = &cq->mcq;
1740         int err;
1741         u32 i;
1742
1743         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1744                                &cq->wq_ctrl);
1745         if (err)
1746                 return err;
1747
1748         mcq->cqe_sz     = 64;
1749         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1750         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1751         *mcq->set_ci_db = 0;
1752         *mcq->arm_db    = 0;
1753         mcq->vector     = param->eq_ix;
1754         mcq->comp       = mlx5e_completion_event;
1755         mcq->event      = mlx5e_cq_error_event;
1756
1757         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1758                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1759
1760                 cqe->op_own = 0xf1;
1761         }
1762
1763         cq->mdev = mdev;
1764         cq->netdev = priv->netdev;
1765         cq->priv = priv;
1766
1767         return 0;
1768 }
1769
1770 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1771                           struct mlx5e_cq_param *param,
1772                           struct mlx5e_create_cq_param *ccp,
1773                           struct mlx5e_cq *cq)
1774 {
1775         int err;
1776
1777         param->wq.buf_numa_node = ccp->node;
1778         param->wq.db_numa_node  = ccp->node;
1779         param->eq_ix            = ccp->ix;
1780
1781         err = mlx5e_alloc_cq_common(priv, param, cq);
1782
1783         cq->napi     = ccp->napi;
1784         cq->ch_stats = ccp->ch_stats;
1785
1786         return err;
1787 }
1788
1789 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1790 {
1791         mlx5_wq_destroy(&cq->wq_ctrl);
1792 }
1793
1794 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1795 {
1796         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1797         struct mlx5_core_dev *mdev = cq->mdev;
1798         struct mlx5_core_cq *mcq = &cq->mcq;
1799
1800         void *in;
1801         void *cqc;
1802         int inlen;
1803         int eqn;
1804         int err;
1805
1806         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1807         if (err)
1808                 return err;
1809
1810         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1811                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1812         in = kvzalloc(inlen, GFP_KERNEL);
1813         if (!in)
1814                 return -ENOMEM;
1815
1816         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1817
1818         memcpy(cqc, param->cqc, sizeof(param->cqc));
1819
1820         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1821                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1822
1823         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1824         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
1825         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1826         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1827                                             MLX5_ADAPTER_PAGE_SHIFT);
1828         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1829
1830         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1831
1832         kvfree(in);
1833
1834         if (err)
1835                 return err;
1836
1837         mlx5e_cq_arm(cq);
1838
1839         return 0;
1840 }
1841
1842 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1843 {
1844         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1845 }
1846
1847 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1848                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1849                   struct mlx5e_cq *cq)
1850 {
1851         struct mlx5_core_dev *mdev = priv->mdev;
1852         int err;
1853
1854         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1855         if (err)
1856                 return err;
1857
1858         err = mlx5e_create_cq(cq, param);
1859         if (err)
1860                 goto err_free_cq;
1861
1862         if (MLX5_CAP_GEN(mdev, cq_moderation))
1863                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1864         return 0;
1865
1866 err_free_cq:
1867         mlx5e_free_cq(cq);
1868
1869         return err;
1870 }
1871
1872 void mlx5e_close_cq(struct mlx5e_cq *cq)
1873 {
1874         mlx5e_destroy_cq(cq);
1875         mlx5e_free_cq(cq);
1876 }
1877
1878 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1879                              struct mlx5e_params *params,
1880                              struct mlx5e_create_cq_param *ccp,
1881                              struct mlx5e_channel_param *cparam)
1882 {
1883         int err;
1884         int tc;
1885
1886         for (tc = 0; tc < c->num_tc; tc++) {
1887                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1888                                     ccp, &c->sq[tc].cq);
1889                 if (err)
1890                         goto err_close_tx_cqs;
1891         }
1892
1893         return 0;
1894
1895 err_close_tx_cqs:
1896         for (tc--; tc >= 0; tc--)
1897                 mlx5e_close_cq(&c->sq[tc].cq);
1898
1899         return err;
1900 }
1901
1902 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1903 {
1904         int tc;
1905
1906         for (tc = 0; tc < c->num_tc; tc++)
1907                 mlx5e_close_cq(&c->sq[tc].cq);
1908 }
1909
1910 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
1911 {
1912         int tc;
1913
1914         for (tc = 0; tc < TC_MAX_QUEUE; tc++)
1915                 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
1916                         return tc;
1917
1918         WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
1919         return -ENOENT;
1920 }
1921
1922 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
1923                                         u32 *hw_id)
1924 {
1925         int tc;
1926
1927         if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL ||
1928             !params->mqprio.channel.rl) {
1929                 *hw_id = 0;
1930                 return 0;
1931         }
1932
1933         tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
1934         if (tc < 0)
1935                 return tc;
1936
1937         return mlx5e_mqprio_rl_get_node_hw_id(params->mqprio.channel.rl, tc, hw_id);
1938 }
1939
1940 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1941                           struct mlx5e_params *params,
1942                           struct mlx5e_channel_param *cparam)
1943 {
1944         int err, tc;
1945
1946         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1947                 int txq_ix = c->ix + tc * params->num_channels;
1948                 u32 qos_queue_group_id;
1949
1950                 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
1951                 if (err)
1952                         goto err_close_sqs;
1953
1954                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1955                                        params, &cparam->txq_sq, &c->sq[tc], tc,
1956                                        qos_queue_group_id,
1957                                        &c->priv->channel_stats[c->ix]->sq[tc]);
1958                 if (err)
1959                         goto err_close_sqs;
1960         }
1961
1962         return 0;
1963
1964 err_close_sqs:
1965         for (tc--; tc >= 0; tc--)
1966                 mlx5e_close_txqsq(&c->sq[tc]);
1967
1968         return err;
1969 }
1970
1971 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1972 {
1973         int tc;
1974
1975         for (tc = 0; tc < c->num_tc; tc++)
1976                 mlx5e_close_txqsq(&c->sq[tc]);
1977 }
1978
1979 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1980                                 struct mlx5e_txqsq *sq, u32 rate)
1981 {
1982         struct mlx5e_priv *priv = netdev_priv(dev);
1983         struct mlx5_core_dev *mdev = priv->mdev;
1984         struct mlx5e_modify_sq_param msp = {0};
1985         struct mlx5_rate_limit rl = {0};
1986         u16 rl_index = 0;
1987         int err;
1988
1989         if (rate == sq->rate_limit)
1990                 /* nothing to do */
1991                 return 0;
1992
1993         if (sq->rate_limit) {
1994                 rl.rate = sq->rate_limit;
1995                 /* remove current rl index to free space to next ones */
1996                 mlx5_rl_remove_rate(mdev, &rl);
1997         }
1998
1999         sq->rate_limit = 0;
2000
2001         if (rate) {
2002                 rl.rate = rate;
2003                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
2004                 if (err) {
2005                         netdev_err(dev, "Failed configuring rate %u: %d\n",
2006                                    rate, err);
2007                         return err;
2008                 }
2009         }
2010
2011         msp.curr_state = MLX5_SQC_STATE_RDY;
2012         msp.next_state = MLX5_SQC_STATE_RDY;
2013         msp.rl_index   = rl_index;
2014         msp.rl_update  = true;
2015         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2016         if (err) {
2017                 netdev_err(dev, "Failed configuring rate %u: %d\n",
2018                            rate, err);
2019                 /* remove the rate from the table */
2020                 if (rate)
2021                         mlx5_rl_remove_rate(mdev, &rl);
2022                 return err;
2023         }
2024
2025         sq->rate_limit = rate;
2026         return 0;
2027 }
2028
2029 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2030 {
2031         struct mlx5e_priv *priv = netdev_priv(dev);
2032         struct mlx5_core_dev *mdev = priv->mdev;
2033         struct mlx5e_txqsq *sq = priv->txq2sq[index];
2034         int err = 0;
2035
2036         if (!mlx5_rl_is_supported(mdev)) {
2037                 netdev_err(dev, "Rate limiting is not supported on this device\n");
2038                 return -EINVAL;
2039         }
2040
2041         /* rate is given in Mb/sec, HW config is in Kb/sec */
2042         rate = rate << 10;
2043
2044         /* Check whether rate in valid range, 0 is always valid */
2045         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2046                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2047                 return -ERANGE;
2048         }
2049
2050         mutex_lock(&priv->state_lock);
2051         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2052                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2053         if (!err)
2054                 priv->tx_rates[index] = rate;
2055         mutex_unlock(&priv->state_lock);
2056
2057         return err;
2058 }
2059
2060 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2061                              struct mlx5e_rq_param *rq_params)
2062 {
2063         int err;
2064
2065         err = mlx5e_init_rxq_rq(c, params, &c->rq);
2066         if (err)
2067                 return err;
2068
2069         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2070 }
2071
2072 static int mlx5e_open_queues(struct mlx5e_channel *c,
2073                              struct mlx5e_params *params,
2074                              struct mlx5e_channel_param *cparam)
2075 {
2076         struct dim_cq_moder icocq_moder = {0, 0};
2077         struct mlx5e_create_cq_param ccp;
2078         int err;
2079
2080         mlx5e_build_create_cq_param(&ccp, c);
2081
2082         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2083                             &c->async_icosq.cq);
2084         if (err)
2085                 return err;
2086
2087         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2088                             &c->icosq.cq);
2089         if (err)
2090                 goto err_close_async_icosq_cq;
2091
2092         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2093         if (err)
2094                 goto err_close_icosq_cq;
2095
2096         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2097                             &c->xdpsq.cq);
2098         if (err)
2099                 goto err_close_tx_cqs;
2100
2101         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2102                             &c->rq.cq);
2103         if (err)
2104                 goto err_close_xdp_tx_cqs;
2105
2106         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2107                                      &ccp, &c->rq_xdpsq.cq) : 0;
2108         if (err)
2109                 goto err_close_rx_cq;
2110
2111         spin_lock_init(&c->async_icosq_lock);
2112
2113         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2114                                mlx5e_async_icosq_err_cqe_work);
2115         if (err)
2116                 goto err_close_xdpsq_cq;
2117
2118         mutex_init(&c->icosq_recovery_lock);
2119
2120         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2121                                mlx5e_icosq_err_cqe_work);
2122         if (err)
2123                 goto err_close_async_icosq;
2124
2125         err = mlx5e_open_sqs(c, params, cparam);
2126         if (err)
2127                 goto err_close_icosq;
2128
2129         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2130         if (err)
2131                 goto err_close_sqs;
2132
2133         if (c->xdp) {
2134                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2135                                        &c->rq_xdpsq, false);
2136                 if (err)
2137                         goto err_close_rq;
2138         }
2139
2140         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2141         if (err)
2142                 goto err_close_xdp_sq;
2143
2144         return 0;
2145
2146 err_close_xdp_sq:
2147         if (c->xdp)
2148                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2149
2150 err_close_rq:
2151         mlx5e_close_rq(&c->rq);
2152
2153 err_close_sqs:
2154         mlx5e_close_sqs(c);
2155
2156 err_close_icosq:
2157         mlx5e_close_icosq(&c->icosq);
2158
2159 err_close_async_icosq:
2160         mlx5e_close_icosq(&c->async_icosq);
2161
2162 err_close_xdpsq_cq:
2163         if (c->xdp)
2164                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2165
2166 err_close_rx_cq:
2167         mlx5e_close_cq(&c->rq.cq);
2168
2169 err_close_xdp_tx_cqs:
2170         mlx5e_close_cq(&c->xdpsq.cq);
2171
2172 err_close_tx_cqs:
2173         mlx5e_close_tx_cqs(c);
2174
2175 err_close_icosq_cq:
2176         mlx5e_close_cq(&c->icosq.cq);
2177
2178 err_close_async_icosq_cq:
2179         mlx5e_close_cq(&c->async_icosq.cq);
2180
2181         return err;
2182 }
2183
2184 static void mlx5e_close_queues(struct mlx5e_channel *c)
2185 {
2186         mlx5e_close_xdpsq(&c->xdpsq);
2187         if (c->xdp)
2188                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2189         /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2190         cancel_work_sync(&c->icosq.recover_work);
2191         mlx5e_close_rq(&c->rq);
2192         mlx5e_close_sqs(c);
2193         mlx5e_close_icosq(&c->icosq);
2194         mutex_destroy(&c->icosq_recovery_lock);
2195         mlx5e_close_icosq(&c->async_icosq);
2196         if (c->xdp)
2197                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2198         mlx5e_close_cq(&c->rq.cq);
2199         mlx5e_close_cq(&c->xdpsq.cq);
2200         mlx5e_close_tx_cqs(c);
2201         mlx5e_close_cq(&c->icosq.cq);
2202         mlx5e_close_cq(&c->async_icosq.cq);
2203 }
2204
2205 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2206 {
2207         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2208
2209         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2210 }
2211
2212 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2213 {
2214         if (ix > priv->stats_nch)  {
2215                 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2216                             priv->stats_nch);
2217                 return -EINVAL;
2218         }
2219
2220         if (priv->channel_stats[ix])
2221                 return 0;
2222
2223         /* Asymmetric dynamic memory allocation.
2224          * Freed in mlx5e_priv_arrays_free, not on channel closure.
2225          */
2226         mlx5e_dbg(DRV, priv, "Creating channel stats %d\n", ix);
2227         priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2228                                                 GFP_KERNEL, cpu_to_node(cpu));
2229         if (!priv->channel_stats[ix])
2230                 return -ENOMEM;
2231         priv->stats_nch++;
2232
2233         return 0;
2234 }
2235
2236 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2237                               struct mlx5e_params *params,
2238                               struct mlx5e_channel_param *cparam,
2239                               struct xsk_buff_pool *xsk_pool,
2240                               struct mlx5e_channel **cp)
2241 {
2242         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
2243         struct net_device *netdev = priv->netdev;
2244         struct mlx5e_xsk_param xsk;
2245         struct mlx5e_channel *c;
2246         unsigned int irq;
2247         int err;
2248
2249         err = mlx5_vector2irqn(priv->mdev, ix, &irq);
2250         if (err)
2251                 return err;
2252
2253         err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2254         if (err)
2255                 return err;
2256
2257         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2258         if (!c)
2259                 return -ENOMEM;
2260
2261         c->priv     = priv;
2262         c->mdev     = priv->mdev;
2263         c->tstamp   = &priv->tstamp;
2264         c->ix       = ix;
2265         c->cpu      = cpu;
2266         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2267         c->netdev   = priv->netdev;
2268         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2269         c->num_tc   = mlx5e_get_dcb_num_tc(params);
2270         c->xdp      = !!params->xdp_prog;
2271         c->stats    = &priv->channel_stats[ix]->ch;
2272         c->aff_mask = irq_get_effective_affinity_mask(irq);
2273         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2274
2275         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2276
2277         err = mlx5e_open_queues(c, params, cparam);
2278         if (unlikely(err))
2279                 goto err_napi_del;
2280
2281         if (xsk_pool) {
2282                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2283                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2284                 if (unlikely(err))
2285                         goto err_close_queues;
2286         }
2287
2288         *cp = c;
2289
2290         return 0;
2291
2292 err_close_queues:
2293         mlx5e_close_queues(c);
2294
2295 err_napi_del:
2296         netif_napi_del(&c->napi);
2297
2298         kvfree(c);
2299
2300         return err;
2301 }
2302
2303 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2304 {
2305         int tc;
2306
2307         napi_enable(&c->napi);
2308
2309         for (tc = 0; tc < c->num_tc; tc++)
2310                 mlx5e_activate_txqsq(&c->sq[tc]);
2311         mlx5e_activate_icosq(&c->icosq);
2312         mlx5e_activate_icosq(&c->async_icosq);
2313         mlx5e_activate_rq(&c->rq);
2314
2315         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2316                 mlx5e_activate_xsk(c);
2317 }
2318
2319 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2320 {
2321         int tc;
2322
2323         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2324                 mlx5e_deactivate_xsk(c);
2325
2326         mlx5e_deactivate_rq(&c->rq);
2327         mlx5e_deactivate_icosq(&c->async_icosq);
2328         mlx5e_deactivate_icosq(&c->icosq);
2329         for (tc = 0; tc < c->num_tc; tc++)
2330                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2331         mlx5e_qos_deactivate_queues(c);
2332
2333         napi_disable(&c->napi);
2334 }
2335
2336 static void mlx5e_close_channel(struct mlx5e_channel *c)
2337 {
2338         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2339                 mlx5e_close_xsk(c);
2340         mlx5e_close_queues(c);
2341         mlx5e_qos_close_queues(c);
2342         netif_napi_del(&c->napi);
2343
2344         kvfree(c);
2345 }
2346
2347 int mlx5e_open_channels(struct mlx5e_priv *priv,
2348                         struct mlx5e_channels *chs)
2349 {
2350         struct mlx5e_channel_param *cparam;
2351         int err = -ENOMEM;
2352         int i;
2353
2354         chs->num = chs->params.num_channels;
2355
2356         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2357         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2358         if (!chs->c || !cparam)
2359                 goto err_free;
2360
2361         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2362         if (err)
2363                 goto err_free;
2364
2365         for (i = 0; i < chs->num; i++) {
2366                 struct xsk_buff_pool *xsk_pool = NULL;
2367
2368                 if (chs->params.xdp_prog)
2369                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2370
2371                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2372                 if (err)
2373                         goto err_close_channels;
2374         }
2375
2376         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2377                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2378                 if (err)
2379                         goto err_close_channels;
2380         }
2381
2382         err = mlx5e_qos_open_queues(priv, chs);
2383         if (err)
2384                 goto err_close_ptp;
2385
2386         mlx5e_health_channels_update(priv);
2387         kvfree(cparam);
2388         return 0;
2389
2390 err_close_ptp:
2391         if (chs->ptp)
2392                 mlx5e_ptp_close(chs->ptp);
2393
2394 err_close_channels:
2395         for (i--; i >= 0; i--)
2396                 mlx5e_close_channel(chs->c[i]);
2397
2398 err_free:
2399         kfree(chs->c);
2400         kvfree(cparam);
2401         chs->num = 0;
2402         return err;
2403 }
2404
2405 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2406 {
2407         int i;
2408
2409         for (i = 0; i < chs->num; i++)
2410                 mlx5e_activate_channel(chs->c[i]);
2411
2412         if (chs->ptp)
2413                 mlx5e_ptp_activate_channel(chs->ptp);
2414 }
2415
2416 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2417
2418 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2419 {
2420         int err = 0;
2421         int i;
2422
2423         for (i = 0; i < chs->num; i++) {
2424                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2425
2426                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2427
2428                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2429                  * doesn't provide any Fill Ring entries at the setup stage.
2430                  */
2431         }
2432
2433         return err ? -ETIMEDOUT : 0;
2434 }
2435
2436 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2437 {
2438         int i;
2439
2440         if (chs->ptp)
2441                 mlx5e_ptp_deactivate_channel(chs->ptp);
2442
2443         for (i = 0; i < chs->num; i++)
2444                 mlx5e_deactivate_channel(chs->c[i]);
2445 }
2446
2447 void mlx5e_close_channels(struct mlx5e_channels *chs)
2448 {
2449         int i;
2450
2451         if (chs->ptp) {
2452                 mlx5e_ptp_close(chs->ptp);
2453                 chs->ptp = NULL;
2454         }
2455         for (i = 0; i < chs->num; i++)
2456                 mlx5e_close_channel(chs->c[i]);
2457
2458         kfree(chs->c);
2459         chs->num = 0;
2460 }
2461
2462 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2463 {
2464         struct mlx5e_rx_res *res = priv->rx_res;
2465
2466         return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2467 }
2468
2469 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2470
2471 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2472                          struct mlx5e_params *params, u16 mtu)
2473 {
2474         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2475         int err;
2476
2477         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2478         if (err)
2479                 return err;
2480
2481         /* Update vport context MTU */
2482         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2483         return 0;
2484 }
2485
2486 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2487                             struct mlx5e_params *params, u16 *mtu)
2488 {
2489         u16 hw_mtu = 0;
2490         int err;
2491
2492         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2493         if (err || !hw_mtu) /* fallback to port oper mtu */
2494                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2495
2496         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2497 }
2498
2499 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2500 {
2501         struct mlx5e_params *params = &priv->channels.params;
2502         struct net_device *netdev = priv->netdev;
2503         struct mlx5_core_dev *mdev = priv->mdev;
2504         u16 mtu;
2505         int err;
2506
2507         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2508         if (err)
2509                 return err;
2510
2511         mlx5e_query_mtu(mdev, params, &mtu);
2512         if (mtu != params->sw_mtu)
2513                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2514                             __func__, mtu, params->sw_mtu);
2515
2516         params->sw_mtu = mtu;
2517         return 0;
2518 }
2519
2520 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2521
2522 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2523 {
2524         struct mlx5e_params *params = &priv->channels.params;
2525         struct net_device *netdev   = priv->netdev;
2526         struct mlx5_core_dev *mdev  = priv->mdev;
2527         u16 max_mtu;
2528
2529         /* MTU range: 68 - hw-specific max */
2530         netdev->min_mtu = ETH_MIN_MTU;
2531
2532         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2533         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2534                                 ETH_MAX_MTU);
2535 }
2536
2537 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2538                                 struct netdev_tc_txq *tc_to_txq)
2539 {
2540         int tc, err;
2541
2542         netdev_reset_tc(netdev);
2543
2544         if (ntc == 1)
2545                 return 0;
2546
2547         err = netdev_set_num_tc(netdev, ntc);
2548         if (err) {
2549                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2550                 return err;
2551         }
2552
2553         for (tc = 0; tc < ntc; tc++) {
2554                 u16 count, offset;
2555
2556                 count = tc_to_txq[tc].count;
2557                 offset = tc_to_txq[tc].offset;
2558                 netdev_set_tc_queue(netdev, tc, count, offset);
2559         }
2560
2561         return 0;
2562 }
2563
2564 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2565 {
2566         int qos_queues, nch, ntc, num_txqs, err;
2567
2568         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2569
2570         nch = priv->channels.params.num_channels;
2571         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2572         num_txqs = nch * ntc + qos_queues;
2573         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2574                 num_txqs += ntc;
2575
2576         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2577         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2578         if (err)
2579                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2580
2581         return err;
2582 }
2583
2584 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2585 {
2586         struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2587         struct net_device *netdev = priv->netdev;
2588         int old_num_txqs, old_ntc;
2589         int num_rxqs, nch, ntc;
2590         int err;
2591         int i;
2592
2593         old_num_txqs = netdev->real_num_tx_queues;
2594         old_ntc = netdev->num_tc ? : 1;
2595         for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2596                 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2597
2598         nch = priv->channels.params.num_channels;
2599         ntc = priv->channels.params.mqprio.num_tc;
2600         num_rxqs = nch * priv->profile->rq_groups;
2601         tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2602
2603         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2604         if (err)
2605                 goto err_out;
2606         err = mlx5e_update_tx_netdev_queues(priv);
2607         if (err)
2608                 goto err_tcs;
2609         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2610         if (err) {
2611                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2612                 goto err_txqs;
2613         }
2614         if (priv->mqprio_rl != priv->channels.params.mqprio.channel.rl) {
2615                 if (priv->mqprio_rl) {
2616                         mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
2617                         mlx5e_mqprio_rl_free(priv->mqprio_rl);
2618                 }
2619                 priv->mqprio_rl = priv->channels.params.mqprio.channel.rl;
2620         }
2621
2622         return 0;
2623
2624 err_txqs:
2625         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2626          * one of nch and ntc is changed in this function. That means, the call
2627          * to netif_set_real_num_tx_queues below should not fail, because it
2628          * decreases the number of TX queues.
2629          */
2630         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2631
2632 err_tcs:
2633         WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2634                                           old_tc_to_txq));
2635 err_out:
2636         return err;
2637 }
2638
2639 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2640
2641 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2642                                            struct mlx5e_params *params)
2643 {
2644         struct mlx5_core_dev *mdev = priv->mdev;
2645         int num_comp_vectors, ix, irq;
2646
2647         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2648
2649         for (ix = 0; ix < params->num_channels; ix++) {
2650                 cpumask_clear(priv->scratchpad.cpumask);
2651
2652                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2653                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2654
2655                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2656                 }
2657
2658                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2659         }
2660 }
2661
2662 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2663 {
2664         u16 count = priv->channels.params.num_channels;
2665         int err;
2666
2667         err = mlx5e_update_netdev_queues(priv);
2668         if (err)
2669                 return err;
2670
2671         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2672
2673         /* This function may be called on attach, before priv->rx_res is created. */
2674         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2675                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2676
2677         return 0;
2678 }
2679
2680 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2681
2682 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2683 {
2684         int i, ch, tc, num_tc;
2685
2686         ch = priv->channels.num;
2687         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2688
2689         for (i = 0; i < ch; i++) {
2690                 for (tc = 0; tc < num_tc; tc++) {
2691                         struct mlx5e_channel *c = priv->channels.c[i];
2692                         struct mlx5e_txqsq *sq = &c->sq[tc];
2693
2694                         priv->txq2sq[sq->txq_ix] = sq;
2695                 }
2696         }
2697
2698         if (!priv->channels.ptp)
2699                 goto out;
2700
2701         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2702                 goto out;
2703
2704         for (tc = 0; tc < num_tc; tc++) {
2705                 struct mlx5e_ptp *c = priv->channels.ptp;
2706                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2707
2708                 priv->txq2sq[sq->txq_ix] = sq;
2709         }
2710
2711 out:
2712         /* Make the change to txq2sq visible before the queue is started.
2713          * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
2714          * which pairs with this barrier.
2715          */
2716         smp_wmb();
2717 }
2718
2719 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2720 {
2721         mlx5e_build_txq_maps(priv);
2722         mlx5e_activate_channels(&priv->channels);
2723         mlx5e_qos_activate_queues(priv);
2724         mlx5e_xdp_tx_enable(priv);
2725
2726         /* dev_watchdog() wants all TX queues to be started when the carrier is
2727          * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
2728          * Make it happy to avoid TX timeout false alarms.
2729          */
2730         netif_tx_start_all_queues(priv->netdev);
2731
2732         if (mlx5e_is_vport_rep(priv))
2733                 mlx5e_add_sqs_fwd_rules(priv);
2734
2735         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2736
2737         if (priv->rx_res)
2738                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2739 }
2740
2741 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2742 {
2743         if (priv->rx_res)
2744                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2745
2746         if (mlx5e_is_vport_rep(priv))
2747                 mlx5e_remove_sqs_fwd_rules(priv);
2748
2749         /* The results of ndo_select_queue are unreliable, while netdev config
2750          * is being changed (real_num_tx_queues, num_tc). Stop all queues to
2751          * prevent ndo_start_xmit from being called, so that it can assume that
2752          * the selected queue is always valid.
2753          */
2754         netif_tx_disable(priv->netdev);
2755
2756         mlx5e_xdp_tx_disable(priv);
2757         mlx5e_deactivate_channels(&priv->channels);
2758 }
2759
2760 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2761                                     struct mlx5e_params *new_params,
2762                                     mlx5e_fp_preactivate preactivate,
2763                                     void *context)
2764 {
2765         struct mlx5e_params old_params;
2766
2767         old_params = priv->channels.params;
2768         priv->channels.params = *new_params;
2769
2770         if (preactivate) {
2771                 int err;
2772
2773                 err = preactivate(priv, context);
2774                 if (err) {
2775                         priv->channels.params = old_params;
2776                         return err;
2777                 }
2778         }
2779
2780         return 0;
2781 }
2782
2783 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2784                                       struct mlx5e_channels *new_chs,
2785                                       mlx5e_fp_preactivate preactivate,
2786                                       void *context)
2787 {
2788         struct net_device *netdev = priv->netdev;
2789         struct mlx5e_channels old_chs;
2790         int carrier_ok;
2791         int err = 0;
2792
2793         carrier_ok = netif_carrier_ok(netdev);
2794         netif_carrier_off(netdev);
2795
2796         mlx5e_deactivate_priv_channels(priv);
2797
2798         old_chs = priv->channels;
2799         priv->channels = *new_chs;
2800
2801         /* New channels are ready to roll, call the preactivate hook if needed
2802          * to modify HW settings or update kernel parameters.
2803          */
2804         if (preactivate) {
2805                 err = preactivate(priv, context);
2806                 if (err) {
2807                         priv->channels = old_chs;
2808                         goto out;
2809                 }
2810         }
2811
2812         mlx5e_close_channels(&old_chs);
2813         priv->profile->update_rx(priv);
2814
2815         mlx5e_selq_apply(&priv->selq);
2816 out:
2817         mlx5e_activate_priv_channels(priv);
2818
2819         /* return carrier back if needed */
2820         if (carrier_ok)
2821                 netif_carrier_on(netdev);
2822
2823         return err;
2824 }
2825
2826 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2827                              struct mlx5e_params *params,
2828                              mlx5e_fp_preactivate preactivate,
2829                              void *context, bool reset)
2830 {
2831         struct mlx5e_channels new_chs = {};
2832         int err;
2833
2834         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2835         if (!reset)
2836                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2837
2838         new_chs.params = *params;
2839
2840         mlx5e_selq_prepare(&priv->selq, &new_chs.params, !!priv->htb.maj_id);
2841
2842         err = mlx5e_open_channels(priv, &new_chs);
2843         if (err)
2844                 goto err_cancel_selq;
2845
2846         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2847         if (err)
2848                 goto err_close;
2849
2850         return 0;
2851
2852 err_close:
2853         mlx5e_close_channels(&new_chs);
2854
2855 err_cancel_selq:
2856         mlx5e_selq_cancel(&priv->selq);
2857         return err;
2858 }
2859
2860 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2861 {
2862         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2863 }
2864
2865 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2866 {
2867         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2868         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2869 }
2870
2871 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2872                                      enum mlx5_port_status state)
2873 {
2874         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2875         int vport_admin_state;
2876
2877         mlx5_set_port_admin_status(mdev, state);
2878
2879         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2880             !MLX5_CAP_GEN(mdev, uplink_follow))
2881                 return;
2882
2883         if (state == MLX5_PORT_UP)
2884                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2885         else
2886                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2887
2888         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2889 }
2890
2891 int mlx5e_open_locked(struct net_device *netdev)
2892 {
2893         struct mlx5e_priv *priv = netdev_priv(netdev);
2894         int err;
2895
2896         mlx5e_selq_prepare(&priv->selq, &priv->channels.params, !!priv->htb.maj_id);
2897
2898         set_bit(MLX5E_STATE_OPENED, &priv->state);
2899
2900         err = mlx5e_open_channels(priv, &priv->channels);
2901         if (err)
2902                 goto err_clear_state_opened_flag;
2903
2904         priv->profile->update_rx(priv);
2905         mlx5e_selq_apply(&priv->selq);
2906         mlx5e_activate_priv_channels(priv);
2907         mlx5e_apply_traps(priv, true);
2908         if (priv->profile->update_carrier)
2909                 priv->profile->update_carrier(priv);
2910
2911         mlx5e_queue_update_stats(priv);
2912         return 0;
2913
2914 err_clear_state_opened_flag:
2915         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2916         mlx5e_selq_cancel(&priv->selq);
2917         return err;
2918 }
2919
2920 int mlx5e_open(struct net_device *netdev)
2921 {
2922         struct mlx5e_priv *priv = netdev_priv(netdev);
2923         int err;
2924
2925         mutex_lock(&priv->state_lock);
2926         err = mlx5e_open_locked(netdev);
2927         if (!err)
2928                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2929         mutex_unlock(&priv->state_lock);
2930
2931         return err;
2932 }
2933
2934 int mlx5e_close_locked(struct net_device *netdev)
2935 {
2936         struct mlx5e_priv *priv = netdev_priv(netdev);
2937
2938         /* May already be CLOSED in case a previous configuration operation
2939          * (e.g RX/TX queue size change) that involves close&open failed.
2940          */
2941         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2942                 return 0;
2943
2944         mlx5e_apply_traps(priv, false);
2945         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2946
2947         netif_carrier_off(priv->netdev);
2948         mlx5e_deactivate_priv_channels(priv);
2949         mlx5e_close_channels(&priv->channels);
2950
2951         return 0;
2952 }
2953
2954 int mlx5e_close(struct net_device *netdev)
2955 {
2956         struct mlx5e_priv *priv = netdev_priv(netdev);
2957         int err;
2958
2959         if (!netif_device_present(netdev))
2960                 return -ENODEV;
2961
2962         mutex_lock(&priv->state_lock);
2963         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2964         err = mlx5e_close_locked(netdev);
2965         mutex_unlock(&priv->state_lock);
2966
2967         return err;
2968 }
2969
2970 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2971 {
2972         mlx5_wq_destroy(&rq->wq_ctrl);
2973 }
2974
2975 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2976                                struct mlx5e_rq *rq,
2977                                struct mlx5e_rq_param *param)
2978 {
2979         void *rqc = param->rqc;
2980         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2981         int err;
2982
2983         param->wq.db_numa_node = param->wq.buf_numa_node;
2984
2985         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2986                                  &rq->wq_ctrl);
2987         if (err)
2988                 return err;
2989
2990         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2991         xdp_rxq_info_unused(&rq->xdp_rxq);
2992
2993         rq->mdev = mdev;
2994
2995         return 0;
2996 }
2997
2998 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2999                                struct mlx5e_cq *cq,
3000                                struct mlx5e_cq_param *param)
3001 {
3002         struct mlx5_core_dev *mdev = priv->mdev;
3003
3004         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3005         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3006
3007         return mlx5e_alloc_cq_common(priv, param, cq);
3008 }
3009
3010 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3011                        struct mlx5e_rq *drop_rq)
3012 {
3013         struct mlx5_core_dev *mdev = priv->mdev;
3014         struct mlx5e_cq_param cq_param = {};
3015         struct mlx5e_rq_param rq_param = {};
3016         struct mlx5e_cq *cq = &drop_rq->cq;
3017         int err;
3018
3019         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3020
3021         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3022         if (err)
3023                 return err;
3024
3025         err = mlx5e_create_cq(cq, &cq_param);
3026         if (err)
3027                 goto err_free_cq;
3028
3029         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3030         if (err)
3031                 goto err_destroy_cq;
3032
3033         err = mlx5e_create_rq(drop_rq, &rq_param);
3034         if (err)
3035                 goto err_free_rq;
3036
3037         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3038         if (err)
3039                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3040
3041         return 0;
3042
3043 err_free_rq:
3044         mlx5e_free_drop_rq(drop_rq);
3045
3046 err_destroy_cq:
3047         mlx5e_destroy_cq(cq);
3048
3049 err_free_cq:
3050         mlx5e_free_cq(cq);
3051
3052         return err;
3053 }
3054
3055 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3056 {
3057         mlx5e_destroy_rq(drop_rq);
3058         mlx5e_free_drop_rq(drop_rq);
3059         mlx5e_destroy_cq(&drop_rq->cq);
3060         mlx5e_free_cq(&drop_rq->cq);
3061 }
3062
3063 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3064 {
3065         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3066
3067         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3068
3069         if (MLX5_GET(tisc, tisc, tls_en))
3070                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3071
3072         if (mlx5_lag_is_lacp_owner(mdev))
3073                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3074
3075         return mlx5_core_create_tis(mdev, in, tisn);
3076 }
3077
3078 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3079 {
3080         mlx5_core_destroy_tis(mdev, tisn);
3081 }
3082
3083 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3084 {
3085         int tc, i;
3086
3087         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3088                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3089                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3090 }
3091
3092 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3093 {
3094         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3095 }
3096
3097 int mlx5e_create_tises(struct mlx5e_priv *priv)
3098 {
3099         int tc, i;
3100         int err;
3101
3102         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3103                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3104                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3105                         void *tisc;
3106
3107                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3108
3109                         MLX5_SET(tisc, tisc, prio, tc << 1);
3110
3111                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3112                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3113
3114                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3115                         if (err)
3116                                 goto err_close_tises;
3117                 }
3118         }
3119
3120         return 0;
3121
3122 err_close_tises:
3123         for (; i >= 0; i--) {
3124                 for (tc--; tc >= 0; tc--)
3125                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3126                 tc = priv->profile->max_tc;
3127         }
3128
3129         return err;
3130 }
3131
3132 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3133 {
3134         mlx5e_destroy_tises(priv);
3135 }
3136
3137 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3138 {
3139         int err = 0;
3140         int i;
3141
3142         for (i = 0; i < chs->num; i++) {
3143                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3144                 if (err)
3145                         return err;
3146         }
3147
3148         return 0;
3149 }
3150
3151 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3152 {
3153         int err;
3154         int i;
3155
3156         for (i = 0; i < chs->num; i++) {
3157                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3158                 if (err)
3159                         return err;
3160         }
3161         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3162                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3163
3164         return 0;
3165 }
3166
3167 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3168                                                  int ntc, int nch)
3169 {
3170         int tc;
3171
3172         memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3173
3174         /* Map netdev TCs to offset 0.
3175          * We have our own UP to TXQ mapping for DCB mode of QoS
3176          */
3177         for (tc = 0; tc < ntc; tc++) {
3178                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3179                         .count = nch,
3180                         .offset = 0,
3181                 };
3182         }
3183 }
3184
3185 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3186                                          struct tc_mqprio_qopt *qopt)
3187 {
3188         int tc;
3189
3190         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3191                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3192                         .count = qopt->count[tc],
3193                         .offset = qopt->offset[tc],
3194                 };
3195         }
3196 }
3197
3198 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3199 {
3200         params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3201         params->mqprio.num_tc = num_tc;
3202         params->mqprio.channel.rl = NULL;
3203         mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3204                                              params->num_channels);
3205 }
3206
3207 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3208                                             struct tc_mqprio_qopt *qopt,
3209                                             struct mlx5e_mqprio_rl *rl)
3210 {
3211         params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3212         params->mqprio.num_tc = qopt->num_tc;
3213         params->mqprio.channel.rl = rl;
3214         mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
3215 }
3216
3217 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3218 {
3219         mlx5e_params_mqprio_dcb_set(params, 1);
3220 }
3221
3222 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3223                                      struct tc_mqprio_qopt *mqprio)
3224 {
3225         struct mlx5e_params new_params;
3226         u8 tc = mqprio->num_tc;
3227         int err;
3228
3229         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3230
3231         if (tc && tc != MLX5E_MAX_NUM_TC)
3232                 return -EINVAL;
3233
3234         new_params = priv->channels.params;
3235         mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3236
3237         err = mlx5e_safe_switch_params(priv, &new_params,
3238                                        mlx5e_num_channels_changed_ctx, NULL, true);
3239
3240         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3241                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
3242         return err;
3243 }
3244
3245 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3246                                          struct tc_mqprio_qopt_offload *mqprio)
3247 {
3248         struct net_device *netdev = priv->netdev;
3249         struct mlx5e_ptp *ptp_channel;
3250         int agg_count = 0;
3251         int i;
3252
3253         ptp_channel = priv->channels.ptp;
3254         if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3255                 netdev_err(netdev,
3256                            "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3257                 return -EINVAL;
3258         }
3259
3260         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3261             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3262                 return -EINVAL;
3263
3264         for (i = 0; i < mqprio->qopt.num_tc; i++) {
3265                 if (!mqprio->qopt.count[i]) {
3266                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3267                         return -EINVAL;
3268                 }
3269                 if (mqprio->min_rate[i]) {
3270                         netdev_err(netdev, "Min tx rate is not supported\n");
3271                         return -EINVAL;
3272                 }
3273
3274                 if (mqprio->max_rate[i]) {
3275                         int err;
3276
3277                         err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3278                         if (err)
3279                                 return err;
3280                 }
3281
3282                 if (mqprio->qopt.offset[i] != agg_count) {
3283                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
3284                         return -EINVAL;
3285                 }
3286                 agg_count += mqprio->qopt.count[i];
3287         }
3288
3289         if (priv->channels.params.num_channels != agg_count) {
3290                 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3291                            agg_count, priv->channels.params.num_channels);
3292                 return -EINVAL;
3293         }
3294
3295         return 0;
3296 }
3297
3298 static bool mlx5e_mqprio_rate_limit(struct tc_mqprio_qopt_offload *mqprio)
3299 {
3300         int tc;
3301
3302         for (tc = 0; tc < mqprio->qopt.num_tc; tc++)
3303                 if (mqprio->max_rate[tc])
3304                         return true;
3305         return false;
3306 }
3307
3308 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3309                                          struct tc_mqprio_qopt_offload *mqprio)
3310 {
3311         mlx5e_fp_preactivate preactivate;
3312         struct mlx5e_params new_params;
3313         struct mlx5e_mqprio_rl *rl;
3314         bool nch_changed;
3315         int err;
3316
3317         err = mlx5e_mqprio_channel_validate(priv, mqprio);
3318         if (err)
3319                 return err;
3320
3321         rl = NULL;
3322         if (mlx5e_mqprio_rate_limit(mqprio)) {
3323                 rl = mlx5e_mqprio_rl_alloc();
3324                 if (!rl)
3325                         return -ENOMEM;
3326                 err = mlx5e_mqprio_rl_init(rl, priv->mdev, mqprio->qopt.num_tc,
3327                                            mqprio->max_rate);
3328                 if (err) {
3329                         mlx5e_mqprio_rl_free(rl);
3330                         return err;
3331                 }
3332         }
3333
3334         new_params = priv->channels.params;
3335         mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt, rl);
3336
3337         nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3338         preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3339                 mlx5e_update_netdev_queues_ctx;
3340         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3341         if (err && rl) {
3342                 mlx5e_mqprio_rl_cleanup(rl);
3343                 mlx5e_mqprio_rl_free(rl);
3344         }
3345
3346         return err;
3347 }
3348
3349 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3350                                  struct tc_mqprio_qopt_offload *mqprio)
3351 {
3352         /* MQPRIO is another toplevel qdisc that can't be attached
3353          * simultaneously with the offloaded HTB.
3354          */
3355         if (WARN_ON(priv->htb.maj_id))
3356                 return -EINVAL;
3357
3358         switch (mqprio->mode) {
3359         case TC_MQPRIO_MODE_DCB:
3360                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3361         case TC_MQPRIO_MODE_CHANNEL:
3362                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3363         default:
3364                 return -EOPNOTSUPP;
3365         }
3366 }
3367
3368 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3369 {
3370         int res;
3371
3372         switch (htb->command) {
3373         case TC_HTB_CREATE:
3374                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3375                                           htb->extack);
3376         case TC_HTB_DESTROY:
3377                 return mlx5e_htb_root_del(priv);
3378         case TC_HTB_LEAF_ALLOC_QUEUE:
3379                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3380                                                  htb->rate, htb->ceil, htb->extack);
3381                 if (res < 0)
3382                         return res;
3383                 htb->qid = res;
3384                 return 0;
3385         case TC_HTB_LEAF_TO_INNER:
3386                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3387                                                htb->rate, htb->ceil, htb->extack);
3388         case TC_HTB_LEAF_DEL:
3389                 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3390         case TC_HTB_LEAF_DEL_LAST:
3391         case TC_HTB_LEAF_DEL_LAST_FORCE:
3392                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3393                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3394                                                htb->extack);
3395         case TC_HTB_NODE_MODIFY:
3396                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3397                                              htb->extack);
3398         case TC_HTB_LEAF_QUERY_QUEUE:
3399                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3400                 if (res < 0)
3401                         return res;
3402                 htb->qid = res;
3403                 return 0;
3404         default:
3405                 return -EOPNOTSUPP;
3406         }
3407 }
3408
3409 static LIST_HEAD(mlx5e_block_cb_list);
3410
3411 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3412                           void *type_data)
3413 {
3414         struct mlx5e_priv *priv = netdev_priv(dev);
3415         bool tc_unbind = false;
3416         int err;
3417
3418         if (type == TC_SETUP_BLOCK &&
3419             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3420                 tc_unbind = true;
3421
3422         if (!netif_device_present(dev) && !tc_unbind)
3423                 return -ENODEV;
3424
3425         switch (type) {
3426         case TC_SETUP_BLOCK: {
3427                 struct flow_block_offload *f = type_data;
3428
3429                 f->unlocked_driver_cb = true;
3430                 return flow_block_cb_setup_simple(type_data,
3431                                                   &mlx5e_block_cb_list,
3432                                                   mlx5e_setup_tc_block_cb,
3433                                                   priv, priv, true);
3434         }
3435         case TC_SETUP_QDISC_MQPRIO:
3436                 mutex_lock(&priv->state_lock);
3437                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3438                 mutex_unlock(&priv->state_lock);
3439                 return err;
3440         case TC_SETUP_QDISC_HTB:
3441                 mutex_lock(&priv->state_lock);
3442                 err = mlx5e_setup_tc_htb(priv, type_data);
3443                 mutex_unlock(&priv->state_lock);
3444                 return err;
3445         default:
3446                 return -EOPNOTSUPP;
3447         }
3448 }
3449
3450 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3451 {
3452         int i;
3453
3454         for (i = 0; i < priv->stats_nch; i++) {
3455                 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3456                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3457                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3458                 int j;
3459
3460                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3461                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3462                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3463
3464                 for (j = 0; j < priv->max_opened_tc; j++) {
3465                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3466
3467                         s->tx_packets    += sq_stats->packets;
3468                         s->tx_bytes      += sq_stats->bytes;
3469                         s->tx_dropped    += sq_stats->dropped;
3470                 }
3471         }
3472         if (priv->tx_ptp_opened) {
3473                 for (i = 0; i < priv->max_opened_tc; i++) {
3474                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3475
3476                         s->tx_packets    += sq_stats->packets;
3477                         s->tx_bytes      += sq_stats->bytes;
3478                         s->tx_dropped    += sq_stats->dropped;
3479                 }
3480         }
3481         if (priv->rx_ptp_opened) {
3482                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3483
3484                 s->rx_packets   += rq_stats->packets;
3485                 s->rx_bytes     += rq_stats->bytes;
3486                 s->multicast    += rq_stats->mcast_packets;
3487         }
3488 }
3489
3490 void
3491 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3492 {
3493         struct mlx5e_priv *priv = netdev_priv(dev);
3494         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3495
3496         if (!netif_device_present(dev))
3497                 return;
3498
3499         /* In switchdev mode, monitor counters doesn't monitor
3500          * rx/tx stats of 802_3. The update stats mechanism
3501          * should keep the 802_3 layout counters updated
3502          */
3503         if (!mlx5e_monitor_counter_supported(priv) ||
3504             mlx5e_is_uplink_rep(priv)) {
3505                 /* update HW stats in background for next time */
3506                 mlx5e_queue_update_stats(priv);
3507         }
3508
3509         if (mlx5e_is_uplink_rep(priv)) {
3510                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3511
3512                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3513                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3514                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3515                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3516
3517                 /* vport multicast also counts packets that are dropped due to steering
3518                  * or rx out of buffer
3519                  */
3520                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3521         } else {
3522                 mlx5e_fold_sw_stats64(priv, stats);
3523         }
3524
3525         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3526
3527         stats->rx_length_errors =
3528                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3529                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3530                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3531         stats->rx_crc_errors =
3532                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3533         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3534         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3535         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3536                            stats->rx_frame_errors;
3537         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3538 }
3539
3540 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3541 {
3542         if (mlx5e_is_uplink_rep(priv))
3543                 return; /* no rx mode for uplink rep */
3544
3545         queue_work(priv->wq, &priv->set_rx_mode_work);
3546 }
3547
3548 static void mlx5e_set_rx_mode(struct net_device *dev)
3549 {
3550         struct mlx5e_priv *priv = netdev_priv(dev);
3551
3552         mlx5e_nic_set_rx_mode(priv);
3553 }
3554
3555 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3556 {
3557         struct mlx5e_priv *priv = netdev_priv(netdev);
3558         struct sockaddr *saddr = addr;
3559
3560         if (!is_valid_ether_addr(saddr->sa_data))
3561                 return -EADDRNOTAVAIL;
3562
3563         netif_addr_lock_bh(netdev);
3564         eth_hw_addr_set(netdev, saddr->sa_data);
3565         netif_addr_unlock_bh(netdev);
3566
3567         mlx5e_nic_set_rx_mode(priv);
3568
3569         return 0;
3570 }
3571
3572 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3573         do {                                            \
3574                 if (enable)                             \
3575                         *features |= feature;           \
3576                 else                                    \
3577                         *features &= ~feature;          \
3578         } while (0)
3579
3580 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3581
3582 static int set_feature_lro(struct net_device *netdev, bool enable)
3583 {
3584         struct mlx5e_priv *priv = netdev_priv(netdev);
3585         struct mlx5_core_dev *mdev = priv->mdev;
3586         struct mlx5e_params *cur_params;
3587         struct mlx5e_params new_params;
3588         bool reset = true;
3589         int err = 0;
3590
3591         mutex_lock(&priv->state_lock);
3592
3593         if (enable && priv->xsk.refcnt) {
3594                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3595                             priv->xsk.refcnt);
3596                 err = -EINVAL;
3597                 goto out;
3598         }
3599
3600         cur_params = &priv->channels.params;
3601         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3602                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3603                 err = -EINVAL;
3604                 goto out;
3605         }
3606
3607         new_params = *cur_params;
3608
3609         if (enable)
3610                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3611         else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3612                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3613         else
3614                 goto out;
3615
3616         if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3617               new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3618                 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3619                         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3620                             mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3621                                 reset = false;
3622                 }
3623         }
3624
3625         err = mlx5e_safe_switch_params(priv, &new_params,
3626                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3627 out:
3628         mutex_unlock(&priv->state_lock);
3629         return err;
3630 }
3631
3632 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3633 {
3634         struct mlx5e_priv *priv = netdev_priv(netdev);
3635         struct mlx5e_params new_params;
3636         bool reset = true;
3637         int err = 0;
3638
3639         mutex_lock(&priv->state_lock);
3640         new_params = priv->channels.params;
3641
3642         if (enable) {
3643                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3644                 new_params.packet_merge.shampo.match_criteria_type =
3645                         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3646                 new_params.packet_merge.shampo.alignment_granularity =
3647                         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3648         } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3649                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3650         } else {
3651                 goto out;
3652         }
3653
3654         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3655 out:
3656         mutex_unlock(&priv->state_lock);
3657         return err;
3658 }
3659
3660 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3661 {
3662         struct mlx5e_priv *priv = netdev_priv(netdev);
3663
3664         if (enable)
3665                 mlx5e_enable_cvlan_filter(priv);
3666         else
3667                 mlx5e_disable_cvlan_filter(priv);
3668
3669         return 0;
3670 }
3671
3672 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3673 {
3674         struct mlx5e_priv *priv = netdev_priv(netdev);
3675
3676 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3677         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3678                 netdev_err(netdev,
3679                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3680                 return -EINVAL;
3681         }
3682 #endif
3683
3684         if (!enable && priv->htb.maj_id) {
3685                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3686                 return -EINVAL;
3687         }
3688
3689         return 0;
3690 }
3691
3692 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3693 {
3694         struct mlx5e_priv *priv = netdev_priv(netdev);
3695         struct mlx5_core_dev *mdev = priv->mdev;
3696
3697         return mlx5_set_port_fcs(mdev, !enable);
3698 }
3699
3700 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3701 {
3702         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3703         bool supported, curr_state;
3704         int err;
3705
3706         if (!MLX5_CAP_GEN(mdev, ports_check))
3707                 return 0;
3708
3709         err = mlx5_query_ports_check(mdev, in, sizeof(in));
3710         if (err)
3711                 return err;
3712
3713         supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3714         curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3715
3716         if (!supported || enable == curr_state)
3717                 return 0;
3718
3719         MLX5_SET(pcmr_reg, in, local_port, 1);
3720         MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3721
3722         return mlx5_set_ports_check(mdev, in, sizeof(in));
3723 }
3724
3725 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3726 {
3727         struct mlx5e_priv *priv = netdev_priv(netdev);
3728         struct mlx5e_channels *chs = &priv->channels;
3729         struct mlx5_core_dev *mdev = priv->mdev;
3730         int err;
3731
3732         mutex_lock(&priv->state_lock);
3733
3734         if (enable) {
3735                 err = mlx5e_set_rx_port_ts(mdev, false);
3736                 if (err)
3737                         goto out;
3738
3739                 chs->params.scatter_fcs_en = true;
3740                 err = mlx5e_modify_channels_scatter_fcs(chs, true);
3741                 if (err) {
3742                         chs->params.scatter_fcs_en = false;
3743                         mlx5e_set_rx_port_ts(mdev, true);
3744                 }
3745         } else {
3746                 chs->params.scatter_fcs_en = false;
3747                 err = mlx5e_modify_channels_scatter_fcs(chs, false);
3748                 if (err) {
3749                         chs->params.scatter_fcs_en = true;
3750                         goto out;
3751                 }
3752                 err = mlx5e_set_rx_port_ts(mdev, true);
3753                 if (err) {
3754                         mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
3755                         err = 0;
3756                 }
3757         }
3758
3759 out:
3760         mutex_unlock(&priv->state_lock);
3761         return err;
3762 }
3763
3764 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3765 {
3766         struct mlx5e_priv *priv = netdev_priv(netdev);
3767         int err = 0;
3768
3769         mutex_lock(&priv->state_lock);
3770
3771         priv->channels.params.vlan_strip_disable = !enable;
3772         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3773                 goto unlock;
3774
3775         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3776         if (err)
3777                 priv->channels.params.vlan_strip_disable = enable;
3778
3779 unlock:
3780         mutex_unlock(&priv->state_lock);
3781
3782         return err;
3783 }
3784
3785 #ifdef CONFIG_MLX5_EN_ARFS
3786 static int set_feature_arfs(struct net_device *netdev, bool enable)
3787 {
3788         struct mlx5e_priv *priv = netdev_priv(netdev);
3789         int err;
3790
3791         if (enable)
3792                 err = mlx5e_arfs_enable(priv);
3793         else
3794                 err = mlx5e_arfs_disable(priv);
3795
3796         return err;
3797 }
3798 #endif
3799
3800 static int mlx5e_handle_feature(struct net_device *netdev,
3801                                 netdev_features_t *features,
3802                                 netdev_features_t feature,
3803                                 mlx5e_feature_handler feature_handler)
3804 {
3805         netdev_features_t changes = *features ^ netdev->features;
3806         bool enable = !!(*features & feature);
3807         int err;
3808
3809         if (!(changes & feature))
3810                 return 0;
3811
3812         err = feature_handler(netdev, enable);
3813         if (err) {
3814                 MLX5E_SET_FEATURE(features, feature, !enable);
3815                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3816                            enable ? "Enable" : "Disable", &feature, err);
3817                 return err;
3818         }
3819
3820         return 0;
3821 }
3822
3823 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3824 {
3825         netdev_features_t oper_features = features;
3826         int err = 0;
3827
3828 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3829         mlx5e_handle_feature(netdev, &oper_features, feature, handler)
3830
3831         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3832         err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
3833         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3834                                     set_feature_cvlan_filter);
3835         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3836         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3837         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3838         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3839 #ifdef CONFIG_MLX5_EN_ARFS
3840         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3841 #endif
3842         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3843
3844         if (err) {
3845                 netdev->features = oper_features;
3846                 return -EINVAL;
3847         }
3848
3849         return 0;
3850 }
3851
3852 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3853                                                        netdev_features_t features)
3854 {
3855         features &= ~NETIF_F_HW_TLS_RX;
3856         if (netdev->features & NETIF_F_HW_TLS_RX)
3857                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3858
3859         features &= ~NETIF_F_HW_TLS_TX;
3860         if (netdev->features & NETIF_F_HW_TLS_TX)
3861                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3862
3863         features &= ~NETIF_F_NTUPLE;
3864         if (netdev->features & NETIF_F_NTUPLE)
3865                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3866
3867         features &= ~NETIF_F_GRO_HW;
3868         if (netdev->features & NETIF_F_GRO_HW)
3869                 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n");
3870
3871         return features;
3872 }
3873
3874 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3875                                             netdev_features_t features)
3876 {
3877         struct mlx5e_priv *priv = netdev_priv(netdev);
3878         struct mlx5e_params *params;
3879
3880         mutex_lock(&priv->state_lock);
3881         params = &priv->channels.params;
3882         if (!priv->fs.vlan ||
3883             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3884                 /* HW strips the outer C-tag header, this is a problem
3885                  * for S-tag traffic.
3886                  */
3887                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3888                 if (!params->vlan_strip_disable)
3889                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3890         }
3891
3892         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3893                 if (features & NETIF_F_LRO) {
3894                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3895                         features &= ~NETIF_F_LRO;
3896                 }
3897                 if (features & NETIF_F_GRO_HW) {
3898                         netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
3899                         features &= ~NETIF_F_GRO_HW;
3900                 }
3901         }
3902
3903         if (params->xdp_prog) {
3904                 if (features & NETIF_F_LRO) {
3905                         netdev_warn(netdev, "LRO is incompatible with XDP\n");
3906                         features &= ~NETIF_F_LRO;
3907                 }
3908                 if (features & NETIF_F_GRO_HW) {
3909                         netdev_warn(netdev, "HW GRO is incompatible with XDP\n");
3910                         features &= ~NETIF_F_GRO_HW;
3911                 }
3912         }
3913
3914         if (priv->xsk.refcnt) {
3915                 if (features & NETIF_F_GRO_HW) {
3916                         netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
3917                                     priv->xsk.refcnt);
3918                         features &= ~NETIF_F_GRO_HW;
3919                 }
3920         }
3921
3922         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3923                 features &= ~NETIF_F_RXHASH;
3924                 if (netdev->features & NETIF_F_RXHASH)
3925                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3926
3927                 if (features & NETIF_F_GRO_HW) {
3928                         netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
3929                         features &= ~NETIF_F_GRO_HW;
3930                 }
3931         }
3932
3933         if (mlx5e_is_uplink_rep(priv))
3934                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3935
3936         mutex_unlock(&priv->state_lock);
3937
3938         return features;
3939 }
3940
3941 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3942                                    struct mlx5e_channels *chs,
3943                                    struct mlx5e_params *new_params,
3944                                    struct mlx5_core_dev *mdev)
3945 {
3946         u16 ix;
3947
3948         for (ix = 0; ix < chs->params.num_channels; ix++) {
3949                 struct xsk_buff_pool *xsk_pool =
3950                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3951                 struct mlx5e_xsk_param xsk;
3952
3953                 if (!xsk_pool)
3954                         continue;
3955
3956                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3957
3958                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3959                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3960                         int max_mtu_frame, max_mtu_page, max_mtu;
3961
3962                         /* Two criteria must be met:
3963                          * 1. HW MTU + all headrooms <= XSK frame size.
3964                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3965                          */
3966                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3967                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3968                         max_mtu = min(max_mtu_frame, max_mtu_page);
3969
3970                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3971                                    new_params->sw_mtu, ix, max_mtu);
3972                         return false;
3973                 }
3974         }
3975
3976         return true;
3977 }
3978
3979 static bool mlx5e_params_validate_xdp(struct net_device *netdev, struct mlx5e_params *params)
3980 {
3981         bool is_linear;
3982
3983         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
3984          * the XDP program.
3985          */
3986         is_linear = mlx5e_rx_is_linear_skb(params, NULL);
3987
3988         if (!is_linear && params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3989                 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
3990                             params->sw_mtu,
3991                             mlx5e_xdp_max_mtu(params, NULL));
3992                 return false;
3993         }
3994         if (!is_linear && !params->xdp_prog->aux->xdp_has_frags) {
3995                 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
3996                             params->sw_mtu,
3997                             mlx5e_xdp_max_mtu(params, NULL));
3998                 return false;
3999         }
4000
4001         return true;
4002 }
4003
4004 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4005                      mlx5e_fp_preactivate preactivate)
4006 {
4007         struct mlx5e_priv *priv = netdev_priv(netdev);
4008         struct mlx5e_params new_params;
4009         struct mlx5e_params *params;
4010         bool reset = true;
4011         int err = 0;
4012
4013         mutex_lock(&priv->state_lock);
4014
4015         params = &priv->channels.params;
4016
4017         new_params = *params;
4018         new_params.sw_mtu = new_mtu;
4019         err = mlx5e_validate_params(priv->mdev, &new_params);
4020         if (err)
4021                 goto out;
4022
4023         if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, &new_params)) {
4024                 err = -EINVAL;
4025                 goto out;
4026         }
4027
4028         if (priv->xsk.refcnt &&
4029             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4030                                     &new_params, priv->mdev)) {
4031                 err = -EINVAL;
4032                 goto out;
4033         }
4034
4035         if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4036                 reset = false;
4037
4038         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4039                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4040                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4041                                                                   &new_params, NULL);
4042                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
4043                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
4044
4045                 /* Always reset in linear mode - hw_mtu is used in data path.
4046                  * Check that the mode was non-linear and didn't change.
4047                  * If XSK is active, XSK RQs are linear.
4048                  */
4049                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4050                     ppw_old == ppw_new)
4051                         reset = false;
4052         }
4053
4054         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4055
4056 out:
4057         netdev->mtu = params->sw_mtu;
4058         mutex_unlock(&priv->state_lock);
4059         return err;
4060 }
4061
4062 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4063 {
4064         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4065 }
4066
4067 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4068 {
4069         bool set  = *(bool *)ctx;
4070
4071         return mlx5e_ptp_rx_manage_fs(priv, set);
4072 }
4073
4074 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4075 {
4076         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4077         int err;
4078
4079         if (!rx_filter)
4080                 /* Reset CQE compression to Admin default */
4081                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4082
4083         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4084                 return 0;
4085
4086         /* Disable CQE compression */
4087         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4088         err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4089         if (err)
4090                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4091
4092         return err;
4093 }
4094
4095 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4096 {
4097         struct mlx5e_params new_params;
4098
4099         if (ptp_rx == priv->channels.params.ptp_rx)
4100                 return 0;
4101
4102         new_params = priv->channels.params;
4103         new_params.ptp_rx = ptp_rx;
4104         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4105                                         &new_params.ptp_rx, true);
4106 }
4107
4108 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4109 {
4110         struct hwtstamp_config config;
4111         bool rx_cqe_compress_def;
4112         bool ptp_rx;
4113         int err;
4114
4115         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4116             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4117                 return -EOPNOTSUPP;
4118
4119         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4120                 return -EFAULT;
4121
4122         /* TX HW timestamp */
4123         switch (config.tx_type) {
4124         case HWTSTAMP_TX_OFF:
4125         case HWTSTAMP_TX_ON:
4126                 break;
4127         default:
4128                 return -ERANGE;
4129         }
4130
4131         mutex_lock(&priv->state_lock);
4132         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4133
4134         /* RX HW timestamp */
4135         switch (config.rx_filter) {
4136         case HWTSTAMP_FILTER_NONE:
4137                 ptp_rx = false;
4138                 break;
4139         case HWTSTAMP_FILTER_ALL:
4140         case HWTSTAMP_FILTER_SOME:
4141         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4142         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4143         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4144         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4145         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4146         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4147         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4148         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4149         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4150         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4151         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4152         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4153         case HWTSTAMP_FILTER_NTP_ALL:
4154                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4155                 /* ptp_rx is set if both HW TS is set and CQE
4156                  * compression is set
4157                  */
4158                 ptp_rx = rx_cqe_compress_def;
4159                 break;
4160         default:
4161                 err = -ERANGE;
4162                 goto err_unlock;
4163         }
4164
4165         if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4166                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4167                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4168         else
4169                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4170         if (err)
4171                 goto err_unlock;
4172
4173         memcpy(&priv->tstamp, &config, sizeof(config));
4174         mutex_unlock(&priv->state_lock);
4175
4176         /* might need to fix some features */
4177         netdev_update_features(priv->netdev);
4178
4179         return copy_to_user(ifr->ifr_data, &config,
4180                             sizeof(config)) ? -EFAULT : 0;
4181 err_unlock:
4182         mutex_unlock(&priv->state_lock);
4183         return err;
4184 }
4185
4186 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4187 {
4188         struct hwtstamp_config *cfg = &priv->tstamp;
4189
4190         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4191                 return -EOPNOTSUPP;
4192
4193         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4194 }
4195
4196 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4197 {
4198         struct mlx5e_priv *priv = netdev_priv(dev);
4199
4200         switch (cmd) {
4201         case SIOCSHWTSTAMP:
4202                 return mlx5e_hwstamp_set(priv, ifr);
4203         case SIOCGHWTSTAMP:
4204                 return mlx5e_hwstamp_get(priv, ifr);
4205         default:
4206                 return -EOPNOTSUPP;
4207         }
4208 }
4209
4210 #ifdef CONFIG_MLX5_ESWITCH
4211 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4212 {
4213         struct mlx5e_priv *priv = netdev_priv(dev);
4214         struct mlx5_core_dev *mdev = priv->mdev;
4215
4216         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4217 }
4218
4219 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4220                              __be16 vlan_proto)
4221 {
4222         struct mlx5e_priv *priv = netdev_priv(dev);
4223         struct mlx5_core_dev *mdev = priv->mdev;
4224
4225         if (vlan_proto != htons(ETH_P_8021Q))
4226                 return -EPROTONOSUPPORT;
4227
4228         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4229                                            vlan, qos);
4230 }
4231
4232 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4233 {
4234         struct mlx5e_priv *priv = netdev_priv(dev);
4235         struct mlx5_core_dev *mdev = priv->mdev;
4236
4237         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4238 }
4239
4240 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4241 {
4242         struct mlx5e_priv *priv = netdev_priv(dev);
4243         struct mlx5_core_dev *mdev = priv->mdev;
4244
4245         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4246 }
4247
4248 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4249                       int max_tx_rate)
4250 {
4251         struct mlx5e_priv *priv = netdev_priv(dev);
4252         struct mlx5_core_dev *mdev = priv->mdev;
4253
4254         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4255                                            max_tx_rate, min_tx_rate);
4256 }
4257
4258 static int mlx5_vport_link2ifla(u8 esw_link)
4259 {
4260         switch (esw_link) {
4261         case MLX5_VPORT_ADMIN_STATE_DOWN:
4262                 return IFLA_VF_LINK_STATE_DISABLE;
4263         case MLX5_VPORT_ADMIN_STATE_UP:
4264                 return IFLA_VF_LINK_STATE_ENABLE;
4265         }
4266         return IFLA_VF_LINK_STATE_AUTO;
4267 }
4268
4269 static int mlx5_ifla_link2vport(u8 ifla_link)
4270 {
4271         switch (ifla_link) {
4272         case IFLA_VF_LINK_STATE_DISABLE:
4273                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4274         case IFLA_VF_LINK_STATE_ENABLE:
4275                 return MLX5_VPORT_ADMIN_STATE_UP;
4276         }
4277         return MLX5_VPORT_ADMIN_STATE_AUTO;
4278 }
4279
4280 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4281                                    int link_state)
4282 {
4283         struct mlx5e_priv *priv = netdev_priv(dev);
4284         struct mlx5_core_dev *mdev = priv->mdev;
4285
4286         if (mlx5e_is_uplink_rep(priv))
4287                 return -EOPNOTSUPP;
4288
4289         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4290                                             mlx5_ifla_link2vport(link_state));
4291 }
4292
4293 int mlx5e_get_vf_config(struct net_device *dev,
4294                         int vf, struct ifla_vf_info *ivi)
4295 {
4296         struct mlx5e_priv *priv = netdev_priv(dev);
4297         struct mlx5_core_dev *mdev = priv->mdev;
4298         int err;
4299
4300         if (!netif_device_present(dev))
4301                 return -EOPNOTSUPP;
4302
4303         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4304         if (err)
4305                 return err;
4306         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4307         return 0;
4308 }
4309
4310 int mlx5e_get_vf_stats(struct net_device *dev,
4311                        int vf, struct ifla_vf_stats *vf_stats)
4312 {
4313         struct mlx5e_priv *priv = netdev_priv(dev);
4314         struct mlx5_core_dev *mdev = priv->mdev;
4315
4316         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4317                                             vf_stats);
4318 }
4319
4320 static bool
4321 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4322 {
4323         struct mlx5e_priv *priv = netdev_priv(dev);
4324
4325         if (!netif_device_present(dev))
4326                 return false;
4327
4328         if (!mlx5e_is_uplink_rep(priv))
4329                 return false;
4330
4331         return mlx5e_rep_has_offload_stats(dev, attr_id);
4332 }
4333
4334 static int
4335 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4336                         void *sp)
4337 {
4338         struct mlx5e_priv *priv = netdev_priv(dev);
4339
4340         if (!mlx5e_is_uplink_rep(priv))
4341                 return -EOPNOTSUPP;
4342
4343         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4344 }
4345 #endif
4346
4347 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4348 {
4349         switch (proto_type) {
4350         case IPPROTO_GRE:
4351                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4352         case IPPROTO_IPIP:
4353         case IPPROTO_IPV6:
4354                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4355                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4356         default:
4357                 return false;
4358         }
4359 }
4360
4361 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4362                                                            struct sk_buff *skb)
4363 {
4364         switch (skb->inner_protocol) {
4365         case htons(ETH_P_IP):
4366         case htons(ETH_P_IPV6):
4367         case htons(ETH_P_TEB):
4368                 return true;
4369         case htons(ETH_P_MPLS_UC):
4370         case htons(ETH_P_MPLS_MC):
4371                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4372         }
4373         return false;
4374 }
4375
4376 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4377                                                      struct sk_buff *skb,
4378                                                      netdev_features_t features)
4379 {
4380         unsigned int offset = 0;
4381         struct udphdr *udph;
4382         u8 proto;
4383         u16 port;
4384
4385         switch (vlan_get_protocol(skb)) {
4386         case htons(ETH_P_IP):
4387                 proto = ip_hdr(skb)->protocol;
4388                 break;
4389         case htons(ETH_P_IPV6):
4390                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4391                 break;
4392         default:
4393                 goto out;
4394         }
4395
4396         switch (proto) {
4397         case IPPROTO_GRE:
4398                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4399                         return features;
4400                 break;
4401         case IPPROTO_IPIP:
4402         case IPPROTO_IPV6:
4403                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4404                         return features;
4405                 break;
4406         case IPPROTO_UDP:
4407                 udph = udp_hdr(skb);
4408                 port = be16_to_cpu(udph->dest);
4409
4410                 /* Verify if UDP port is being offloaded by HW */
4411                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4412                         return features;
4413
4414 #if IS_ENABLED(CONFIG_GENEVE)
4415                 /* Support Geneve offload for default UDP port */
4416                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4417                         return features;
4418 #endif
4419                 break;
4420 #ifdef CONFIG_MLX5_EN_IPSEC
4421         case IPPROTO_ESP:
4422                 return mlx5e_ipsec_feature_check(skb, features);
4423 #endif
4424         }
4425
4426 out:
4427         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4428         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4429 }
4430
4431 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4432                                        struct net_device *netdev,
4433                                        netdev_features_t features)
4434 {
4435         struct mlx5e_priv *priv = netdev_priv(netdev);
4436
4437         features = vlan_features_check(skb, features);
4438         features = vxlan_features_check(skb, features);
4439
4440         /* Validate if the tunneled packet is being offloaded by HW */
4441         if (skb->encapsulation &&
4442             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4443                 return mlx5e_tunnel_features_check(priv, skb, features);
4444
4445         return features;
4446 }
4447
4448 static void mlx5e_tx_timeout_work(struct work_struct *work)
4449 {
4450         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4451                                                tx_timeout_work);
4452         struct net_device *netdev = priv->netdev;
4453         int i;
4454
4455         rtnl_lock();
4456         mutex_lock(&priv->state_lock);
4457
4458         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4459                 goto unlock;
4460
4461         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4462                 struct netdev_queue *dev_queue =
4463                         netdev_get_tx_queue(netdev, i);
4464                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4465
4466                 if (!netif_xmit_stopped(dev_queue))
4467                         continue;
4468
4469                 if (mlx5e_reporter_tx_timeout(sq))
4470                 /* break if tried to reopened channels */
4471                         break;
4472         }
4473
4474 unlock:
4475         mutex_unlock(&priv->state_lock);
4476         rtnl_unlock();
4477 }
4478
4479 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4480 {
4481         struct mlx5e_priv *priv = netdev_priv(dev);
4482
4483         netdev_err(dev, "TX timeout detected\n");
4484         queue_work(priv->wq, &priv->tx_timeout_work);
4485 }
4486
4487 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4488 {
4489         struct net_device *netdev = priv->netdev;
4490         struct mlx5e_params new_params;
4491
4492         if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4493                 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4494                 return -EINVAL;
4495         }
4496
4497         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4498                 netdev_warn(netdev,
4499                             "XDP is not available on Innova cards with IPsec support\n");
4500                 return -EINVAL;
4501         }
4502
4503         new_params = priv->channels.params;
4504         new_params.xdp_prog = prog;
4505
4506         if (!mlx5e_params_validate_xdp(netdev, &new_params))
4507                 return -EINVAL;
4508
4509         return 0;
4510 }
4511
4512 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4513 {
4514         struct bpf_prog *old_prog;
4515
4516         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4517                                        lockdep_is_held(&rq->priv->state_lock));
4518         if (old_prog)
4519                 bpf_prog_put(old_prog);
4520 }
4521
4522 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4523 {
4524         struct mlx5e_priv *priv = netdev_priv(netdev);
4525         struct mlx5e_params new_params;
4526         struct bpf_prog *old_prog;
4527         int err = 0;
4528         bool reset;
4529         int i;
4530
4531         mutex_lock(&priv->state_lock);
4532
4533         if (prog) {
4534                 err = mlx5e_xdp_allowed(priv, prog);
4535                 if (err)
4536                         goto unlock;
4537         }
4538
4539         /* no need for full reset when exchanging programs */
4540         reset = (!priv->channels.params.xdp_prog || !prog);
4541
4542         new_params = priv->channels.params;
4543         new_params.xdp_prog = prog;
4544         if (reset)
4545                 mlx5e_set_rq_type(priv->mdev, &new_params);
4546         old_prog = priv->channels.params.xdp_prog;
4547
4548         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4549         if (err)
4550                 goto unlock;
4551
4552         if (old_prog)
4553                 bpf_prog_put(old_prog);
4554
4555         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4556                 goto unlock;
4557
4558         /* exchanging programs w/o reset, we update ref counts on behalf
4559          * of the channels RQs here.
4560          */
4561         bpf_prog_add(prog, priv->channels.num);
4562         for (i = 0; i < priv->channels.num; i++) {
4563                 struct mlx5e_channel *c = priv->channels.c[i];
4564
4565                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4566                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4567                         bpf_prog_inc(prog);
4568                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4569                 }
4570         }
4571
4572 unlock:
4573         mutex_unlock(&priv->state_lock);
4574         return err;
4575 }
4576
4577 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4578 {
4579         switch (xdp->command) {
4580         case XDP_SETUP_PROG:
4581                 return mlx5e_xdp_set(dev, xdp->prog);
4582         case XDP_SETUP_XSK_POOL:
4583                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4584                                             xdp->xsk.queue_id);
4585         default:
4586                 return -EINVAL;
4587         }
4588 }
4589
4590 #ifdef CONFIG_MLX5_ESWITCH
4591 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4592                                 struct net_device *dev, u32 filter_mask,
4593                                 int nlflags)
4594 {
4595         struct mlx5e_priv *priv = netdev_priv(dev);
4596         struct mlx5_core_dev *mdev = priv->mdev;
4597         u8 mode, setting;
4598         int err;
4599
4600         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4601         if (err)
4602                 return err;
4603         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4604         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4605                                        mode,
4606                                        0, 0, nlflags, filter_mask, NULL);
4607 }
4608
4609 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4610                                 u16 flags, struct netlink_ext_ack *extack)
4611 {
4612         struct mlx5e_priv *priv = netdev_priv(dev);
4613         struct mlx5_core_dev *mdev = priv->mdev;
4614         struct nlattr *attr, *br_spec;
4615         u16 mode = BRIDGE_MODE_UNDEF;
4616         u8 setting;
4617         int rem;
4618
4619         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4620         if (!br_spec)
4621                 return -EINVAL;
4622
4623         nla_for_each_nested(attr, br_spec, rem) {
4624                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4625                         continue;
4626
4627                 if (nla_len(attr) < sizeof(mode))
4628                         return -EINVAL;
4629
4630                 mode = nla_get_u16(attr);
4631                 if (mode > BRIDGE_MODE_VEPA)
4632                         return -EINVAL;
4633
4634                 break;
4635         }
4636
4637         if (mode == BRIDGE_MODE_UNDEF)
4638                 return -EINVAL;
4639
4640         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4641         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4642 }
4643 #endif
4644
4645 const struct net_device_ops mlx5e_netdev_ops = {
4646         .ndo_open                = mlx5e_open,
4647         .ndo_stop                = mlx5e_close,
4648         .ndo_start_xmit          = mlx5e_xmit,
4649         .ndo_setup_tc            = mlx5e_setup_tc,
4650         .ndo_select_queue        = mlx5e_select_queue,
4651         .ndo_get_stats64         = mlx5e_get_stats,
4652         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4653         .ndo_set_mac_address     = mlx5e_set_mac,
4654         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4655         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4656         .ndo_set_features        = mlx5e_set_features,
4657         .ndo_fix_features        = mlx5e_fix_features,
4658         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4659         .ndo_eth_ioctl            = mlx5e_ioctl,
4660         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4661         .ndo_features_check      = mlx5e_features_check,
4662         .ndo_tx_timeout          = mlx5e_tx_timeout,
4663         .ndo_bpf                 = mlx5e_xdp,
4664         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4665         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4666 #ifdef CONFIG_MLX5_EN_ARFS
4667         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4668 #endif
4669 #ifdef CONFIG_MLX5_ESWITCH
4670         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4671         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4672
4673         /* SRIOV E-Switch NDOs */
4674         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4675         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4676         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4677         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4678         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4679         .ndo_get_vf_config       = mlx5e_get_vf_config,
4680         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4681         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4682         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4683         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4684 #endif
4685         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4686 };
4687
4688 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4689 {
4690         int i;
4691
4692         /* The supported periods are organized in ascending order */
4693         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4694                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4695                         break;
4696
4697         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4698 }
4699
4700 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4701 {
4702         struct mlx5e_params *params = &priv->channels.params;
4703         struct mlx5_core_dev *mdev = priv->mdev;
4704         u8 rx_cq_period_mode;
4705
4706         params->sw_mtu = mtu;
4707         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4708         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4709                                      priv->max_nch);
4710         mlx5e_params_mqprio_reset(params);
4711
4712         /* SQ */
4713         params->log_sq_size = is_kdump_kernel() ?
4714                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4715                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4716         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4717
4718         /* XDP SQ */
4719         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4720
4721         /* set CQE compression */
4722         params->rx_cqe_compress_def = false;
4723         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4724             MLX5_CAP_GEN(mdev, vport_group_manager))
4725                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4726
4727         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4728         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4729
4730         /* RQ */
4731         mlx5e_build_rq_params(mdev, params);
4732
4733         /* HW LRO */
4734         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4735             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4736                 /* No XSK params: checking the availability of striding RQ in general. */
4737                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4738                         params->packet_merge.type = slow_pci_heuristic(mdev) ?
4739                                 MLX5E_PACKET_MERGE_NONE : MLX5E_PACKET_MERGE_LRO;
4740         }
4741         params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4742
4743         /* CQ moderation params */
4744         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4745                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4746                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4747         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4748         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4749         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4750         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4751
4752         /* TX inline */
4753         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4754
4755         params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4756
4757         /* AF_XDP */
4758         params->xsk = xsk;
4759
4760         /* Do not update netdev->features directly in here
4761          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4762          * To update netdev->features please modify mlx5e_fix_features()
4763          */
4764 }
4765
4766 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4767 {
4768         struct mlx5e_priv *priv = netdev_priv(netdev);
4769         u8 addr[ETH_ALEN];
4770
4771         mlx5_query_mac_address(priv->mdev, addr);
4772         if (is_zero_ether_addr(addr) &&
4773             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4774                 eth_hw_addr_random(netdev);
4775                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4776                 return;
4777         }
4778
4779         eth_hw_addr_set(netdev, addr);
4780 }
4781
4782 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4783                                 unsigned int entry, struct udp_tunnel_info *ti)
4784 {
4785         struct mlx5e_priv *priv = netdev_priv(netdev);
4786
4787         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4788 }
4789
4790 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4791                                   unsigned int entry, struct udp_tunnel_info *ti)
4792 {
4793         struct mlx5e_priv *priv = netdev_priv(netdev);
4794
4795         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4796 }
4797
4798 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4799 {
4800         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4801                 return;
4802
4803         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4804         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4805         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4806                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4807         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4808         /* Don't count the space hard-coded to the IANA port */
4809         priv->nic_info.tables[0].n_entries =
4810                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4811
4812         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4813 }
4814
4815 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4816 {
4817         int tt;
4818
4819         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4820                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4821                         return true;
4822         }
4823         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4824 }
4825
4826 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4827 {
4828         struct mlx5e_priv *priv = netdev_priv(netdev);
4829         struct mlx5_core_dev *mdev = priv->mdev;
4830         bool fcs_supported;
4831         bool fcs_enabled;
4832
4833         SET_NETDEV_DEV(netdev, mdev->device);
4834
4835         netdev->netdev_ops = &mlx5e_netdev_ops;
4836
4837         mlx5e_dcbnl_build_netdev(netdev);
4838
4839         netdev->watchdog_timeo    = 15 * HZ;
4840
4841         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4842
4843         netdev->vlan_features    |= NETIF_F_SG;
4844         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4845         netdev->vlan_features    |= NETIF_F_GRO;
4846         netdev->vlan_features    |= NETIF_F_TSO;
4847         netdev->vlan_features    |= NETIF_F_TSO6;
4848         netdev->vlan_features    |= NETIF_F_RXCSUM;
4849         netdev->vlan_features    |= NETIF_F_RXHASH;
4850
4851         netdev->mpls_features    |= NETIF_F_SG;
4852         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4853         netdev->mpls_features    |= NETIF_F_TSO;
4854         netdev->mpls_features    |= NETIF_F_TSO6;
4855
4856         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4857         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4858
4859         /* Tunneled LRO is not supported in the driver, and the same RQs are
4860          * shared between inner and outer TIRs, so the driver can't disable LRO
4861          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4862          * block LRO altogether if the firmware declares tunneled LRO support.
4863          */
4864         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4865             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4866             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4867             mlx5e_check_fragmented_striding_rq_cap(mdev))
4868                 netdev->vlan_features    |= NETIF_F_LRO;
4869
4870         netdev->hw_features       = netdev->vlan_features;
4871         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4872         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4873         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4874         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4875
4876         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4877                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4878                 netdev->hw_enc_features |= NETIF_F_TSO;
4879                 netdev->hw_enc_features |= NETIF_F_TSO6;
4880                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4881         }
4882
4883         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4884                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4885                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4886                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4887                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4888                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4889                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4890                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4891         }
4892
4893         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4894                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4895                                            NETIF_F_GSO_GRE_CSUM;
4896                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4897                                            NETIF_F_GSO_GRE_CSUM;
4898                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4899                                                 NETIF_F_GSO_GRE_CSUM;
4900         }
4901
4902         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4903                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4904                                        NETIF_F_GSO_IPXIP6;
4905                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4906                                            NETIF_F_GSO_IPXIP6;
4907                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4908                                                 NETIF_F_GSO_IPXIP6;
4909         }
4910
4911         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4912         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4913         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4914         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4915
4916         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4917
4918         if (fcs_supported)
4919                 netdev->hw_features |= NETIF_F_RXALL;
4920
4921         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4922                 netdev->hw_features |= NETIF_F_RXFCS;
4923
4924         if (mlx5_qos_is_supported(mdev))
4925                 netdev->hw_features |= NETIF_F_HW_TC;
4926
4927         netdev->features          = netdev->hw_features;
4928
4929         /* Defaults */
4930         if (fcs_enabled)
4931                 netdev->features  &= ~NETIF_F_RXALL;
4932         netdev->features  &= ~NETIF_F_LRO;
4933         netdev->features  &= ~NETIF_F_GRO_HW;
4934         netdev->features  &= ~NETIF_F_RXFCS;
4935
4936 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4937         if (FT_CAP(flow_modify_en) &&
4938             FT_CAP(modify_root) &&
4939             FT_CAP(identified_miss_table_mode) &&
4940             FT_CAP(flow_table_modify)) {
4941 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4942                 netdev->hw_features      |= NETIF_F_HW_TC;
4943 #endif
4944 #ifdef CONFIG_MLX5_EN_ARFS
4945                 netdev->hw_features      |= NETIF_F_NTUPLE;
4946 #endif
4947         }
4948
4949         netdev->features         |= NETIF_F_HIGHDMA;
4950         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4951
4952         netdev->priv_flags       |= IFF_UNICAST_FLT;
4953
4954         mlx5e_set_netdev_dev_addr(netdev);
4955         mlx5e_ipsec_build_netdev(priv);
4956         mlx5e_tls_build_netdev(priv);
4957 }
4958
4959 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4960 {
4961         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4962         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4963         struct mlx5_core_dev *mdev = priv->mdev;
4964         int err;
4965
4966         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4967         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4968         if (!err)
4969                 priv->q_counter =
4970                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4971
4972         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4973         if (!err)
4974                 priv->drop_rq_q_counter =
4975                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4976 }
4977
4978 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4979 {
4980         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4981
4982         MLX5_SET(dealloc_q_counter_in, in, opcode,
4983                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4984         if (priv->q_counter) {
4985                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4986                          priv->q_counter);
4987                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4988         }
4989
4990         if (priv->drop_rq_q_counter) {
4991                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4992                          priv->drop_rq_q_counter);
4993                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4994         }
4995 }
4996
4997 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4998                           struct net_device *netdev)
4999 {
5000         struct mlx5e_priv *priv = netdev_priv(netdev);
5001         int err;
5002
5003         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
5004         mlx5e_vxlan_set_netdev_info(priv);
5005
5006         mlx5e_timestamp_init(priv);
5007
5008         err = mlx5e_fs_init(priv);
5009         if (err) {
5010                 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5011                 return err;
5012         }
5013
5014         err = mlx5e_ipsec_init(priv);
5015         if (err)
5016                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5017
5018         err = mlx5e_tls_init(priv);
5019         if (err)
5020                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5021
5022         mlx5e_health_create_reporters(priv);
5023         return 0;
5024 }
5025
5026 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5027 {
5028         mlx5e_health_destroy_reporters(priv);
5029         mlx5e_tls_cleanup(priv);
5030         mlx5e_ipsec_cleanup(priv);
5031         mlx5e_fs_cleanup(priv);
5032 }
5033
5034 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5035 {
5036         struct mlx5_core_dev *mdev = priv->mdev;
5037         enum mlx5e_rx_res_features features;
5038         int err;
5039
5040         priv->rx_res = mlx5e_rx_res_alloc();
5041         if (!priv->rx_res)
5042                 return -ENOMEM;
5043
5044         mlx5e_create_q_counters(priv);
5045
5046         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5047         if (err) {
5048                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5049                 goto err_destroy_q_counters;
5050         }
5051
5052         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
5053         if (priv->channels.params.tunneled_offload_en)
5054                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5055         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
5056                                 priv->max_nch, priv->drop_rq.rqn,
5057                                 &priv->channels.params.packet_merge,
5058                                 priv->channels.params.num_channels);
5059         if (err)
5060                 goto err_close_drop_rq;
5061
5062         err = mlx5e_create_flow_steering(priv);
5063         if (err) {
5064                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5065                 goto err_destroy_rx_res;
5066         }
5067
5068         err = mlx5e_tc_nic_init(priv);
5069         if (err)
5070                 goto err_destroy_flow_steering;
5071
5072         err = mlx5e_accel_init_rx(priv);
5073         if (err)
5074                 goto err_tc_nic_cleanup;
5075
5076 #ifdef CONFIG_MLX5_EN_ARFS
5077         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5078 #endif
5079
5080         return 0;
5081
5082 err_tc_nic_cleanup:
5083         mlx5e_tc_nic_cleanup(priv);
5084 err_destroy_flow_steering:
5085         mlx5e_destroy_flow_steering(priv);
5086 err_destroy_rx_res:
5087         mlx5e_rx_res_destroy(priv->rx_res);
5088 err_close_drop_rq:
5089         mlx5e_close_drop_rq(&priv->drop_rq);
5090 err_destroy_q_counters:
5091         mlx5e_destroy_q_counters(priv);
5092         mlx5e_rx_res_free(priv->rx_res);
5093         priv->rx_res = NULL;
5094         return err;
5095 }
5096
5097 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5098 {
5099         mlx5e_accel_cleanup_rx(priv);
5100         mlx5e_tc_nic_cleanup(priv);
5101         mlx5e_destroy_flow_steering(priv);
5102         mlx5e_rx_res_destroy(priv->rx_res);
5103         mlx5e_close_drop_rq(&priv->drop_rq);
5104         mlx5e_destroy_q_counters(priv);
5105         mlx5e_rx_res_free(priv->rx_res);
5106         priv->rx_res = NULL;
5107 }
5108
5109 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5110 {
5111         int err;
5112
5113         err = mlx5e_create_tises(priv);
5114         if (err) {
5115                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5116                 return err;
5117         }
5118
5119         mlx5e_dcbnl_initialize(priv);
5120         return 0;
5121 }
5122
5123 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5124 {
5125         struct net_device *netdev = priv->netdev;
5126         struct mlx5_core_dev *mdev = priv->mdev;
5127
5128         mlx5e_init_l2_addr(priv);
5129
5130         /* Marking the link as currently not needed by the Driver */
5131         if (!netif_running(netdev))
5132                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5133
5134         mlx5e_set_netdev_mtu_boundaries(priv);
5135         mlx5e_set_dev_port_mtu(priv);
5136
5137         mlx5_lag_add_netdev(mdev, netdev);
5138
5139         mlx5e_enable_async_events(priv);
5140         mlx5e_enable_blocking_events(priv);
5141         if (mlx5e_monitor_counter_supported(priv))
5142                 mlx5e_monitor_counter_init(priv);
5143
5144         mlx5e_hv_vhca_stats_create(priv);
5145         if (netdev->reg_state != NETREG_REGISTERED)
5146                 return;
5147         mlx5e_dcbnl_init_app(priv);
5148
5149         mlx5e_nic_set_rx_mode(priv);
5150
5151         rtnl_lock();
5152         if (netif_running(netdev))
5153                 mlx5e_open(netdev);
5154         udp_tunnel_nic_reset_ntf(priv->netdev);
5155         netif_device_attach(netdev);
5156         rtnl_unlock();
5157 }
5158
5159 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5160 {
5161         struct mlx5_core_dev *mdev = priv->mdev;
5162
5163         if (priv->netdev->reg_state == NETREG_REGISTERED)
5164                 mlx5e_dcbnl_delete_app(priv);
5165
5166         rtnl_lock();
5167         if (netif_running(priv->netdev))
5168                 mlx5e_close(priv->netdev);
5169         netif_device_detach(priv->netdev);
5170         rtnl_unlock();
5171
5172         mlx5e_nic_set_rx_mode(priv);
5173
5174         mlx5e_hv_vhca_stats_destroy(priv);
5175         if (mlx5e_monitor_counter_supported(priv))
5176                 mlx5e_monitor_counter_cleanup(priv);
5177
5178         mlx5e_disable_blocking_events(priv);
5179         if (priv->en_trap) {
5180                 mlx5e_deactivate_trap(priv);
5181                 mlx5e_close_trap(priv->en_trap);
5182                 priv->en_trap = NULL;
5183         }
5184         mlx5e_disable_async_events(priv);
5185         mlx5_lag_remove_netdev(mdev, priv->netdev);
5186         mlx5_vxlan_reset_to_default(mdev->vxlan);
5187 }
5188
5189 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5190 {
5191         return mlx5e_refresh_tirs(priv, false, false);
5192 }
5193
5194 static const struct mlx5e_profile mlx5e_nic_profile = {
5195         .init              = mlx5e_nic_init,
5196         .cleanup           = mlx5e_nic_cleanup,
5197         .init_rx           = mlx5e_init_nic_rx,
5198         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5199         .init_tx           = mlx5e_init_nic_tx,
5200         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5201         .enable            = mlx5e_nic_enable,
5202         .disable           = mlx5e_nic_disable,
5203         .update_rx         = mlx5e_update_nic_rx,
5204         .update_stats      = mlx5e_stats_update_ndo_stats,
5205         .update_carrier    = mlx5e_update_carrier,
5206         .rx_handlers       = &mlx5e_rx_handlers_nic,
5207         .max_tc            = MLX5E_MAX_NUM_TC,
5208         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5209         .stats_grps        = mlx5e_nic_stats_grps,
5210         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5211         .features          = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5212                 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5213                 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB),
5214 };
5215
5216 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5217                                           const struct mlx5e_profile *profile)
5218 {
5219         int nch;
5220
5221         nch = mlx5e_get_max_num_channels(mdev);
5222
5223         if (profile->max_nch_limit)
5224                 nch = min_t(int, nch, profile->max_nch_limit(mdev));
5225         return nch;
5226 }
5227
5228 static unsigned int
5229 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5230                    const struct mlx5e_profile *profile)
5231
5232 {
5233         unsigned int max_nch, tmp;
5234
5235         /* core resources */
5236         max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5237
5238         /* netdev rx queues */
5239         tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5240         max_nch = min_t(unsigned int, max_nch, tmp);
5241
5242         /* netdev tx queues */
5243         tmp = netdev->num_tx_queues;
5244         if (mlx5_qos_is_supported(mdev))
5245                 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5246         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5247                 tmp -= profile->max_tc;
5248         tmp = tmp / profile->max_tc;
5249         max_nch = min_t(unsigned int, max_nch, tmp);
5250
5251         return max_nch;
5252 }
5253
5254 /* mlx5e generic netdev management API (move to en_common.c) */
5255 int mlx5e_priv_init(struct mlx5e_priv *priv,
5256                     const struct mlx5e_profile *profile,
5257                     struct net_device *netdev,
5258                     struct mlx5_core_dev *mdev)
5259 {
5260         int nch, num_txqs, node;
5261         int err;
5262
5263         num_txqs = netdev->num_tx_queues;
5264         nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5265         node = dev_to_node(mlx5_core_dma_dev(mdev));
5266
5267         /* priv init */
5268         priv->mdev        = mdev;
5269         priv->netdev      = netdev;
5270         priv->msglevel    = MLX5E_MSG_LEVEL;
5271         priv->max_nch     = nch;
5272         priv->max_opened_tc = 1;
5273
5274         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5275                 return -ENOMEM;
5276
5277         mutex_init(&priv->state_lock);
5278
5279         err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
5280         if (err)
5281                 goto err_free_cpumask;
5282
5283         hash_init(priv->htb.qos_tc2node);
5284         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5285         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5286         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5287         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5288
5289         priv->wq = create_singlethread_workqueue("mlx5e");
5290         if (!priv->wq)
5291                 goto err_free_selq;
5292
5293         priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
5294         if (!priv->txq2sq)
5295                 goto err_destroy_workqueue;
5296
5297         priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
5298         if (!priv->tx_rates)
5299                 goto err_free_txq2sq;
5300
5301         priv->channel_stats =
5302                 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
5303         if (!priv->channel_stats)
5304                 goto err_free_tx_rates;
5305
5306         return 0;
5307
5308 err_free_tx_rates:
5309         kfree(priv->tx_rates);
5310 err_free_txq2sq:
5311         kfree(priv->txq2sq);
5312 err_destroy_workqueue:
5313         destroy_workqueue(priv->wq);
5314 err_free_selq:
5315         mlx5e_selq_cleanup(&priv->selq);
5316 err_free_cpumask:
5317         free_cpumask_var(priv->scratchpad.cpumask);
5318         return -ENOMEM;
5319 }
5320
5321 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5322 {
5323         int i;
5324
5325         /* bail if change profile failed and also rollback failed */
5326         if (!priv->mdev)
5327                 return;
5328
5329         for (i = 0; i < priv->stats_nch; i++)
5330                 kvfree(priv->channel_stats[i]);
5331         kfree(priv->channel_stats);
5332         kfree(priv->tx_rates);
5333         kfree(priv->txq2sq);
5334         destroy_workqueue(priv->wq);
5335         mutex_lock(&priv->state_lock);
5336         mlx5e_selq_cleanup(&priv->selq);
5337         mutex_unlock(&priv->state_lock);
5338         free_cpumask_var(priv->scratchpad.cpumask);
5339
5340         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5341                 kfree(priv->htb.qos_sq_stats[i]);
5342         kvfree(priv->htb.qos_sq_stats);
5343
5344         if (priv->mqprio_rl) {
5345                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
5346                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
5347         }
5348
5349         memset(priv, 0, sizeof(*priv));
5350 }
5351
5352 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5353                                            const struct mlx5e_profile *profile)
5354 {
5355         unsigned int nch, ptp_txqs, qos_txqs;
5356
5357         nch = mlx5e_profile_max_num_channels(mdev, profile);
5358
5359         ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5360                 mlx5e_profile_feature_cap(profile, PTP_TX) ?
5361                 profile->max_tc : 0;
5362
5363         qos_txqs = mlx5_qos_is_supported(mdev) &&
5364                 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5365                 mlx5e_qos_max_leaf_nodes(mdev) : 0;
5366
5367         return nch * profile->max_tc + ptp_txqs + qos_txqs;
5368 }
5369
5370 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5371                                            const struct mlx5e_profile *profile)
5372 {
5373         unsigned int nch;
5374
5375         nch = mlx5e_profile_max_num_channels(mdev, profile);
5376
5377         return nch * profile->rq_groups;
5378 }
5379
5380 struct net_device *
5381 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5382 {
5383         struct net_device *netdev;
5384         unsigned int txqs, rxqs;
5385         int err;
5386
5387         txqs = mlx5e_get_max_num_txqs(mdev, profile);
5388         rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5389
5390         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5391         if (!netdev) {
5392                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5393                 return NULL;
5394         }
5395
5396         err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5397         if (err) {
5398                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5399                 goto err_free_netdev;
5400         }
5401
5402         netif_carrier_off(netdev);
5403         netif_tx_disable(netdev);
5404         dev_net_set(netdev, mlx5_core_net(mdev));
5405
5406         return netdev;
5407
5408 err_free_netdev:
5409         free_netdev(netdev);
5410
5411         return NULL;
5412 }
5413
5414 static void mlx5e_update_features(struct net_device *netdev)
5415 {
5416         if (netdev->reg_state != NETREG_REGISTERED)
5417                 return; /* features will be updated on netdev registration */
5418
5419         rtnl_lock();
5420         netdev_update_features(netdev);
5421         rtnl_unlock();
5422 }
5423
5424 static void mlx5e_reset_channels(struct net_device *netdev)
5425 {
5426         netdev_reset_tc(netdev);
5427 }
5428
5429 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5430 {
5431         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5432         const struct mlx5e_profile *profile = priv->profile;
5433         int max_nch;
5434         int err;
5435
5436         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5437
5438         /* max number of channels may have changed */
5439         max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5440         if (priv->channels.params.num_channels > max_nch) {
5441                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5442                 /* Reducing the number of channels - RXFH has to be reset, and
5443                  * mlx5e_num_channels_changed below will build the RQT.
5444                  */
5445                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5446                 priv->channels.params.num_channels = max_nch;
5447                 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5448                         mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5449                         mlx5e_params_mqprio_reset(&priv->channels.params);
5450                 }
5451         }
5452         if (max_nch != priv->max_nch) {
5453                 mlx5_core_warn(priv->mdev,
5454                                "MLX5E: Updating max number of channels from %u to %u\n",
5455                                priv->max_nch, max_nch);
5456                 priv->max_nch = max_nch;
5457         }
5458
5459         /* 1. Set the real number of queues in the kernel the first time.
5460          * 2. Set our default XPS cpumask.
5461          * 3. Build the RQT.
5462          *
5463          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5464          * netdev has been registered by this point (if this function was called
5465          * in the reload or resume flow).
5466          */
5467         if (take_rtnl)
5468                 rtnl_lock();
5469         err = mlx5e_num_channels_changed(priv);
5470         if (take_rtnl)
5471                 rtnl_unlock();
5472         if (err)
5473                 goto out;
5474
5475         err = profile->init_tx(priv);
5476         if (err)
5477                 goto out;
5478
5479         err = profile->init_rx(priv);
5480         if (err)
5481                 goto err_cleanup_tx;
5482
5483         if (profile->enable)
5484                 profile->enable(priv);
5485
5486         mlx5e_update_features(priv->netdev);
5487
5488         return 0;
5489
5490 err_cleanup_tx:
5491         profile->cleanup_tx(priv);
5492
5493 out:
5494         mlx5e_reset_channels(priv->netdev);
5495         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5496         cancel_work_sync(&priv->update_stats_work);
5497         return err;
5498 }
5499
5500 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5501 {
5502         const struct mlx5e_profile *profile = priv->profile;
5503
5504         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5505
5506         if (profile->disable)
5507                 profile->disable(priv);
5508         flush_workqueue(priv->wq);
5509
5510         profile->cleanup_rx(priv);
5511         profile->cleanup_tx(priv);
5512         mlx5e_reset_channels(priv->netdev);
5513         cancel_work_sync(&priv->update_stats_work);
5514 }
5515
5516 static int
5517 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5518                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5519 {
5520         struct mlx5e_priv *priv = netdev_priv(netdev);
5521         int err;
5522
5523         err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5524         if (err) {
5525                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5526                 return err;
5527         }
5528         netif_carrier_off(netdev);
5529         priv->profile = new_profile;
5530         priv->ppriv = new_ppriv;
5531         err = new_profile->init(priv->mdev, priv->netdev);
5532         if (err)
5533                 goto priv_cleanup;
5534         err = mlx5e_attach_netdev(priv);
5535         if (err)
5536                 goto profile_cleanup;
5537         return err;
5538
5539 profile_cleanup:
5540         new_profile->cleanup(priv);
5541 priv_cleanup:
5542         mlx5e_priv_cleanup(priv);
5543         return err;
5544 }
5545
5546 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5547                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5548 {
5549         const struct mlx5e_profile *orig_profile = priv->profile;
5550         struct net_device *netdev = priv->netdev;
5551         struct mlx5_core_dev *mdev = priv->mdev;
5552         void *orig_ppriv = priv->ppriv;
5553         int err, rollback_err;
5554
5555         /* cleanup old profile */
5556         mlx5e_detach_netdev(priv);
5557         priv->profile->cleanup(priv);
5558         mlx5e_priv_cleanup(priv);
5559
5560         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5561         if (err) { /* roll back to original profile */
5562                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5563                 goto rollback;
5564         }
5565
5566         return 0;
5567
5568 rollback:
5569         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5570         if (rollback_err)
5571                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5572                            __func__, rollback_err);
5573         return err;
5574 }
5575
5576 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5577 {
5578         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5579 }
5580
5581 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5582 {
5583         struct net_device *netdev = priv->netdev;
5584
5585         mlx5e_priv_cleanup(priv);
5586         free_netdev(netdev);
5587 }
5588
5589 static int mlx5e_resume(struct auxiliary_device *adev)
5590 {
5591         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5592         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5593         struct net_device *netdev = priv->netdev;
5594         struct mlx5_core_dev *mdev = edev->mdev;
5595         int err;
5596
5597         if (netif_device_present(netdev))
5598                 return 0;
5599
5600         err = mlx5e_create_mdev_resources(mdev);
5601         if (err)
5602                 return err;
5603
5604         err = mlx5e_attach_netdev(priv);
5605         if (err) {
5606                 mlx5e_destroy_mdev_resources(mdev);
5607                 return err;
5608         }
5609
5610         return 0;
5611 }
5612
5613 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5614 {
5615         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5616         struct net_device *netdev = priv->netdev;
5617         struct mlx5_core_dev *mdev = priv->mdev;
5618
5619         if (!netif_device_present(netdev))
5620                 return -ENODEV;
5621
5622         mlx5e_detach_netdev(priv);
5623         mlx5e_destroy_mdev_resources(mdev);
5624         return 0;
5625 }
5626
5627 static int mlx5e_probe(struct auxiliary_device *adev,
5628                        const struct auxiliary_device_id *id)
5629 {
5630         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5631         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5632         struct mlx5_core_dev *mdev = edev->mdev;
5633         struct net_device *netdev;
5634         pm_message_t state = {};
5635         struct mlx5e_priv *priv;
5636         int err;
5637
5638         netdev = mlx5e_create_netdev(mdev, profile);
5639         if (!netdev) {
5640                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5641                 return -ENOMEM;
5642         }
5643
5644         mlx5e_build_nic_netdev(netdev);
5645
5646         priv = netdev_priv(netdev);
5647         auxiliary_set_drvdata(adev, priv);
5648
5649         priv->profile = profile;
5650         priv->ppriv = NULL;
5651
5652         err = mlx5e_devlink_port_register(priv);
5653         if (err) {
5654                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5655                 goto err_destroy_netdev;
5656         }
5657
5658         err = profile->init(mdev, netdev);
5659         if (err) {
5660                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5661                 goto err_devlink_cleanup;
5662         }
5663
5664         err = mlx5e_resume(adev);
5665         if (err) {
5666                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5667                 goto err_profile_cleanup;
5668         }
5669
5670         err = register_netdev(netdev);
5671         if (err) {
5672                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5673                 goto err_resume;
5674         }
5675
5676         mlx5e_devlink_port_type_eth_set(priv);
5677
5678         mlx5e_dcbnl_init_app(priv);
5679         mlx5_uplink_netdev_set(mdev, netdev);
5680         return 0;
5681
5682 err_resume:
5683         mlx5e_suspend(adev, state);
5684 err_profile_cleanup:
5685         profile->cleanup(priv);
5686 err_devlink_cleanup:
5687         mlx5e_devlink_port_unregister(priv);
5688 err_destroy_netdev:
5689         mlx5e_destroy_netdev(priv);
5690         return err;
5691 }
5692
5693 static void mlx5e_remove(struct auxiliary_device *adev)
5694 {
5695         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5696         pm_message_t state = {};
5697
5698         mlx5e_dcbnl_delete_app(priv);
5699         unregister_netdev(priv->netdev);
5700         mlx5e_suspend(adev, state);
5701         priv->profile->cleanup(priv);
5702         mlx5e_devlink_port_unregister(priv);
5703         mlx5e_destroy_netdev(priv);
5704 }
5705
5706 static const struct auxiliary_device_id mlx5e_id_table[] = {
5707         { .name = MLX5_ADEV_NAME ".eth", },
5708         {},
5709 };
5710
5711 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5712
5713 static struct auxiliary_driver mlx5e_driver = {
5714         .name = "eth",
5715         .probe = mlx5e_probe,
5716         .remove = mlx5e_remove,
5717         .suspend = mlx5e_suspend,
5718         .resume = mlx5e_resume,
5719         .id_table = mlx5e_id_table,
5720 };
5721
5722 int mlx5e_init(void)
5723 {
5724         int ret;
5725
5726         mlx5e_ipsec_build_inverse_table();
5727         mlx5e_build_ptys2ethtool_map();
5728         ret = auxiliary_driver_register(&mlx5e_driver);
5729         if (ret)
5730                 return ret;
5731
5732         ret = mlx5e_rep_init();
5733         if (ret)
5734                 auxiliary_driver_unregister(&mlx5e_driver);
5735         return ret;
5736 }
5737
5738 void mlx5e_cleanup(void)
5739 {
5740         mlx5e_rep_cleanup();
5741         auxiliary_driver_unregister(&mlx5e_driver);
5742 }