2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
58 extern const struct net_device_ops mlx5e_netdev_ops;
61 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
62 #define MLX5E_METADATA_ETHER_LEN 8
64 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
66 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
68 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
69 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
71 #define MLX5E_MAX_PRIORITY 8
72 #define MLX5E_MAX_DSCP 64
73 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5E_RX_MAX_HEAD (256)
81 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
82 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
83 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
84 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
85 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
86 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
88 #define MLX5_MPWRQ_LOG_WQE_SZ 18
89 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
90 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
91 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
94 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
95 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
96 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
97 #define MLX5E_MAX_RQ_NUM_MTTS \
98 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
99 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
100 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
101 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
102 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
103 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
104 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
106 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
107 #define MLX5E_LOG_MAX_RX_WQE_BULK \
108 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
110 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
111 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
112 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
114 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
115 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
116 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
117 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
119 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
121 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
122 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
123 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
128 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
131 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
135 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
136 #define MLX5E_MIN_NUM_CHANNELS 0x1
137 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
138 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
139 #define MLX5E_TX_CQ_POLL_BUDGET 128
140 #define MLX5E_TX_XSK_POLL_BUDGET 64
141 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
143 #define MLX5E_UMR_WQE_INLINE_SZ \
144 (sizeof(struct mlx5e_umr_wqe) + \
145 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
146 MLX5_UMR_MTT_ALIGNMENT))
147 #define MLX5E_UMR_WQEBBS \
148 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
150 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
152 #define mlx5e_dbg(mlevel, priv, format, ...) \
154 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
155 netdev_warn(priv->netdev, format, \
159 enum mlx5e_rq_group {
160 MLX5E_RQ_GROUP_REGULAR,
162 MLX5E_NUM_RQ_GROUPS /* Keep last. */
165 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
168 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
169 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
172 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
177 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
178 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
180 return is_kdump_kernel() ?
181 MLX5E_MIN_NUM_CHANNELS :
182 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
185 /* Use this function to get max num channels after netdev was created */
186 static inline int mlx5e_get_netdev_max_channels(struct net_device *netdev)
188 return min_t(unsigned int,
189 netdev->num_rx_queues / MLX5E_NUM_RQ_GROUPS,
190 netdev->num_tx_queues);
193 struct mlx5e_tx_wqe {
194 struct mlx5_wqe_ctrl_seg ctrl;
195 struct mlx5_wqe_eth_seg eth;
196 struct mlx5_wqe_data_seg data[0];
199 struct mlx5e_rx_wqe_ll {
200 struct mlx5_wqe_srq_next_seg next;
201 struct mlx5_wqe_data_seg data[0];
204 struct mlx5e_rx_wqe_cyc {
205 struct mlx5_wqe_data_seg data[0];
208 struct mlx5e_umr_wqe {
209 struct mlx5_wqe_ctrl_seg ctrl;
210 struct mlx5_wqe_umr_ctrl_seg uctrl;
211 struct mlx5_mkey_seg mkc;
213 struct mlx5_mtt inline_mtts[0];
214 u8 tls_static_params_ctx[0];
218 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
220 enum mlx5e_priv_flag {
221 MLX5E_PFLAG_RX_CQE_BASED_MODER,
222 MLX5E_PFLAG_TX_CQE_BASED_MODER,
223 MLX5E_PFLAG_RX_CQE_COMPRESS,
224 MLX5E_PFLAG_RX_STRIDING_RQ,
225 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
226 MLX5E_PFLAG_XDP_TX_MPWQE,
227 MLX5E_NUM_PFLAGS, /* Keep last */
230 #define MLX5E_SET_PFLAG(params, pflag, enable) \
233 (params)->pflags |= BIT(pflag); \
235 (params)->pflags &= ~(BIT(pflag)); \
238 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
240 #ifdef CONFIG_MLX5_CORE_EN_DCB
241 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
244 struct mlx5e_params {
247 u8 log_rq_mtu_frames;
250 bool rx_cqe_compress_def;
251 bool tunneled_offload_en;
252 struct dim_cq_moder rx_cq_moderation;
253 struct dim_cq_moder tx_cq_moderation;
255 u8 tx_min_inline_mode;
256 bool vlan_strip_disable;
262 struct bpf_prog *xdp_prog;
263 struct mlx5e_xsk *xsk;
268 #ifdef CONFIG_MLX5_CORE_EN_DCB
269 struct mlx5e_cee_config {
270 /* bw pct for priority group */
271 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
272 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
273 bool pfc_setting[CEE_DCBX_MAX_PRIO];
280 MLX5_DCB_CHG_NO_RESET,
284 enum mlx5_dcbx_oper_mode mode;
285 struct mlx5e_cee_config cee_cfg; /* pending configuration */
288 /* The only setting that cannot be read from FW */
289 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
292 /* Buffer configuration */
298 struct mlx5e_dcbx_dp {
299 u8 dscp2prio[MLX5E_MAX_DSCP];
305 MLX5E_RQ_STATE_ENABLED,
307 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
308 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
312 /* data path - accessed per cqe */
315 /* data path - accessed per napi poll */
317 struct napi_struct *napi;
318 struct mlx5_core_cq mcq;
319 struct mlx5e_channel *channel;
322 struct mlx5_core_dev *mdev;
323 struct mlx5_wq_ctrl wq_ctrl;
324 } ____cacheline_aligned_in_smp;
326 struct mlx5e_cq_decomp {
327 /* cqe decompression */
328 struct mlx5_cqe64 title;
329 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
333 } ____cacheline_aligned_in_smp;
335 struct mlx5e_tx_wqe_info {
340 #ifdef CONFIG_MLX5_EN_TLS
341 skb_frag_t *resync_dump_frag;
345 enum mlx5e_dma_map_type {
346 MLX5E_DMA_MAP_SINGLE,
350 struct mlx5e_sq_dma {
353 enum mlx5e_dma_map_type type;
357 MLX5E_SQ_STATE_ENABLED,
358 MLX5E_SQ_STATE_RECOVERING,
359 MLX5E_SQ_STATE_IPSEC,
364 struct mlx5e_sq_wqe_info {
367 /* Auxiliary data for different opcodes. */
378 /* dirtied @completion */
381 struct dim dim; /* Adaptive Moderation */
384 u16 pc ____cacheline_aligned_in_smp;
390 struct mlx5_wq_cyc wq;
392 struct mlx5e_sq_stats *stats;
394 struct mlx5e_sq_dma *dma_fifo;
395 struct mlx5e_tx_wqe_info *wqe_info;
397 void __iomem *uar_map;
398 struct netdev_queue *txq;
405 struct hwtstamp_config *tstamp;
406 struct mlx5_clock *clock;
409 struct mlx5_wq_ctrl wq_ctrl;
410 struct mlx5e_channel *channel;
414 struct work_struct recover_work;
415 } ____cacheline_aligned_in_smp;
417 struct mlx5e_dma_info {
428 /* XDP packets can be transmitted in different ways. On completion, we need to
429 * distinguish between them to clean up things in a proper way.
431 enum mlx5e_xdp_xmit_mode {
432 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
433 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
436 MLX5E_XDP_XMIT_MODE_FRAME,
438 /* The xdp_frame was created in place as a result of XDP_TX from a
439 * regular RQ. No DMA remapping happened, and the page belongs to us.
441 MLX5E_XDP_XMIT_MODE_PAGE,
443 /* No xdp_frame was created at all, the transmit happened from a UMEM
444 * page. The UMEM Completion Ring producer pointer has to be increased.
446 MLX5E_XDP_XMIT_MODE_XSK,
449 struct mlx5e_xdp_info {
450 enum mlx5e_xdp_xmit_mode mode;
453 struct xdp_frame *xdpf;
458 struct mlx5e_dma_info di;
463 struct mlx5e_xdp_xmit_data {
469 struct mlx5e_xdp_info_fifo {
470 struct mlx5e_xdp_info *xi;
476 struct mlx5e_xdp_wqe_info {
481 struct mlx5e_xdp_mpwqe {
482 /* Current MPWQE session */
483 struct mlx5e_tx_wqe *wqe;
492 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
493 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
494 struct mlx5e_xdp_xmit_data *,
495 struct mlx5e_xdp_info *,
501 /* dirtied @completion */
506 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
508 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
509 struct mlx5e_xdp_mpwqe mpwqe;
514 struct xdp_umem *umem;
515 struct mlx5_wq_cyc wq;
516 struct mlx5e_xdpsq_stats *stats;
517 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
518 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
520 struct mlx5e_xdp_wqe_info *wqe_info;
521 struct mlx5e_xdp_info_fifo xdpi_fifo;
523 void __iomem *uar_map;
532 struct mlx5_wq_ctrl wq_ctrl;
533 struct mlx5e_channel *channel;
534 } ____cacheline_aligned_in_smp;
541 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
544 /* write@xmit, read@completion */
546 struct mlx5e_sq_wqe_info *ico_wqe;
550 struct mlx5_wq_cyc wq;
551 void __iomem *uar_map;
556 struct mlx5_wq_ctrl wq_ctrl;
557 struct mlx5e_channel *channel;
558 } ____cacheline_aligned_in_smp;
560 struct mlx5e_wqe_frag_info {
561 struct mlx5e_dma_info *di;
566 struct mlx5e_umr_dma_info {
567 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
570 struct mlx5e_mpw_info {
571 struct mlx5e_umr_dma_info umr;
572 u16 consumed_strides;
573 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
576 #define MLX5E_MAX_RX_FRAGS 4
578 /* a single cache unit is capable to serve one napi call (for non-striding rq)
579 * or a MPWQE (for striding rq).
581 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
582 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
583 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
584 struct mlx5e_page_cache {
587 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
591 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
592 typedef struct sk_buff *
593 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
594 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
595 typedef struct sk_buff *
596 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
597 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
598 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
599 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
602 MLX5E_RQ_FLAG_XDP_XMIT,
603 MLX5E_RQ_FLAG_XDP_REDIRECT,
606 struct mlx5e_rq_frag_info {
611 struct mlx5e_rq_frags_info {
612 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
622 struct mlx5_wq_cyc wq;
623 struct mlx5e_wqe_frag_info *frags;
624 struct mlx5e_dma_info *di;
625 struct mlx5e_rq_frags_info info;
626 mlx5e_fp_skb_from_cqe skb_from_cqe;
629 struct mlx5_wq_ll wq;
630 struct mlx5e_umr_wqe umr_wqe;
631 struct mlx5e_mpw_info *info;
632 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
644 u8 map_dir; /* dma map direction */
647 struct mlx5e_channel *channel;
649 struct net_device *netdev;
650 struct mlx5e_rq_stats *stats;
652 struct mlx5e_cq_decomp cqd;
653 struct mlx5e_page_cache page_cache;
654 struct hwtstamp_config *tstamp;
655 struct mlx5_clock *clock;
657 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
658 mlx5e_fp_post_rx_wqes post_wqes;
659 mlx5e_fp_dealloc_wqe dealloc_wqe;
665 struct dim dim; /* Dynamic Interrupt Moderation */
668 struct bpf_prog *xdp_prog;
669 struct mlx5e_xdpsq *xdpsq;
670 DECLARE_BITMAP(flags, 8);
671 struct page_pool *page_pool;
673 /* AF_XDP zero-copy */
674 struct zero_copy_allocator zca;
675 struct xdp_umem *umem;
678 struct mlx5_wq_ctrl wq_ctrl;
682 struct mlx5_core_dev *mdev;
683 struct mlx5_core_mkey umr_mkey;
685 /* XDP read-mostly */
686 struct xdp_rxq_info xdp_rxq;
687 } ____cacheline_aligned_in_smp;
689 enum mlx5e_channel_state {
690 MLX5E_CHANNEL_STATE_XSK,
691 MLX5E_CHANNEL_NUM_STATES
694 struct mlx5e_channel {
697 struct mlx5e_xdpsq rq_xdpsq;
698 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
699 struct mlx5e_icosq icosq; /* internal control operations */
701 struct napi_struct napi;
703 struct net_device *netdev;
708 struct mlx5e_xdpsq xdpsq;
710 /* AF_XDP zero-copy */
711 struct mlx5e_rq xskrq;
712 struct mlx5e_xdpsq xsksq;
713 struct mlx5e_icosq xskicosq;
714 /* xskicosq can be accessed from any CPU - the spinlock protects it. */
715 spinlock_t xskicosq_lock;
717 /* data path - accessed per napi poll */
718 struct irq_desc *irq_desc;
719 struct mlx5e_ch_stats *stats;
722 struct mlx5e_priv *priv;
723 struct mlx5_core_dev *mdev;
724 struct hwtstamp_config *tstamp;
725 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
728 cpumask_var_t xps_cpumask;
731 struct mlx5e_channels {
732 struct mlx5e_channel **c;
734 struct mlx5e_params params;
737 struct mlx5e_channel_stats {
738 struct mlx5e_ch_stats ch;
739 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
740 struct mlx5e_rq_stats rq;
741 struct mlx5e_rq_stats xskrq;
742 struct mlx5e_xdpsq_stats rq_xdpsq;
743 struct mlx5e_xdpsq_stats xdpsq;
744 struct mlx5e_xdpsq_stats xsksq;
745 } ____cacheline_aligned_in_smp;
749 MLX5E_STATE_DESTROYING,
750 MLX5E_STATE_XDP_TX_ENABLED,
751 MLX5E_STATE_XDP_OPEN,
761 struct mlx5e_rqt rqt;
762 struct list_head list;
770 struct mlx5e_rss_params {
771 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
772 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
773 u8 toeplitz_hash_key[40];
777 struct mlx5e_modify_sq_param {
785 /* UMEMs are stored separately from channels, because we don't want to
786 * lose them when channels are recreated. The kernel also stores UMEMs,
787 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
788 * so rely on our mechanism.
790 struct xdp_umem **umems;
796 /* priv data path fields - start */
797 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
798 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
799 #ifdef CONFIG_MLX5_CORE_EN_DCB
800 struct mlx5e_dcbx_dp dcbx_dp;
802 /* priv data path fields - end */
806 struct mutex state_lock; /* Protects Interface state */
807 struct mlx5e_rq drop_rq;
809 struct mlx5e_channels channels;
810 u32 tisn[MLX5E_MAX_NUM_TC];
811 struct mlx5e_rqt indir_rqt;
812 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
813 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
814 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
815 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
816 struct mlx5e_rss_params rss_params;
817 u32 tx_rates[MLX5E_MAX_NUM_SQS];
819 struct mlx5e_flow_steering fs;
821 struct workqueue_struct *wq;
822 struct work_struct update_carrier_work;
823 struct work_struct set_rx_mode_work;
824 struct work_struct tx_timeout_work;
825 struct work_struct update_stats_work;
826 struct work_struct monitor_counters_work;
827 struct mlx5_nb monitor_counters_nb;
829 struct mlx5_core_dev *mdev;
830 struct net_device *netdev;
831 struct mlx5e_stats stats;
832 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
834 struct hwtstamp_config tstamp;
836 u16 drop_rq_q_counter;
837 struct notifier_block events_nb;
839 #ifdef CONFIG_MLX5_CORE_EN_DCB
840 struct mlx5e_dcbx dcbx;
843 const struct mlx5e_profile *profile;
845 #ifdef CONFIG_MLX5_EN_IPSEC
846 struct mlx5e_ipsec *ipsec;
848 #ifdef CONFIG_MLX5_EN_TLS
849 struct mlx5e_tls *tls;
851 struct devlink_health_reporter *tx_reporter;
852 struct mlx5e_xsk xsk;
855 struct mlx5e_profile {
856 int (*init)(struct mlx5_core_dev *mdev,
857 struct net_device *netdev,
858 const struct mlx5e_profile *profile, void *ppriv);
859 void (*cleanup)(struct mlx5e_priv *priv);
860 int (*init_rx)(struct mlx5e_priv *priv);
861 void (*cleanup_rx)(struct mlx5e_priv *priv);
862 int (*init_tx)(struct mlx5e_priv *priv);
863 void (*cleanup_tx)(struct mlx5e_priv *priv);
864 void (*enable)(struct mlx5e_priv *priv);
865 void (*disable)(struct mlx5e_priv *priv);
866 int (*update_rx)(struct mlx5e_priv *priv);
867 void (*update_stats)(struct mlx5e_priv *priv);
868 void (*update_carrier)(struct mlx5e_priv *priv);
870 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
871 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
876 void mlx5e_build_ptys2ethtool_map(void);
878 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
879 struct net_device *sb_dev);
880 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
881 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
882 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more);
884 void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
885 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
886 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
887 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
888 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
889 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
890 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
892 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
893 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
894 struct mlx5e_params *params);
896 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
897 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
898 struct mlx5e_dma_info *dma_info,
900 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
901 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
902 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
903 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
904 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
905 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
906 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
908 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
909 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
911 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
912 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
914 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
915 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
917 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
918 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
920 void mlx5e_update_stats(struct mlx5e_priv *priv);
921 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
922 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
924 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
925 int mlx5e_self_test_num(struct mlx5e_priv *priv);
926 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
928 void mlx5e_set_rx_mode_work(struct work_struct *work);
930 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
931 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
932 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
934 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
936 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
938 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
940 struct mlx5e_redirect_rqt_param {
943 u32 rqn; /* Direct RQN (Non-RSS) */
946 struct mlx5e_channels *channels;
947 } rss; /* RSS data */
951 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
952 struct mlx5e_redirect_rqt_param rrp);
953 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
954 const struct mlx5e_tirc_config *ttconfig,
955 void *tirc, bool inner);
956 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
957 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
959 struct mlx5e_xsk_param;
961 struct mlx5e_rq_param;
962 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
963 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
964 struct xdp_umem *umem, struct mlx5e_rq *rq);
965 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
966 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
967 void mlx5e_close_rq(struct mlx5e_rq *rq);
969 struct mlx5e_sq_param;
970 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
971 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
972 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
973 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
974 struct mlx5e_sq_param *param, struct xdp_umem *umem,
975 struct mlx5e_xdpsq *sq, bool is_redirect);
976 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
978 struct mlx5e_cq_param;
979 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
980 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
981 void mlx5e_close_cq(struct mlx5e_cq *cq);
983 int mlx5e_open_locked(struct net_device *netdev);
984 int mlx5e_close_locked(struct net_device *netdev);
986 int mlx5e_open_channels(struct mlx5e_priv *priv,
987 struct mlx5e_channels *chs);
988 void mlx5e_close_channels(struct mlx5e_channels *chs);
990 /* Function pointer to be used to modify WH settings while
993 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
994 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
995 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
996 struct mlx5e_channels *new_chs,
997 mlx5e_fp_hw_modify hw_modify);
998 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
999 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1001 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1003 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
1005 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
1007 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
1008 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
1009 struct mlx5e_params *params);
1011 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1012 struct mlx5e_modify_sq_param *p);
1013 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1014 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1016 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
1018 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
1019 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
1022 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1024 return MLX5_CAP_ETH(mdev, swp) &&
1025 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1028 extern const struct ethtool_ops mlx5e_ethtool_ops;
1029 #ifdef CONFIG_MLX5_CORE_EN_DCB
1030 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1031 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1032 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1033 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1034 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1037 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1038 struct mlx5e_tir *tir, u32 *in, int inlen);
1039 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1040 struct mlx5e_tir *tir);
1041 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1042 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1043 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1045 /* common netdev helpers */
1046 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1047 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1048 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1049 struct mlx5e_rq *drop_rq);
1050 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1052 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1054 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1055 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1057 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1058 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1059 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1060 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1061 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1063 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1064 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1066 int mlx5e_create_tises(struct mlx5e_priv *priv);
1067 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1068 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1069 int mlx5e_close(struct net_device *netdev);
1070 int mlx5e_open(struct net_device *netdev);
1071 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
1073 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1074 int mlx5e_bits_invert(unsigned long a, int size);
1076 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
1077 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1078 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1079 change_hw_mtu_cb set_mtu_cb);
1081 /* ethtool helpers */
1082 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1083 struct ethtool_drvinfo *drvinfo);
1084 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1085 uint32_t stringset, uint8_t *data);
1086 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1087 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1088 struct ethtool_stats *stats, u64 *data);
1089 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1090 struct ethtool_ringparam *param);
1091 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1092 struct ethtool_ringparam *param);
1093 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1094 struct ethtool_channels *ch);
1095 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1096 struct ethtool_channels *ch);
1097 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1098 struct ethtool_coalesce *coal);
1099 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1100 struct ethtool_coalesce *coal);
1101 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1102 struct ethtool_link_ksettings *link_ksettings);
1103 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1104 const struct ethtool_link_ksettings *link_ksettings);
1105 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1106 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1107 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1108 struct ethtool_ts_info *info);
1109 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1110 struct ethtool_pauseparam *pauseparam);
1111 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1112 struct ethtool_pauseparam *pauseparam);
1114 /* mlx5e generic netdev management API */
1115 int mlx5e_netdev_init(struct net_device *netdev,
1116 struct mlx5e_priv *priv,
1117 struct mlx5_core_dev *mdev,
1118 const struct mlx5e_profile *profile,
1120 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1122 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1123 int nch, void *ppriv);
1124 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1125 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1126 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1127 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1128 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1129 struct mlx5e_xsk *xsk,
1130 struct mlx5e_rss_params *rss_params,
1131 struct mlx5e_params *params,
1132 u16 max_channels, u16 mtu);
1133 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1134 struct mlx5e_params *params);
1135 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1137 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1138 void mlx5e_rx_dim_work(struct work_struct *work);
1139 void mlx5e_tx_dim_work(struct work_struct *work);
1141 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1142 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1143 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1144 struct net_device *netdev,
1145 netdev_features_t features);
1146 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1147 #ifdef CONFIG_MLX5_ESWITCH
1148 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1149 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1150 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1151 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1153 #endif /* __MLX5_EN_H__ */