1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies */
11 #include "sf/dev/dev.h"
14 static int mlx5_devlink_flash_update(struct devlink *devlink,
15 struct devlink_flash_update_params *params,
16 struct netlink_ext_ack *extack)
18 struct mlx5_core_dev *dev = devlink_priv(devlink);
20 return mlx5_firmware_flash(dev, params->fw, extack);
23 static u8 mlx5_fw_ver_major(u32 version)
25 return (version >> 24) & 0xff;
28 static u8 mlx5_fw_ver_minor(u32 version)
30 return (version >> 16) & 0xff;
33 static u16 mlx5_fw_ver_subminor(u32 version)
35 return version & 0xffff;
38 #define DEVLINK_FW_STRING_LEN 32
41 mlx5_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
42 struct netlink_ext_ack *extack)
44 struct mlx5_core_dev *dev = devlink_priv(devlink);
45 char version_str[DEVLINK_FW_STRING_LEN];
46 u32 running_fw, stored_fw;
49 err = devlink_info_version_fixed_put(req, "fw.psid", dev->board_id);
53 err = mlx5_fw_version_query(dev, &running_fw, &stored_fw);
57 snprintf(version_str, sizeof(version_str), "%d.%d.%04d",
58 mlx5_fw_ver_major(running_fw), mlx5_fw_ver_minor(running_fw),
59 mlx5_fw_ver_subminor(running_fw));
60 err = devlink_info_version_running_put(req, "fw.version", version_str);
63 err = devlink_info_version_running_put(req,
64 DEVLINK_INFO_VERSION_GENERIC_FW,
69 /* no pending version, return running (stored) version */
71 stored_fw = running_fw;
73 snprintf(version_str, sizeof(version_str), "%d.%d.%04d",
74 mlx5_fw_ver_major(stored_fw), mlx5_fw_ver_minor(stored_fw),
75 mlx5_fw_ver_subminor(stored_fw));
76 err = devlink_info_version_stored_put(req, "fw.version", version_str);
79 return devlink_info_version_stored_put(req,
80 DEVLINK_INFO_VERSION_GENERIC_FW,
84 static int mlx5_devlink_reload_fw_activate(struct devlink *devlink, struct netlink_ext_ack *extack)
86 struct mlx5_core_dev *dev = devlink_priv(devlink);
87 u8 reset_level, reset_type, net_port_alive;
90 err = mlx5_fw_reset_query(dev, &reset_level, &reset_type);
93 if (!(reset_level & MLX5_MFRL_REG_RESET_LEVEL3)) {
94 NL_SET_ERR_MSG_MOD(extack, "FW activate requires reboot");
98 net_port_alive = !!(reset_type & MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE);
99 err = mlx5_fw_reset_set_reset_sync(dev, net_port_alive, extack);
103 err = mlx5_fw_reset_wait_reset_done(dev);
107 mlx5_unload_one_devl_locked(dev, true);
108 err = mlx5_health_wait_pci_up(dev);
110 NL_SET_ERR_MSG_MOD(extack, "FW activate aborted, PCI reads fail after reset");
115 static int mlx5_devlink_trigger_fw_live_patch(struct devlink *devlink,
116 struct netlink_ext_ack *extack)
118 struct mlx5_core_dev *dev = devlink_priv(devlink);
122 err = mlx5_fw_reset_query(dev, &reset_level, NULL);
125 if (!(reset_level & MLX5_MFRL_REG_RESET_LEVEL0)) {
126 NL_SET_ERR_MSG_MOD(extack,
127 "FW upgrade to the stored FW can't be done by FW live patching");
131 return mlx5_fw_reset_set_live_patch(dev);
134 static int mlx5_devlink_reload_down(struct devlink *devlink, bool netns_change,
135 enum devlink_reload_action action,
136 enum devlink_reload_limit limit,
137 struct netlink_ext_ack *extack)
139 struct mlx5_core_dev *dev = devlink_priv(devlink);
140 struct pci_dev *pdev = dev->pdev;
143 if (mlx5_dev_is_lightweight(dev)) {
144 if (action != DEVLINK_RELOAD_ACTION_DRIVER_REINIT)
146 mlx5_unload_one_light(dev);
150 if (mlx5_lag_is_active(dev)) {
151 NL_SET_ERR_MSG_MOD(extack, "reload is unsupported in Lag mode");
155 if (mlx5_core_is_mp_slave(dev)) {
156 NL_SET_ERR_MSG_MOD(extack, "reload is unsupported for multi port slave");
160 if (mlx5_core_is_pf(dev) && pci_num_vf(pdev))
161 NL_SET_ERR_MSG_MOD(extack, "reload while VFs are present is unfavorable");
164 case DEVLINK_RELOAD_ACTION_DRIVER_REINIT:
165 mlx5_unload_one_devl_locked(dev, false);
167 case DEVLINK_RELOAD_ACTION_FW_ACTIVATE:
168 if (limit == DEVLINK_RELOAD_LIMIT_NO_RESET)
169 ret = mlx5_devlink_trigger_fw_live_patch(devlink, extack);
171 ret = mlx5_devlink_reload_fw_activate(devlink, extack);
174 /* Unsupported action should not get to this function */
182 static int mlx5_devlink_reload_up(struct devlink *devlink, enum devlink_reload_action action,
183 enum devlink_reload_limit limit, u32 *actions_performed,
184 struct netlink_ext_ack *extack)
186 struct mlx5_core_dev *dev = devlink_priv(devlink);
189 *actions_performed = BIT(action);
191 case DEVLINK_RELOAD_ACTION_DRIVER_REINIT:
192 if (mlx5_dev_is_lightweight(dev)) {
193 mlx5_fw_reporters_create(dev);
194 return mlx5_init_one_devl_locked(dev);
196 ret = mlx5_load_one_devl_locked(dev, false);
198 case DEVLINK_RELOAD_ACTION_FW_ACTIVATE:
199 if (limit == DEVLINK_RELOAD_LIMIT_NO_RESET)
201 /* On fw_activate action, also driver is reloaded and reinit performed */
202 *actions_performed |= BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT);
203 ret = mlx5_load_one_devl_locked(dev, true);
206 ret = mlx5_fw_reset_verify_fw_complete(dev, extack);
209 /* Unsupported action should not get to this function */
217 static struct mlx5_devlink_trap *mlx5_find_trap_by_id(struct mlx5_core_dev *dev, int trap_id)
219 struct mlx5_devlink_trap *dl_trap;
221 list_for_each_entry(dl_trap, &dev->priv.traps, list)
222 if (dl_trap->trap.id == trap_id)
228 static int mlx5_devlink_trap_init(struct devlink *devlink, const struct devlink_trap *trap,
231 struct mlx5_core_dev *dev = devlink_priv(devlink);
232 struct mlx5_devlink_trap *dl_trap;
234 dl_trap = kzalloc(sizeof(*dl_trap), GFP_KERNEL);
238 dl_trap->trap.id = trap->id;
239 dl_trap->trap.action = DEVLINK_TRAP_ACTION_DROP;
240 dl_trap->item = trap_ctx;
242 if (mlx5_find_trap_by_id(dev, trap->id)) {
244 mlx5_core_err(dev, "Devlink trap: Trap 0x%x already found", trap->id);
248 list_add_tail(&dl_trap->list, &dev->priv.traps);
252 static void mlx5_devlink_trap_fini(struct devlink *devlink, const struct devlink_trap *trap,
255 struct mlx5_core_dev *dev = devlink_priv(devlink);
256 struct mlx5_devlink_trap *dl_trap;
258 dl_trap = mlx5_find_trap_by_id(dev, trap->id);
260 mlx5_core_err(dev, "Devlink trap: Missing trap id 0x%x", trap->id);
263 list_del(&dl_trap->list);
267 static int mlx5_devlink_trap_action_set(struct devlink *devlink,
268 const struct devlink_trap *trap,
269 enum devlink_trap_action action,
270 struct netlink_ext_ack *extack)
272 struct mlx5_core_dev *dev = devlink_priv(devlink);
273 struct mlx5_devlink_trap_event_ctx trap_event_ctx;
274 enum devlink_trap_action action_orig;
275 struct mlx5_devlink_trap *dl_trap;
278 if (is_mdev_switchdev_mode(dev)) {
279 NL_SET_ERR_MSG_MOD(extack, "Devlink traps can't be set in switchdev mode");
283 dl_trap = mlx5_find_trap_by_id(dev, trap->id);
285 mlx5_core_err(dev, "Devlink trap: Set action on invalid trap id 0x%x", trap->id);
289 if (action != DEVLINK_TRAP_ACTION_DROP && action != DEVLINK_TRAP_ACTION_TRAP)
292 if (action == dl_trap->trap.action)
295 action_orig = dl_trap->trap.action;
296 dl_trap->trap.action = action;
297 trap_event_ctx.trap = &dl_trap->trap;
298 trap_event_ctx.err = 0;
299 err = mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_TYPE_TRAP,
301 if (err == NOTIFY_BAD)
302 dl_trap->trap.action = action_orig;
304 return trap_event_ctx.err;
307 static const struct devlink_ops mlx5_devlink_ops = {
308 #ifdef CONFIG_MLX5_ESWITCH
309 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
310 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
311 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
312 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
313 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
314 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
315 .rate_leaf_tx_share_set = mlx5_esw_devlink_rate_leaf_tx_share_set,
316 .rate_leaf_tx_max_set = mlx5_esw_devlink_rate_leaf_tx_max_set,
317 .rate_node_tx_share_set = mlx5_esw_devlink_rate_node_tx_share_set,
318 .rate_node_tx_max_set = mlx5_esw_devlink_rate_node_tx_max_set,
319 .rate_node_new = mlx5_esw_devlink_rate_node_new,
320 .rate_node_del = mlx5_esw_devlink_rate_node_del,
321 .rate_leaf_parent_set = mlx5_esw_devlink_rate_parent_set,
323 #ifdef CONFIG_MLX5_SF_MANAGER
324 .port_new = mlx5_devlink_sf_port_new,
326 .flash_update = mlx5_devlink_flash_update,
327 .info_get = mlx5_devlink_info_get,
328 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
329 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE),
330 .reload_limits = BIT(DEVLINK_RELOAD_LIMIT_NO_RESET),
331 .reload_down = mlx5_devlink_reload_down,
332 .reload_up = mlx5_devlink_reload_up,
333 .trap_init = mlx5_devlink_trap_init,
334 .trap_fini = mlx5_devlink_trap_fini,
335 .trap_action_set = mlx5_devlink_trap_action_set,
338 void mlx5_devlink_trap_report(struct mlx5_core_dev *dev, int trap_id, struct sk_buff *skb,
339 struct devlink_port *dl_port)
341 struct devlink *devlink = priv_to_devlink(dev);
342 struct mlx5_devlink_trap *dl_trap;
344 dl_trap = mlx5_find_trap_by_id(dev, trap_id);
346 mlx5_core_err(dev, "Devlink trap: Report on invalid trap id 0x%x", trap_id);
350 if (dl_trap->trap.action != DEVLINK_TRAP_ACTION_TRAP) {
351 mlx5_core_dbg(dev, "Devlink trap: Trap id %d has action %d", trap_id,
352 dl_trap->trap.action);
355 devlink_trap_report(devlink, skb, dl_trap->item, dl_port, NULL);
358 int mlx5_devlink_trap_get_num_active(struct mlx5_core_dev *dev)
360 struct mlx5_devlink_trap *dl_trap;
363 list_for_each_entry(dl_trap, &dev->priv.traps, list)
364 if (dl_trap->trap.action == DEVLINK_TRAP_ACTION_TRAP)
370 int mlx5_devlink_traps_get_action(struct mlx5_core_dev *dev, int trap_id,
371 enum devlink_trap_action *action)
373 struct mlx5_devlink_trap *dl_trap;
375 dl_trap = mlx5_find_trap_by_id(dev, trap_id);
377 mlx5_core_err(dev, "Devlink trap: Get action on invalid trap id 0x%x",
382 *action = dl_trap->trap.action;
386 struct devlink *mlx5_devlink_alloc(struct device *dev)
388 return devlink_alloc(&mlx5_devlink_ops, sizeof(struct mlx5_core_dev),
392 void mlx5_devlink_free(struct devlink *devlink)
394 devlink_free(devlink);
397 static int mlx5_devlink_enable_roce_validate(struct devlink *devlink, u32 id,
398 union devlink_param_value val,
399 struct netlink_ext_ack *extack)
401 struct mlx5_core_dev *dev = devlink_priv(devlink);
402 bool new_state = val.vbool;
404 if (new_state && !MLX5_CAP_GEN(dev, roce) &&
405 !(MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))) {
406 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support RoCE");
409 if (mlx5_core_is_mp_slave(dev) || mlx5_lag_is_active(dev)) {
410 NL_SET_ERR_MSG_MOD(extack, "Multi port slave/Lag device can't configure RoCE");
417 #ifdef CONFIG_MLX5_ESWITCH
418 static int mlx5_devlink_large_group_num_validate(struct devlink *devlink, u32 id,
419 union devlink_param_value val,
420 struct netlink_ext_ack *extack)
422 int group_num = val.vu32;
424 if (group_num < 1 || group_num > 1024) {
425 NL_SET_ERR_MSG_MOD(extack,
426 "Unsupported group number, supported range is 1-1024");
434 static int mlx5_devlink_eq_depth_validate(struct devlink *devlink, u32 id,
435 union devlink_param_value val,
436 struct netlink_ext_ack *extack)
438 return (val.vu32 >= 64 && val.vu32 <= 4096) ? 0 : -EINVAL;
442 mlx5_devlink_hairpin_num_queues_validate(struct devlink *devlink, u32 id,
443 union devlink_param_value val,
444 struct netlink_ext_ack *extack)
446 return val.vu32 ? 0 : -EINVAL;
450 mlx5_devlink_hairpin_queue_size_validate(struct devlink *devlink, u32 id,
451 union devlink_param_value val,
452 struct netlink_ext_ack *extack)
454 struct mlx5_core_dev *dev = devlink_priv(devlink);
455 u32 val32 = val.vu32;
457 if (!is_power_of_2(val32)) {
458 NL_SET_ERR_MSG_MOD(extack, "Value is not power of two");
462 if (val32 > BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))) {
463 NL_SET_ERR_MSG_FMT_MOD(
464 extack, "Maximum hairpin queue size is %lu",
465 BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets)));
472 static void mlx5_devlink_hairpin_params_init_values(struct devlink *devlink)
474 struct mlx5_core_dev *dev = devlink_priv(devlink);
475 union devlink_param_value value;
479 /* set hairpin pair per each 50Gbs share of the link */
480 mlx5_port_max_linkspeed(dev, &link_speed);
481 link_speed = max_t(u32, link_speed, 50000);
482 link_speed64 = link_speed;
483 do_div(link_speed64, 50000);
485 value.vu32 = link_speed64;
486 devl_param_driverinit_value_set(
487 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, value);
490 BIT(min_t(u32, 16 - MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(dev),
491 MLX5_CAP_GEN(dev, log_max_hairpin_num_packets)));
492 devl_param_driverinit_value_set(
493 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, value);
496 static const struct devlink_param mlx5_devlink_params[] = {
497 DEVLINK_PARAM_GENERIC(ENABLE_ROCE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
498 NULL, NULL, mlx5_devlink_enable_roce_validate),
499 #ifdef CONFIG_MLX5_ESWITCH
500 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM,
501 "fdb_large_groups", DEVLINK_PARAM_TYPE_U32,
502 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
504 mlx5_devlink_large_group_num_validate),
506 DEVLINK_PARAM_GENERIC(IO_EQ_SIZE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
507 NULL, NULL, mlx5_devlink_eq_depth_validate),
508 DEVLINK_PARAM_GENERIC(EVENT_EQ_SIZE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
509 NULL, NULL, mlx5_devlink_eq_depth_validate),
512 static void mlx5_devlink_set_params_init_values(struct devlink *devlink)
514 struct mlx5_core_dev *dev = devlink_priv(devlink);
515 union devlink_param_value value;
517 value.vbool = MLX5_CAP_GEN(dev, roce) && !mlx5_dev_is_lightweight(dev);
518 devl_param_driverinit_value_set(devlink,
519 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
522 #ifdef CONFIG_MLX5_ESWITCH
523 value.vu32 = ESW_OFFLOADS_DEFAULT_NUM_GROUPS;
524 devl_param_driverinit_value_set(devlink,
525 MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM,
529 value.vu32 = MLX5_COMP_EQ_SIZE;
530 devl_param_driverinit_value_set(devlink,
531 DEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE,
534 value.vu32 = MLX5_NUM_ASYNC_EQE;
535 devl_param_driverinit_value_set(devlink,
536 DEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE,
540 static const struct devlink_param mlx5_devlink_eth_params[] = {
541 DEVLINK_PARAM_GENERIC(ENABLE_ETH, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
543 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES,
544 "hairpin_num_queues", DEVLINK_PARAM_TYPE_U32,
545 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL,
546 mlx5_devlink_hairpin_num_queues_validate),
547 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE,
548 "hairpin_queue_size", DEVLINK_PARAM_TYPE_U32,
549 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL,
550 mlx5_devlink_hairpin_queue_size_validate),
553 static int mlx5_devlink_eth_params_register(struct devlink *devlink)
555 struct mlx5_core_dev *dev = devlink_priv(devlink);
556 union devlink_param_value value;
559 if (!mlx5_eth_supported(dev))
562 err = devl_params_register(devlink, mlx5_devlink_eth_params,
563 ARRAY_SIZE(mlx5_devlink_eth_params));
567 value.vbool = !mlx5_dev_is_lightweight(dev);
568 devl_param_driverinit_value_set(devlink,
569 DEVLINK_PARAM_GENERIC_ID_ENABLE_ETH,
572 mlx5_devlink_hairpin_params_init_values(devlink);
577 static void mlx5_devlink_eth_params_unregister(struct devlink *devlink)
579 struct mlx5_core_dev *dev = devlink_priv(devlink);
581 if (!mlx5_eth_supported(dev))
584 devl_params_unregister(devlink, mlx5_devlink_eth_params,
585 ARRAY_SIZE(mlx5_devlink_eth_params));
588 static int mlx5_devlink_enable_rdma_validate(struct devlink *devlink, u32 id,
589 union devlink_param_value val,
590 struct netlink_ext_ack *extack)
592 struct mlx5_core_dev *dev = devlink_priv(devlink);
593 bool new_state = val.vbool;
595 if (new_state && !mlx5_rdma_supported(dev))
600 static const struct devlink_param mlx5_devlink_rdma_params[] = {
601 DEVLINK_PARAM_GENERIC(ENABLE_RDMA, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
602 NULL, NULL, mlx5_devlink_enable_rdma_validate),
605 static int mlx5_devlink_rdma_params_register(struct devlink *devlink)
607 struct mlx5_core_dev *dev = devlink_priv(devlink);
608 union devlink_param_value value;
611 if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
614 err = devl_params_register(devlink, mlx5_devlink_rdma_params,
615 ARRAY_SIZE(mlx5_devlink_rdma_params));
619 value.vbool = !mlx5_dev_is_lightweight(dev);
620 devl_param_driverinit_value_set(devlink,
621 DEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA,
626 static void mlx5_devlink_rdma_params_unregister(struct devlink *devlink)
628 if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
631 devl_params_unregister(devlink, mlx5_devlink_rdma_params,
632 ARRAY_SIZE(mlx5_devlink_rdma_params));
635 static const struct devlink_param mlx5_devlink_vnet_params[] = {
636 DEVLINK_PARAM_GENERIC(ENABLE_VNET, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
640 static int mlx5_devlink_vnet_params_register(struct devlink *devlink)
642 struct mlx5_core_dev *dev = devlink_priv(devlink);
643 union devlink_param_value value;
646 if (!mlx5_vnet_supported(dev))
649 err = devl_params_register(devlink, mlx5_devlink_vnet_params,
650 ARRAY_SIZE(mlx5_devlink_vnet_params));
654 value.vbool = !mlx5_dev_is_lightweight(dev);
655 devl_param_driverinit_value_set(devlink,
656 DEVLINK_PARAM_GENERIC_ID_ENABLE_VNET,
661 static void mlx5_devlink_vnet_params_unregister(struct devlink *devlink)
663 struct mlx5_core_dev *dev = devlink_priv(devlink);
665 if (!mlx5_vnet_supported(dev))
668 devl_params_unregister(devlink, mlx5_devlink_vnet_params,
669 ARRAY_SIZE(mlx5_devlink_vnet_params));
672 static int mlx5_devlink_auxdev_params_register(struct devlink *devlink)
676 err = mlx5_devlink_eth_params_register(devlink);
680 err = mlx5_devlink_rdma_params_register(devlink);
684 err = mlx5_devlink_vnet_params_register(devlink);
690 mlx5_devlink_rdma_params_unregister(devlink);
692 mlx5_devlink_eth_params_unregister(devlink);
696 static void mlx5_devlink_auxdev_params_unregister(struct devlink *devlink)
698 mlx5_devlink_vnet_params_unregister(devlink);
699 mlx5_devlink_rdma_params_unregister(devlink);
700 mlx5_devlink_eth_params_unregister(devlink);
703 static int mlx5_devlink_max_uc_list_validate(struct devlink *devlink, u32 id,
704 union devlink_param_value val,
705 struct netlink_ext_ack *extack)
707 struct mlx5_core_dev *dev = devlink_priv(devlink);
710 NL_SET_ERR_MSG_MOD(extack, "max_macs value must be greater than 0");
714 if (!is_power_of_2(val.vu32)) {
715 NL_SET_ERR_MSG_MOD(extack, "Only power of 2 values are supported for max_macs");
719 if (ilog2(val.vu32) >
720 MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list)) {
721 NL_SET_ERR_MSG_MOD(extack, "max_macs value is out of the supported range");
728 static const struct devlink_param mlx5_devlink_max_uc_list_params[] = {
729 DEVLINK_PARAM_GENERIC(MAX_MACS, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
730 NULL, NULL, mlx5_devlink_max_uc_list_validate),
733 static int mlx5_devlink_max_uc_list_params_register(struct devlink *devlink)
735 struct mlx5_core_dev *dev = devlink_priv(devlink);
736 union devlink_param_value value;
739 if (!MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list_wr_supported))
742 err = devl_params_register(devlink, mlx5_devlink_max_uc_list_params,
743 ARRAY_SIZE(mlx5_devlink_max_uc_list_params));
747 value.vu32 = 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list);
748 devl_param_driverinit_value_set(devlink,
749 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
755 mlx5_devlink_max_uc_list_params_unregister(struct devlink *devlink)
757 struct mlx5_core_dev *dev = devlink_priv(devlink);
759 if (!MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list_wr_supported))
762 devl_params_unregister(devlink, mlx5_devlink_max_uc_list_params,
763 ARRAY_SIZE(mlx5_devlink_max_uc_list_params));
766 #define MLX5_TRAP_DROP(_id, _group_id) \
767 DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
768 DEVLINK_TRAP_GROUP_GENERIC_ID_##_group_id, \
769 DEVLINK_TRAP_METADATA_TYPE_F_IN_PORT)
771 static const struct devlink_trap mlx5_traps_arr[] = {
772 MLX5_TRAP_DROP(INGRESS_VLAN_FILTER, L2_DROPS),
773 MLX5_TRAP_DROP(DMAC_FILTER, L2_DROPS),
776 static const struct devlink_trap_group mlx5_trap_groups_arr[] = {
777 DEVLINK_TRAP_GROUP_GENERIC(L2_DROPS, 0),
780 int mlx5_devlink_traps_register(struct devlink *devlink)
782 struct mlx5_core_dev *core_dev = devlink_priv(devlink);
785 err = devl_trap_groups_register(devlink, mlx5_trap_groups_arr,
786 ARRAY_SIZE(mlx5_trap_groups_arr));
790 err = devl_traps_register(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr),
797 devl_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
798 ARRAY_SIZE(mlx5_trap_groups_arr));
802 void mlx5_devlink_traps_unregister(struct devlink *devlink)
804 devl_traps_unregister(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr));
805 devl_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
806 ARRAY_SIZE(mlx5_trap_groups_arr));
809 int mlx5_devlink_params_register(struct devlink *devlink)
813 /* Here only the driver init params should be registered.
814 * Runtime params should be registered by the code which
815 * behaviour they configure.
818 err = devl_params_register(devlink, mlx5_devlink_params,
819 ARRAY_SIZE(mlx5_devlink_params));
823 mlx5_devlink_set_params_init_values(devlink);
825 err = mlx5_devlink_auxdev_params_register(devlink);
829 err = mlx5_devlink_max_uc_list_params_register(devlink);
831 goto max_uc_list_err;
836 mlx5_devlink_auxdev_params_unregister(devlink);
838 devl_params_unregister(devlink, mlx5_devlink_params,
839 ARRAY_SIZE(mlx5_devlink_params));
843 void mlx5_devlink_params_unregister(struct devlink *devlink)
845 mlx5_devlink_max_uc_list_params_unregister(devlink);
846 mlx5_devlink_auxdev_params_unregister(devlink);
847 devl_params_unregister(devlink, mlx5_devlink_params,
848 ARRAY_SIZE(mlx5_devlink_params));