1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Intel Corporation */
6 #include <linux/module.h>
7 #include <linux/device.h>
9 #include <linux/ptp_classify.h>
10 #include <linux/clocksource.h>
11 #include <linux/ktime.h>
12 #include <linux/delay.h>
13 #include <linux/iopoll.h>
15 #define INCVALUE_MASK 0x7fffffff
16 #define ISGN 0x80000000
18 #define IGC_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
19 #define IGC_PTP_TX_TIMEOUT (HZ * 15)
21 #define IGC_PTM_STAT_SLEEP 2
22 #define IGC_PTM_STAT_TIMEOUT 100
24 /* SYSTIM read access for I225 */
25 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
27 struct igc_hw *hw = &adapter->hw;
30 /* The timestamp is latched when SYSTIML is read. */
31 nsec = rd32(IGC_SYSTIML);
32 sec = rd32(IGC_SYSTIMH);
38 static void igc_ptp_write_i225(struct igc_adapter *adapter,
39 const struct timespec64 *ts)
41 struct igc_hw *hw = &adapter->hw;
43 wr32(IGC_SYSTIML, ts->tv_nsec);
44 wr32(IGC_SYSTIMH, ts->tv_sec);
47 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
49 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
51 struct igc_hw *hw = &igc->hw;
58 scaled_ppm = -scaled_ppm;
62 rate = div_u64(rate, 78125);
64 inca = rate & INCVALUE_MASK;
68 wr32(IGC_TIMINCA, inca);
73 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
75 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
77 struct timespec64 now, then = ns_to_timespec64(delta);
80 spin_lock_irqsave(&igc->tmreg_lock, flags);
82 igc_ptp_read(igc, &now);
83 now = timespec64_add(now, then);
84 igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
86 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
91 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
92 struct timespec64 *ts,
93 struct ptp_system_timestamp *sts)
95 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
97 struct igc_hw *hw = &igc->hw;
100 spin_lock_irqsave(&igc->tmreg_lock, flags);
102 ptp_read_system_prets(sts);
103 ts->tv_nsec = rd32(IGC_SYSTIML);
104 ts->tv_sec = rd32(IGC_SYSTIMH);
105 ptp_read_system_postts(sts);
107 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
112 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
113 const struct timespec64 *ts)
115 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
119 spin_lock_irqsave(&igc->tmreg_lock, flags);
121 igc_ptp_write_i225(igc, ts);
123 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
128 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
130 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
131 static const u32 mask[IGC_N_SDP] = {
134 IGC_CTRL_EXT_SDP2_DIR,
135 IGC_CTRL_EXT_SDP3_DIR,
144 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
146 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
147 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
149 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
150 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
152 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
153 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
155 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
156 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
157 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
159 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
160 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
161 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
163 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
164 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
165 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
167 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
168 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
169 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
171 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
172 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
173 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
175 struct igc_hw *hw = &igc->hw;
176 u32 ctrl, ctrl_ext, tssdp = 0;
178 ctrl = rd32(IGC_CTRL);
179 ctrl_ext = rd32(IGC_CTRL_EXT);
180 tssdp = rd32(IGC_TSSDP);
182 igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
184 /* Make sure this pin is not enabled as an input. */
185 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
186 tssdp &= ~IGC_AUX0_TS_SDP_EN;
188 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
189 tssdp &= ~IGC_AUX1_TS_SDP_EN;
191 tssdp &= ~igc_ts_sdp_sel_clr[pin];
194 tssdp |= igc_ts_sdp_sel_fc1[pin];
196 tssdp |= igc_ts_sdp_sel_fc0[pin];
199 tssdp |= igc_ts_sdp_sel_tt1[pin];
201 tssdp |= igc_ts_sdp_sel_tt0[pin];
203 tssdp |= igc_ts_sdp_en[pin];
205 wr32(IGC_TSSDP, tssdp);
206 wr32(IGC_CTRL, ctrl);
207 wr32(IGC_CTRL_EXT, ctrl_ext);
210 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
212 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
213 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
215 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
216 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
218 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
219 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
221 struct igc_hw *hw = &igc->hw;
222 u32 ctrl, ctrl_ext, tssdp = 0;
224 ctrl = rd32(IGC_CTRL);
225 ctrl_ext = rd32(IGC_CTRL_EXT);
226 tssdp = rd32(IGC_TSSDP);
228 igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
230 /* Make sure this pin is not enabled as an output. */
231 tssdp &= ~igc_ts_sdp_en[pin];
234 tssdp &= ~IGC_AUX1_SEL_SDP3;
235 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
237 tssdp &= ~IGC_AUX0_SEL_SDP3;
238 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
241 wr32(IGC_TSSDP, tssdp);
242 wr32(IGC_CTRL, ctrl);
243 wr32(IGC_CTRL_EXT, ctrl_ext);
246 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
247 struct ptp_clock_request *rq, int on)
249 struct igc_adapter *igc =
250 container_of(ptp, struct igc_adapter, ptp_caps);
251 struct igc_hw *hw = &igc->hw;
253 struct timespec64 ts;
254 int use_freq = 0, pin = -1;
255 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
259 case PTP_CLK_REQ_EXTTS:
260 /* Reject requests with unsupported flags */
261 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
267 /* Reject requests failing to enable both edges. */
268 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
269 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
270 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
274 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
279 if (rq->extts.index == 1) {
280 tsauxc_mask = IGC_TSAUXC_EN_TS1;
281 tsim_mask = IGC_TSICR_AUTT1;
283 tsauxc_mask = IGC_TSAUXC_EN_TS0;
284 tsim_mask = IGC_TSICR_AUTT0;
286 spin_lock_irqsave(&igc->tmreg_lock, flags);
287 tsauxc = rd32(IGC_TSAUXC);
288 tsim = rd32(IGC_TSIM);
290 igc_pin_extts(igc, rq->extts.index, pin);
291 tsauxc |= tsauxc_mask;
294 tsauxc &= ~tsauxc_mask;
297 wr32(IGC_TSAUXC, tsauxc);
298 wr32(IGC_TSIM, tsim);
299 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
302 case PTP_CLK_REQ_PEROUT:
303 /* Reject requests with unsupported flags */
304 if (rq->perout.flags)
308 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
313 ts.tv_sec = rq->perout.period.sec;
314 ts.tv_nsec = rq->perout.period.nsec;
315 ns = timespec64_to_ns(&ts);
317 if (on && (ns <= 70000000LL || ns == 125000000LL ||
318 ns == 250000000LL || ns == 500000000LL)) {
323 ts = ns_to_timespec64(ns);
324 if (rq->perout.index == 1) {
326 tsauxc_mask = IGC_TSAUXC_EN_CLK1;
329 tsauxc_mask = IGC_TSAUXC_EN_TT1;
330 tsim_mask = IGC_TSICR_TT1;
332 trgttiml = IGC_TRGTTIML1;
333 trgttimh = IGC_TRGTTIMH1;
334 freqout = IGC_FREQOUT1;
337 tsauxc_mask = IGC_TSAUXC_EN_CLK0;
340 tsauxc_mask = IGC_TSAUXC_EN_TT0;
341 tsim_mask = IGC_TSICR_TT0;
343 trgttiml = IGC_TRGTTIML0;
344 trgttimh = IGC_TRGTTIMH0;
345 freqout = IGC_FREQOUT0;
347 spin_lock_irqsave(&igc->tmreg_lock, flags);
348 tsauxc = rd32(IGC_TSAUXC);
349 tsim = rd32(IGC_TSIM);
350 if (rq->perout.index == 1) {
351 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1);
352 tsim &= ~IGC_TSICR_TT1;
354 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0);
355 tsim &= ~IGC_TSICR_TT0;
358 int i = rq->perout.index;
360 igc_pin_perout(igc, i, pin, use_freq);
361 igc->perout[i].start.tv_sec = rq->perout.start.sec;
362 igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
363 igc->perout[i].period.tv_sec = ts.tv_sec;
364 igc->perout[i].period.tv_nsec = ts.tv_nsec;
365 wr32(trgttimh, rq->perout.start.sec);
366 /* For now, always select timer 0 as source. */
367 wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
370 tsauxc |= tsauxc_mask;
373 wr32(IGC_TSAUXC, tsauxc);
374 wr32(IGC_TSIM, tsim);
375 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
378 case PTP_CLK_REQ_PPS:
379 spin_lock_irqsave(&igc->tmreg_lock, flags);
380 tsim = rd32(IGC_TSIM);
382 tsim |= IGC_TSICR_SYS_WRAP;
384 tsim &= ~IGC_TSICR_SYS_WRAP;
385 igc->pps_sys_wrap_on = on;
386 wr32(IGC_TSIM, tsim);
387 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
397 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
398 enum ptp_pin_function func, unsigned int chan)
412 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
413 * @adapter: board private structure
414 * @hwtstamps: timestamp structure to update
415 * @systim: unsigned 64bit system time value
417 * We need to convert the system time value stored in the RX/TXSTMP registers
418 * into a hwtstamp which can be used by the upper level timestamping functions.
420 static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
421 struct skb_shared_hwtstamps *hwtstamps,
424 switch (adapter->hw.mac.type) {
426 memset(hwtstamps, 0, sizeof(*hwtstamps));
427 /* Upper 32 bits contain s, lower 32 bits contain ns. */
428 hwtstamps->hwtstamp = ktime_set(systim >> 32,
429 systim & 0xFFFFFFFF);
437 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
438 * @adapter: Pointer to adapter the packet buffer belongs to
439 * @buf: Pointer to packet buffer
441 * This function retrieves the timestamp saved in the beginning of packet
442 * buffer. While two timestamps are available, one in timer0 reference and the
443 * other in timer1 reference, this function considers only the timestamp in
446 * Returns timestamp value.
448 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
454 /* Timestamps are saved in little endian at the beginning of the packet
455 * buffer following the layout:
457 * DWORD: | 0 | 1 | 2 | 3 |
458 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
460 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
461 * part of the timestamp.
463 nsecs = le32_to_cpu(buf[2]);
464 secs = le32_to_cpu(buf[3]);
466 timestamp = ktime_set(secs, nsecs);
468 /* Adjust timestamp for the RX latency based on link speed */
469 switch (adapter->link_speed) {
471 adjust = IGC_I225_RX_LATENCY_10;
474 adjust = IGC_I225_RX_LATENCY_100;
477 adjust = IGC_I225_RX_LATENCY_1000;
480 adjust = IGC_I225_RX_LATENCY_2500;
484 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
488 return ktime_sub_ns(timestamp, adjust);
491 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
493 struct igc_hw *hw = &adapter->hw;
497 wr32(IGC_TSYNCRXCTL, 0);
499 for (i = 0; i < adapter->num_rx_queues; i++) {
500 val = rd32(IGC_SRRCTL(i));
501 val &= ~IGC_SRRCTL_TIMESTAMP;
502 wr32(IGC_SRRCTL(i), val);
505 val = rd32(IGC_RXPBS);
506 val &= ~IGC_RXPBS_CFG_TS_EN;
507 wr32(IGC_RXPBS, val);
510 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
512 struct igc_hw *hw = &adapter->hw;
516 val = rd32(IGC_RXPBS);
517 val |= IGC_RXPBS_CFG_TS_EN;
518 wr32(IGC_RXPBS, val);
520 for (i = 0; i < adapter->num_rx_queues; i++) {
521 val = rd32(IGC_SRRCTL(i));
522 /* FIXME: For now, only support retrieving RX timestamps from
525 val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
526 IGC_SRRCTL_TIMESTAMP;
527 wr32(IGC_SRRCTL(i), val);
530 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
531 IGC_TSYNCRXCTL_RXSYNSIG;
532 wr32(IGC_TSYNCRXCTL, val);
535 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
537 struct igc_hw *hw = &adapter->hw;
539 wr32(IGC_TSYNCTXCTL, 0);
542 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
544 struct igc_hw *hw = &adapter->hw;
546 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
548 /* Read TXSTMP registers to discard any timestamp previously stored. */
554 * igc_ptp_set_timestamp_mode - setup hardware for timestamping
555 * @adapter: networking device structure
556 * @config: hwtstamp configuration
558 * Return: 0 in case of success, negative errno code otherwise.
560 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
561 struct hwtstamp_config *config)
563 /* reserved for future extensions */
567 switch (config->tx_type) {
568 case HWTSTAMP_TX_OFF:
569 igc_ptp_disable_tx_timestamp(adapter);
572 igc_ptp_enable_tx_timestamp(adapter);
578 switch (config->rx_filter) {
579 case HWTSTAMP_FILTER_NONE:
580 igc_ptp_disable_rx_timestamp(adapter);
582 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
584 case HWTSTAMP_FILTER_PTP_V2_EVENT:
585 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
586 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
587 case HWTSTAMP_FILTER_PTP_V2_SYNC:
588 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
589 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
590 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
591 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
592 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
593 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
594 case HWTSTAMP_FILTER_NTP_ALL:
595 case HWTSTAMP_FILTER_ALL:
596 igc_ptp_enable_rx_timestamp(adapter);
597 config->rx_filter = HWTSTAMP_FILTER_ALL;
606 static void igc_ptp_tx_timeout(struct igc_adapter *adapter)
608 struct igc_hw *hw = &adapter->hw;
610 dev_kfree_skb_any(adapter->ptp_tx_skb);
611 adapter->ptp_tx_skb = NULL;
612 adapter->tx_hwtstamp_timeouts++;
613 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
614 /* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */
616 netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
619 void igc_ptp_tx_hang(struct igc_adapter *adapter)
621 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
624 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
627 /* If we haven't received a timestamp within the timeout, it is
628 * reasonable to assume that it will never occur, so we can unlock the
629 * timestamp bit when this occurs.
632 cancel_work_sync(&adapter->ptp_tx_work);
633 igc_ptp_tx_timeout(adapter);
638 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
639 * @adapter: Board private structure
641 * If we were asked to do hardware stamping and such a time stamp is
642 * available, then it must have been for this skb here because we only
643 * allow only one such packet into the queue.
645 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
647 struct sk_buff *skb = adapter->ptp_tx_skb;
648 struct skb_shared_hwtstamps shhwtstamps;
649 struct igc_hw *hw = &adapter->hw;
653 if (WARN_ON_ONCE(!skb))
656 regval = rd32(IGC_TXSTMPL);
657 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
658 igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
660 switch (adapter->link_speed) {
662 adjust = IGC_I225_TX_LATENCY_10;
665 adjust = IGC_I225_TX_LATENCY_100;
668 adjust = IGC_I225_TX_LATENCY_1000;
671 adjust = IGC_I225_TX_LATENCY_2500;
675 shhwtstamps.hwtstamp =
676 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
678 /* Clear the lock early before calling skb_tstamp_tx so that
679 * applications are not woken up before the lock bit is clear. We use
680 * a copy of the skb pointer to ensure other threads can't change it
681 * while we're notifying the stack.
683 adapter->ptp_tx_skb = NULL;
684 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
686 /* Notify the stack and free the skb after we've unlocked */
687 skb_tstamp_tx(skb, &shhwtstamps);
688 dev_kfree_skb_any(skb);
693 * @work: pointer to work struct
695 * This work function polls the TSYNCTXCTL valid bit to determine when a
696 * timestamp has been taken for the current stored skb.
698 static void igc_ptp_tx_work(struct work_struct *work)
700 struct igc_adapter *adapter = container_of(work, struct igc_adapter,
702 struct igc_hw *hw = &adapter->hw;
705 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
708 tsynctxctl = rd32(IGC_TSYNCTXCTL);
709 if (WARN_ON_ONCE(!(tsynctxctl & IGC_TSYNCTXCTL_TXTT_0)))
712 igc_ptp_tx_hwtstamp(adapter);
716 * igc_ptp_set_ts_config - set hardware time stamping config
717 * @netdev: network interface device structure
718 * @ifr: interface request data
721 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
723 struct igc_adapter *adapter = netdev_priv(netdev);
724 struct hwtstamp_config config;
727 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
730 err = igc_ptp_set_timestamp_mode(adapter, &config);
734 /* save these settings for future reference */
735 memcpy(&adapter->tstamp_config, &config,
736 sizeof(adapter->tstamp_config));
738 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
743 * igc_ptp_get_ts_config - get hardware time stamping config
744 * @netdev: network interface device structure
745 * @ifr: interface request data
747 * Get the hwtstamp_config settings to return to the user. Rather than attempt
748 * to deconstruct the settings from the registers, just return a shadow copy
749 * of the last known settings.
751 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
753 struct igc_adapter *adapter = netdev_priv(netdev);
754 struct hwtstamp_config *config = &adapter->tstamp_config;
756 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
760 /* The two conditions below must be met for cross timestamping via
763 * 1. We have an way to convert the timestamps in the PTM messages
764 * to something related to the system clocks (right now, only
765 * X86 systems with support for the Always Running Timer allow that);
767 * 2. We have PTM enabled in the path from the device to the PCIe root port.
769 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
771 return IS_ENABLED(CONFIG_X86_TSC) ? pcie_ptm_enabled(adapter->pdev) : false;
774 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
776 #if IS_ENABLED(CONFIG_X86_TSC)
777 return convert_art_ns_to_tsc(tstamp);
779 return (struct system_counterval_t) { };
783 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
785 struct net_device *netdev = adapter->netdev;
788 case IGC_PTM_STAT_RET_ERR:
789 netdev_err(netdev, "PTM Error: Root port timeout\n");
791 case IGC_PTM_STAT_BAD_PTM_RES:
792 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
794 case IGC_PTM_STAT_T4M1_OVFL:
795 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
797 case IGC_PTM_STAT_ADJUST_1ST:
798 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
800 case IGC_PTM_STAT_ADJUST_CYC:
801 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
804 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
809 static int igc_phc_get_syncdevicetime(ktime_t *device,
810 struct system_counterval_t *system,
813 u32 stat, t2_curr_h, t2_curr_l, ctrl;
814 struct igc_adapter *adapter = ctx;
815 struct igc_hw *hw = &adapter->hw;
816 int err, count = 100;
819 /* Get a snapshot of system clocks to use as historic value. */
820 ktime_get_snapshot(&adapter->snapshot);
823 /* Doing this in a loop because in the event of a
824 * badly timed (ha!) system clock adjustment, we may
825 * get PTM errors from the PCI root, but these errors
826 * are transitory. Repeating the process returns valid
830 /* To "manually" start the PTM cycle we need to clear and
831 * then set again the TRIG bit.
833 ctrl = rd32(IGC_PTM_CTRL);
834 ctrl &= ~IGC_PTM_CTRL_TRIG;
835 wr32(IGC_PTM_CTRL, ctrl);
836 ctrl |= IGC_PTM_CTRL_TRIG;
837 wr32(IGC_PTM_CTRL, ctrl);
839 /* The cycle only starts "for real" when software notifies
840 * that it has read the registers, this is done by setting
843 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
845 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
846 stat, IGC_PTM_STAT_SLEEP,
847 IGC_PTM_STAT_TIMEOUT);
849 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
853 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
856 if (stat & ~IGC_PTM_STAT_VALID) {
857 /* An error occurred, log it. */
858 igc_ptm_log_error(adapter, stat);
859 /* The STAT register is write-1-to-clear (W1C),
860 * so write the previous error status to clear it.
862 wr32(IGC_PTM_STAT, stat);
868 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
872 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
874 t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
875 t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
877 /* FIXME: When the register that tells the endianness of the
878 * PTM registers are implemented, check them here and add the
879 * appropriate conversion.
881 t2_curr_h = swab32(t2_curr_h);
883 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
886 *system = igc_device_tstamp_to_system(t2_curr);
891 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
892 struct system_device_crosststamp *cts)
894 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
897 return get_device_system_crosststamp(igc_phc_get_syncdevicetime,
898 adapter, &adapter->snapshot, cts);
902 * igc_ptp_init - Initialize PTP functionality
903 * @adapter: Board private structure
905 * This function is called at device probe to initialize the PTP
908 void igc_ptp_init(struct igc_adapter *adapter)
910 struct net_device *netdev = adapter->netdev;
911 struct igc_hw *hw = &adapter->hw;
914 switch (hw->mac.type) {
916 for (i = 0; i < IGC_N_SDP; i++) {
917 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
919 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
921 ppd->func = PTP_PF_NONE;
923 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
924 adapter->ptp_caps.owner = THIS_MODULE;
925 adapter->ptp_caps.max_adj = 62499999;
926 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
927 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
928 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
929 adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
930 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
931 adapter->ptp_caps.pps = 1;
932 adapter->ptp_caps.pin_config = adapter->sdp_config;
933 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
934 adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
935 adapter->ptp_caps.n_pins = IGC_N_SDP;
936 adapter->ptp_caps.verify = igc_ptp_verify_pin;
938 if (!igc_is_crosststamp_supported(adapter))
941 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
944 adapter->ptp_clock = NULL;
948 spin_lock_init(&adapter->tmreg_lock);
949 INIT_WORK(&adapter->ptp_tx_work, igc_ptp_tx_work);
951 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
952 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
954 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
955 adapter->ptp_reset_start = ktime_get();
957 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
958 &adapter->pdev->dev);
959 if (IS_ERR(adapter->ptp_clock)) {
960 adapter->ptp_clock = NULL;
961 netdev_err(netdev, "ptp_clock_register failed\n");
962 } else if (adapter->ptp_clock) {
963 netdev_info(netdev, "PHC added\n");
964 adapter->ptp_flags |= IGC_PTP_ENABLED;
968 static void igc_ptp_time_save(struct igc_adapter *adapter)
970 igc_ptp_read(adapter, &adapter->prev_ptp_time);
971 adapter->ptp_reset_start = ktime_get();
974 static void igc_ptp_time_restore(struct igc_adapter *adapter)
976 struct timespec64 ts = adapter->prev_ptp_time;
979 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
981 timespec64_add_ns(&ts, ktime_to_ns(delta));
983 igc_ptp_write_i225(adapter, &ts);
987 * igc_ptp_suspend - Disable PTP work items and prepare for suspend
988 * @adapter: Board private structure
990 * This function stops the overflow check work and PTP Tx timestamp work, and
991 * will prepare the device for OS suspend.
993 void igc_ptp_suspend(struct igc_adapter *adapter)
995 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
998 cancel_work_sync(&adapter->ptp_tx_work);
999 dev_kfree_skb_any(adapter->ptp_tx_skb);
1000 adapter->ptp_tx_skb = NULL;
1001 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
1003 igc_ptp_time_save(adapter);
1007 * igc_ptp_stop - Disable PTP device and stop the overflow check.
1008 * @adapter: Board private structure.
1010 * This function stops the PTP support and cancels the delayed work.
1012 void igc_ptp_stop(struct igc_adapter *adapter)
1014 igc_ptp_suspend(adapter);
1016 if (adapter->ptp_clock) {
1017 ptp_clock_unregister(adapter->ptp_clock);
1018 netdev_info(adapter->netdev, "PHC removed\n");
1019 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1024 * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1025 * @adapter: Board private structure.
1027 * This function handles the reset work required to re-enable the PTP device.
1029 void igc_ptp_reset(struct igc_adapter *adapter)
1031 struct igc_hw *hw = &adapter->hw;
1032 u32 cycle_ctrl, ctrl;
1033 unsigned long flags;
1036 /* reset the tstamp_config */
1037 igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1039 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1041 switch (adapter->hw.mac.type) {
1043 timadj = rd32(IGC_TIMADJ);
1044 timadj |= IGC_TIMADJ_ADJUST_METH;
1045 wr32(IGC_TIMADJ, timadj);
1047 wr32(IGC_TSAUXC, 0x0);
1048 wr32(IGC_TSSDP, 0x0);
1050 IGC_TSICR_INTERRUPTS |
1051 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1052 wr32(IGC_IMS, IGC_IMS_TS);
1054 if (!igc_is_crosststamp_supported(adapter))
1057 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1058 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1060 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1062 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1064 ctrl = IGC_PTM_CTRL_EN |
1065 IGC_PTM_CTRL_START_NOW |
1066 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1067 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |
1070 wr32(IGC_PTM_CTRL, ctrl);
1072 /* Force the first cycle to run. */
1073 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
1077 /* No work to do. */
1081 /* Re-initialize the timer. */
1082 if (hw->mac.type == igc_i225) {
1083 igc_ptp_time_restore(adapter);
1085 timecounter_init(&adapter->tc, &adapter->cc,
1086 ktime_to_ns(ktime_get_real()));
1089 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);