1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/kobject.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/bitfield.h>
17 #include <linux/hrtimer.h>
21 void igc_ethtool_set_ops(struct net_device *);
23 /* Transmit and receive queues */
24 #define IGC_MAX_RX_QUEUES 4
25 #define IGC_MAX_TX_QUEUES 4
27 #define MAX_Q_VECTORS 8
28 #define MAX_STD_JUMBO_FRAME_SIZE 9216
30 #define MAX_ETYPE_FILTER 8
31 #define IGC_RETA_SIZE 128
35 #define IGC_N_PEROUT 2
38 #define MAX_FLEX_FILTER 32
40 enum igc_mac_filter_type {
41 IGC_MAC_FILTER_TYPE_DST = 0,
42 IGC_MAC_FILTER_TYPE_SRC
45 struct igc_tx_queue_stats {
52 struct igc_rx_queue_stats {
60 struct igc_rx_packet_stats {
61 u64 ipv4_packets; /* IPv4 headers processed */
62 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
63 u64 ipv6_packets; /* IPv6 headers processed */
64 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
65 u64 tcp_packets; /* TCP headers processed */
66 u64 udp_packets; /* UDP headers processed */
67 u64 sctp_packets; /* SCTP headers processed */
68 u64 nfs_packets; /* NFS headers processe */
72 struct igc_ring_container {
73 struct igc_ring *ring; /* pointer to linked list of rings */
74 unsigned int total_bytes; /* total bytes processed this int */
75 unsigned int total_packets; /* total packets processed this int */
76 u16 work_limit; /* total work allowed per interrupt */
77 u8 count; /* total number of rings in vector */
78 u8 itr; /* current ITR setting for ring */
82 struct igc_q_vector *q_vector; /* backlink to q_vector */
83 struct net_device *netdev; /* back pointer to net_device */
84 struct device *dev; /* device for dma mapping */
85 union { /* array of buffer info structs */
86 struct igc_tx_buffer *tx_buffer_info;
87 struct igc_rx_buffer *rx_buffer_info;
89 void *desc; /* descriptor ring memory */
90 unsigned long flags; /* ring specific flags */
91 void __iomem *tail; /* pointer to ring tail register */
92 dma_addr_t dma; /* phys address of the ring */
93 unsigned int size; /* length of desc. ring in bytes */
95 u16 count; /* number of desc. in the ring */
96 u8 queue_index; /* logical index of the ring*/
97 u8 reg_idx; /* physical index of the ring */
98 bool launchtime_enable; /* true if LaunchTime is enabled */
99 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
100 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
105 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */
106 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */
109 bool cbs_enable; /* indicates if CBS is enabled */
110 s32 idleslope; /* idleSlope in kbps */
111 s32 sendslope; /* sendSlope in kbps */
112 s32 hicredit; /* hiCredit in bytes */
113 s32 locredit; /* loCredit in bytes */
115 /* everything past this point are written often */
123 struct igc_tx_queue_stats tx_stats;
124 struct u64_stats_sync tx_syncp;
125 struct u64_stats_sync tx_syncp2;
129 struct igc_rx_queue_stats rx_stats;
130 struct igc_rx_packet_stats pkt_stats;
131 struct u64_stats_sync rx_syncp;
136 struct xdp_rxq_info xdp_rxq;
137 struct xsk_buff_pool *xsk_pool;
138 } ____cacheline_internodealigned_in_smp;
140 /* Board specific private data structure */
142 struct net_device *netdev;
144 struct ethtool_eee eee;
149 unsigned int num_q_vectors;
151 struct msix_entry *msix_entries;
155 u32 tx_timeout_count;
157 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
161 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
163 struct timer_list watchdog_timer;
164 struct timer_list dma_err_timer;
165 struct timer_list phy_info_timer;
166 struct hrtimer hrtimer;
176 /* Interrupt Throttle Rate */
180 struct work_struct reset_task;
181 struct work_struct watchdog_task;
182 struct work_struct dma_err_task;
185 u8 tx_timeout_factor;
194 bool taprio_offload_enable;
195 u32 qbv_config_change_errors;
197 unsigned int qbv_count;
199 /* OS defined structs */
200 struct pci_dev *pdev;
201 /* lock for statistics */
202 spinlock_t stats64_lock;
203 struct rtnl_link_stats64 stats64;
205 /* structs defined in igc_hw.h */
207 struct igc_hw_stats stats;
209 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
210 u32 eims_enable_mask;
216 u32 tx_hwtstamp_timeouts;
217 u32 tx_hwtstamp_skipped;
218 u32 rx_hwtstamp_cleared;
221 u32 rss_indir_tbl_init;
223 /* Any access to elements in nfc_rule_list is protected by the
226 struct mutex nfc_rule_lock;
227 struct list_head nfc_rule_list;
228 unsigned int nfc_rule_count;
230 u8 rss_indir_tbl[IGC_RETA_SIZE];
232 unsigned long link_check_timeout;
237 struct ptp_clock *ptp_clock;
238 struct ptp_clock_info ptp_caps;
239 /* Access to ptp_tx_skb and ptp_tx_start are protected by the
242 spinlock_t ptp_tx_lock;
243 struct sk_buff *ptp_tx_skb;
244 struct hwtstamp_config tstamp_config;
245 unsigned long ptp_tx_start;
246 unsigned int ptp_flags;
247 /* System time value lock */
248 spinlock_t tmreg_lock;
249 struct cyclecounter cc;
250 struct timecounter tc;
251 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
252 ktime_t ptp_reset_start; /* Reset time in clock mono */
253 struct system_time_snapshot snapshot;
257 struct bpf_prog *xdp_prog;
259 bool pps_sys_wrap_on;
261 struct ptp_pin_desc sdp_config[IGC_N_SDP];
263 struct timespec64 start;
264 struct timespec64 period;
265 } perout[IGC_N_PEROUT];
268 void igc_up(struct igc_adapter *adapter);
269 void igc_down(struct igc_adapter *adapter);
270 int igc_open(struct net_device *netdev);
271 int igc_close(struct net_device *netdev);
272 int igc_setup_tx_resources(struct igc_ring *ring);
273 int igc_setup_rx_resources(struct igc_ring *ring);
274 void igc_free_tx_resources(struct igc_ring *ring);
275 void igc_free_rx_resources(struct igc_ring *ring);
276 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
277 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
278 const u32 max_rss_queues);
279 int igc_reinit_queues(struct igc_adapter *adapter);
280 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
281 bool igc_has_link(struct igc_adapter *adapter);
282 void igc_reset(struct igc_adapter *adapter);
283 void igc_update_stats(struct igc_adapter *adapter);
284 void igc_disable_rx_ring(struct igc_ring *ring);
285 void igc_enable_rx_ring(struct igc_ring *ring);
286 void igc_disable_tx_ring(struct igc_ring *ring);
287 void igc_enable_tx_ring(struct igc_ring *ring);
288 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
290 /* igc_dump declarations */
291 void igc_rings_dump(struct igc_adapter *adapter);
292 void igc_regs_dump(struct igc_adapter *adapter);
294 extern char igc_driver_name[];
296 #define IGC_REGS_LEN 740
298 /* flags controlling PTP/1588 function */
299 #define IGC_PTP_ENABLED BIT(0)
301 /* Flags definitions */
302 #define IGC_FLAG_HAS_MSI BIT(0)
303 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
304 #define IGC_FLAG_DMAC BIT(4)
305 #define IGC_FLAG_PTP BIT(8)
306 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
307 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
308 #define IGC_FLAG_HAS_MSIX BIT(13)
309 #define IGC_FLAG_EEE BIT(14)
310 #define IGC_FLAG_VLAN_PROMISC BIT(15)
311 #define IGC_FLAG_RX_LEGACY BIT(16)
312 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
313 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
315 #define IGC_FLAG_TSN_ANY_ENABLED \
316 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
318 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
319 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
321 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
322 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
323 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
325 /* RX-desc Write-Back format RSS Type's */
326 enum igc_rss_type_num {
327 IGC_RSS_TYPE_NO_HASH = 0,
328 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,
329 IGC_RSS_TYPE_HASH_IPV4 = 2,
330 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,
331 IGC_RSS_TYPE_HASH_IPV6_EX = 4,
332 IGC_RSS_TYPE_HASH_IPV6 = 5,
333 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,
334 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,
335 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,
336 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,
337 IGC_RSS_TYPE_MAX = 10,
339 #define IGC_RSS_TYPE_MAX_TABLE 16
340 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
342 /* igc_rss_type - Rx descriptor RSS type field */
343 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
345 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
346 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
347 * is slightly slower than via u32 (wb.lower.lo_dword.data)
349 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
352 /* Interrupt defines */
353 #define IGC_START_ITR 648 /* ~6000 ints/sec */
354 #define IGC_4K_ITR 980
355 #define IGC_20K_ITR 196
356 #define IGC_70K_ITR 56
358 #define IGC_DEFAULT_ITR 3 /* dynamic */
359 #define IGC_MAX_ITR_USECS 10000
360 #define IGC_MIN_ITR_USECS 10
361 #define NON_Q_VECTORS 1
362 #define MAX_MSIX_ENTRIES 10
364 /* TX/RX descriptor defines */
365 #define IGC_DEFAULT_TXD 256
366 #define IGC_DEFAULT_TX_WORK 128
367 #define IGC_MIN_TXD 80
368 #define IGC_MAX_TXD 4096
370 #define IGC_DEFAULT_RXD 256
371 #define IGC_MIN_RXD 80
372 #define IGC_MAX_RXD 4096
374 /* Supported Rx Buffer Sizes */
375 #define IGC_RXBUFFER_256 256
376 #define IGC_RXBUFFER_2048 2048
377 #define IGC_RXBUFFER_3072 3072
379 #define AUTO_ALL_MODES 0
380 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
382 /* Transmit and receive latency (for PTP timestamps) */
383 #define IGC_I225_TX_LATENCY_10 240
384 #define IGC_I225_TX_LATENCY_100 58
385 #define IGC_I225_TX_LATENCY_1000 80
386 #define IGC_I225_TX_LATENCY_2500 1325
387 #define IGC_I225_RX_LATENCY_10 6450
388 #define IGC_I225_RX_LATENCY_100 185
389 #define IGC_I225_RX_LATENCY_1000 300
390 #define IGC_I225_RX_LATENCY_2500 1485
392 /* RX and TX descriptor control thresholds.
393 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
394 * descriptors available in its onboard memory.
395 * Setting this to 0 disables RX descriptor prefetch.
396 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
397 * available in host memory.
398 * If PTHRESH is 0, this should also be 0.
399 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
400 * descriptors until either it has this many to write back, or the
403 #define IGC_RX_PTHRESH 8
404 #define IGC_RX_HTHRESH 8
405 #define IGC_TX_PTHRESH 8
406 #define IGC_TX_HTHRESH 1
407 #define IGC_RX_WTHRESH 4
408 #define IGC_TX_WTHRESH 16
410 #define IGC_RX_DMA_ATTR \
411 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
413 #define IGC_TS_HDR_LEN 16
415 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
417 #if (PAGE_SIZE < 8192)
418 #define IGC_MAX_FRAME_BUILD_SKB \
419 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
421 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
424 /* How many Rx Buffers do we bundle into one write to the hardware ? */
425 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
428 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
429 #define IGC_TX_FLAGS_VLAN_SHIFT 16
431 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
432 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
433 const u32 stat_err_bits)
435 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
446 IGC_TX_FLAGS_VLAN = 0x01,
447 IGC_TX_FLAGS_TSO = 0x02,
448 IGC_TX_FLAGS_TSTAMP = 0x04,
451 IGC_TX_FLAGS_IPV4 = 0x10,
452 IGC_TX_FLAGS_CSUM = 0x20,
459 /* The largest size we can write to the descriptor is 65535. In order to
460 * maintain a power of two alignment we have to limit ourselves to 32K.
462 #define IGC_MAX_TXD_PWR 15
463 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
465 /* Tx Descriptors needed, worst case */
466 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
467 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
469 enum igc_tx_buffer_type {
470 IGC_TX_BUFFER_TYPE_SKB,
471 IGC_TX_BUFFER_TYPE_XDP,
472 IGC_TX_BUFFER_TYPE_XSK,
475 /* wrapper around a pointer to a socket buffer,
476 * so a DMA handle can be stored along with the buffer
478 struct igc_tx_buffer {
479 union igc_adv_tx_desc *next_to_watch;
480 unsigned long time_stamp;
481 enum igc_tx_buffer_type type;
484 struct xdp_frame *xdpf;
486 unsigned int bytecount;
490 DEFINE_DMA_UNMAP_ADDR(dma);
491 DEFINE_DMA_UNMAP_LEN(len);
495 struct igc_rx_buffer {
500 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
507 struct xdp_buff *xdp;
511 /* context wrapper around xdp_buff to provide access to descriptor metadata */
512 struct igc_xdp_buff {
514 union igc_adv_rx_desc *rx_desc;
515 ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */
518 struct igc_q_vector {
519 struct igc_adapter *adapter; /* backlink */
520 void __iomem *itr_register;
521 u32 eims_value; /* EIMS mask value */
526 struct igc_ring_container rx, tx;
528 struct napi_struct napi;
530 struct rcu_head rcu; /* to avoid race with update stats on free */
531 char name[IFNAMSIZ + 9];
532 struct net_device poll_dev;
534 /* for dynamic allocation of rings associated with this q_vector */
535 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
538 enum igc_filter_match_flags {
539 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
540 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
541 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
542 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
543 IGC_FILTER_FLAG_USER_DATA = BIT(4),
544 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
547 struct igc_nfc_filter {
552 u8 src_addr[ETH_ALEN];
553 u8 dst_addr[ETH_ALEN];
563 struct igc_nfc_rule {
564 struct list_head list;
565 struct igc_nfc_filter filter;
571 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
572 * based, 8 ethertype based and 32 Flex filter based rules.
574 #define IGC_MAX_RXNFC_RULES 64
576 struct igc_flex_filter {
587 /* igc_desc_unused - calculate if we have unused descriptors */
588 static inline u16 igc_desc_unused(const struct igc_ring *ring)
590 u16 ntc = ring->next_to_clean;
591 u16 ntu = ring->next_to_use;
593 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
596 static inline s32 igc_get_phy_info(struct igc_hw *hw)
598 if (hw->phy.ops.get_phy_info)
599 return hw->phy.ops.get_phy_info(hw);
604 static inline s32 igc_reset_phy(struct igc_hw *hw)
606 if (hw->phy.ops.reset)
607 return hw->phy.ops.reset(hw);
612 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
614 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
617 enum igc_ring_flags_t {
618 IGC_RING_FLAG_RX_3K_BUFFER,
619 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
620 IGC_RING_FLAG_RX_SCTP_CSUM,
621 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
622 IGC_RING_FLAG_TX_CTX_IDX,
623 IGC_RING_FLAG_TX_DETECT_HANG,
624 IGC_RING_FLAG_AF_XDP_ZC,
625 IGC_RING_FLAG_TX_HWTSTAMP,
628 #define ring_uses_large_buffer(ring) \
629 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
630 #define set_ring_uses_large_buffer(ring) \
631 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
632 #define clear_ring_uses_large_buffer(ring) \
633 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
635 #define ring_uses_build_skb(ring) \
636 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
638 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
640 #if (PAGE_SIZE < 8192)
641 if (ring_uses_large_buffer(ring))
642 return IGC_RXBUFFER_3072;
644 if (ring_uses_build_skb(ring))
645 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
647 return IGC_RXBUFFER_2048;
650 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
652 #if (PAGE_SIZE < 8192)
653 if (ring_uses_large_buffer(ring))
659 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
661 if (hw->phy.ops.read_reg)
662 return hw->phy.ops.read_reg(hw, offset, data);
667 void igc_reinit_locked(struct igc_adapter *);
668 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
670 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
671 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
673 void igc_ptp_init(struct igc_adapter *adapter);
674 void igc_ptp_reset(struct igc_adapter *adapter);
675 void igc_ptp_suspend(struct igc_adapter *adapter);
676 void igc_ptp_stop(struct igc_adapter *adapter);
677 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
678 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
679 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
680 void igc_ptp_tx_hang(struct igc_adapter *adapter);
681 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
682 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);
684 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
686 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
688 #define IGC_RX_DESC(R, i) \
689 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
690 #define IGC_TX_DESC(R, i) \
691 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
692 #define IGC_TX_CTXTDESC(R, i) \
693 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))