drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * The full GNU General Public License is included in this distribution in
  16  * the file called "COPYING".
  17  *
  18  * Contact Information:
  19  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  20  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  21  *
  22  ******************************************************************************/
  23
  24 #include <linux/prefetch.h>
  25
  26 #include "i40evf.h"
  27 #include "i40e_prototype.h"
  28
  29 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  30                                 u32 td_tag)
  31 {
  32         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  33                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  34                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  35                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  36                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  37 }
  38
  39 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  40
  41 /**
  42  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  43  * @ring:      the ring that owns the buffer
  44  * @tx_buffer: the buffer to free
  45  **/
  46 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  47                                             struct i40e_tx_buffer *tx_buffer)
  48 {
  49         if (tx_buffer->skb) {
  50                 dev_kfree_skb_any(tx_buffer->skb);
  51                 if (dma_unmap_len(tx_buffer, len))
  52                         dma_unmap_single(ring->dev,
  53                                          dma_unmap_addr(tx_buffer, dma),
  54                                          dma_unmap_len(tx_buffer, len),
  55                                          DMA_TO_DEVICE);
  56         } else if (dma_unmap_len(tx_buffer, len)) {
  57                 dma_unmap_page(ring->dev,
  58                                dma_unmap_addr(tx_buffer, dma),
  59                                dma_unmap_len(tx_buffer, len),
  60                                DMA_TO_DEVICE);
  61         }
  62         tx_buffer->next_to_watch = NULL;
  63         tx_buffer->skb = NULL;
  64         dma_unmap_len_set(tx_buffer, len, 0);
  65         /* tx_buffer must be completely set up in the transmit path */
  66 }
  67
  68 /**
  69  * i40evf_clean_tx_ring - Free any empty Tx buffers
  70  * @tx_ring: ring to be cleaned
  71  **/
  72 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  73 {
  74         unsigned long bi_size;
  75         u16 i;
  76
  77         /* ring already cleared, nothing to do */
  78         if (!tx_ring->tx_bi)
  79                 return;
  80
  81         /* Free all the Tx ring sk_buffs */
  82         for (i = 0; i < tx_ring->count; i++)
  83                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  84
  85         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  86         memset(tx_ring->tx_bi, 0, bi_size);
  87
  88         /* Zero out the descriptor ring */
  89         memset(tx_ring->desc, 0, tx_ring->size);
  90
  91         tx_ring->next_to_use = 0;
  92         tx_ring->next_to_clean = 0;
  93
  94         if (!tx_ring->netdev)
  95                 return;
  96
  97         /* cleanup Tx queue statistics */
  98         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
  99                                                   tx_ring->queue_index));
 100 }
 101
 102 /**
 103  * i40evf_free_tx_resources - Free Tx resources per queue
 104  * @tx_ring: Tx descriptor ring for a specific queue
 105  *
 106  * Free all transmit software resources
 107  **/
 108 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 109 {
 110         i40evf_clean_tx_ring(tx_ring);
 111         kfree(tx_ring->tx_bi);
 112         tx_ring->tx_bi = NULL;
 113
 114         if (tx_ring->desc) {
 115                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 116                                   tx_ring->desc, tx_ring->dma);
 117                 tx_ring->desc = NULL;
 118         }
 119 }
 120
 121 /**
 122  * i40e_get_tx_pending - how many tx descriptors not processed
 123  * @tx_ring: the ring of descriptors
 124  *
 125  * Since there is no access to the ring head register
 126  * in XL710, we need to use our local copies
 127  **/
 128 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
 129 {
 130         u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
 131                         ? ring->next_to_use
 132                         : ring->next_to_use + ring->count);
 133         return ntu - ring->next_to_clean;
 134 }
 135
 136 /**
 137  * i40e_check_tx_hang - Is there a hang in the Tx queue
 138  * @tx_ring: the ring of descriptors
 139  **/
 140 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
 141 {
 142         u32 tx_pending = i40e_get_tx_pending(tx_ring);
 143         bool ret = false;
 144
 145         clear_check_for_tx_hang(tx_ring);
 146
 147         /* Check for a hung queue, but be thorough. This verifies
 148          * that a transmit has been completed since the previous
 149          * check AND there is at least one packet pending. The
 150          * ARMED bit is set to indicate a potential hang. The
 151          * bit is cleared if a pause frame is received to remove
 152          * false hang detection due to PFC or 802.3x frames. By
 153          * requiring this to fail twice we avoid races with
 154          * PFC clearing the ARMED bit and conditions where we
 155          * run the check_tx_hang logic with a transmit completion
 156          * pending but without time to complete it yet.
 157          */
 158         if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
 159             tx_pending) {
 160                 /* make sure it is true for two checks in a row */
 161                 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
 162                                        &tx_ring->state);
 163         } else {
 164                 /* update completed stats and disarm the hang check */
 165                 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
 166                 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
 167         }
 168
 169         return ret;
 170 }
 171
 172 /**
 173  * i40e_get_head - Retrieve head from head writeback
 174  * @tx_ring:  tx ring to fetch head of
 175  *
 176  * Returns value of Tx ring head based on value stored
 177  * in head write-back location
 178  **/
 179 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 180 {
 181         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 182
 183         return le32_to_cpu(*(volatile __le32 *)head);
 184 }
 185
 186 /**
 187  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 188  * @tx_ring:  tx ring to clean
 189  * @budget:   how many cleans we're allowed
 190  *
 191  * Returns true if there's any budget left (e.g. the clean is finished)
 192  **/
 193 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 194 {
 195         u16 i = tx_ring->next_to_clean;
 196         struct i40e_tx_buffer *tx_buf;
 197         struct i40e_tx_desc *tx_head;
 198         struct i40e_tx_desc *tx_desc;
 199         unsigned int total_packets = 0;
 200         unsigned int total_bytes = 0;
 201
 202         tx_buf = &tx_ring->tx_bi[i];
 203         tx_desc = I40E_TX_DESC(tx_ring, i);
 204         i -= tx_ring->count;
 205
 206         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 207
 208         do {
 209                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 210
 211                 /* if next_to_watch is not set then there is no work pending */
 212                 if (!eop_desc)
 213                         break;
 214
 215                 /* prevent any other reads prior to eop_desc */
 216                 read_barrier_depends();
 217
 218                 /* we have caught up to head, no work left to do */
 219                 if (tx_head == tx_desc)
 220                         break;
 221
 222                 /* clear next_to_watch to prevent false hangs */
 223                 tx_buf->next_to_watch = NULL;
 224
 225                 /* update the statistics for this packet */
 226                 total_bytes += tx_buf->bytecount;
 227                 total_packets += tx_buf->gso_segs;
 228
 229                 /* free the skb */
 230                 dev_kfree_skb_any(tx_buf->skb);
 231
 232                 /* unmap skb header data */
 233                 dma_unmap_single(tx_ring->dev,
 234                                  dma_unmap_addr(tx_buf, dma),
 235                                  dma_unmap_len(tx_buf, len),
 236                                  DMA_TO_DEVICE);
 237
 238                 /* clear tx_buffer data */
 239                 tx_buf->skb = NULL;
 240                 dma_unmap_len_set(tx_buf, len, 0);
 241
 242                 /* unmap remaining buffers */
 243                 while (tx_desc != eop_desc) {
 244
 245                         tx_buf++;
 246                         tx_desc++;
 247                         i++;
 248                         if (unlikely(!i)) {
 249                                 i -= tx_ring->count;
 250                                 tx_buf = tx_ring->tx_bi;
 251                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 252                         }
 253
 254                         /* unmap any remaining paged data */
 255                         if (dma_unmap_len(tx_buf, len)) {
 256                                 dma_unmap_page(tx_ring->dev,
 257                                                dma_unmap_addr(tx_buf, dma),
 258                                                dma_unmap_len(tx_buf, len),
 259                                                DMA_TO_DEVICE);
 260                                 dma_unmap_len_set(tx_buf, len, 0);
 261                         }
 262                 }
 263
 264                 /* move us one more past the eop_desc for start of next pkt */
 265                 tx_buf++;
 266                 tx_desc++;
 267                 i++;
 268                 if (unlikely(!i)) {
 269                         i -= tx_ring->count;
 270                         tx_buf = tx_ring->tx_bi;
 271                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 272                 }
 273
 274                 /* update budget accounting */
 275                 budget--;
 276         } while (likely(budget));
 277
 278         i += tx_ring->count;
 279         tx_ring->next_to_clean = i;
 280         u64_stats_update_begin(&tx_ring->syncp);
 281         tx_ring->stats.bytes += total_bytes;
 282         tx_ring->stats.packets += total_packets;
 283         u64_stats_update_end(&tx_ring->syncp);
 284         tx_ring->q_vector->tx.total_bytes += total_bytes;
 285         tx_ring->q_vector->tx.total_packets += total_packets;
 286
 287         if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
 288                 /* schedule immediate reset if we believe we hung */
 289                 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
 290                          "  VSI                  <%d>\n"
 291                          "  Tx Queue             <%d>\n"
 292                          "  next_to_use          <%x>\n"
 293                          "  next_to_clean        <%x>\n",
 294                          tx_ring->vsi->seid,
 295                          tx_ring->queue_index,
 296                          tx_ring->next_to_use, i);
 297                 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
 298                          "  time_stamp           <%lx>\n"
 299                          "  jiffies              <%lx>\n",
 300                          tx_ring->tx_bi[i].time_stamp, jiffies);
 301
 302                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 303
 304                 dev_info(tx_ring->dev,
 305                          "tx hang detected on queue %d, resetting adapter\n",
 306                          tx_ring->queue_index);
 307
 308                 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
 309
 310                 /* the adapter is about to reset, no point in enabling stuff */
 311                 return true;
 312         }
 313
 314         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 315                                                       tx_ring->queue_index),
 316                                   total_packets, total_bytes);
 317
 318 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 319         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 320                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 321                 /* Make sure that anybody stopping the queue after this
 322                  * sees the new next_to_clean.
 323                  */
 324                 smp_mb();
 325                 if (__netif_subqueue_stopped(tx_ring->netdev,
 326                                              tx_ring->queue_index) &&
 327                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 328                         netif_wake_subqueue(tx_ring->netdev,
 329                                             tx_ring->queue_index);
 330                         ++tx_ring->tx_stats.restart_queue;
 331                 }
 332         }
 333
 334         return budget > 0;
 335 }
 336
 337 /**
 338  * i40e_set_new_dynamic_itr - Find new ITR level
 339  * @rc: structure containing ring performance data
 340  *
 341  * Stores a new ITR value based on packets and byte counts during
 342  * the last interrupt.  The advantage of per interrupt computation
 343  * is faster updates and more accurate ITR for the current traffic
 344  * pattern.  Constants in this function were computed based on
 345  * theoretical maximum wire speed and thresholds were set based on
 346  * testing data as well as attempting to minimize response time
 347  * while increasing bulk throughput.
 348  **/
 349 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 350 {
 351         enum i40e_latency_range new_latency_range = rc->latency_range;
 352         u32 new_itr = rc->itr;
 353         int bytes_per_int;
 354
 355         if (rc->total_packets == 0 || !rc->itr)
 356                 return;
 357
 358         /* simple throttlerate management
 359          *   0-10MB/s   lowest (100000 ints/s)
 360          *  10-20MB/s   low    (20000 ints/s)
 361          *  20-1249MB/s bulk   (8000 ints/s)
 362          */
 363         bytes_per_int = rc->total_bytes / rc->itr;
 364         switch (rc->itr) {
 365         case I40E_LOWEST_LATENCY:
 366                 if (bytes_per_int > 10)
 367                         new_latency_range = I40E_LOW_LATENCY;
 368                 break;
 369         case I40E_LOW_LATENCY:
 370                 if (bytes_per_int > 20)
 371                         new_latency_range = I40E_BULK_LATENCY;
 372                 else if (bytes_per_int <= 10)
 373                         new_latency_range = I40E_LOWEST_LATENCY;
 374                 break;
 375         case I40E_BULK_LATENCY:
 376                 if (bytes_per_int <= 20)
 377                         rc->latency_range = I40E_LOW_LATENCY;
 378                 break;
 379         }
 380
 381         switch (new_latency_range) {
 382         case I40E_LOWEST_LATENCY:
 383                 new_itr = I40E_ITR_100K;
 384                 break;
 385         case I40E_LOW_LATENCY:
 386                 new_itr = I40E_ITR_20K;
 387                 break;
 388         case I40E_BULK_LATENCY:
 389                 new_itr = I40E_ITR_8K;
 390                 break;
 391         default:
 392                 break;
 393         }
 394
 395         if (new_itr != rc->itr) {
 396                 /* do an exponential smoothing */
 397                 new_itr = (10 * new_itr * rc->itr) /
 398                           ((9 * new_itr) + rc->itr);
 399                 rc->itr = new_itr & I40E_MAX_ITR;
 400         }
 401
 402         rc->total_bytes = 0;
 403         rc->total_packets = 0;
 404 }
 405
 406 /**
 407  * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
 408  * @q_vector: the vector to adjust
 409  **/
 410 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
 411 {
 412         u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
 413         struct i40e_hw *hw = &q_vector->vsi->back->hw;
 414         u32 reg_addr;
 415         u16 old_itr;
 416
 417         reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
 418         old_itr = q_vector->rx.itr;
 419         i40e_set_new_dynamic_itr(&q_vector->rx);
 420         if (old_itr != q_vector->rx.itr)
 421                 wr32(hw, reg_addr, q_vector->rx.itr);
 422
 423         reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
 424         old_itr = q_vector->tx.itr;
 425         i40e_set_new_dynamic_itr(&q_vector->tx);
 426         if (old_itr != q_vector->tx.itr)
 427                 wr32(hw, reg_addr, q_vector->tx.itr);
 428 }
 429
 430 /**
 431  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 432  * @tx_ring: the tx ring to set up
 433  *
 434  * Return 0 on success, negative on error
 435  **/
 436 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 437 {
 438         struct device *dev = tx_ring->dev;
 439         int bi_size;
 440
 441         if (!dev)
 442                 return -ENOMEM;
 443
 444         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 445         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 446         if (!tx_ring->tx_bi)
 447                 goto err;
 448
 449         /* round up to nearest 4K */
 450         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 451         /* add u32 for head writeback, align after this takes care of
 452          * guaranteeing this is at least one cache line in size
 453          */
 454         tx_ring->size += sizeof(u32);
 455         tx_ring->size = ALIGN(tx_ring->size, 4096);
 456         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 457                                            &tx_ring->dma, GFP_KERNEL);
 458         if (!tx_ring->desc) {
 459                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 460                          tx_ring->size);
 461                 goto err;
 462         }
 463
 464         tx_ring->next_to_use = 0;
 465         tx_ring->next_to_clean = 0;
 466         return 0;
 467
 468 err:
 469         kfree(tx_ring->tx_bi);
 470         tx_ring->tx_bi = NULL;
 471         return -ENOMEM;
 472 }
 473
 474 /**
 475  * i40evf_clean_rx_ring - Free Rx buffers
 476  * @rx_ring: ring to be cleaned
 477  **/
 478 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 479 {
 480         struct device *dev = rx_ring->dev;
 481         struct i40e_rx_buffer *rx_bi;
 482         unsigned long bi_size;
 483         u16 i;
 484
 485         /* ring already cleared, nothing to do */
 486         if (!rx_ring->rx_bi)
 487                 return;
 488
 489         /* Free all the Rx ring sk_buffs */
 490         for (i = 0; i < rx_ring->count; i++) {
 491                 rx_bi = &rx_ring->rx_bi[i];
 492                 if (rx_bi->dma) {
 493                         dma_unmap_single(dev,
 494                                          rx_bi->dma,
 495                                          rx_ring->rx_buf_len,
 496                                          DMA_FROM_DEVICE);
 497                         rx_bi->dma = 0;
 498                 }
 499                 if (rx_bi->skb) {
 500                         dev_kfree_skb(rx_bi->skb);
 501                         rx_bi->skb = NULL;
 502                 }
 503                 if (rx_bi->page) {
 504                         if (rx_bi->page_dma) {
 505                                 dma_unmap_page(dev,
 506                                                rx_bi->page_dma,
 507                                                PAGE_SIZE / 2,
 508                                                DMA_FROM_DEVICE);
 509                                 rx_bi->page_dma = 0;
 510                         }
 511                         __free_page(rx_bi->page);
 512                         rx_bi->page = NULL;
 513                         rx_bi->page_offset = 0;
 514                 }
 515         }
 516
 517         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 518         memset(rx_ring->rx_bi, 0, bi_size);
 519
 520         /* Zero out the descriptor ring */
 521         memset(rx_ring->desc, 0, rx_ring->size);
 522
 523         rx_ring->next_to_clean = 0;
 524         rx_ring->next_to_use = 0;
 525 }
 526
 527 /**
 528  * i40evf_free_rx_resources - Free Rx resources
 529  * @rx_ring: ring to clean the resources from
 530  *
 531  * Free all receive software resources
 532  **/
 533 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 534 {
 535         i40evf_clean_rx_ring(rx_ring);
 536         kfree(rx_ring->rx_bi);
 537         rx_ring->rx_bi = NULL;
 538
 539         if (rx_ring->desc) {
 540                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 541                                   rx_ring->desc, rx_ring->dma);
 542                 rx_ring->desc = NULL;
 543         }
 544 }
 545
 546 /**
 547  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 548  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 549  *
 550  * Returns 0 on success, negative on failure
 551  **/
 552 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 553 {
 554         struct device *dev = rx_ring->dev;
 555         int bi_size;
 556
 557         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 558         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 559         if (!rx_ring->rx_bi)
 560                 goto err;
 561
 562         /* Round up to nearest 4K */
 563         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 564                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 565                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 566         rx_ring->size = ALIGN(rx_ring->size, 4096);
 567         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 568                                            &rx_ring->dma, GFP_KERNEL);
 569
 570         if (!rx_ring->desc) {
 571                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 572                          rx_ring->size);
 573                 goto err;
 574         }
 575
 576         rx_ring->next_to_clean = 0;
 577         rx_ring->next_to_use = 0;
 578
 579         return 0;
 580 err:
 581         kfree(rx_ring->rx_bi);
 582         rx_ring->rx_bi = NULL;
 583         return -ENOMEM;
 584 }
 585
 586 /**
 587  * i40e_release_rx_desc - Store the new tail and head values
 588  * @rx_ring: ring to bump
 589  * @val: new head index
 590  **/
 591 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 592 {
 593         rx_ring->next_to_use = val;
 594         /* Force memory writes to complete before letting h/w
 595          * know there are new descriptors to fetch.  (Only
 596          * applicable for weak-ordered memory model archs,
 597          * such as IA-64).
 598          */
 599         wmb();
 600         writel(val, rx_ring->tail);
 601 }
 602
 603 /**
 604  * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
 605  * @rx_ring: ring to place buffers on
 606  * @cleaned_count: number of buffers to replace
 607  **/
 608 void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
 609 {
 610         u16 i = rx_ring->next_to_use;
 611         union i40e_rx_desc *rx_desc;
 612         struct i40e_rx_buffer *bi;
 613         struct sk_buff *skb;
 614
 615         /* do nothing if no valid netdev defined */
 616         if (!rx_ring->netdev || !cleaned_count)
 617                 return;
 618
 619         while (cleaned_count--) {
 620                 rx_desc = I40E_RX_DESC(rx_ring, i);
 621                 bi = &rx_ring->rx_bi[i];
 622                 skb = bi->skb;
 623
 624                 if (!skb) {
 625                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 626                                                         rx_ring->rx_buf_len);
 627                         if (!skb) {
 628                                 rx_ring->rx_stats.alloc_buff_failed++;
 629                                 goto no_buffers;
 630                         }
 631                         /* initialize queue mapping */
 632                         skb_record_rx_queue(skb, rx_ring->queue_index);
 633                         bi->skb = skb;
 634                 }
 635
 636                 if (!bi->dma) {
 637                         bi->dma = dma_map_single(rx_ring->dev,
 638                                                  skb->data,
 639                                                  rx_ring->rx_buf_len,
 640                                                  DMA_FROM_DEVICE);
 641                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 642                                 rx_ring->rx_stats.alloc_buff_failed++;
 643                                 bi->dma = 0;
 644                                 goto no_buffers;
 645                         }
 646                 }
 647
 648                 if (ring_is_ps_enabled(rx_ring)) {
 649                         if (!bi->page) {
 650                                 bi->page = alloc_page(GFP_ATOMIC);
 651                                 if (!bi->page) {
 652                                         rx_ring->rx_stats.alloc_page_failed++;
 653                                         goto no_buffers;
 654                                 }
 655                         }
 656
 657                         if (!bi->page_dma) {
 658                                 /* use a half page if we're re-using */
 659                                 bi->page_offset ^= PAGE_SIZE / 2;
 660                                 bi->page_dma = dma_map_page(rx_ring->dev,
 661                                                             bi->page,
 662                                                             bi->page_offset,
 663                                                             PAGE_SIZE / 2,
 664                                                             DMA_FROM_DEVICE);
 665                                 if (dma_mapping_error(rx_ring->dev,
 666                                                       bi->page_dma)) {
 667                                         rx_ring->rx_stats.alloc_page_failed++;
 668                                         bi->page_dma = 0;
 669                                         goto no_buffers;
 670                                 }
 671                         }
 672
 673                         /* Refresh the desc even if buffer_addrs didn't change
 674                          * because each write-back erases this info.
 675                          */
 676                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 677                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 678                 } else {
 679                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 680                         rx_desc->read.hdr_addr = 0;
 681                 }
 682                 i++;
 683                 if (i == rx_ring->count)
 684                         i = 0;
 685         }
 686
 687 no_buffers:
 688         if (rx_ring->next_to_use != i)
 689                 i40e_release_rx_desc(rx_ring, i);
 690 }
 691
 692 /**
 693  * i40e_receive_skb - Send a completed packet up the stack
 694  * @rx_ring:  rx ring in play
 695  * @skb: packet to send up
 696  * @vlan_tag: vlan tag for packet
 697  **/
 698 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 699                              struct sk_buff *skb, u16 vlan_tag)
 700 {
 701         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 702         struct i40e_vsi *vsi = rx_ring->vsi;
 703         u64 flags = vsi->back->flags;
 704
 705         if (vlan_tag & VLAN_VID_MASK)
 706                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 707
 708         if (flags & I40E_FLAG_IN_NETPOLL)
 709                 netif_rx(skb);
 710         else
 711                 napi_gro_receive(&q_vector->napi, skb);
 712 }
 713
 714 /**
 715  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 716  * @vsi: the VSI we care about
 717  * @skb: skb currently being received and modified
 718  * @rx_status: status value of last descriptor in packet
 719  * @rx_error: error value of last descriptor in packet
 720  * @rx_ptype: ptype value of last descriptor in packet
 721  **/
 722 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 723                                     struct sk_buff *skb,
 724                                     u32 rx_status,
 725                                     u32 rx_error,
 726                                     u16 rx_ptype)
 727 {
 728         bool ipv4_tunnel, ipv6_tunnel;
 729         __wsum rx_udp_csum;
 730         __sum16 csum;
 731         struct iphdr *iph;
 732
 733         ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 734                       (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 735         ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 736                       (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 737
 738         skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
 739         skb->ip_summed = CHECKSUM_NONE;
 740
 741         /* Rx csum enabled and ip headers found? */
 742         if (!(vsi->netdev->features & NETIF_F_RXCSUM &&
 743               rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 744                 return;
 745
 746         /* likely incorrect csum if alternate IP extension headers found */
 747         if (rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 748                 return;
 749
 750         /* IP or L4 or outmost IP checksum error */
 751         if (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
 752                         (1 << I40E_RX_DESC_ERROR_L4E_SHIFT) |
 753                         (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))) {
 754                 vsi->back->hw_csum_rx_error++;
 755                 return;
 756         }
 757
 758         if (ipv4_tunnel &&
 759             !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
 760                 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 761                  * it in the driver, hardware does not do it for us.
 762                  * Since L3L4P bit was set we assume a valid IHL value (>=5)
 763                  * so the total length of IPv4 header is IHL*4 bytes
 764                  */
 765                 skb->transport_header = skb->mac_header +
 766                                         sizeof(struct ethhdr) +
 767                                         (ip_hdr(skb)->ihl * 4);
 768
 769                 /* Add 4 bytes for VLAN tagged packets */
 770                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 771                                           skb->protocol == htons(ETH_P_8021AD))
 772                                           ? VLAN_HLEN : 0;
 773
 774                 rx_udp_csum = udp_csum(skb);
 775                 iph = ip_hdr(skb);
 776                 csum = csum_tcpudp_magic(
 777                                 iph->saddr, iph->daddr,
 778                                 (skb->len - skb_transport_offset(skb)),
 779                                 IPPROTO_UDP, rx_udp_csum);
 780
 781                 if (udp_hdr(skb)->check != csum) {
 782                         vsi->back->hw_csum_rx_error++;
 783                         return;
 784                 }
 785         }
 786
 787         skb->ip_summed = CHECKSUM_UNNECESSARY;
 788 }
 789
 790 /**
 791  * i40e_rx_hash - returns the hash value from the Rx descriptor
 792  * @ring: descriptor ring
 793  * @rx_desc: specific descriptor
 794  **/
 795 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 796                                union i40e_rx_desc *rx_desc)
 797 {
 798         const __le64 rss_mask =
 799                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 800                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 801
 802         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 803             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 804                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 805         else
 806                 return 0;
 807 }
 808
 809 /**
 810  * i40e_ptype_to_hash - get a hash type
 811  * @ptype: the ptype value from the descriptor
 812  *
 813  * Returns a hash type to be used by skb_set_hash
 814  **/
 815 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 816 {
 817         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 818
 819         if (!decoded.known)
 820                 return PKT_HASH_TYPE_NONE;
 821
 822         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 823             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 824                 return PKT_HASH_TYPE_L4;
 825         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 826                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 827                 return PKT_HASH_TYPE_L3;
 828         else
 829                 return PKT_HASH_TYPE_L2;
 830 }
 831
 832 /**
 833  * i40e_clean_rx_irq - Reclaim resources after receive completes
 834  * @rx_ring:  rx ring to clean
 835  * @budget:   how many cleans we're allowed
 836  *
 837  * Returns true if there's any budget left (e.g. the clean is finished)
 838  **/
 839 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
 840 {
 841         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 842         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 843         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 844         const int current_node = numa_node_id();
 845         struct i40e_vsi *vsi = rx_ring->vsi;
 846         u16 i = rx_ring->next_to_clean;
 847         union i40e_rx_desc *rx_desc;
 848         u32 rx_error, rx_status;
 849         u8 rx_ptype;
 850         u64 qword;
 851
 852         rx_desc = I40E_RX_DESC(rx_ring, i);
 853         qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 854         rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 855                     I40E_RXD_QW1_STATUS_SHIFT;
 856
 857         while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 858                 union i40e_rx_desc *next_rxd;
 859                 struct i40e_rx_buffer *rx_bi;
 860                 struct sk_buff *skb;
 861                 u16 vlan_tag;
 862                 rx_bi = &rx_ring->rx_bi[i];
 863                 skb = rx_bi->skb;
 864                 prefetch(skb->data);
 865
 866                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 867                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 868                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 869                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 870                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 871                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 872
 873                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 874                            I40E_RXD_QW1_ERROR_SHIFT;
 875                 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
 876                 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
 877
 878                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 879                            I40E_RXD_QW1_PTYPE_SHIFT;
 880                 rx_bi->skb = NULL;
 881
 882                 /* This memory barrier is needed to keep us from reading
 883                  * any other fields out of the rx_desc until we know the
 884                  * STATUS_DD bit is set
 885                  */
 886                 rmb();
 887
 888                 /* Get the header and possibly the whole packet
 889                  * If this is an skb from previous receive dma will be 0
 890                  */
 891                 if (rx_bi->dma) {
 892                         u16 len;
 893
 894                         if (rx_hbo)
 895                                 len = I40E_RX_HDR_SIZE;
 896                         else if (rx_sph)
 897                                 len = rx_header_len;
 898                         else if (rx_packet_len)
 899                                 len = rx_packet_len;   /* 1buf/no split found */
 900                         else
 901                                 len = rx_header_len;   /* split always mode */
 902
 903                         skb_put(skb, len);
 904                         dma_unmap_single(rx_ring->dev,
 905                                          rx_bi->dma,
 906                                          rx_ring->rx_buf_len,
 907                                          DMA_FROM_DEVICE);
 908                         rx_bi->dma = 0;
 909                 }
 910
 911                 /* Get the rest of the data if this was a header split */
 912                 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
 913
 914                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 915                                            rx_bi->page,
 916                                            rx_bi->page_offset,
 917                                            rx_packet_len);
 918
 919                         skb->len += rx_packet_len;
 920                         skb->data_len += rx_packet_len;
 921                         skb->truesize += rx_packet_len;
 922
 923                         if ((page_count(rx_bi->page) == 1) &&
 924                             (page_to_nid(rx_bi->page) == current_node))
 925                                 get_page(rx_bi->page);
 926                         else
 927                                 rx_bi->page = NULL;
 928
 929                         dma_unmap_page(rx_ring->dev,
 930                                        rx_bi->page_dma,
 931                                        PAGE_SIZE / 2,
 932                                        DMA_FROM_DEVICE);
 933                         rx_bi->page_dma = 0;
 934                 }
 935                 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
 936
 937                 if (unlikely(
 938                     !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
 939                         struct i40e_rx_buffer *next_buffer;
 940
 941                         next_buffer = &rx_ring->rx_bi[i];
 942
 943                         if (ring_is_ps_enabled(rx_ring)) {
 944                                 rx_bi->skb = next_buffer->skb;
 945                                 rx_bi->dma = next_buffer->dma;
 946                                 next_buffer->skb = skb;
 947                                 next_buffer->dma = 0;
 948                         }
 949                         rx_ring->rx_stats.non_eop_descs++;
 950                         goto next_desc;
 951                 }
 952
 953                 /* ERR_MASK will only have valid bits if EOP set */
 954                 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 955                         dev_kfree_skb_any(skb);
 956                         goto next_desc;
 957                 }
 958
 959                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
 960                              i40e_ptype_to_hash(rx_ptype));
 961                 /* probably a little skewed due to removing CRC */
 962                 total_rx_bytes += skb->len;
 963                 total_rx_packets++;
 964
 965                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
 966
 967                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
 968
 969                 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
 970                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
 971                          : 0;
 972                 i40e_receive_skb(rx_ring, skb, vlan_tag);
 973
 974                 rx_ring->netdev->last_rx = jiffies;
 975                 budget--;
 976 next_desc:
 977                 rx_desc->wb.qword1.status_error_len = 0;
 978                 if (!budget)
 979                         break;
 980
 981                 cleaned_count++;
 982                 /* return some buffers to hardware, one at a time is too slow */
 983                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 984                         i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
 985                         cleaned_count = 0;
 986                 }
 987
 988                 /* use prefetched values */
 989                 rx_desc = next_rxd;
 990                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 991                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 992                             I40E_RXD_QW1_STATUS_SHIFT;
 993         }
 994
 995         rx_ring->next_to_clean = i;
 996         u64_stats_update_begin(&rx_ring->syncp);
 997         rx_ring->stats.packets += total_rx_packets;
 998         rx_ring->stats.bytes += total_rx_bytes;
 999         u64_stats_update_end(&rx_ring->syncp);
1000         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1001         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1002
1003         if (cleaned_count)
1004                 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1005
1006         return budget > 0;
1007 }
1008
1009 /**
1010  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1011  * @napi: napi struct with our devices info in it
1012  * @budget: amount of work driver is allowed to do this pass, in packets
1013  *
1014  * This function will clean all queues associated with a q_vector.
1015  *
1016  * Returns the amount of work done
1017  **/
1018 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1019 {
1020         struct i40e_q_vector *q_vector =
1021                                container_of(napi, struct i40e_q_vector, napi);
1022         struct i40e_vsi *vsi = q_vector->vsi;
1023         struct i40e_ring *ring;
1024         bool clean_complete = true;
1025         int budget_per_ring;
1026
1027         if (test_bit(__I40E_DOWN, &vsi->state)) {
1028                 napi_complete(napi);
1029                 return 0;
1030         }
1031
1032         /* Since the actual Tx work is minimal, we can give the Tx a larger
1033          * budget and be more aggressive about cleaning up the Tx descriptors.
1034          */
1035         i40e_for_each_ring(ring, q_vector->tx)
1036                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1037
1038         /* We attempt to distribute budget to each Rx queue fairly, but don't
1039          * allow the budget to go below 1 because that would exit polling early.
1040          */
1041         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1042
1043         i40e_for_each_ring(ring, q_vector->rx)
1044                 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
1045
1046         /* If work not completed, return budget and polling will return */
1047         if (!clean_complete)
1048                 return budget;
1049
1050         /* Work is done so exit the polling mode and re-enable the interrupt */
1051         napi_complete(napi);
1052         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1053             ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1054                 i40e_update_dynamic_itr(q_vector);
1055
1056         if (!test_bit(__I40E_DOWN, &vsi->state))
1057                 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1058
1059         return 0;
1060 }
1061
1062 /**
1063  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1064  * @skb:     send buffer
1065  * @tx_ring: ring to send buffer on
1066  * @flags:   the tx flags to be set
1067  *
1068  * Checks the skb and set up correspondingly several generic transmit flags
1069  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1070  *
1071  * Returns error code indicate the frame should be dropped upon error and the
1072  * otherwise  returns 0 to indicate the flags has been set properly.
1073  **/
1074 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1075                                       struct i40e_ring *tx_ring,
1076                                       u32 *flags)
1077 {
1078         __be16 protocol = skb->protocol;
1079         u32  tx_flags = 0;
1080
1081         /* if we have a HW VLAN tag being added, default to the HW one */
1082         if (vlan_tx_tag_present(skb)) {
1083                 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1084                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1085         /* else if it is a SW VLAN, check the next protocol and store the tag */
1086         } else if (protocol == htons(ETH_P_8021Q)) {
1087                 struct vlan_hdr *vhdr, _vhdr;
1088                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1089                 if (!vhdr)
1090                         return -EINVAL;
1091
1092                 protocol = vhdr->h_vlan_encapsulated_proto;
1093                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1094                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1095         }
1096
1097         *flags = tx_flags;
1098         return 0;
1099 }
1100
1101 /**
1102  * i40e_tso - set up the tso context descriptor
1103  * @tx_ring:  ptr to the ring to send
1104  * @skb:      ptr to the skb we're sending
1105  * @tx_flags: the collected send information
1106  * @protocol: the send protocol
1107  * @hdr_len:  ptr to the size of the packet header
1108  * @cd_tunneling: ptr to context descriptor bits
1109  *
1110  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1111  **/
1112 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1113                     u32 tx_flags, __be16 protocol, u8 *hdr_len,
1114                     u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1115 {
1116         u32 cd_cmd, cd_tso_len, cd_mss;
1117         struct tcphdr *tcph;
1118         struct iphdr *iph;
1119         u32 l4len;
1120         int err;
1121         struct ipv6hdr *ipv6h;
1122
1123         if (!skb_is_gso(skb))
1124                 return 0;
1125
1126         if (skb_header_cloned(skb)) {
1127                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1128                 if (err)
1129                         return err;
1130         }
1131
1132         if (protocol == htons(ETH_P_IP)) {
1133                 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1134                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1135                 iph->tot_len = 0;
1136                 iph->check = 0;
1137                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1138                                                  0, IPPROTO_TCP, 0);
1139         } else if (skb_is_gso_v6(skb)) {
1140
1141                 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1142                                            : ipv6_hdr(skb);
1143                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1144                 ipv6h->payload_len = 0;
1145                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1146                                                0, IPPROTO_TCP, 0);
1147         }
1148
1149         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1150         *hdr_len = (skb->encapsulation
1151                     ? (skb_inner_transport_header(skb) - skb->data)
1152                     : skb_transport_offset(skb)) + l4len;
1153
1154         /* find the field values */
1155         cd_cmd = I40E_TX_CTX_DESC_TSO;
1156         cd_tso_len = skb->len - *hdr_len;
1157         cd_mss = skb_shinfo(skb)->gso_size;
1158         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1159                                 ((u64)cd_tso_len <<
1160                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1161                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1162         return 1;
1163 }
1164
1165 /**
1166  * i40e_tx_enable_csum - Enable Tx checksum offloads
1167  * @skb: send buffer
1168  * @tx_flags: Tx flags currently set
1169  * @td_cmd: Tx descriptor command bits to set
1170  * @td_offset: Tx descriptor header offsets to set
1171  * @cd_tunneling: ptr to context desc bits
1172  **/
1173 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1174                                 u32 *td_cmd, u32 *td_offset,
1175                                 struct i40e_ring *tx_ring,
1176                                 u32 *cd_tunneling)
1177 {
1178         struct ipv6hdr *this_ipv6_hdr;
1179         unsigned int this_tcp_hdrlen;
1180         struct iphdr *this_ip_hdr;
1181         u32 network_hdr_len;
1182         u8 l4_hdr = 0;
1183
1184         if (skb->encapsulation) {
1185                 network_hdr_len = skb_inner_network_header_len(skb);
1186                 this_ip_hdr = inner_ip_hdr(skb);
1187                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1188                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1189
1190                 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1191
1192                         if (tx_flags & I40E_TX_FLAGS_TSO) {
1193                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1194                                 ip_hdr(skb)->check = 0;
1195                         } else {
1196                                 *cd_tunneling |=
1197                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1198                         }
1199                 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1200                         if (tx_flags & I40E_TX_FLAGS_TSO) {
1201                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1202                                 ip_hdr(skb)->check = 0;
1203                         } else {
1204                                 *cd_tunneling |=
1205                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1206                         }
1207                 }
1208
1209                 /* Now set the ctx descriptor fields */
1210                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1211                                         I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1212                                    I40E_TXD_CTX_UDP_TUNNELING            |
1213                                    ((skb_inner_network_offset(skb) -
1214                                         skb_transport_offset(skb)) >> 1) <<
1215                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1216
1217         } else {
1218                 network_hdr_len = skb_network_header_len(skb);
1219                 this_ip_hdr = ip_hdr(skb);
1220                 this_ipv6_hdr = ipv6_hdr(skb);
1221                 this_tcp_hdrlen = tcp_hdrlen(skb);
1222         }
1223
1224         /* Enable IP checksum offloads */
1225         if (tx_flags & I40E_TX_FLAGS_IPV4) {
1226                 l4_hdr = this_ip_hdr->protocol;
1227                 /* the stack computes the IP header already, the only time we
1228                  * need the hardware to recompute it is in the case of TSO.
1229                  */
1230                 if (tx_flags & I40E_TX_FLAGS_TSO) {
1231                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1232                         this_ip_hdr->check = 0;
1233                 } else {
1234                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1235                 }
1236                 /* Now set the td_offset for IP header length */
1237                 *td_offset = (network_hdr_len >> 2) <<
1238                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1239         } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1240                 l4_hdr = this_ipv6_hdr->nexthdr;
1241                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1242                 /* Now set the td_offset for IP header length */
1243                 *td_offset = (network_hdr_len >> 2) <<
1244                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1245         }
1246         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1247         *td_offset |= (skb_network_offset(skb) >> 1) <<
1248                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1249
1250         /* Enable L4 checksum offloads */
1251         switch (l4_hdr) {
1252         case IPPROTO_TCP:
1253                 /* enable checksum offloads */
1254                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1255                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1256                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1257                 break;
1258         case IPPROTO_SCTP:
1259                 /* enable SCTP checksum offload */
1260                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1261                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1262                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1263                 break;
1264         case IPPROTO_UDP:
1265                 /* enable UDP checksum offload */
1266                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1267                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1268                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1269                 break;
1270         default:
1271                 break;
1272         }
1273 }
1274
1275 /**
1276  * i40e_create_tx_ctx Build the Tx context descriptor
1277  * @tx_ring:  ring to create the descriptor on
1278  * @cd_type_cmd_tso_mss: Quad Word 1
1279  * @cd_tunneling: Quad Word 0 - bits 0-31
1280  * @cd_l2tag2: Quad Word 0 - bits 32-63
1281  **/
1282 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1283                                const u64 cd_type_cmd_tso_mss,
1284                                const u32 cd_tunneling, const u32 cd_l2tag2)
1285 {
1286         struct i40e_tx_context_desc *context_desc;
1287         int i = tx_ring->next_to_use;
1288
1289         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1290             !cd_tunneling && !cd_l2tag2)
1291                 return;
1292
1293         /* grab the next descriptor */
1294         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1295
1296         i++;
1297         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1298
1299         /* cpu_to_le32 and assign to struct fields */
1300         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1301         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1302         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1303 }
1304
1305 /**
1306  * i40e_tx_map - Build the Tx descriptor
1307  * @tx_ring:  ring to send buffer on
1308  * @skb:      send buffer
1309  * @first:    first buffer info buffer to use
1310  * @tx_flags: collected send information
1311  * @hdr_len:  size of the packet header
1312  * @td_cmd:   the command field in the descriptor
1313  * @td_offset: offset for checksum or crc
1314  **/
1315 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1316                         struct i40e_tx_buffer *first, u32 tx_flags,
1317                         const u8 hdr_len, u32 td_cmd, u32 td_offset)
1318 {
1319         unsigned int data_len = skb->data_len;
1320         unsigned int size = skb_headlen(skb);
1321         struct skb_frag_struct *frag;
1322         struct i40e_tx_buffer *tx_bi;
1323         struct i40e_tx_desc *tx_desc;
1324         u16 i = tx_ring->next_to_use;
1325         u32 td_tag = 0;
1326         dma_addr_t dma;
1327         u16 gso_segs;
1328
1329         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1330                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1331                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1332                          I40E_TX_FLAGS_VLAN_SHIFT;
1333         }
1334
1335         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1336                 gso_segs = skb_shinfo(skb)->gso_segs;
1337         else
1338                 gso_segs = 1;
1339
1340         /* multiply data chunks by size of headers */
1341         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1342         first->gso_segs = gso_segs;
1343         first->skb = skb;
1344         first->tx_flags = tx_flags;
1345
1346         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1347
1348         tx_desc = I40E_TX_DESC(tx_ring, i);
1349         tx_bi = first;
1350
1351         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1352                 if (dma_mapping_error(tx_ring->dev, dma))
1353                         goto dma_error;
1354
1355                 /* record length, and DMA address */
1356                 dma_unmap_len_set(tx_bi, len, size);
1357                 dma_unmap_addr_set(tx_bi, dma, dma);
1358
1359                 tx_desc->buffer_addr = cpu_to_le64(dma);
1360
1361                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1362                         tx_desc->cmd_type_offset_bsz =
1363                                 build_ctob(td_cmd, td_offset,
1364                                            I40E_MAX_DATA_PER_TXD, td_tag);
1365
1366                         tx_desc++;
1367                         i++;
1368                         if (i == tx_ring->count) {
1369                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1370                                 i = 0;
1371                         }
1372
1373                         dma += I40E_MAX_DATA_PER_TXD;
1374                         size -= I40E_MAX_DATA_PER_TXD;
1375
1376                         tx_desc->buffer_addr = cpu_to_le64(dma);
1377                 }
1378
1379                 if (likely(!data_len))
1380                         break;
1381
1382                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1383                                                           size, td_tag);
1384
1385                 tx_desc++;
1386                 i++;
1387                 if (i == tx_ring->count) {
1388                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1389                         i = 0;
1390                 }
1391
1392                 size = skb_frag_size(frag);
1393                 data_len -= size;
1394
1395                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1396                                        DMA_TO_DEVICE);
1397
1398                 tx_bi = &tx_ring->tx_bi[i];
1399         }
1400
1401         /* Place RS bit on last descriptor of any packet that spans across the
1402          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1403          */
1404 #define WB_STRIDE 0x3
1405         if (((i & WB_STRIDE) != WB_STRIDE) &&
1406             (first <= &tx_ring->tx_bi[i]) &&
1407             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1408                 tx_desc->cmd_type_offset_bsz =
1409                         build_ctob(td_cmd, td_offset, size, td_tag) |
1410                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1411                                          I40E_TXD_QW1_CMD_SHIFT);
1412         } else {
1413                 tx_desc->cmd_type_offset_bsz =
1414                         build_ctob(td_cmd, td_offset, size, td_tag) |
1415                         cpu_to_le64((u64)I40E_TXD_CMD <<
1416                                          I40E_TXD_QW1_CMD_SHIFT);
1417         }
1418
1419         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1420                                                  tx_ring->queue_index),
1421                              first->bytecount);
1422
1423         /* set the timestamp */
1424         first->time_stamp = jiffies;
1425
1426         /* Force memory writes to complete before letting h/w
1427          * know there are new descriptors to fetch.  (Only
1428          * applicable for weak-ordered memory model archs,
1429          * such as IA-64).
1430          */
1431         wmb();
1432
1433         /* set next_to_watch value indicating a packet is present */
1434         first->next_to_watch = tx_desc;
1435
1436         i++;
1437         if (i == tx_ring->count)
1438                 i = 0;
1439
1440         tx_ring->next_to_use = i;
1441
1442         /* notify HW of packet */
1443         writel(i, tx_ring->tail);
1444
1445         return;
1446
1447 dma_error:
1448         dev_info(tx_ring->dev, "TX DMA map failed\n");
1449
1450         /* clear dma mappings for failed tx_bi map */
1451         for (;;) {
1452                 tx_bi = &tx_ring->tx_bi[i];
1453                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1454                 if (tx_bi == first)
1455                         break;
1456                 if (i == 0)
1457                         i = tx_ring->count;
1458                 i--;
1459         }
1460
1461         tx_ring->next_to_use = i;
1462 }
1463
1464 /**
1465  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1466  * @tx_ring: the ring to be checked
1467  * @size:    the size buffer we want to assure is available
1468  *
1469  * Returns -EBUSY if a stop is needed, else 0
1470  **/
1471 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1472 {
1473         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1474         /* Memory barrier before checking head and tail */
1475         smp_mb();
1476
1477         /* Check again in a case another CPU has just made room available. */
1478         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1479                 return -EBUSY;
1480
1481         /* A reprieve! - use start_queue because it doesn't call schedule */
1482         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1483         ++tx_ring->tx_stats.restart_queue;
1484         return 0;
1485 }
1486
1487 /**
1488  * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1489  * @tx_ring: the ring to be checked
1490  * @size:    the size buffer we want to assure is available
1491  *
1492  * Returns 0 if stop is not needed
1493  **/
1494 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1495 {
1496         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1497                 return 0;
1498         return __i40e_maybe_stop_tx(tx_ring, size);
1499 }
1500
1501 /**
1502  * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1503  * @skb:     send buffer
1504  * @tx_ring: ring to send buffer on
1505  *
1506  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1507  * there is not enough descriptors available in this ring since we need at least
1508  * one descriptor.
1509  **/
1510 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1511                                       struct i40e_ring *tx_ring)
1512 {
1513 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1514         unsigned int f;
1515 #endif
1516         int count = 0;
1517
1518         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1519          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1520          *       + 4 desc gap to avoid the cache line where head is,
1521          *       + 1 desc for context descriptor,
1522          * otherwise try next time
1523          */
1524 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1525         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1526                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1527 #else
1528         count += skb_shinfo(skb)->nr_frags;
1529 #endif
1530         count += TXD_USE_COUNT(skb_headlen(skb));
1531         if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1532                 tx_ring->tx_stats.tx_busy++;
1533                 return 0;
1534         }
1535         return count;
1536 }
1537
1538 /**
1539  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1540  * @skb:     send buffer
1541  * @tx_ring: ring to send buffer on
1542  *
1543  * Returns NETDEV_TX_OK if sent, else an error code
1544  **/
1545 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1546                                         struct i40e_ring *tx_ring)
1547 {
1548         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1549         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1550         struct i40e_tx_buffer *first;
1551         u32 td_offset = 0;
1552         u32 tx_flags = 0;
1553         __be16 protocol;
1554         u32 td_cmd = 0;
1555         u8 hdr_len = 0;
1556         int tso;
1557         if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1558                 return NETDEV_TX_BUSY;
1559
1560         /* prepare the xmit flags */
1561         if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1562                 goto out_drop;
1563
1564         /* obtain protocol of skb */
1565         protocol = skb->protocol;
1566
1567         /* record the location of the first descriptor for this packet */
1568         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1569
1570         /* setup IPv4/IPv6 offloads */
1571         if (protocol == htons(ETH_P_IP))
1572                 tx_flags |= I40E_TX_FLAGS_IPV4;
1573         else if (protocol == htons(ETH_P_IPV6))
1574                 tx_flags |= I40E_TX_FLAGS_IPV6;
1575
1576         tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1577                        &cd_type_cmd_tso_mss, &cd_tunneling);
1578
1579         if (tso < 0)
1580                 goto out_drop;
1581         else if (tso)
1582                 tx_flags |= I40E_TX_FLAGS_TSO;
1583
1584         skb_tx_timestamp(skb);
1585
1586         /* always enable CRC insertion offload */
1587         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1588
1589         /* Always offload the checksum, since it's in the data descriptor */
1590         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1591                 tx_flags |= I40E_TX_FLAGS_CSUM;
1592
1593                 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1594                                     tx_ring, &cd_tunneling);
1595         }
1596
1597         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1598                            cd_tunneling, cd_l2tag2);
1599
1600         i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1601                     td_cmd, td_offset);
1602
1603         i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1604
1605         return NETDEV_TX_OK;
1606
1607 out_drop:
1608         dev_kfree_skb_any(skb);
1609         return NETDEV_TX_OK;
1610 }
1611
1612 /**
1613  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1614  * @skb:    send buffer
1615  * @netdev: network interface device structure
1616  *
1617  * Returns NETDEV_TX_OK if sent, else an error code
1618  **/
1619 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1620 {
1621         struct i40evf_adapter *adapter = netdev_priv(netdev);
1622         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1623
1624         /* hardware can't handle really short frames, hardware padding works
1625          * beyond this point
1626          */
1627         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1628                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1629                         return NETDEV_TX_OK;
1630                 skb->len = I40E_MIN_TX_LEN;
1631                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1632         }
1633
1634         return i40e_xmit_frame_ring(skb, tx_ring);
1635 }