drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #ifndef __HCLGE_CMD_H
   5 #define __HCLGE_CMD_H
   6 #include <linux/types.h>
   7 #include <linux/io.h>
   8 #include <linux/etherdevice.h>
   9 #include "hnae3.h"
  10
  11 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  12 #define HCLGE_DESC_DATA_LEN             6
  13
  14 struct hclge_dev;
  15 struct hclge_desc {
  16         __le16 opcode;
  17
  18 #define HCLGE_CMDQ_RX_INVLD_B           0
  19 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  20
  21         __le16 flag;
  22         __le16 retval;
  23         __le16 rsv;
  24         __le32 data[HCLGE_DESC_DATA_LEN];
  25 };
  26
  27 struct hclge_cmq_ring {
  28         dma_addr_t desc_dma_addr;
  29         struct hclge_desc *desc;
  30         struct hclge_dev *dev;
  31         u32 head;
  32         u32 tail;
  33
  34         u16 buf_size;
  35         u16 desc_num;
  36         int next_to_use;
  37         int next_to_clean;
  38         u8 ring_type; /* cmq ring type */
  39         spinlock_t lock; /* Command queue lock */
  40 };
  41
  42 enum hclge_cmd_return_status {
  43         HCLGE_CMD_EXEC_SUCCESS  = 0,
  44         HCLGE_CMD_NO_AUTH       = 1,
  45         HCLGE_CMD_NOT_SUPPORTED = 2,
  46         HCLGE_CMD_QUEUE_FULL    = 3,
  47         HCLGE_CMD_NEXT_ERR      = 4,
  48         HCLGE_CMD_UNEXE_ERR     = 5,
  49         HCLGE_CMD_PARA_ERR      = 6,
  50         HCLGE_CMD_RESULT_ERR    = 7,
  51         HCLGE_CMD_TIMEOUT       = 8,
  52         HCLGE_CMD_HILINK_ERR    = 9,
  53         HCLGE_CMD_QUEUE_ILLEGAL = 10,
  54         HCLGE_CMD_INVALID       = 11,
  55 };
  56
  57 enum hclge_cmd_status {
  58         HCLGE_STATUS_SUCCESS    = 0,
  59         HCLGE_ERR_CSQ_FULL      = -1,
  60         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  61         HCLGE_ERR_CSQ_ERROR     = -3,
  62 };
  63
  64 struct hclge_misc_vector {
  65         u8 __iomem *addr;
  66         int vector_irq;
  67         char name[HNAE3_INT_NAME_LEN];
  68 };
  69
  70 struct hclge_cmq {
  71         struct hclge_cmq_ring csq;
  72         struct hclge_cmq_ring crq;
  73         u16 tx_timeout;
  74         enum hclge_cmd_status last_status;
  75 };
  76
  77 #define HCLGE_CMD_FLAG_IN       BIT(0)
  78 #define HCLGE_CMD_FLAG_OUT      BIT(1)
  79 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
  80 #define HCLGE_CMD_FLAG_WR       BIT(3)
  81 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  83
  84 enum hclge_opcode_type {
  85         /* Generic commands */
  86         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  87         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  88         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  89         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  90         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  91         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  92         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  93         HCLGE_OPC_PF_RST_DONE           = 0x0026,
  94         HCLGE_OPC_QUERY_VF_RST_RDY      = 0x0027,
  95
  96         HCLGE_OPC_STATS_64_BIT          = 0x0030,
  97         HCLGE_OPC_STATS_32_BIT          = 0x0031,
  98         HCLGE_OPC_STATS_MAC             = 0x0032,
  99         HCLGE_OPC_QUERY_MAC_REG_NUM     = 0x0033,
 100         HCLGE_OPC_STATS_MAC_ALL         = 0x0034,
 101
 102         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
 103         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
 104         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
 105         HCLGE_OPC_DFX_BD_NUM            = 0x0043,
 106         HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
 107         HCLGE_OPC_DFX_SSU_REG_0         = 0x0045,
 108         HCLGE_OPC_DFX_SSU_REG_1         = 0x0046,
 109         HCLGE_OPC_DFX_IGU_EGU_REG       = 0x0047,
 110         HCLGE_OPC_DFX_RPU_REG_0         = 0x0048,
 111         HCLGE_OPC_DFX_RPU_REG_1         = 0x0049,
 112         HCLGE_OPC_DFX_NCSI_REG          = 0x004A,
 113         HCLGE_OPC_DFX_RTC_REG           = 0x004B,
 114         HCLGE_OPC_DFX_PPP_REG           = 0x004C,
 115         HCLGE_OPC_DFX_RCB_REG           = 0x004D,
 116         HCLGE_OPC_DFX_TQP_REG           = 0x004E,
 117         HCLGE_OPC_DFX_SSU_REG_2         = 0x004F,
 118         HCLGE_OPC_DFX_QUERY_CHIP_CAP    = 0x0050,
 119
 120         /* MAC command */
 121         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 122         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 123         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 124         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 125         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 126         HCLGE_OPC_QUERY_MAC_TNL_INT     = 0x0310,
 127         HCLGE_OPC_MAC_TNL_INT_EN        = 0x0311,
 128         HCLGE_OPC_CLEAR_MAC_TNL_INT     = 0x0312,
 129         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
 130         HCLGE_OPC_CONFIG_FEC_MODE       = 0x031A,
 131
 132         /* PFC/Pause commands */
 133         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 134         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 135         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 136         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 137         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 138         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 139         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 140         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 141         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 142         HCLGE_OPC_QOS_MAP               = 0x070A,
 143
 144         /* ETS/scheduler commands */
 145         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 146         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 147         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 148         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 149         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 150         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 151         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 152         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 153         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 154         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 155         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 156         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 157         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 158         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 159         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 160         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 161         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 162         HCLGE_OPC_ETS_TC_WEIGHT         = 0x0843,
 163         HCLGE_OPC_QSET_DFX_STS          = 0x0844,
 164         HCLGE_OPC_PRI_DFX_STS           = 0x0845,
 165         HCLGE_OPC_PG_DFX_STS            = 0x0846,
 166         HCLGE_OPC_PORT_DFX_STS          = 0x0847,
 167         HCLGE_OPC_SCH_NQ_CNT            = 0x0848,
 168         HCLGE_OPC_SCH_RQ_CNT            = 0x0849,
 169         HCLGE_OPC_TM_INTERNAL_STS       = 0x0850,
 170         HCLGE_OPC_TM_INTERNAL_CNT       = 0x0851,
 171         HCLGE_OPC_TM_INTERNAL_STS_1     = 0x0852,
 172
 173         /* Packet buffer allocate commands */
 174         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 175         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 176         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 177         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 178         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 179         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 180
 181         /* TQP management command */
 182         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 183
 184         /* TQP commands */
 185         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 186         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 187         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
 188         HCLGE_OPC_TQP_TX_QUEUE_TC       = 0x0B04,
 189         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 190         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 191         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
 192         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 193         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 194         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 195         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 196
 197         /* PPU commands */
 198         HCLGE_OPC_PPU_PF_OTHER_INT_DFX  = 0x0B4A,
 199
 200         /* TSO command */
 201         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 202         HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
 203
 204         /* RSS commands */
 205         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 206         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 207         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 208         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 209
 210         /* Promisuous mode command */
 211         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 212
 213         /* Vlan offload commands */
 214         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 215         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 216
 217         /* Interrupts commands */
 218         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 219         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 220
 221         /* MAC commands */
 222         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 223         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 224         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 225         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 226         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
 227         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 228         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 229
 230         /* MAC VLAN commands */
 231         HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
 232
 233         /* VLAN commands */
 234         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 235         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 236         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 237
 238         /* Flow Director commands */
 239         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
 240         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
 241         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
 242         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
 243         HCLGE_OPC_FD_AD_OP              = 0x1204,
 244
 245         /* MDIO command */
 246         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 247
 248         /* QCN commands */
 249         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 250         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 251         HCLGE_OPC_QCN_SHAPPING_CFG      = 0x1A03,
 252         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 253         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 254         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 255         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 256         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 257
 258         /* Mailbox command */
 259         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 260
 261         /* Led command */
 262         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 263
 264         /* NCL config command */
 265         HCLGE_OPC_QUERY_NCL_CONFIG      = 0x7011,
 266
 267         /* M7 stats command */
 268         HCLGE_OPC_M7_STATS_BD           = 0x7012,
 269         HCLGE_OPC_M7_STATS_INFO         = 0x7013,
 270         HCLGE_OPC_M7_COMPAT_CFG         = 0x701A,
 271
 272         /* SFP command */
 273         HCLGE_OPC_GET_SFP_INFO          = 0x7104,
 274
 275         /* Error INT commands */
 276         HCLGE_MAC_COMMON_INT_EN         = 0x030E,
 277         HCLGE_TM_SCH_ECC_INT_EN         = 0x0829,
 278         HCLGE_SSU_ECC_INT_CMD           = 0x0989,
 279         HCLGE_SSU_COMMON_INT_CMD        = 0x098C,
 280         HCLGE_PPU_MPF_ECC_INT_CMD       = 0x0B40,
 281         HCLGE_PPU_MPF_OTHER_INT_CMD     = 0x0B41,
 282         HCLGE_PPU_PF_OTHER_INT_CMD      = 0x0B42,
 283         HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
 284         HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
 285         HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
 286         HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
 287         HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
 288         HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT      = 0x1514,
 289         HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT       = 0x1515,
 290         HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
 291         HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
 292         HCLGE_ROCEE_PF_RAS_INT_CMD      = 0x1584,
 293         HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD      = 0x1585,
 294         HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD      = 0x1586,
 295         HCLGE_IGU_EGU_TNL_INT_EN        = 0x1803,
 296         HCLGE_IGU_COMMON_INT_EN         = 0x1806,
 297         HCLGE_TM_QCN_MEM_INT_CFG        = 0x1A14,
 298         HCLGE_PPP_CMD0_INT_CMD          = 0x2100,
 299         HCLGE_PPP_CMD1_INT_CMD          = 0x2101,
 300         HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
 301         HCLGE_NCSI_INT_EN               = 0x2401,
 302 };
 303
 304 #define HCLGE_TQP_REG_OFFSET            0x80000
 305 #define HCLGE_TQP_REG_SIZE              0x200
 306
 307 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 308 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 309 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 310 struct hclge_config_rcb_init_cmd {
 311         __le16 rcb_init_flag;
 312         u8 rsv[22];
 313 };
 314
 315 struct hclge_tqp_map_cmd {
 316         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 317         u8 tqp_vf;      /* VF id */
 318 #define HCLGE_TQP_MAP_TYPE_PF           0
 319 #define HCLGE_TQP_MAP_TYPE_VF           1
 320 #define HCLGE_TQP_MAP_TYPE_B            0
 321 #define HCLGE_TQP_MAP_EN_B              1
 322         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 323         __le16 tqp_vid; /* Virtual id in this pf/vf */
 324         u8 rsv[18];
 325 };
 326
 327 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 328
 329 enum hclge_int_type {
 330         HCLGE_INT_TX,
 331         HCLGE_INT_RX,
 332         HCLGE_INT_EVENT,
 333 };
 334
 335 struct hclge_ctrl_vector_chain_cmd {
 336         u8 int_vector_id;
 337         u8 int_cause_num;
 338 #define HCLGE_INT_TYPE_S        0
 339 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 340 #define HCLGE_TQP_ID_S          2
 341 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 342 #define HCLGE_INT_GL_IDX_S      13
 343 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 344         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 345         u8 vfid;
 346         u8 rsv;
 347 };
 348
 349 #define HCLGE_MAX_TC_NUM                8
 350 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 351 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 352 struct hclge_tx_buff_alloc_cmd {
 353         __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
 354         u8 tx_buff_rsv[8];
 355 };
 356
 357 struct hclge_rx_priv_buff_cmd {
 358         __le16 buf_num[HCLGE_MAX_TC_NUM];
 359         __le16 shared_buf;
 360         u8 rsv[6];
 361 };
 362
 363 struct hclge_query_version_cmd {
 364         __le32 firmware;
 365         __le32 firmware_rsv[5];
 366 };
 367
 368 #define HCLGE_RX_PRIV_EN_B      15
 369 #define HCLGE_TC_NUM_ONE_DESC   4
 370 struct hclge_priv_wl {
 371         __le16 high;
 372         __le16 low;
 373 };
 374
 375 struct hclge_rx_priv_wl_buf {
 376         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 377 };
 378
 379 struct hclge_rx_com_thrd {
 380         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 381 };
 382
 383 struct hclge_rx_com_wl {
 384         struct hclge_priv_wl com_wl;
 385 };
 386
 387 struct hclge_waterline {
 388         u32 low;
 389         u32 high;
 390 };
 391
 392 struct hclge_tc_thrd {
 393         u32 low;
 394         u32 high;
 395 };
 396
 397 struct hclge_priv_buf {
 398         struct hclge_waterline wl;      /* Waterline for low and high*/
 399         u32 buf_size;   /* TC private buffer size */
 400         u32 tx_buf_size;
 401         u32 enable;     /* Enable TC private buffer or not */
 402 };
 403
 404 struct hclge_shared_buf {
 405         struct hclge_waterline self;
 406         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 407         u32 buf_size;
 408 };
 409
 410 struct hclge_pkt_buf_alloc {
 411         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 412         struct hclge_shared_buf s_buf;
 413 };
 414
 415 #define HCLGE_RX_COM_WL_EN_B    15
 416 struct hclge_rx_com_wl_buf_cmd {
 417         __le16 high_wl;
 418         __le16 low_wl;
 419         u8 rsv[20];
 420 };
 421
 422 #define HCLGE_RX_PKT_EN_B       15
 423 struct hclge_rx_pkt_buf_cmd {
 424         __le16 high_pkt;
 425         __le16 low_pkt;
 426         u8 rsv[20];
 427 };
 428
 429 #define HCLGE_PF_STATE_DONE_B   0
 430 #define HCLGE_PF_STATE_MAIN_B   1
 431 #define HCLGE_PF_STATE_BOND_B   2
 432 #define HCLGE_PF_STATE_MAC_N_B  6
 433 #define HCLGE_PF_MAC_NUM_MASK   0x3
 434 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 435 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 436 #define HCLGE_VF_RST_STATUS_CMD 4
 437
 438 struct hclge_func_status_cmd {
 439         __le32  vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
 440         u8 pf_state;
 441         u8 mac_id;
 442         u8 rsv1;
 443         u8 pf_cnt_in_mac;
 444         u8 pf_num;
 445         u8 vf_num;
 446         u8 rsv[2];
 447 };
 448
 449 struct hclge_pf_res_cmd {
 450         __le16 tqp_num;
 451         __le16 buf_size;
 452         __le16 msixcap_localid_ba_nic;
 453         __le16 msixcap_localid_ba_rocee;
 454 #define HCLGE_MSIX_OFT_ROCEE_S          0
 455 #define HCLGE_MSIX_OFT_ROCEE_M          GENMASK(15, 0)
 456 #define HCLGE_PF_VEC_NUM_S              0
 457 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
 458         __le16 pf_intr_vector_number;
 459         __le16 pf_own_fun_number;
 460         __le16 tx_buf_size;
 461         __le16 dv_buf_size;
 462         __le32 rsv[2];
 463 };
 464
 465 #define HCLGE_CFG_OFFSET_S      0
 466 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 467 #define HCLGE_CFG_RD_LEN_S      24
 468 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 469 #define HCLGE_CFG_RD_LEN_BYTES  16
 470 #define HCLGE_CFG_RD_LEN_UNIT   4
 471
 472 #define HCLGE_CFG_VMDQ_S        0
 473 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
 474 #define HCLGE_CFG_TC_NUM_S      8
 475 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 476 #define HCLGE_CFG_TQP_DESC_N_S  16
 477 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 478 #define HCLGE_CFG_PHY_ADDR_S    0
 479 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 480 #define HCLGE_CFG_MEDIA_TP_S    8
 481 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 482 #define HCLGE_CFG_RX_BUF_LEN_S  16
 483 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 484 #define HCLGE_CFG_MAC_ADDR_H_S  0
 485 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 486 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 487 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 488 #define HCLGE_CFG_RSS_SIZE_S    24
 489 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 490 #define HCLGE_CFG_SPEED_ABILITY_S       0
 491 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 492 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
 493 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
 494
 495 #define HCLGE_CFG_CMD_CNT               4
 496
 497 struct hclge_cfg_param_cmd {
 498         __le32 offset;
 499         __le32 rsv;
 500         __le32 param[HCLGE_CFG_CMD_CNT];
 501 };
 502
 503 #define HCLGE_MAC_MODE          0x0
 504 #define HCLGE_DESC_NUM          0x40
 505
 506 #define HCLGE_ALLOC_VALID_B     0
 507 struct hclge_vf_num_cmd {
 508         u8 alloc_valid;
 509         u8 rsv[23];
 510 };
 511
 512 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 513 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 514 #define HCLGE_RSS_HASH_KEY_NUM          16
 515 struct hclge_rss_config_cmd {
 516         u8 hash_config;
 517         u8 rsv[7];
 518         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 519 };
 520
 521 struct hclge_rss_input_tuple_cmd {
 522         u8 ipv4_tcp_en;
 523         u8 ipv4_udp_en;
 524         u8 ipv4_sctp_en;
 525         u8 ipv4_fragment_en;
 526         u8 ipv6_tcp_en;
 527         u8 ipv6_udp_en;
 528         u8 ipv6_sctp_en;
 529         u8 ipv6_fragment_en;
 530         u8 rsv[16];
 531 };
 532
 533 #define HCLGE_RSS_CFG_TBL_SIZE  16
 534
 535 struct hclge_rss_indirection_table_cmd {
 536         __le16 start_table_index;
 537         __le16 rss_set_bitmap;
 538         u8 rsv[4];
 539         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
 540 };
 541
 542 #define HCLGE_RSS_TC_OFFSET_S           0
 543 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
 544 #define HCLGE_RSS_TC_SIZE_S             12
 545 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 546 #define HCLGE_RSS_TC_VALID_B            15
 547 struct hclge_rss_tc_mode_cmd {
 548         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 549         u8 rsv[8];
 550 };
 551
 552 #define HCLGE_LINK_STATUS_UP_B  0
 553 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 554 struct hclge_link_status_cmd {
 555         u8 status;
 556         u8 rsv[23];
 557 };
 558
 559 struct hclge_promisc_param {
 560         u8 vf_id;
 561         u8 enable;
 562 };
 563
 564 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
 565 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
 566 #define HCLGE_PROMISC_EN_B      1
 567 #define HCLGE_PROMISC_EN_ALL    0x7
 568 #define HCLGE_PROMISC_EN_UC     0x1
 569 #define HCLGE_PROMISC_EN_MC     0x2
 570 #define HCLGE_PROMISC_EN_BC     0x4
 571 struct hclge_promisc_cfg_cmd {
 572         u8 flag;
 573         u8 vf_id;
 574         __le16 rsv0;
 575         u8 rsv1[20];
 576 };
 577
 578 enum hclge_promisc_type {
 579         HCLGE_UNICAST   = 1,
 580         HCLGE_MULTICAST = 2,
 581         HCLGE_BROADCAST = 3,
 582 };
 583
 584 #define HCLGE_MAC_TX_EN_B       6
 585 #define HCLGE_MAC_RX_EN_B       7
 586 #define HCLGE_MAC_PAD_TX_B      11
 587 #define HCLGE_MAC_PAD_RX_B      12
 588 #define HCLGE_MAC_1588_TX_B     13
 589 #define HCLGE_MAC_1588_RX_B     14
 590 #define HCLGE_MAC_APP_LP_B      15
 591 #define HCLGE_MAC_LINE_LP_B     16
 592 #define HCLGE_MAC_FCS_TX_B      17
 593 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 594 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 595 #define HCLGE_MAC_RX_FCS_B      20
 596 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 597 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 598
 599 struct hclge_config_mac_mode_cmd {
 600         __le32 txrx_pad_fcs_loop_en;
 601         u8 rsv[20];
 602 };
 603
 604 struct hclge_pf_rst_sync_cmd {
 605 #define HCLGE_PF_RST_ALL_VF_RDY_B       0
 606         u8 all_vf_ready;
 607         u8 rsv[23];
 608 };
 609
 610 #define HCLGE_CFG_SPEED_S               0
 611 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 612
 613 #define HCLGE_CFG_DUPLEX_B              7
 614 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 615
 616 struct hclge_config_mac_speed_dup_cmd {
 617         u8 speed_dup;
 618
 619 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 620         u8 mac_change_fec_en;
 621         u8 rsv[22];
 622 };
 623
 624 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
 625 #define HCLGE_TQP_ENABLE_B              0
 626
 627 #define HCLGE_MAC_CFG_AN_EN_B           0
 628 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 629 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 630 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 631 #define HCLGE_MAC_CFG_AN_RST_B          4
 632
 633 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 634
 635 struct hclge_config_auto_neg_cmd {
 636         __le32  cfg_an_cmd_flag;
 637         u8      rsv[20];
 638 };
 639
 640 struct hclge_sfp_info_cmd {
 641         __le32 speed;
 642         u8 query_type; /* 0: sfp speed, 1: active speed */
 643         u8 active_fec;
 644         u8 autoneg; /* autoneg state */
 645         u8 autoneg_ability; /* whether support autoneg */
 646         __le32 speed_ability; /* speed ability for current media */
 647         __le32 module_type;
 648         u8 rsv[8];
 649 };
 650
 651 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B     0
 652 #define HCLGE_MAC_CFG_FEC_MODE_S        1
 653 #define HCLGE_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
 654 #define HCLGE_MAC_CFG_FEC_SET_DEF_B     0
 655 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B     1
 656
 657 #define HCLGE_MAC_FEC_OFF               0
 658 #define HCLGE_MAC_FEC_BASER             1
 659 #define HCLGE_MAC_FEC_RS                2
 660 struct hclge_config_fec_cmd {
 661         u8 fec_mode;
 662         u8 default_config;
 663         u8 rsv[22];
 664 };
 665
 666 #define HCLGE_MAC_UPLINK_PORT           0x100
 667
 668 struct hclge_config_max_frm_size_cmd {
 669         __le16  max_frm_size;
 670         u8      min_frm_size;
 671         u8      rsv[21];
 672 };
 673
 674 enum hclge_mac_vlan_tbl_opcode {
 675         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 676         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 677         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 678         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 679 };
 680
 681 enum hclge_mac_vlan_add_resp_code {
 682         HCLGE_ADD_UC_OVERFLOW = 2,      /* ADD failed for UC overflow */
 683         HCLGE_ADD_MC_OVERFLOW,          /* ADD failed for MC overflow */
 684 };
 685
 686 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
 687 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
 688 #define HCLGE_MAC_EPORT_SW_EN_B         12
 689 #define HCLGE_MAC_EPORT_TYPE_B          11
 690 #define HCLGE_MAC_EPORT_VFID_S          3
 691 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 692 #define HCLGE_MAC_EPORT_PFID_S          0
 693 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 694 struct hclge_mac_vlan_tbl_entry_cmd {
 695         u8      flags;
 696         u8      resp_code;
 697         __le16  vlan_tag;
 698         __le32  mac_addr_hi32;
 699         __le16  mac_addr_lo16;
 700         __le16  rsv1;
 701         u8      entry_type;
 702         u8      mc_mac_en;
 703         __le16  egress_port;
 704         __le16  egress_queue;
 705         u8      rsv2[6];
 706 };
 707
 708 #define HCLGE_UMV_SPC_ALC_B     0
 709 struct hclge_umv_spc_alc_cmd {
 710         u8 allocate;
 711         u8 rsv1[3];
 712         __le32 space_size;
 713         u8 rsv2[16];
 714 };
 715
 716 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 717 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 718 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 719
 720 struct hclge_mac_mgr_tbl_entry_cmd {
 721         u8      flags;
 722         u8      resp_code;
 723         __le16  vlan_tag;
 724         u8      mac_addr[ETH_ALEN];
 725         __le16  rsv1;
 726         __le16  ethter_type;
 727         __le16  egress_port;
 728         __le16  egress_queue;
 729         u8      sw_port_id_aware;
 730         u8      rsv2;
 731         u8      i_port_bitmap;
 732         u8      i_port_direction;
 733         u8      rsv3[2];
 734 };
 735
 736 struct hclge_mac_vlan_add_cmd {
 737         __le16  flags;
 738         __le16  mac_addr_hi16;
 739         __le32  mac_addr_lo32;
 740         __le32  mac_addr_msk_hi32;
 741         __le16  mac_addr_msk_lo16;
 742         __le16  vlan_tag;
 743         __le16  ingress_port;
 744         __le16  egress_port;
 745         u8      rsv[4];
 746 };
 747
 748 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
 749 struct hclge_mac_vlan_remove_cmd {
 750         __le16  flags;
 751         __le16  mac_addr_hi16;
 752         __le32  mac_addr_lo32;
 753         __le32  mac_addr_msk_hi32;
 754         __le16  mac_addr_msk_lo16;
 755         __le16  vlan_tag;
 756         __le16  ingress_port;
 757         __le16  egress_port;
 758         u8      rsv[4];
 759 };
 760
 761 struct hclge_vlan_filter_ctrl_cmd {
 762         u8 vlan_type;
 763         u8 vlan_fe;
 764         u8 rsv1[2];
 765         u8 vf_id;
 766         u8 rsv2[19];
 767 };
 768
 769 #define HCLGE_VLAN_ID_OFFSET_STEP       160
 770 #define HCLGE_VLAN_BYTE_SIZE            8
 771 #define HCLGE_VLAN_OFFSET_BITMAP \
 772         (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
 773
 774 struct hclge_vlan_filter_pf_cfg_cmd {
 775         u8 vlan_offset;
 776         u8 vlan_cfg;
 777         u8 rsv[2];
 778         u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
 779 };
 780
 781 #define HCLGE_MAX_VF_BYTES  16
 782
 783 struct hclge_vlan_filter_vf_cfg_cmd {
 784         __le16 vlan_id;
 785         u8  resp_code;
 786         u8  rsv;
 787         u8  vlan_cfg;
 788         u8  rsv1[3];
 789         u8  vf_bitmap[HCLGE_MAX_VF_BYTES];
 790 };
 791
 792 #define HCLGE_SWITCH_ANTI_SPOOF_B       0U
 793 #define HCLGE_SWITCH_ALW_LPBK_B         1U
 794 #define HCLGE_SWITCH_ALW_LCL_LPBK_B     2U
 795 #define HCLGE_SWITCH_ALW_DST_OVRD_B     3U
 796 #define HCLGE_SWITCH_NO_MASK            0x0
 797 #define HCLGE_SWITCH_ANTI_SPOOF_MASK    0xFE
 798 #define HCLGE_SWITCH_ALW_LPBK_MASK      0xFD
 799 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK  0xFB
 800 #define HCLGE_SWITCH_LW_DST_OVRD_MASK   0xF7
 801
 802 struct hclge_mac_vlan_switch_cmd {
 803         u8 roce_sel;
 804         u8 rsv1[3];
 805         __le32 func_id;
 806         u8 switch_param;
 807         u8 rsv2[3];
 808         u8 param_mask;
 809         u8 rsv3[11];
 810 };
 811
 812 enum hclge_mac_vlan_cfg_sel {
 813         HCLGE_MAC_VLAN_NIC_SEL = 0,
 814         HCLGE_MAC_VLAN_ROCE_SEL,
 815 };
 816
 817 #define HCLGE_ACCEPT_TAG1_B             0
 818 #define HCLGE_ACCEPT_UNTAG1_B           1
 819 #define HCLGE_PORT_INS_TAG1_EN_B        2
 820 #define HCLGE_PORT_INS_TAG2_EN_B        3
 821 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 822 #define HCLGE_ACCEPT_TAG2_B             5
 823 #define HCLGE_ACCEPT_UNTAG2_B           6
 824 #define HCLGE_VF_NUM_PER_BYTE           8
 825
 826 struct hclge_vport_vtag_tx_cfg_cmd {
 827         u8 vport_vlan_cfg;
 828         u8 vf_offset;
 829         u8 rsv1[2];
 830         __le16 def_vlan_tag1;
 831         __le16 def_vlan_tag2;
 832         u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 833         u8 rsv2[8];
 834 };
 835
 836 #define HCLGE_REM_TAG1_EN_B             0
 837 #define HCLGE_REM_TAG2_EN_B             1
 838 #define HCLGE_SHOW_TAG1_EN_B            2
 839 #define HCLGE_SHOW_TAG2_EN_B            3
 840 struct hclge_vport_vtag_rx_cfg_cmd {
 841         u8 vport_vlan_cfg;
 842         u8 vf_offset;
 843         u8 rsv1[6];
 844         u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 845         u8 rsv2[8];
 846 };
 847
 848 struct hclge_tx_vlan_type_cfg_cmd {
 849         __le16 ot_vlan_type;
 850         __le16 in_vlan_type;
 851         u8 rsv[20];
 852 };
 853
 854 struct hclge_rx_vlan_type_cfg_cmd {
 855         __le16 ot_fst_vlan_type;
 856         __le16 ot_sec_vlan_type;
 857         __le16 in_fst_vlan_type;
 858         __le16 in_sec_vlan_type;
 859         u8 rsv[16];
 860 };
 861
 862 struct hclge_cfg_com_tqp_queue_cmd {
 863         __le16 tqp_id;
 864         __le16 stream_id;
 865         u8 enable;
 866         u8 rsv[19];
 867 };
 868
 869 struct hclge_cfg_tx_queue_pointer_cmd {
 870         __le16 tqp_id;
 871         __le16 tx_tail;
 872         __le16 tx_head;
 873         __le16 fbd_num;
 874         __le16 ring_offset;
 875         u8 rsv[14];
 876 };
 877
 878 #pragma pack(1)
 879 struct hclge_mac_ethertype_idx_rd_cmd {
 880         u8      flags;
 881         u8      resp_code;
 882         __le16  vlan_tag;
 883         u8      mac_addr[ETH_ALEN];
 884         __le16  index;
 885         __le16  ethter_type;
 886         __le16  egress_port;
 887         __le16  egress_queue;
 888         __le16  rev0;
 889         u8      i_port_bitmap;
 890         u8      i_port_direction;
 891         u8      rev1[2];
 892 };
 893
 894 #pragma pack()
 895
 896 #define HCLGE_TSO_MSS_MIN_S     0
 897 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 898
 899 #define HCLGE_TSO_MSS_MAX_S     16
 900 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 901
 902 struct hclge_cfg_tso_status_cmd {
 903         __le16 tso_mss_min;
 904         __le16 tso_mss_max;
 905         u8 rsv[20];
 906 };
 907
 908 #define HCLGE_GRO_EN_B          0
 909 struct hclge_cfg_gro_status_cmd {
 910         __le16 gro_en;
 911         u8 rsv[22];
 912 };
 913
 914 #define HCLGE_TSO_MSS_MIN       256
 915 #define HCLGE_TSO_MSS_MAX       9668
 916
 917 #define HCLGE_TQP_RESET_B       0
 918 struct hclge_reset_tqp_queue_cmd {
 919         __le16 tqp_id;
 920         u8 reset_req;
 921         u8 ready_to_reset;
 922         u8 rsv[20];
 923 };
 924
 925 #define HCLGE_CFG_RESET_MAC_B           3
 926 #define HCLGE_CFG_RESET_FUNC_B          7
 927 struct hclge_reset_cmd {
 928         u8 mac_func_reset;
 929         u8 fun_reset_vfid;
 930         u8 rsv[22];
 931 };
 932
 933 #define HCLGE_PF_RESET_DONE_BIT         BIT(0)
 934
 935 struct hclge_pf_rst_done_cmd {
 936         u8 pf_rst_done;
 937         u8 rsv[23];
 938 };
 939
 940 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 941 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
 942 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
 943 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
 944 struct hclge_serdes_lb_cmd {
 945         u8 mask;
 946         u8 enable;
 947         u8 result;
 948         u8 rsv[21];
 949 };
 950
 951 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
 952 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
 953 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
 954 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
 955 #define HCLGE_NON_DCB_ADDITIONAL_BUF    0x1400  /* 5120 byte */
 956
 957 #define HCLGE_TYPE_CRQ                  0
 958 #define HCLGE_TYPE_CSQ                  1
 959 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
 960 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
 961 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
 962 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
 963 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
 964 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
 965 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
 966 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
 967 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
 968 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
 969
 970 /* this bit indicates that the driver is ready for hardware reset */
 971 #define HCLGE_NIC_SW_RST_RDY_B          16
 972 #define HCLGE_NIC_SW_RST_RDY            BIT(HCLGE_NIC_SW_RST_RDY_B)
 973
 974 #define HCLGE_NIC_CMQ_DESC_NUM          1024
 975 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
 976
 977 #define HCLGE_LED_LOCATE_STATE_S        0
 978 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
 979
 980 struct hclge_set_led_state_cmd {
 981         u8 rsv1[3];
 982         u8 locate_led_config;
 983         u8 rsv2[20];
 984 };
 985
 986 struct hclge_get_fd_mode_cmd {
 987         u8 mode;
 988         u8 enable;
 989         u8 rsv[22];
 990 };
 991
 992 struct hclge_get_fd_allocation_cmd {
 993         __le32 stage1_entry_num;
 994         __le32 stage2_entry_num;
 995         __le16 stage1_counter_num;
 996         __le16 stage2_counter_num;
 997         u8 rsv[12];
 998 };
 999
1000 struct hclge_set_fd_key_config_cmd {
1001         u8 stage;
1002         u8 key_select;
1003         u8 inner_sipv6_word_en;
1004         u8 inner_dipv6_word_en;
1005         u8 outer_sipv6_word_en;
1006         u8 outer_dipv6_word_en;
1007         u8 rsv1[2];
1008         __le32 tuple_mask;
1009         __le32 meta_data_mask;
1010         u8 rsv2[8];
1011 };
1012
1013 #define HCLGE_FD_EPORT_SW_EN_B          0
1014 struct hclge_fd_tcam_config_1_cmd {
1015         u8 stage;
1016         u8 xy_sel;
1017         u8 port_info;
1018         u8 rsv1[1];
1019         __le32 index;
1020         u8 entry_vld;
1021         u8 rsv2[7];
1022         u8 tcam_data[8];
1023 };
1024
1025 struct hclge_fd_tcam_config_2_cmd {
1026         u8 tcam_data[24];
1027 };
1028
1029 struct hclge_fd_tcam_config_3_cmd {
1030         u8 tcam_data[20];
1031         u8 rsv[4];
1032 };
1033
1034 #define HCLGE_FD_AD_DROP_B              0
1035 #define HCLGE_FD_AD_DIRECT_QID_B        1
1036 #define HCLGE_FD_AD_QID_S               2
1037 #define HCLGE_FD_AD_QID_M               GENMASK(12, 2)
1038 #define HCLGE_FD_AD_USE_COUNTER_B       12
1039 #define HCLGE_FD_AD_COUNTER_NUM_S       13
1040 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
1041 #define HCLGE_FD_AD_NXT_STEP_B          20
1042 #define HCLGE_FD_AD_NXT_KEY_S           21
1043 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(26, 21)
1044 #define HCLGE_FD_AD_WR_RULE_ID_B        0
1045 #define HCLGE_FD_AD_RULE_ID_S           1
1046 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(13, 1)
1047
1048 struct hclge_fd_ad_config_cmd {
1049         u8 stage;
1050         u8 rsv1[3];
1051         __le32 index;
1052         __le64 ad_data;
1053         u8 rsv2[8];
1054 };
1055
1056 struct hclge_get_m7_bd_cmd {
1057         __le32 bd_num;
1058         u8 rsv[20];
1059 };
1060
1061 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1062         __le16 over_8bd_no_fe_qid;
1063         __le16 over_8bd_no_fe_vf_id;
1064         __le16 tso_mss_cmp_min_err_qid;
1065         __le16 tso_mss_cmp_min_err_vf_id;
1066         __le16 tso_mss_cmp_max_err_qid;
1067         __le16 tso_mss_cmp_max_err_vf_id;
1068         __le16 tx_rd_fbd_poison_qid;
1069         __le16 tx_rd_fbd_poison_vf_id;
1070         __le16 rx_rd_fbd_poison_qid;
1071         __le16 rx_rd_fbd_poison_vf_id;
1072         u8 rsv[4];
1073 };
1074
1075 #define HCLGE_LINK_EVENT_REPORT_EN_B    0
1076 #define HCLGE_NCSI_ERROR_REPORT_EN_B    1
1077 struct hclge_firmware_compat_cmd {
1078         __le32 compat;
1079         u8 rsv[20];
1080 };
1081
1082 int hclge_cmd_init(struct hclge_dev *hdev);
1083 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1084 {
1085         writel(value, base + reg);
1086 }
1087
1088 #define hclge_write_dev(a, reg, value) \
1089         hclge_write_reg((a)->io_base, (reg), (value))
1090 #define hclge_read_dev(a, reg) \
1091         hclge_read_reg((a)->io_base, (reg))
1092
1093 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1094 {
1095         u8 __iomem *reg_addr = READ_ONCE(base);
1096
1097         return readl(reg_addr + reg);
1098 }
1099
1100 #define HCLGE_SEND_SYNC(flag) \
1101         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1102
1103 struct hclge_hw;
1104 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1105 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1106                                 enum hclge_opcode_type opcode, bool is_read);
1107 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1108
1109 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1110                                            struct hclge_desc *desc);
1111 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1112                                           struct hclge_desc *desc);
1113
1114 void hclge_cmd_uninit(struct hclge_dev *hdev);
1115 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1116 #endif