1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
6 #include <linux/types.h>
8 #include <linux/etherdevice.h>
11 #define HCLGE_CMDQ_TX_TIMEOUT 30000
12 #define HCLGE_DESC_DATA_LEN 6
18 #define HCLGE_CMDQ_RX_INVLD_B 0
19 #define HCLGE_CMDQ_RX_OUTVLD_B 1
24 __le32 data[HCLGE_DESC_DATA_LEN];
27 struct hclge_cmq_ring {
28 dma_addr_t desc_dma_addr;
29 struct hclge_desc *desc;
30 struct hclge_dev *dev;
38 u8 ring_type; /* cmq ring type */
39 spinlock_t lock; /* Command queue lock */
42 enum hclge_cmd_return_status {
43 HCLGE_CMD_EXEC_SUCCESS = 0,
44 HCLGE_CMD_NO_AUTH = 1,
45 HCLGE_CMD_NOT_SUPPORTED = 2,
46 HCLGE_CMD_QUEUE_FULL = 3,
47 HCLGE_CMD_NEXT_ERR = 4,
48 HCLGE_CMD_UNEXE_ERR = 5,
49 HCLGE_CMD_PARA_ERR = 6,
50 HCLGE_CMD_RESULT_ERR = 7,
51 HCLGE_CMD_TIMEOUT = 8,
52 HCLGE_CMD_HILINK_ERR = 9,
53 HCLGE_CMD_QUEUE_ILLEGAL = 10,
54 HCLGE_CMD_INVALID = 11,
57 enum hclge_cmd_status {
58 HCLGE_STATUS_SUCCESS = 0,
59 HCLGE_ERR_CSQ_FULL = -1,
60 HCLGE_ERR_CSQ_TIMEOUT = -2,
61 HCLGE_ERR_CSQ_ERROR = -3,
64 struct hclge_misc_vector {
67 char name[HNAE3_INT_NAME_LEN];
71 struct hclge_cmq_ring csq;
72 struct hclge_cmq_ring crq;
74 enum hclge_cmd_status last_status;
77 #define HCLGE_CMD_FLAG_IN BIT(0)
78 #define HCLGE_CMD_FLAG_OUT BIT(1)
79 #define HCLGE_CMD_FLAG_NEXT BIT(2)
80 #define HCLGE_CMD_FLAG_WR BIT(3)
81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
84 enum hclge_opcode_type {
85 /* Generic commands */
86 HCLGE_OPC_QUERY_FW_VER = 0x0001,
87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
88 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
92 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
93 HCLGE_OPC_PF_RST_DONE = 0x0026,
94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
96 HCLGE_OPC_STATS_64_BIT = 0x0030,
97 HCLGE_OPC_STATS_32_BIT = 0x0031,
98 HCLGE_OPC_STATS_MAC = 0x0032,
99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
100 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
102 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
105 HCLGE_OPC_DFX_BD_NUM = 0x0043,
106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
112 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
113 HCLGE_OPC_DFX_RTC_REG = 0x004B,
114 HCLGE_OPC_DFX_PPP_REG = 0x004C,
115 HCLGE_OPC_DFX_RCB_REG = 0x004D,
116 HCLGE_OPC_DFX_TQP_REG = 0x004E,
117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
130 HCLGE_OPC_COMMON_LOOPBACK = 0x0315,
131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
134 HCLGE_OPC_PTP_INT_EN = 0x0501,
135 HCLGE_OPC_PTP_MODE_CFG = 0x0507,
137 /* PFC/Pause commands */
138 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
139 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
140 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
141 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
142 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
143 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
144 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
145 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
146 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
147 HCLGE_OPC_QOS_MAP = 0x070A,
149 /* ETS/scheduler commands */
150 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
151 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
152 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
153 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
154 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
155 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
156 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
157 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
158 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
159 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
160 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
161 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
162 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
163 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
164 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
165 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
166 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
167 HCLGE_OPC_TM_NODES = 0x0816,
168 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
169 HCLGE_OPC_QSET_DFX_STS = 0x0844,
170 HCLGE_OPC_PRI_DFX_STS = 0x0845,
171 HCLGE_OPC_PG_DFX_STS = 0x0846,
172 HCLGE_OPC_PORT_DFX_STS = 0x0847,
173 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
174 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
175 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
176 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
177 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
179 /* Packet buffer allocate commands */
180 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
181 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
182 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
183 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
184 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
185 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
187 /* TQP management command */
188 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
191 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
192 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
193 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
194 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
195 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
196 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
197 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
198 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
199 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
200 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
201 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
204 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
207 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
208 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
211 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
212 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
213 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
214 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
216 /* Promisuous mode command */
217 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
219 /* Vlan offload commands */
220 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
221 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
223 /* Interrupts commands */
224 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
225 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
228 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
229 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
230 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
231 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
232 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
233 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
234 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
236 /* MAC VLAN commands */
237 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
240 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
241 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
242 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
243 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103,
245 /* Flow Director commands */
246 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
247 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
248 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
249 HCLGE_OPC_FD_TCAM_OP = 0x1203,
250 HCLGE_OPC_FD_AD_OP = 0x1204,
251 HCLGE_OPC_FD_CNT_OP = 0x1205,
252 HCLGE_OPC_FD_USER_DEF_OP = 0x1207,
255 HCLGE_OPC_MDIO_CONFIG = 0x1900,
258 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
259 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
260 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
261 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
262 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
263 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
264 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
265 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
267 /* Mailbox command */
268 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
271 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
273 /* NCL config command */
274 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
276 /* IMP stats command */
277 HCLGE_OPC_IMP_STATS_BD = 0x7012,
278 HCLGE_OPC_IMP_STATS_INFO = 0x7013,
279 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A,
282 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
283 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
284 HCLGE_OPC_GET_SFP_INFO = 0x7104,
286 /* Error INT commands */
287 HCLGE_MAC_COMMON_INT_EN = 0x030E,
288 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
289 HCLGE_SSU_ECC_INT_CMD = 0x0989,
290 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
291 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
292 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
293 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
294 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
295 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
296 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
297 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
298 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
299 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
300 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
301 HCLGE_QUERY_ALL_ERR_BD_NUM = 0x1516,
302 HCLGE_QUERY_ALL_ERR_INFO = 0x1517,
303 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
304 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
305 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
306 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
307 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
308 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
309 HCLGE_IGU_COMMON_INT_EN = 0x1806,
310 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
311 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
312 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
313 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
314 HCLGE_NCSI_INT_EN = 0x2401,
317 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025,
318 HCLGE_OPC_PHY_REG = 0x7026,
321 #define HCLGE_TQP_REG_OFFSET 0x80000
322 #define HCLGE_TQP_REG_SIZE 0x200
324 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024
325 #define HCLGE_TQP_EXT_REG_OFFSET 0x100
327 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
328 #define HCLGE_RCB_INIT_FLAG_EN_B 0
329 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
330 struct hclge_config_rcb_init_cmd {
331 __le16 rcb_init_flag;
335 struct hclge_tqp_map_cmd {
336 __le16 tqp_id; /* Absolute tqp id for in this pf */
337 u8 tqp_vf; /* VF id */
338 #define HCLGE_TQP_MAP_TYPE_PF 0
339 #define HCLGE_TQP_MAP_TYPE_VF 1
340 #define HCLGE_TQP_MAP_TYPE_B 0
341 #define HCLGE_TQP_MAP_EN_B 1
342 u8 tqp_flag; /* Indicate it's pf or vf tqp */
343 __le16 tqp_vid; /* Virtual id in this pf/vf */
347 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
349 enum hclge_int_type {
355 struct hclge_ctrl_vector_chain_cmd {
356 #define HCLGE_VECTOR_ID_L_S 0
357 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)
360 #define HCLGE_INT_TYPE_S 0
361 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
362 #define HCLGE_TQP_ID_S 2
363 #define HCLGE_TQP_ID_M GENMASK(12, 2)
364 #define HCLGE_INT_GL_IDX_S 13
365 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
366 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
368 #define HCLGE_VECTOR_ID_H_S 8
369 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8)
373 #define HCLGE_MAX_TC_NUM 8
374 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
375 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
376 struct hclge_tx_buff_alloc_cmd {
377 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
381 struct hclge_rx_priv_buff_cmd {
382 __le16 buf_num[HCLGE_MAX_TC_NUM];
387 enum HCLGE_CAP_BITS {
390 HCLGE_CAP_FD_FORWARD_TC_B,
393 HCLGE_CAP_HW_TX_CSUM_B,
396 HCLGE_CAP_TQP_TXRX_INDEP_B,
399 HCLGE_CAP_UDP_TUNNEL_CSUM_B,
400 HCLGE_CAP_RAS_IMP_B = 12,
401 HCLGE_CAP_FEC_B = 13,
402 HCLGE_CAP_PAUSE_B = 14,
403 HCLGE_CAP_RXD_ADV_LAYOUT_B = 15,
404 HCLGE_CAP_PORT_VLAN_BYPASS_B = 17,
407 enum HCLGE_API_CAP_BITS {
408 HCLGE_API_CAP_FLEX_RSS_TBL_B,
411 #define HCLGE_QUERY_CAP_LENGTH 3
412 struct hclge_query_version_cmd {
416 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
419 #define HCLGE_RX_PRIV_EN_B 15
420 #define HCLGE_TC_NUM_ONE_DESC 4
421 struct hclge_priv_wl {
426 struct hclge_rx_priv_wl_buf {
427 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
430 struct hclge_rx_com_thrd {
431 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
434 struct hclge_rx_com_wl {
435 struct hclge_priv_wl com_wl;
438 struct hclge_waterline {
443 struct hclge_tc_thrd {
448 struct hclge_priv_buf {
449 struct hclge_waterline wl; /* Waterline for low and high*/
450 u32 buf_size; /* TC private buffer size */
452 u32 enable; /* Enable TC private buffer or not */
455 struct hclge_shared_buf {
456 struct hclge_waterline self;
457 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
461 struct hclge_pkt_buf_alloc {
462 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
463 struct hclge_shared_buf s_buf;
466 #define HCLGE_RX_COM_WL_EN_B 15
467 struct hclge_rx_com_wl_buf_cmd {
473 #define HCLGE_RX_PKT_EN_B 15
474 struct hclge_rx_pkt_buf_cmd {
480 #define HCLGE_PF_STATE_DONE_B 0
481 #define HCLGE_PF_STATE_MAIN_B 1
482 #define HCLGE_PF_STATE_BOND_B 2
483 #define HCLGE_PF_STATE_MAC_N_B 6
484 #define HCLGE_PF_MAC_NUM_MASK 0x3
485 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
486 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
487 #define HCLGE_VF_RST_STATUS_CMD 4
489 struct hclge_func_status_cmd {
490 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
500 struct hclge_pf_res_cmd {
503 __le16 msixcap_localid_ba_nic;
504 __le16 msixcap_localid_number_nic;
505 __le16 pf_intr_vector_number_roce;
506 __le16 pf_own_fun_number;
513 #define HCLGE_CFG_OFFSET_S 0
514 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
515 #define HCLGE_CFG_RD_LEN_S 24
516 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
517 #define HCLGE_CFG_RD_LEN_BYTES 16
518 #define HCLGE_CFG_RD_LEN_UNIT 4
520 #define HCLGE_CFG_TC_NUM_S 8
521 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
522 #define HCLGE_CFG_TQP_DESC_N_S 16
523 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
524 #define HCLGE_CFG_PHY_ADDR_S 0
525 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
526 #define HCLGE_CFG_MEDIA_TP_S 8
527 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
528 #define HCLGE_CFG_RX_BUF_LEN_S 16
529 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
530 #define HCLGE_CFG_MAC_ADDR_H_S 0
531 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
532 #define HCLGE_CFG_DEFAULT_SPEED_S 16
533 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
534 #define HCLGE_CFG_RSS_SIZE_S 24
535 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
536 #define HCLGE_CFG_SPEED_ABILITY_S 0
537 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
538 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10
539 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)
540 #define HCLGE_CFG_VLAN_FLTR_CAP_S 8
541 #define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8)
542 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
543 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
544 #define HCLGE_CFG_PF_RSS_SIZE_S 0
545 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)
546 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_S 4
547 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_M GENMASK(15, 4)
549 #define HCLGE_CFG_CMD_CNT 4
551 struct hclge_cfg_param_cmd {
554 __le32 param[HCLGE_CFG_CMD_CNT];
557 #define HCLGE_MAC_MODE 0x0
558 #define HCLGE_DESC_NUM 0x40
560 #define HCLGE_ALLOC_VALID_B 0
561 struct hclge_vf_num_cmd {
566 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
567 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
568 #define HCLGE_RSS_HASH_KEY_NUM 16
569 struct hclge_rss_config_cmd {
572 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
575 struct hclge_rss_input_tuple_cmd {
587 #define HCLGE_RSS_CFG_TBL_SIZE 16
588 #define HCLGE_RSS_CFG_TBL_SIZE_H 4
589 #define HCLGE_RSS_CFG_TBL_BW_H 2U
590 #define HCLGE_RSS_CFG_TBL_BW_L 8U
592 struct hclge_rss_indirection_table_cmd {
593 __le16 start_table_index;
594 __le16 rss_set_bitmap;
595 u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H];
596 u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE];
599 #define HCLGE_RSS_TC_OFFSET_S 0
600 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0)
601 #define HCLGE_RSS_TC_SIZE_MSB_B 11
602 #define HCLGE_RSS_TC_SIZE_S 12
603 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
604 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3
605 #define HCLGE_RSS_TC_VALID_B 15
606 struct hclge_rss_tc_mode_cmd {
607 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
611 #define HCLGE_LINK_STATUS_UP_B 0
612 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
613 struct hclge_link_status_cmd {
618 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */
619 #define HCLGE_PROMISC_EN_UC 1
620 #define HCLGE_PROMISC_EN_MC 2
621 #define HCLGE_PROMISC_EN_BC 3
622 #define HCLGE_PROMISC_TX_EN 4
623 #define HCLGE_PROMISC_RX_EN 5
625 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */
626 #define HCLGE_PROMISC_UC_RX_EN 2
627 #define HCLGE_PROMISC_MC_RX_EN 3
628 #define HCLGE_PROMISC_BC_RX_EN 4
629 #define HCLGE_PROMISC_UC_TX_EN 5
630 #define HCLGE_PROMISC_MC_TX_EN 6
631 #define HCLGE_PROMISC_BC_TX_EN 7
633 struct hclge_promisc_cfg_cmd {
640 enum hclge_promisc_type {
646 #define HCLGE_MAC_TX_EN_B 6
647 #define HCLGE_MAC_RX_EN_B 7
648 #define HCLGE_MAC_PAD_TX_B 11
649 #define HCLGE_MAC_PAD_RX_B 12
650 #define HCLGE_MAC_1588_TX_B 13
651 #define HCLGE_MAC_1588_RX_B 14
652 #define HCLGE_MAC_APP_LP_B 15
653 #define HCLGE_MAC_LINE_LP_B 16
654 #define HCLGE_MAC_FCS_TX_B 17
655 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
656 #define HCLGE_MAC_RX_FCS_STRIP_B 19
657 #define HCLGE_MAC_RX_FCS_B 20
658 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
659 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
661 struct hclge_config_mac_mode_cmd {
662 __le32 txrx_pad_fcs_loop_en;
666 struct hclge_pf_rst_sync_cmd {
667 #define HCLGE_PF_RST_ALL_VF_RDY_B 0
672 #define HCLGE_CFG_SPEED_S 0
673 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
675 #define HCLGE_CFG_DUPLEX_B 7
676 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
678 struct hclge_config_mac_speed_dup_cmd {
681 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
682 u8 mac_change_fec_en;
686 #define HCLGE_TQP_ENABLE_B 0
688 #define HCLGE_MAC_CFG_AN_EN_B 0
689 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
690 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
691 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
692 #define HCLGE_MAC_CFG_AN_RST_B 4
694 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
696 struct hclge_config_auto_neg_cmd {
697 __le32 cfg_an_cmd_flag;
701 struct hclge_sfp_info_cmd {
703 u8 query_type; /* 0: sfp speed, 1: active speed */
705 u8 autoneg; /* autoneg state */
706 u8 autoneg_ability; /* whether support autoneg */
707 __le32 speed_ability; /* speed ability for current media */
712 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
713 #define HCLGE_MAC_CFG_FEC_MODE_S 1
714 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
715 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
716 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
718 #define HCLGE_MAC_FEC_OFF 0
719 #define HCLGE_MAC_FEC_BASER 1
720 #define HCLGE_MAC_FEC_RS 2
721 struct hclge_config_fec_cmd {
727 #define HCLGE_MAC_UPLINK_PORT 0x100
729 struct hclge_config_max_frm_size_cmd {
735 enum hclge_mac_vlan_tbl_opcode {
736 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
737 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
738 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
739 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
742 enum hclge_mac_vlan_add_resp_code {
743 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
744 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
747 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
748 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
749 #define HCLGE_MAC_EPORT_SW_EN_B 12
750 #define HCLGE_MAC_EPORT_TYPE_B 11
751 #define HCLGE_MAC_EPORT_VFID_S 3
752 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
753 #define HCLGE_MAC_EPORT_PFID_S 0
754 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
755 struct hclge_mac_vlan_tbl_entry_cmd {
759 __le32 mac_addr_hi32;
760 __le16 mac_addr_lo16;
769 #define HCLGE_UMV_SPC_ALC_B 0
770 struct hclge_umv_spc_alc_cmd {
777 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
778 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
779 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
781 struct hclge_mac_mgr_tbl_entry_cmd {
785 u8 mac_addr[ETH_ALEN];
797 struct hclge_vlan_filter_ctrl_cmd {
805 #define HCLGE_VLAN_ID_OFFSET_STEP 160
806 #define HCLGE_VLAN_BYTE_SIZE 8
807 #define HCLGE_VLAN_OFFSET_BITMAP \
808 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
810 struct hclge_vlan_filter_pf_cfg_cmd {
814 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
817 #define HCLGE_MAX_VF_BYTES 16
819 struct hclge_vlan_filter_vf_cfg_cmd {
825 u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
828 #define HCLGE_INGRESS_BYPASS_B 0
829 struct hclge_port_vlan_filter_bypass_cmd {
836 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
837 #define HCLGE_SWITCH_ALW_LPBK_B 1U
838 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
839 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
840 #define HCLGE_SWITCH_NO_MASK 0x0
841 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
842 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
843 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
844 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
846 struct hclge_mac_vlan_switch_cmd {
856 enum hclge_mac_vlan_cfg_sel {
857 HCLGE_MAC_VLAN_NIC_SEL = 0,
858 HCLGE_MAC_VLAN_ROCE_SEL,
861 #define HCLGE_ACCEPT_TAG1_B 0
862 #define HCLGE_ACCEPT_UNTAG1_B 1
863 #define HCLGE_PORT_INS_TAG1_EN_B 2
864 #define HCLGE_PORT_INS_TAG2_EN_B 3
865 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
866 #define HCLGE_ACCEPT_TAG2_B 5
867 #define HCLGE_ACCEPT_UNTAG2_B 6
868 #define HCLGE_TAG_SHIFT_MODE_EN_B 7
869 #define HCLGE_VF_NUM_PER_BYTE 8
871 struct hclge_vport_vtag_tx_cfg_cmd {
875 __le16 def_vlan_tag1;
876 __le16 def_vlan_tag2;
877 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
881 #define HCLGE_REM_TAG1_EN_B 0
882 #define HCLGE_REM_TAG2_EN_B 1
883 #define HCLGE_SHOW_TAG1_EN_B 2
884 #define HCLGE_SHOW_TAG2_EN_B 3
885 #define HCLGE_DISCARD_TAG1_EN_B 5
886 #define HCLGE_DISCARD_TAG2_EN_B 6
887 struct hclge_vport_vtag_rx_cfg_cmd {
891 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
895 struct hclge_tx_vlan_type_cfg_cmd {
901 struct hclge_rx_vlan_type_cfg_cmd {
902 __le16 ot_fst_vlan_type;
903 __le16 ot_sec_vlan_type;
904 __le16 in_fst_vlan_type;
905 __le16 in_sec_vlan_type;
909 struct hclge_cfg_com_tqp_queue_cmd {
916 struct hclge_cfg_tx_queue_pointer_cmd {
926 struct hclge_mac_ethertype_idx_rd_cmd {
930 u8 mac_addr[ETH_ALEN];
943 #define HCLGE_TSO_MSS_MIN_S 0
944 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
946 #define HCLGE_TSO_MSS_MAX_S 16
947 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
949 struct hclge_cfg_tso_status_cmd {
955 #define HCLGE_GRO_EN_B 0
956 struct hclge_cfg_gro_status_cmd {
961 #define HCLGE_TSO_MSS_MIN 256
962 #define HCLGE_TSO_MSS_MAX 9668
964 #define HCLGE_TQP_RESET_B 0
965 struct hclge_reset_tqp_queue_cmd {
972 #define HCLGE_CFG_RESET_MAC_B 3
973 #define HCLGE_CFG_RESET_FUNC_B 7
974 #define HCLGE_CFG_RESET_RCB_B 1
975 struct hclge_reset_cmd {
980 __le16 fun_reset_rcb_vqid_start;
981 __le16 fun_reset_rcb_vqid_num;
982 u8 fun_reset_rcb_return_status;
986 #define HCLGE_PF_RESET_DONE_BIT BIT(0)
988 struct hclge_pf_rst_done_cmd {
993 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
994 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
995 #define HCLGE_CMD_GE_PHY_INNER_LOOP_B BIT(3)
996 #define HCLGE_CMD_COMMON_LB_DONE_B BIT(0)
997 #define HCLGE_CMD_COMMON_LB_SUCCESS_B BIT(1)
998 struct hclge_common_lb_cmd {
1005 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
1006 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
1007 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
1008 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
1009 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
1011 #define HCLGE_TYPE_CRQ 0
1012 #define HCLGE_TYPE_CSQ 1
1013 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
1014 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
1015 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
1016 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
1017 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
1018 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
1019 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
1020 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
1021 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
1022 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
1024 /* this bit indicates that the driver is ready for hardware reset */
1025 #define HCLGE_NIC_SW_RST_RDY_B 16
1026 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
1028 #define HCLGE_NIC_CMQ_DESC_NUM 1024
1029 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
1031 #define HCLGE_LED_LOCATE_STATE_S 0
1032 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
1034 struct hclge_set_led_state_cmd {
1036 u8 locate_led_config;
1040 struct hclge_get_fd_mode_cmd {
1046 struct hclge_get_fd_allocation_cmd {
1047 __le32 stage1_entry_num;
1048 __le32 stage2_entry_num;
1049 __le16 stage1_counter_num;
1050 __le16 stage2_counter_num;
1054 struct hclge_set_fd_key_config_cmd {
1057 u8 inner_sipv6_word_en;
1058 u8 inner_dipv6_word_en;
1059 u8 outer_sipv6_word_en;
1060 u8 outer_dipv6_word_en;
1063 __le32 meta_data_mask;
1067 #define HCLGE_FD_EPORT_SW_EN_B 0
1068 struct hclge_fd_tcam_config_1_cmd {
1079 struct hclge_fd_tcam_config_2_cmd {
1083 struct hclge_fd_tcam_config_3_cmd {
1088 #define HCLGE_FD_AD_DROP_B 0
1089 #define HCLGE_FD_AD_DIRECT_QID_B 1
1090 #define HCLGE_FD_AD_QID_S 2
1091 #define HCLGE_FD_AD_QID_M GENMASK(11, 2)
1092 #define HCLGE_FD_AD_USE_COUNTER_B 12
1093 #define HCLGE_FD_AD_COUNTER_NUM_S 13
1094 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
1095 #define HCLGE_FD_AD_NXT_STEP_B 20
1096 #define HCLGE_FD_AD_NXT_KEY_S 21
1097 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)
1098 #define HCLGE_FD_AD_WR_RULE_ID_B 0
1099 #define HCLGE_FD_AD_RULE_ID_S 1
1100 #define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)
1101 #define HCLGE_FD_AD_TC_OVRD_B 16
1102 #define HCLGE_FD_AD_TC_SIZE_S 17
1103 #define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17)
1105 struct hclge_fd_ad_config_cmd {
1113 struct hclge_fd_ad_cnt_read_cmd {
1121 #define HCLGE_FD_USER_DEF_OFT_S 0
1122 #define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0)
1123 #define HCLGE_FD_USER_DEF_EN_B 15
1124 struct hclge_fd_user_def_cfg_cmd {
1134 struct hclge_get_imp_bd_cmd {
1139 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1140 __le16 over_8bd_no_fe_qid;
1141 __le16 over_8bd_no_fe_vf_id;
1142 __le16 tso_mss_cmp_min_err_qid;
1143 __le16 tso_mss_cmp_min_err_vf_id;
1144 __le16 tso_mss_cmp_max_err_qid;
1145 __le16 tso_mss_cmp_max_err_vf_id;
1146 __le16 tx_rd_fbd_poison_qid;
1147 __le16 tx_rd_fbd_poison_vf_id;
1148 __le16 rx_rd_fbd_poison_qid;
1149 __le16 rx_rd_fbd_poison_vf_id;
1153 #define HCLGE_LINK_EVENT_REPORT_EN_B 0
1154 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1
1155 #define HCLGE_PHY_IMP_EN_B 2
1156 struct hclge_firmware_compat_cmd {
1161 #define HCLGE_SFP_INFO_CMD_NUM 6
1162 #define HCLGE_SFP_INFO_BD0_LEN 20
1163 #define HCLGE_SFP_INFO_BDX_LEN 24
1164 #define HCLGE_SFP_INFO_MAX_LEN \
1165 (HCLGE_SFP_INFO_BD0_LEN + \
1166 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1168 struct hclge_sfp_info_bd0_cmd {
1171 u8 data[HCLGE_SFP_INFO_BD0_LEN];
1174 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4
1176 struct hclge_dev_specs_0_cmd {
1178 __le32 mac_entry_num;
1179 __le32 mng_entry_num;
1180 __le16 rss_ind_tbl_size;
1181 __le16 rss_key_size;
1183 u8 max_non_tso_bd_num;
1188 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U
1190 struct hclge_dev_specs_1_cmd {
1191 __le16 max_frm_size;
1192 __le16 max_qset_num;
1197 #define HCLGE_PHY_LINK_SETTING_BD_NUM 2
1199 struct hclge_phy_link_ksetting_0_cmd {
1204 u8 eth_tp_mdix_ctrl;
1211 __le32 lp_advertising;
1214 struct hclge_phy_link_ksetting_1_cmd {
1215 u8 master_slave_cfg;
1216 u8 master_slave_state;
1220 struct hclge_phy_reg_cmd {
1227 int hclge_cmd_init(struct hclge_dev *hdev);
1228 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1230 writel(value, base + reg);
1233 #define hclge_write_dev(a, reg, value) \
1234 hclge_write_reg((a)->io_base, reg, value)
1235 #define hclge_read_dev(a, reg) \
1236 hclge_read_reg((a)->io_base, reg)
1238 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1240 u8 __iomem *reg_addr = READ_ONCE(base);
1242 return readl(reg_addr + reg);
1245 #define HCLGE_SEND_SYNC(flag) \
1246 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1249 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1250 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1251 enum hclge_opcode_type opcode, bool is_read);
1252 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1254 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1255 struct hclge_desc *desc);
1256 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1257 struct hclge_desc *desc);
1259 void hclge_cmd_uninit(struct hclge_dev *hdev);
1260 int hclge_cmd_queue_init(struct hclge_dev *hdev);