2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/mfd/syscon.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/vmalloc.h>
25 #include "hns_dsaf_mac.h"
26 #include "hns_dsaf_main.h"
27 #include "hns_dsaf_ppe.h"
28 #include "hns_dsaf_rcb.h"
29 #include "hns_dsaf_misc.h"
31 const static char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
32 [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
33 [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
34 [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
35 [DSAF_MODE_DISABLE_SP] = "single-port",
38 static const struct acpi_device_id hns_dsaf_acpi_match[] = {
43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
45 static int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
53 struct regmap *syscon;
55 struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
56 struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
58 if (dev_of_node(dsaf_dev->dev)) {
59 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
60 dsaf_dev->dsaf_ver = AE_VERSION_1;
62 dsaf_dev->dsaf_ver = AE_VERSION_2;
63 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
64 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
65 dsaf_dev->dsaf_ver = AE_VERSION_1;
66 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
67 dsaf_dev->dsaf_ver = AE_VERSION_2;
71 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
75 ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
77 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
80 for (i = 0; i < DSAF_MODE_MAX; i++) {
81 if (g_dsaf_mode_match[i] &&
82 !strcmp(mode_str, g_dsaf_mode_match[i]))
85 if (i >= DSAF_MODE_MAX ||
86 i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
87 dev_err(dsaf_dev->dev,
88 "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
91 dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
93 if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
94 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
96 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
98 if ((i == DSAF_MODE_ENABLE_16VM) ||
99 (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
100 (i == DSAF_MODE_DISABLE_6PORT_2VM))
101 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
103 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
105 if (dev_of_node(dsaf_dev->dev)) {
106 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
107 syscon = syscon_node_to_regmap(np_temp);
108 of_node_put(np_temp);
109 if (IS_ERR_OR_NULL(syscon)) {
110 res = platform_get_resource(pdev, IORESOURCE_MEM,
113 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
117 dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
119 if (IS_ERR(dsaf_dev->sc_base))
120 return PTR_ERR(dsaf_dev->sc_base);
122 res = platform_get_resource(pdev, IORESOURCE_MEM,
125 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
129 dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
131 if (IS_ERR(dsaf_dev->sds_base))
132 return PTR_ERR(dsaf_dev->sds_base);
134 dsaf_dev->sub_ctrl = syscon;
138 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
140 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
142 dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
146 dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
147 if (IS_ERR(dsaf_dev->ppe_base))
148 return PTR_ERR(dsaf_dev->ppe_base);
149 dsaf_dev->ppe_paddr = res->start;
151 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
155 res = platform_get_resource(pdev, IORESOURCE_MEM,
158 dev_err(dsaf_dev->dev,
159 "dsaf-base info is needed!\n");
163 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
164 if (IS_ERR(dsaf_dev->io_base))
165 return PTR_ERR(dsaf_dev->io_base);
168 ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
169 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
170 desc_num > HNS_DSAF_MAX_DESC_CNT) {
171 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
175 dsaf_dev->desc_num = desc_num;
177 ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
180 dev_dbg(dsaf_dev->dev,
181 "get reset-field-offset fail, ret=%d!\r\n", ret);
183 dsaf_dev->reset_offset = reset_offset;
185 ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
187 dev_err(dsaf_dev->dev,
188 "get buf-size fail, ret=%d!\r\n", ret);
191 dsaf_dev->buf_size = buf_size;
193 dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
194 if (dsaf_dev->buf_size_type < 0) {
195 dev_err(dsaf_dev->dev,
196 "buf_size(%d) is wrong!\n", buf_size);
200 dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
201 if (!dsaf_dev->misc_op)
204 if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
205 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
207 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
213 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
214 * @dsaf_id: dsa fabric id
216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
218 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
222 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
223 * @dsaf_id: dsa fabric id
224 * @hns_dsaf_reg_cnt_clr_ce: config value
227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
229 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
230 DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
234 * hns_ppe_qid_cfg - config ppe qid
235 * @dsaf_id: dsa fabric id
236 * @pppe_qid_cfg: value array
239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
243 for (i = 0; i < DSAF_COMM_CHN; i++) {
244 dsaf_set_dev_field(dsaf_dev,
245 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
246 DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
253 u16 max_q_per_vf, max_vfn;
254 u32 q_id, q_num_per_port;
257 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
258 q_num_per_port = max_vfn * max_q_per_vf;
260 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
261 dsaf_set_dev_field(dsaf_dev,
262 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
264 q_id += q_num_per_port;
268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
270 u16 max_q_per_vf, max_vfn;
271 u32 q_id, q_num_per_port;
274 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
277 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
278 q_num_per_port = max_vfn * max_q_per_vf;
280 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
281 dsaf_set_dev_field(dsaf_dev,
282 DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
283 DSAFV2_SERDES_LBK_QID_M,
284 DSAFV2_SERDES_LBK_QID_S,
286 q_id += q_num_per_port;
291 * hns_dsaf_sw_port_type_cfg - cfg sw type
292 * @dsaf_id: dsa fabric id
293 * @psw_port_type: array
295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
296 enum dsaf_sw_port_type port_type)
300 for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
301 dsaf_set_dev_field(dsaf_dev,
302 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
303 DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
309 * hns_dsaf_stp_port_type_cfg - cfg stp type
310 * @dsaf_id: dsa fabric id
311 * @pstp_port_type: array
313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
314 enum dsaf_stp_port_type port_type)
318 for (i = 0; i < DSAF_COMM_CHN; i++) {
319 dsaf_set_dev_field(dsaf_dev,
320 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
321 DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
326 #define HNS_DSAF_SBM_NUM(dev) \
327 (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
329 * hns_dsaf_sbm_cfg - config sbm
330 * @dsaf_id: dsa fabric id
332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
337 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
338 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
339 DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
340 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
341 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
342 dsaf_write_dev(dsaf_dev,
343 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
348 * hns_dsaf_sbm_cfg_mib_en - config sbm
349 * @dsaf_id: dsa fabric id
351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
358 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
359 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
360 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
361 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
364 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
365 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
366 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
369 /* waitint for all sbm enable finished */
370 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
372 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
375 sbm_cfg_mib_en = dsaf_get_dev_bit(
376 dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
378 } while (sbm_cfg_mib_en == 0 &&
379 read_cnt < DSAF_CFG_READ_CNT);
381 if (sbm_cfg_mib_en == 0) {
382 dev_err(dsaf_dev->dev,
383 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
384 dsaf_dev->ae_dev.name, i);
393 * hns_dsaf_sbm_bp_wl_cfg - config sbm
394 * @dsaf_id: dsa fabric id
396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
403 for (i = 0; i < DSAF_XGE_NUM; i++) {
404 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
405 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
406 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
407 DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
408 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
409 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
410 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
411 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
412 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
414 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
415 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
416 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
417 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
418 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
419 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
420 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
422 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
423 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
424 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
425 DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
426 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
427 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
428 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
430 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
431 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
432 dsaf_set_field(o_sbm_bp_cfg,
433 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
434 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
435 dsaf_set_field(o_sbm_bp_cfg,
436 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
437 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
438 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
440 /* for no enable pfc mode */
441 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
442 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
443 dsaf_set_field(o_sbm_bp_cfg,
444 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
445 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
446 dsaf_set_field(o_sbm_bp_cfg,
447 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
448 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
449 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
453 for (i = 0; i < DSAF_COMM_CHN; i++) {
454 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
455 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
456 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
457 DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
458 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
459 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
460 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
464 for (i = 0; i < DSAF_COMM_CHN; i++) {
465 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
466 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
467 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
468 DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
469 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
470 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
471 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
482 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
483 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
484 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
485 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
486 DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
487 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
488 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
489 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
490 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
491 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
493 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
494 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
495 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
496 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
497 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
498 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
499 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
501 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
502 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
503 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
504 DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
505 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
506 DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
507 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
509 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
510 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
511 dsaf_set_field(o_sbm_bp_cfg,
512 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
513 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55);
514 dsaf_set_field(o_sbm_bp_cfg,
515 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
516 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110);
517 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
519 /* for no enable pfc mode */
520 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
521 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
522 dsaf_set_field(o_sbm_bp_cfg,
523 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
524 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128);
525 dsaf_set_field(o_sbm_bp_cfg,
526 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
527 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192);
528 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
532 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
533 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
534 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
535 dsaf_set_field(o_sbm_bp_cfg,
536 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
537 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
538 dsaf_set_field(o_sbm_bp_cfg,
539 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
540 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
541 dsaf_set_field(o_sbm_bp_cfg,
542 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
543 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
544 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
548 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
549 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
550 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
551 dsaf_set_field(o_sbm_bp_cfg,
552 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
553 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
554 dsaf_set_field(o_sbm_bp_cfg,
555 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
556 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
557 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
562 * hns_dsaf_voq_bp_all_thrd_cfg - voq
563 * @dsaf_id: dsa fabric id
565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
570 for (i = 0; i < DSAF_VOQ_NUM; i++) {
571 voq_bp_all_thrd = dsaf_read_dev(
572 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
573 if (i < DSAF_XGE_NUM) {
574 dsaf_set_field(voq_bp_all_thrd,
575 DSAF_VOQ_BP_ALL_DOWNTHRD_M,
576 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
577 dsaf_set_field(voq_bp_all_thrd,
578 DSAF_VOQ_BP_ALL_UPTHRD_M,
579 DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
581 dsaf_set_field(voq_bp_all_thrd,
582 DSAF_VOQ_BP_ALL_DOWNTHRD_M,
583 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
584 dsaf_set_field(voq_bp_all_thrd,
585 DSAF_VOQ_BP_ALL_UPTHRD_M,
586 DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
589 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
594 static void hns_dsaf_tbl_tcam_match_cfg(
595 struct dsaf_device *dsaf_dev,
596 struct dsaf_tbl_tcam_data *ptbl_tcam_data)
598 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
599 ptbl_tcam_data->tbl_tcam_data_low);
600 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
601 ptbl_tcam_data->tbl_tcam_data_high);
605 * hns_dsaf_tbl_tcam_data_cfg - tbl
606 * @dsaf_id: dsa fabric id
607 * @ptbl_tcam_data: addr
609 static void hns_dsaf_tbl_tcam_data_cfg(
610 struct dsaf_device *dsaf_dev,
611 struct dsaf_tbl_tcam_data *ptbl_tcam_data)
613 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
614 ptbl_tcam_data->tbl_tcam_data_low);
615 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
616 ptbl_tcam_data->tbl_tcam_data_high);
620 * dsaf_tbl_tcam_mcast_cfg - tbl
621 * @dsaf_id: dsa fabric id
622 * @ptbl_tcam_mcast: addr
624 static void hns_dsaf_tbl_tcam_mcast_cfg(
625 struct dsaf_device *dsaf_dev,
626 struct dsaf_tbl_tcam_mcast_cfg *mcast)
630 mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
631 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
632 mcast->tbl_mcast_item_vld);
633 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
634 mcast->tbl_mcast_old_en);
635 dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
636 DSAF_TBL_MCAST_CFG4_VM128_112_S,
637 mcast->tbl_mcast_port_msk[4]);
638 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
640 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
641 mcast->tbl_mcast_port_msk[3]);
643 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
644 mcast->tbl_mcast_port_msk[2]);
646 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
647 mcast->tbl_mcast_port_msk[1]);
649 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
650 mcast->tbl_mcast_port_msk[0]);
654 * hns_dsaf_tbl_tcam_ucast_cfg - tbl
655 * @dsaf_id: dsa fabric id
656 * @ptbl_tcam_ucast: addr
658 static void hns_dsaf_tbl_tcam_ucast_cfg(
659 struct dsaf_device *dsaf_dev,
660 struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
664 ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
665 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
666 tbl_tcam_ucast->tbl_ucast_mac_discard);
667 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
668 tbl_tcam_ucast->tbl_ucast_item_vld);
669 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
670 tbl_tcam_ucast->tbl_ucast_old_en);
671 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
672 tbl_tcam_ucast->tbl_ucast_dvc);
673 dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
674 DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
675 tbl_tcam_ucast->tbl_ucast_out_port);
676 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
680 * hns_dsaf_tbl_line_cfg - tbl
681 * @dsaf_id: dsa fabric id
684 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
685 struct dsaf_tbl_line_cfg *tbl_lin)
689 tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
690 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
691 tbl_lin->tbl_line_mac_discard);
692 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
693 tbl_lin->tbl_line_dvc);
694 dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
695 DSAF_TBL_LINE_CFG_OUT_PORT_S,
696 tbl_lin->tbl_line_out_port);
697 dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
701 * hns_dsaf_tbl_tcam_mcast_pul - tbl
702 * @dsaf_id: dsa fabric id
704 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
708 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
709 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
710 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
711 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
712 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
716 * hns_dsaf_tbl_line_pul - tbl
717 * @dsaf_id: dsa fabric id
719 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
723 tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
724 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
725 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
726 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
727 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
731 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
732 * @dsaf_id: dsa fabric id
734 static void hns_dsaf_tbl_tcam_data_mcast_pul(
735 struct dsaf_device *dsaf_dev)
739 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
740 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
741 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
742 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
743 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
744 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
745 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
749 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
750 * @dsaf_id: dsa fabric id
752 static void hns_dsaf_tbl_tcam_data_ucast_pul(
753 struct dsaf_device *dsaf_dev)
757 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
758 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
759 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
760 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
761 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
762 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
763 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
766 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
768 if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev))
769 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
770 DSAF_CFG_MIX_MODE_S, !!en);
774 * hns_dsaf_tbl_stat_en - tbl
775 * @dsaf_id: dsa fabric id
776 * @ptbl_stat_en: addr
778 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
782 o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
783 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
784 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
785 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
786 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
787 dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
791 * hns_dsaf_rocee_bp_en - rocee back press enable
792 * @dsaf_id: dsa fabric id
794 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
796 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
797 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
798 DSAF_FC_XGE_TX_PAUSE_S, 1);
801 /* set msk for dsaf exception irq*/
802 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
803 u32 chnn_num, u32 mask_set)
805 dsaf_write_dev(dsaf_dev,
806 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
809 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
810 u32 chnn_num, u32 msk_set)
812 dsaf_write_dev(dsaf_dev,
813 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
816 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
817 u32 chnn, u32 msk_set)
819 dsaf_write_dev(dsaf_dev,
820 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
824 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
826 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
829 /* clr dsaf exception irq*/
830 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
831 u32 chnn_num, u32 int_src)
833 dsaf_write_dev(dsaf_dev,
834 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
837 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
838 u32 chnn, u32 int_src)
840 dsaf_write_dev(dsaf_dev,
841 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
844 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
845 u32 chnn, u32 int_src)
847 dsaf_write_dev(dsaf_dev,
848 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
851 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
854 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
858 * hns_dsaf_single_line_tbl_cfg - INT
859 * @dsaf_id: dsa fabric id
863 static void hns_dsaf_single_line_tbl_cfg(
864 struct dsaf_device *dsaf_dev,
865 u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
867 spin_lock_bh(&dsaf_dev->tcam_lock);
870 hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
873 hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
876 hns_dsaf_tbl_line_pul(dsaf_dev);
878 spin_unlock_bh(&dsaf_dev->tcam_lock);
882 * hns_dsaf_tcam_uc_cfg - INT
883 * @dsaf_id: dsa fabric id
887 static void hns_dsaf_tcam_uc_cfg(
888 struct dsaf_device *dsaf_dev, u32 address,
889 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
890 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
892 spin_lock_bh(&dsaf_dev->tcam_lock);
895 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
897 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
899 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
901 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
903 spin_unlock_bh(&dsaf_dev->tcam_lock);
907 * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc
908 * @dsaf_dev: dsa fabric device struct pointer
909 * @address: tcam index
910 * @ptbl_tcam_data: tcam data struct pointer
911 * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1
913 static void hns_dsaf_tcam_mc_cfg(
914 struct dsaf_device *dsaf_dev, u32 address,
915 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
916 struct dsaf_tbl_tcam_data *ptbl_tcam_mask,
917 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
919 spin_lock_bh(&dsaf_dev->tcam_lock);
922 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
924 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
926 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
927 /* Write Match Data */
929 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask);
932 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
934 spin_unlock_bh(&dsaf_dev->tcam_lock);
938 * hns_dsaf_tcam_uc_cfg_vague - INT
939 * @dsaf_dev: dsa fabric device struct pointer
943 static void hns_dsaf_tcam_uc_cfg_vague(struct dsaf_device *dsaf_dev,
945 struct dsaf_tbl_tcam_data *tcam_data,
946 struct dsaf_tbl_tcam_data *tcam_mask,
947 struct dsaf_tbl_tcam_ucast_cfg *tcam_uc)
949 spin_lock_bh(&dsaf_dev->tcam_lock);
950 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
951 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
952 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, tcam_uc);
953 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
954 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
956 /*Restore Match Data*/
957 tcam_mask->tbl_tcam_data_high = 0xffffffff;
958 tcam_mask->tbl_tcam_data_low = 0xffffffff;
959 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
961 spin_unlock_bh(&dsaf_dev->tcam_lock);
965 * hns_dsaf_tcam_mc_cfg_vague - INT
966 * @dsaf_dev: dsa fabric device struct pointer
972 static void hns_dsaf_tcam_mc_cfg_vague(struct dsaf_device *dsaf_dev,
974 struct dsaf_tbl_tcam_data *tcam_data,
975 struct dsaf_tbl_tcam_data *tcam_mask,
976 struct dsaf_tbl_tcam_mcast_cfg *tcam_mc)
978 spin_lock_bh(&dsaf_dev->tcam_lock);
979 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
980 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
981 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, tcam_mc);
982 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
983 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
985 /*Restore Match Data*/
986 tcam_mask->tbl_tcam_data_high = 0xffffffff;
987 tcam_mask->tbl_tcam_data_low = 0xffffffff;
988 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
990 spin_unlock_bh(&dsaf_dev->tcam_lock);
994 * hns_dsaf_tcam_mc_invld - INT
995 * @dsaf_id: dsa fabric id
998 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
1000 spin_lock_bh(&dsaf_dev->tcam_lock);
1003 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1005 /*write tcam mcast*/
1006 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
1007 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
1008 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
1009 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
1010 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
1013 hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
1015 spin_unlock_bh(&dsaf_dev->tcam_lock);
1019 hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr)
1021 addr[0] = mac_key->high.bits.mac_0;
1022 addr[1] = mac_key->high.bits.mac_1;
1023 addr[2] = mac_key->high.bits.mac_2;
1024 addr[3] = mac_key->high.bits.mac_3;
1025 addr[4] = mac_key->low.bits.mac_4;
1026 addr[5] = mac_key->low.bits.mac_5;
1030 * hns_dsaf_tcam_uc_get - INT
1031 * @dsaf_id: dsa fabric id
1036 static void hns_dsaf_tcam_uc_get(
1037 struct dsaf_device *dsaf_dev, u32 address,
1038 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1039 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
1041 u32 tcam_read_data0;
1042 u32 tcam_read_data4;
1044 spin_lock_bh(&dsaf_dev->tcam_lock);
1047 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1049 /*read tcam item puls*/
1050 hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1053 ptbl_tcam_data->tbl_tcam_data_high
1054 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1055 ptbl_tcam_data->tbl_tcam_data_low
1056 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1059 tcam_read_data0 = dsaf_read_dev(dsaf_dev,
1060 DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1061 tcam_read_data4 = dsaf_read_dev(dsaf_dev,
1062 DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1064 ptbl_tcam_ucast->tbl_ucast_item_vld
1065 = dsaf_get_bit(tcam_read_data4,
1066 DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1067 ptbl_tcam_ucast->tbl_ucast_old_en
1068 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1069 ptbl_tcam_ucast->tbl_ucast_mac_discard
1070 = dsaf_get_bit(tcam_read_data0,
1071 DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1072 ptbl_tcam_ucast->tbl_ucast_out_port
1073 = dsaf_get_field(tcam_read_data0,
1074 DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1075 DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1076 ptbl_tcam_ucast->tbl_ucast_dvc
1077 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
1079 spin_unlock_bh(&dsaf_dev->tcam_lock);
1083 * hns_dsaf_tcam_mc_get - INT
1084 * @dsaf_id: dsa fabric id
1089 static void hns_dsaf_tcam_mc_get(
1090 struct dsaf_device *dsaf_dev, u32 address,
1091 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1092 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1096 spin_lock_bh(&dsaf_dev->tcam_lock);
1099 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1101 /*read tcam item puls*/
1102 hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1105 ptbl_tcam_data->tbl_tcam_data_high =
1106 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1107 ptbl_tcam_data->tbl_tcam_data_low =
1108 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1111 ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1112 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1113 ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1114 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1115 ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1116 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1117 ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1118 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1120 data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1121 ptbl_tcam_mcast->tbl_mcast_item_vld =
1122 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1123 ptbl_tcam_mcast->tbl_mcast_old_en =
1124 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1125 ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1126 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1127 DSAF_TBL_MCAST_CFG4_VM128_112_S);
1129 spin_unlock_bh(&dsaf_dev->tcam_lock);
1133 * hns_dsaf_tbl_line_init - INT
1134 * @dsaf_id: dsa fabric id
1136 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1139 /* defaultly set all lineal mac table entry resulting discard */
1140 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1142 for (i = 0; i < DSAF_LINE_SUM; i++)
1143 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1147 * hns_dsaf_tbl_tcam_init - INT
1148 * @dsaf_id: dsa fabric id
1150 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1153 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1154 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1157 for (i = 0; i < DSAF_TCAM_SUM; i++)
1158 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1162 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1163 * @mac_cb: mac contrl block
1165 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1166 int mac_id, int tc_en)
1168 dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1171 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1172 int mac_id, int tx_en, int rx_en)
1174 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1175 if (!tx_en || !rx_en)
1176 dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1181 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1182 DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1183 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1184 DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1187 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1190 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1192 dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1197 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1198 DSAF_MAC_PAUSE_RX_EN_B, !!en);
1203 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1206 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1209 *en = dsaf_get_dev_bit(dsaf_dev,
1210 DSAF_PAUSE_CFG_REG + mac_id * 4,
1211 DSAF_MAC_PAUSE_RX_EN_B);
1215 * hns_dsaf_tbl_tcam_init - INT
1216 * @dsaf_id: dsa fabric id
1219 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1223 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1225 o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1226 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1227 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1228 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1229 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1230 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1231 dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1233 hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1234 hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1236 /* set 22 queue per tx ppe engine, only used in switch mode */
1237 hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1239 /* set promisc def queue id */
1240 hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1242 /* set inner loopback queue id */
1243 hns_dsaf_inner_qid_cfg(dsaf_dev);
1245 /* in non switch mode, set all port to access mode */
1246 hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1248 /*set dsaf pfc to 0 for parseing rx pause*/
1249 for (i = 0; i < DSAF_COMM_CHN; i++) {
1250 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1251 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1254 /*msk and clr exception irqs */
1255 for (i = 0; i < DSAF_COMM_CHN; i++) {
1256 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1257 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1258 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1260 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1261 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1262 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1264 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1265 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1269 * hns_dsaf_inode_init - INT
1270 * @dsaf_id: dsa fabric id
1272 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1278 if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1279 tc_cfg = HNS_DSAF_I4TC_CFG;
1281 tc_cfg = HNS_DSAF_I8TC_CFG;
1283 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1284 for (i = 0; i < DSAF_INODE_NUM; i++) {
1285 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1286 dsaf_set_dev_field(dsaf_dev, reg,
1287 DSAF_INODE_IN_PORT_NUM_M,
1288 DSAF_INODE_IN_PORT_NUM_S,
1292 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1293 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1294 dsaf_set_dev_field(dsaf_dev, reg,
1295 DSAF_INODE_IN_PORT_NUM_M,
1296 DSAF_INODE_IN_PORT_NUM_S, 0);
1297 dsaf_set_dev_field(dsaf_dev, reg,
1298 DSAFV2_INODE_IN_PORT1_NUM_M,
1299 DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1300 dsaf_set_dev_field(dsaf_dev, reg,
1301 DSAFV2_INODE_IN_PORT2_NUM_M,
1302 DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1303 dsaf_set_dev_field(dsaf_dev, reg,
1304 DSAFV2_INODE_IN_PORT3_NUM_M,
1305 DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1306 dsaf_set_dev_field(dsaf_dev, reg,
1307 DSAFV2_INODE_IN_PORT4_NUM_M,
1308 DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1309 dsaf_set_dev_field(dsaf_dev, reg,
1310 DSAFV2_INODE_IN_PORT5_NUM_M,
1311 DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1314 for (i = 0; i < DSAF_INODE_NUM; i++) {
1315 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1316 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1321 * hns_dsaf_sbm_init - INT
1322 * @dsaf_id: dsa fabric id
1324 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1331 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1332 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1333 finish_msk = DSAF_SRAM_INIT_OVER_M;
1335 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1336 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1339 /* enable sbm chanel, disable sbm chanel shcut function*/
1340 hns_dsaf_sbm_cfg(dsaf_dev);
1342 /* enable sbm mib */
1343 ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1345 dev_err(dsaf_dev->dev,
1346 "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1347 dsaf_dev->ae_dev.name, ret);
1351 /* enable sbm initial link sram */
1352 hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1355 usleep_range(200, 210);/*udelay(200);*/
1356 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1357 finish_msk, DSAF_SRAM_INIT_OVER_S);
1359 } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1360 cnt < DSAF_CFG_READ_CNT);
1362 if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1363 dev_err(dsaf_dev->dev,
1364 "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1365 dsaf_dev->ae_dev.name, flag, cnt);
1369 hns_dsaf_rocee_bp_en(dsaf_dev);
1375 * hns_dsaf_tbl_init - INT
1376 * @dsaf_id: dsa fabric id
1378 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1380 hns_dsaf_tbl_stat_en(dsaf_dev);
1382 hns_dsaf_tbl_tcam_init(dsaf_dev);
1383 hns_dsaf_tbl_line_init(dsaf_dev);
1387 * hns_dsaf_voq_init - INT
1388 * @dsaf_id: dsa fabric id
1390 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1392 hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1396 * hns_dsaf_init_hw - init dsa fabric hardware
1397 * @dsaf_dev: dsa fabric device struct pointer
1399 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1403 dev_dbg(dsaf_dev->dev,
1404 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1406 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1408 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1410 hns_dsaf_comm_init(dsaf_dev);
1413 hns_dsaf_inode_init(dsaf_dev);
1416 ret = hns_dsaf_sbm_init(dsaf_dev);
1421 hns_dsaf_tbl_init(dsaf_dev);
1424 hns_dsaf_voq_init(dsaf_dev);
1430 * hns_dsaf_remove_hw - uninit dsa fabric hardware
1431 * @dsaf_dev: dsa fabric device struct pointer
1433 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1436 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1440 * hns_dsaf_init - init dsa fabric
1441 * @dsaf_dev: dsa fabric device struct pointer
1442 * retuen 0 - success , negative --fail
1444 static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1446 struct dsaf_drv_priv *priv =
1447 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1451 if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1454 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1455 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM;
1457 dsaf_dev->tcam_max_num =
1458 DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM;
1460 spin_lock_init(&dsaf_dev->tcam_lock);
1461 ret = hns_dsaf_init_hw(dsaf_dev);
1465 /* malloc mem for tcam mac key(vlan+mac) */
1466 priv->soft_mac_tbl = vzalloc(array_size(DSAF_TCAM_SUM,
1467 sizeof(*priv->soft_mac_tbl)));
1468 if (!priv->soft_mac_tbl) {
1473 /*all entry invall */
1474 for (i = 0; i < DSAF_TCAM_SUM; i++)
1475 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1480 hns_dsaf_remove_hw(dsaf_dev);
1485 * hns_dsaf_free - free dsa fabric
1486 * @dsaf_dev: dsa fabric device struct pointer
1488 static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1490 struct dsaf_drv_priv *priv =
1491 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1493 hns_dsaf_remove_hw(dsaf_dev);
1495 /* free all mac mem */
1496 vfree(priv->soft_mac_tbl);
1497 priv->soft_mac_tbl = NULL;
1501 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1502 * @dsaf_dev: dsa fabric device struct pointer
1503 * @mac_key: mac entry struct pointer
1505 static u16 hns_dsaf_find_soft_mac_entry(
1506 struct dsaf_device *dsaf_dev,
1507 struct dsaf_drv_tbl_tcam_key *mac_key)
1509 struct dsaf_drv_priv *priv =
1510 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1511 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1514 soft_mac_entry = priv->soft_mac_tbl;
1515 for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1516 /* invall tab entry */
1517 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1518 (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1519 (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1520 /* return find result --soft index */
1521 return soft_mac_entry->index;
1525 return DSAF_INVALID_ENTRY_IDX;
1529 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1530 * @dsaf_dev: dsa fabric device struct pointer
1532 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1534 struct dsaf_drv_priv *priv =
1535 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1536 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1539 soft_mac_entry = priv->soft_mac_tbl;
1540 for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1542 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1543 /* return find result --soft index */
1548 return DSAF_INVALID_ENTRY_IDX;
1552 * hns_dsaf_find_empty_mac_entry_reverse
1553 * search dsa fabric soft empty-entry from the end
1554 * @dsaf_dev: dsa fabric device struct pointer
1556 static u16 hns_dsaf_find_empty_mac_entry_reverse(struct dsaf_device *dsaf_dev)
1558 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1559 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1562 soft_mac_entry = priv->soft_mac_tbl + (DSAF_TCAM_SUM - 1);
1563 for (i = (DSAF_TCAM_SUM - 1); i > 0; i--) {
1564 /* search all entry from end to start.*/
1565 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1569 return DSAF_INVALID_ENTRY_IDX;
1573 * hns_dsaf_set_mac_key - set mac key
1574 * @dsaf_dev: dsa fabric device struct pointer
1575 * @mac_key: tcam key pointer
1577 * @in_port_num: input port num
1580 static void hns_dsaf_set_mac_key(
1581 struct dsaf_device *dsaf_dev,
1582 struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1587 if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1588 /*DSAF mode : in port id fixed 0*/
1594 mac_key->high.bits.mac_0 = addr[0];
1595 mac_key->high.bits.mac_1 = addr[1];
1596 mac_key->high.bits.mac_2 = addr[2];
1597 mac_key->high.bits.mac_3 = addr[3];
1598 mac_key->low.bits.mac_4 = addr[4];
1599 mac_key->low.bits.mac_5 = addr[5];
1600 mac_key->low.bits.port_vlan = 0;
1601 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
1602 DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id);
1603 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
1604 DSAF_TBL_TCAM_KEY_PORT_S, port);
1608 * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1609 * @dsaf_dev: dsa fabric device struct pointer
1610 * @mac_entry: uc-mac entry
1612 int hns_dsaf_set_mac_uc_entry(
1613 struct dsaf_device *dsaf_dev,
1614 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1616 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1617 struct dsaf_drv_tbl_tcam_key mac_key;
1618 struct dsaf_tbl_tcam_ucast_cfg mac_data;
1619 struct dsaf_drv_priv *priv =
1620 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1621 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1622 struct dsaf_tbl_tcam_data tcam_data;
1624 /* mac addr check */
1625 if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1626 MAC_IS_BROADCAST(mac_entry->addr) ||
1627 MAC_IS_MULTICAST(mac_entry->addr)) {
1628 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1629 dsaf_dev->ae_dev.name, mac_entry->addr);
1634 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1635 mac_entry->in_port_num, mac_entry->addr);
1637 /* entry ie exist? */
1638 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1639 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1640 /*if has not inv entry,find a empty entry */
1641 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1642 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1643 /* has not empty,return error */
1644 dev_err(dsaf_dev->dev,
1645 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1646 dsaf_dev->ae_dev.name,
1647 mac_key.high.val, mac_key.low.val);
1652 dev_dbg(dsaf_dev->dev,
1653 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1654 dsaf_dev->ae_dev.name, mac_key.high.val,
1655 mac_key.low.val, entry_index);
1657 /* config hardware entry */
1658 mac_data.tbl_ucast_item_vld = 1;
1659 mac_data.tbl_ucast_mac_discard = 0;
1660 mac_data.tbl_ucast_old_en = 0;
1661 /* default config dvc to 0 */
1662 mac_data.tbl_ucast_dvc = 0;
1663 mac_data.tbl_ucast_out_port = mac_entry->port_num;
1664 tcam_data.tbl_tcam_data_high = mac_key.high.val;
1665 tcam_data.tbl_tcam_data_low = mac_key.low.val;
1667 hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data);
1669 /* config software entry */
1670 soft_mac_entry += entry_index;
1671 soft_mac_entry->index = entry_index;
1672 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1673 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1678 int hns_dsaf_rm_mac_addr(
1679 struct dsaf_device *dsaf_dev,
1680 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1682 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1683 struct dsaf_tbl_tcam_ucast_cfg mac_data;
1684 struct dsaf_drv_tbl_tcam_key mac_key;
1686 /* mac addr check */
1687 if (!is_valid_ether_addr(mac_entry->addr)) {
1688 dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n",
1689 dsaf_dev->ae_dev.name, mac_entry->addr);
1694 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1695 mac_entry->in_port_num, mac_entry->addr);
1697 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1698 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1699 /* can not find the tcam entry, return 0 */
1700 dev_info(dsaf_dev->dev,
1701 "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n",
1702 dsaf_dev->ae_dev.name,
1703 mac_key.high.val, mac_key.low.val);
1707 dev_dbg(dsaf_dev->dev,
1708 "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n",
1709 dsaf_dev->ae_dev.name, mac_key.high.val,
1710 mac_key.low.val, entry_index);
1712 hns_dsaf_tcam_uc_get(
1713 dsaf_dev, entry_index,
1714 (struct dsaf_tbl_tcam_data *)&mac_key,
1717 /* unicast entry not used locally should not clear */
1718 if (mac_entry->port_num != mac_data.tbl_ucast_out_port)
1721 return hns_dsaf_del_mac_entry(dsaf_dev,
1722 mac_entry->in_vlan_id,
1723 mac_entry->in_port_num,
1727 static void hns_dsaf_setup_mc_mask(struct dsaf_device *dsaf_dev,
1728 u8 port_num, u8 *mask, u8 *addr)
1730 if (MAC_IS_BROADCAST(addr))
1731 memset(mask, 0xff, ETH_ALEN);
1733 memcpy(mask, dsaf_dev->mac_cb[port_num]->mc_mask, ETH_ALEN);
1736 static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src)
1738 u16 *a = (u16 *)dst;
1739 const u16 *b = (const u16 *)src;
1747 * hns_dsaf_add_mac_mc_port - add mac mc-port
1748 * @dsaf_dev: dsa fabric device struct pointer
1749 * @mac_entry: mc-mac entry
1751 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1752 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1754 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1755 struct dsaf_drv_tbl_tcam_key mac_key;
1756 struct dsaf_drv_tbl_tcam_key mask_key;
1757 struct dsaf_tbl_tcam_data *pmask_key = NULL;
1758 struct dsaf_tbl_tcam_mcast_cfg mac_data;
1759 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1760 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1761 struct dsaf_tbl_tcam_data tcam_data;
1762 u8 mc_addr[ETH_ALEN];
1765 /*chechk mac addr */
1766 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1767 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1772 ether_addr_copy(mc_addr, mac_entry->addr);
1773 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1774 u8 mc_mask[ETH_ALEN];
1776 /* prepare for key data setting */
1777 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1778 mc_mask, mac_entry->addr);
1779 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1781 /* config key mask */
1782 hns_dsaf_set_mac_key(dsaf_dev, &mask_key,
1787 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1791 hns_dsaf_set_mac_key(
1792 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1793 mac_entry->in_port_num, mc_addr);
1795 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1797 /* check if the tcam is exist */
1798 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1799 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1800 /*if hasnot , find a empty*/
1801 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1802 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1803 /*if hasnot empty, error*/
1804 dev_err(dsaf_dev->dev,
1805 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1806 dsaf_dev->ae_dev.name, mac_key.high.val,
1811 /* if exist, add in */
1812 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data,
1816 /* config hardware entry */
1817 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1818 mskid = mac_entry->port_num;
1819 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1820 mskid = mac_entry->port_num -
1821 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1823 dev_err(dsaf_dev->dev,
1824 "%s,pnum(%d)error,key(%#x:%#x)\n",
1825 dsaf_dev->ae_dev.name, mac_entry->port_num,
1826 mac_key.high.val, mac_key.low.val);
1829 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1830 mac_data.tbl_mcast_old_en = 0;
1831 mac_data.tbl_mcast_item_vld = 1;
1833 dev_dbg(dsaf_dev->dev,
1834 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1835 dsaf_dev->ae_dev.name, mac_key.high.val,
1836 mac_key.low.val, entry_index);
1838 tcam_data.tbl_tcam_data_high = mac_key.high.val;
1839 tcam_data.tbl_tcam_data_low = mac_key.low.val;
1841 /* config mc entry with mask */
1842 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data,
1843 pmask_key, &mac_data);
1845 /*config software entry */
1846 soft_mac_entry += entry_index;
1847 soft_mac_entry->index = entry_index;
1848 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1849 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1855 * hns_dsaf_del_mac_entry - del mac mc-port
1856 * @dsaf_dev: dsa fabric device struct pointer
1857 * @vlan_id: vlian id
1858 * @in_port_num: input port num
1861 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1862 u8 in_port_num, u8 *addr)
1864 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1865 struct dsaf_drv_tbl_tcam_key mac_key;
1866 struct dsaf_drv_priv *priv =
1867 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1868 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1871 if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1872 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1878 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1881 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1882 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1883 /*not exist, error */
1884 dev_err(dsaf_dev->dev,
1885 "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1886 dsaf_dev->ae_dev.name,
1887 mac_key.high.val, mac_key.low.val);
1890 dev_dbg(dsaf_dev->dev,
1891 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1892 dsaf_dev->ae_dev.name, mac_key.high.val,
1893 mac_key.low.val, entry_index);
1896 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1899 soft_mac_entry += entry_index;
1900 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1906 * hns_dsaf_del_mac_mc_port - del mac mc- port
1907 * @dsaf_dev: dsa fabric device struct pointer
1908 * @mac_entry: mac entry
1910 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1911 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1913 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1914 struct dsaf_drv_tbl_tcam_key mac_key;
1915 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1916 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1919 struct dsaf_tbl_tcam_mcast_cfg mac_data;
1920 struct dsaf_tbl_tcam_data tcam_data;
1922 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1923 struct dsaf_drv_tbl_tcam_key mask_key;
1924 struct dsaf_tbl_tcam_data *pmask_key = NULL;
1925 u8 mc_addr[ETH_ALEN];
1927 if (!(void *)mac_entry) {
1928 dev_err(dsaf_dev->dev,
1929 "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1934 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1935 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1940 /* always mask vlan_id field */
1941 ether_addr_copy(mc_addr, mac_entry->addr);
1943 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1944 u8 mc_mask[ETH_ALEN];
1946 /* prepare for key data setting */
1947 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1948 mc_mask, mac_entry->addr);
1949 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1951 /* config key mask */
1952 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_mask);
1954 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1958 vlan_id = mac_entry->in_vlan_id;
1959 in_port_num = mac_entry->in_port_num;
1962 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr);
1964 /* check if the tcam entry is exist */
1965 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1966 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1968 dev_err(dsaf_dev->dev,
1969 "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1970 dsaf_dev->ae_dev.name,
1971 mac_key.high.val, mac_key.low.val);
1975 dev_dbg(dsaf_dev->dev,
1976 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1977 dsaf_dev->ae_dev.name, mac_key.high.val,
1978 mac_key.low.val, entry_index);
1981 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
1984 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1985 mskid = mac_entry->port_num;
1986 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1987 mskid = mac_entry->port_num -
1988 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1990 dev_err(dsaf_dev->dev,
1991 "%s,pnum(%d)error,key(%#x:%#x)\n",
1992 dsaf_dev->ae_dev.name, mac_entry->port_num,
1993 mac_key.high.val, mac_key.low.val);
1996 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1998 /*check non port, do del entry */
1999 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2000 sizeof(mac_data.tbl_mcast_port_msk))) {
2001 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
2003 /* del soft entry */
2004 soft_mac_entry += entry_index;
2005 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2006 } else { /* not zero, just del port, update */
2007 tcam_data.tbl_tcam_data_high = mac_key.high.val;
2008 tcam_data.tbl_tcam_data_low = mac_key.low.val;
2010 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
2012 pmask_key, &mac_data);
2018 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id,
2021 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2022 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2023 struct dsaf_tbl_tcam_mcast_cfg mac_data;
2026 if (HNS_DSAF_IS_DEBUG(dsaf_dev))
2029 for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) {
2033 soft_mac_entry = priv->soft_mac_tbl + i;
2035 hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr);
2036 port = dsaf_get_field(
2037 soft_mac_entry->tcam_key.low.bits.port_vlan,
2038 DSAF_TBL_TCAM_KEY_PORT_M,
2039 DSAF_TBL_TCAM_KEY_PORT_S);
2040 /* check valid tcam mc entry */
2041 if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX &&
2043 is_multicast_ether_addr(addr) &&
2044 !is_broadcast_ether_addr(addr)) {
2045 const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0};
2046 struct dsaf_drv_mac_single_dest_entry mac_entry;
2048 /* disable receiving of this multicast address for
2051 ether_addr_copy(mac_entry.addr, addr);
2052 mac_entry.in_vlan_id = dsaf_get_field(
2053 soft_mac_entry->tcam_key.low.bits.port_vlan,
2054 DSAF_TBL_TCAM_KEY_VLAN_M,
2055 DSAF_TBL_TCAM_KEY_VLAN_S);
2056 mac_entry.in_port_num = mac_id;
2057 mac_entry.port_num = port_num;
2058 if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) {
2063 /* disable receiving of this multicast address for
2064 * the mac port if all VF are disable
2066 hns_dsaf_tcam_mc_get(dsaf_dev, i,
2067 (struct dsaf_tbl_tcam_data *)
2068 (&soft_mac_entry->tcam_key),
2070 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32],
2072 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2073 sizeof(u32) * DSAF_PORT_MSK_NUM)) {
2074 mac_entry.port_num = mac_id;
2075 if (hns_dsaf_del_mac_mc_port(dsaf_dev,
2087 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2090 struct dsaf_device *dsaf_dev;
2092 dsaf_dev = devm_kzalloc(dev,
2093 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2094 if (unlikely(!dsaf_dev)) {
2095 dsaf_dev = ERR_PTR(-ENOMEM);
2097 dsaf_dev->dev = dev;
2098 dev_set_drvdata(dev, dsaf_dev);
2105 * hns_dsaf_free_dev - free dev mem
2106 * @dev: struct device pointer
2108 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2110 (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2114 * dsaf_pfc_unit_cnt - set pfc unit count
2115 * @dsaf_id: dsa fabric id
2116 * @pport_rate: value array
2117 * @pdsaf_pfc_unit_cnt: value array
2119 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id,
2120 enum dsaf_port_rate_mode rate)
2125 case DSAF_PORT_RATE_10000:
2126 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2128 case DSAF_PORT_RATE_1000:
2129 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2131 case DSAF_PORT_RATE_2500:
2132 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2135 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2138 dsaf_set_dev_field(dsaf_dev,
2139 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2140 DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2145 * dsaf_port_work_rate_cfg - fifo
2146 * @dsaf_id: dsa fabric id
2150 hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2151 enum dsaf_port_rate_mode rate_mode)
2155 port_work_mode = dsaf_read_dev(
2156 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2158 if (rate_mode == DSAF_PORT_RATE_10000)
2159 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2161 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2163 dsaf_write_dev(dsaf_dev,
2164 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2167 hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2171 * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2172 * @mac_cb: mac contrl block
2174 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2176 enum dsaf_port_rate_mode mode;
2177 struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2178 int mac_id = mac_cb->mac_id;
2180 if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2182 if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2183 mode = DSAF_PORT_RATE_10000;
2185 mode = DSAF_PORT_RATE_1000;
2187 hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2190 static u32 hns_dsaf_get_inode_prio_reg(int index)
2192 int base_index, offset;
2193 u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2195 base_index = (index + 1) / DSAF_REG_PER_ZONE;
2196 offset = (index + 1) % DSAF_REG_PER_ZONE;
2198 return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2199 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2202 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2204 struct dsaf_hw_stats *hw_stats
2205 = &dsaf_dev->hw_stats[node_num];
2206 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2210 hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2211 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2212 hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2213 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2214 hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2215 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2216 hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2217 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2219 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2220 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2221 hw_stats->rx_pause_frame +=
2222 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2224 hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2225 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2226 hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2227 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2228 hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2229 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2230 hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2231 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2232 hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2233 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2234 hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2235 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2237 hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2238 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 4 * (u64)node_num);
2239 hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2240 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 4 * (u64)node_num);
2242 /* pfc pause frame statistics stored in dsaf inode*/
2243 if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2244 for (i = 0; i < DSAF_PRIO_NR; i++) {
2245 reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2246 hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2247 reg_tmp + 0x4 * (u64)node_num);
2248 hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2249 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2250 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2251 0xF0 * (u64)node_num);
2254 hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2255 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2259 *hns_dsaf_get_regs - dump dsaf regs
2260 *@dsaf_dev: dsaf device
2261 *@data:data for value of regs
2263 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2269 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2271 /* dsaf common registers */
2272 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2273 p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2274 p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2275 p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2276 p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2277 p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2278 p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2279 p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2280 p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2282 p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2283 p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2284 p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2285 p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2286 p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2287 p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2288 p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2289 p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2290 p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2291 p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2292 p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2293 p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2294 p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2295 p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2296 p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2298 for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2299 p[24 + i] = dsaf_read_dev(ddev,
2300 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2302 p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2304 for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2305 p[33 + i] = dsaf_read_dev(ddev,
2306 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2308 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2309 p[41 + i] = dsaf_read_dev(ddev,
2310 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2312 /* dsaf inode registers */
2313 p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2315 p[171] = dsaf_read_dev(ddev,
2316 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2318 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2319 j = i * DSAF_COMM_CHN + port;
2320 p[172 + i] = dsaf_read_dev(ddev,
2321 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2322 p[175 + i] = dsaf_read_dev(ddev,
2323 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2324 p[178 + i] = dsaf_read_dev(ddev,
2325 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2326 p[181 + i] = dsaf_read_dev(ddev,
2327 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2328 p[184 + i] = dsaf_read_dev(ddev,
2329 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2330 p[187 + i] = dsaf_read_dev(ddev,
2331 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2332 p[190 + i] = dsaf_read_dev(ddev,
2333 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2334 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2335 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2336 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2337 p[196 + i] = dsaf_read_dev(ddev,
2338 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2339 p[199 + i] = dsaf_read_dev(ddev,
2340 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2341 p[202 + i] = dsaf_read_dev(ddev,
2342 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2343 p[205 + i] = dsaf_read_dev(ddev,
2344 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2345 p[208 + i] = dsaf_read_dev(ddev,
2346 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2347 p[211 + i] = dsaf_read_dev(ddev,
2348 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2349 p[214 + i] = dsaf_read_dev(ddev,
2350 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2351 p[217 + i] = dsaf_read_dev(ddev,
2352 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2353 p[220 + i] = dsaf_read_dev(ddev,
2354 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2355 p[223 + i] = dsaf_read_dev(ddev,
2356 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2357 p[226 + i] = dsaf_read_dev(ddev,
2358 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2361 p[229] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2363 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2364 j = i * DSAF_COMM_CHN + port;
2365 p[230 + i] = dsaf_read_dev(ddev,
2366 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2369 p[233] = dsaf_read_dev(ddev,
2370 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80);
2372 /* dsaf inode registers */
2373 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2374 j = i * DSAF_COMM_CHN + port;
2375 p[234 + i] = dsaf_read_dev(ddev,
2376 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2377 p[237 + i] = dsaf_read_dev(ddev,
2378 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2379 p[240 + i] = dsaf_read_dev(ddev,
2380 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2381 p[243 + i] = dsaf_read_dev(ddev,
2382 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2383 p[246 + i] = dsaf_read_dev(ddev,
2384 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2385 p[249 + i] = dsaf_read_dev(ddev,
2386 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2387 p[252 + i] = dsaf_read_dev(ddev,
2388 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2389 p[255 + i] = dsaf_read_dev(ddev,
2390 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2391 p[258 + i] = dsaf_read_dev(ddev,
2392 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2393 p[261 + i] = dsaf_read_dev(ddev,
2394 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2395 p[264 + i] = dsaf_read_dev(ddev,
2396 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2397 p[267 + i] = dsaf_read_dev(ddev,
2398 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2399 p[270 + i] = dsaf_read_dev(ddev,
2400 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2401 p[273 + i] = dsaf_read_dev(ddev,
2402 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2403 p[276 + i] = dsaf_read_dev(ddev,
2404 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2405 p[279 + i] = dsaf_read_dev(ddev,
2406 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2407 p[282 + i] = dsaf_read_dev(ddev,
2408 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2409 p[285 + i] = dsaf_read_dev(ddev,
2410 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2411 p[288 + i] = dsaf_read_dev(ddev,
2412 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2413 p[291 + i] = dsaf_read_dev(ddev,
2414 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2415 p[294 + i] = dsaf_read_dev(ddev,
2416 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2417 p[297 + i] = dsaf_read_dev(ddev,
2418 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2419 p[300 + i] = dsaf_read_dev(ddev,
2420 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2421 p[303 + i] = dsaf_read_dev(ddev,
2422 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2423 p[306 + i] = dsaf_read_dev(ddev,
2424 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2425 p[309 + i] = dsaf_read_dev(ddev,
2426 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2427 p[312 + i] = dsaf_read_dev(ddev,
2428 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2431 /* dsaf onode registers */
2432 for (i = 0; i < DSAF_XOD_NUM; i++) {
2433 p[315 + i] = dsaf_read_dev(ddev,
2434 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2435 p[323 + i] = dsaf_read_dev(ddev,
2436 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2437 p[331 + i] = dsaf_read_dev(ddev,
2438 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2439 p[339 + i] = dsaf_read_dev(ddev,
2440 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2441 p[347 + i] = dsaf_read_dev(ddev,
2442 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2443 p[355 + i] = dsaf_read_dev(ddev,
2444 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2447 p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2448 p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2449 p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2451 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2452 j = i * DSAF_COMM_CHN + port;
2453 p[366 + i] = dsaf_read_dev(ddev,
2454 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2455 p[369 + i] = dsaf_read_dev(ddev,
2456 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2457 p[372 + i] = dsaf_read_dev(ddev,
2458 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2459 p[375 + i] = dsaf_read_dev(ddev,
2460 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2461 p[378 + i] = dsaf_read_dev(ddev,
2462 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2463 p[381 + i] = dsaf_read_dev(ddev,
2464 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2465 p[384 + i] = dsaf_read_dev(ddev,
2466 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2467 p[387 + i] = dsaf_read_dev(ddev,
2468 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2469 p[390 + i] = dsaf_read_dev(ddev,
2470 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2471 p[393 + i] = dsaf_read_dev(ddev,
2472 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2475 p[396] = dsaf_read_dev(ddev,
2476 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2477 p[397] = dsaf_read_dev(ddev,
2478 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2479 p[398] = dsaf_read_dev(ddev,
2480 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2481 p[399] = dsaf_read_dev(ddev,
2482 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2483 p[400] = dsaf_read_dev(ddev,
2484 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2485 p[401] = dsaf_read_dev(ddev,
2486 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2487 p[402] = dsaf_read_dev(ddev,
2488 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2489 p[403] = dsaf_read_dev(ddev,
2490 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2491 p[404] = dsaf_read_dev(ddev,
2492 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2493 p[405] = dsaf_read_dev(ddev,
2494 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2495 p[406] = dsaf_read_dev(ddev,
2496 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2497 p[407] = dsaf_read_dev(ddev,
2498 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2499 p[408] = dsaf_read_dev(ddev,
2500 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2502 /* dsaf voq registers */
2503 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2504 j = (i * DSAF_COMM_CHN + port) * 0x90;
2505 p[409 + i] = dsaf_read_dev(ddev,
2506 DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2507 p[412 + i] = dsaf_read_dev(ddev,
2508 DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2509 p[415 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2510 p[418 + i] = dsaf_read_dev(ddev,
2511 DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2512 p[421 + i] = dsaf_read_dev(ddev,
2513 DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2514 p[424 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2515 p[427 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2516 p[430 + i] = dsaf_read_dev(ddev,
2517 DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2518 p[433 + i] = dsaf_read_dev(ddev,
2519 DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2520 p[436 + i] = dsaf_read_dev(ddev,
2521 DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2522 p[439 + i] = dsaf_read_dev(ddev,
2523 DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2524 p[442 + i] = dsaf_read_dev(ddev,
2525 DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2528 /* dsaf tbl registers */
2529 p[445] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2530 p[446] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2531 p[447] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2532 p[448] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2533 p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2534 p[450] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2535 p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2536 p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2537 p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2538 p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2539 p[455] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2540 p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2541 p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2542 p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2543 p[459] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2544 p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2545 p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2546 p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2547 p[463] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2548 p[464] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2549 p[465] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2550 p[466] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2551 p[467] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2553 for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2555 p[468 + 2 * i] = dsaf_read_dev(ddev,
2556 DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2557 p[469 + 2 * i] = dsaf_read_dev(ddev,
2558 DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2561 p[484] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2562 p[485] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2563 p[486] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2564 p[487] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2565 p[488] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2566 p[489] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2567 p[490] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2568 p[491] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2569 p[492] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2570 p[493] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2571 p[494] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2572 p[495] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2574 /* dsaf other registers */
2575 p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2576 p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2577 p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2578 p[499] = dsaf_read_dev(ddev,
2579 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2580 p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2581 p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2584 p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2586 /* mark end of dsaf regs */
2587 for (i = 503; i < 504; i++)
2591 static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2592 struct dsaf_device *dsaf_dev)
2596 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2598 snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2599 buff += ETH_GSTRING_LEN;
2600 snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2601 buff += ETH_GSTRING_LEN;
2602 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2603 buff += ETH_GSTRING_LEN;
2604 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2605 buff += ETH_GSTRING_LEN;
2606 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2607 buff += ETH_GSTRING_LEN;
2608 snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2609 buff += ETH_GSTRING_LEN;
2610 snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2611 buff += ETH_GSTRING_LEN;
2612 snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2613 buff += ETH_GSTRING_LEN;
2614 snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2615 buff += ETH_GSTRING_LEN;
2616 snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2617 buff += ETH_GSTRING_LEN;
2618 snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2619 buff += ETH_GSTRING_LEN;
2620 snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2621 buff += ETH_GSTRING_LEN;
2622 snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2623 buff += ETH_GSTRING_LEN;
2624 if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2625 for (i = 0; i < DSAF_PRIO_NR; i++) {
2626 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2627 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2629 snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2630 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2632 buff += ETH_GSTRING_LEN;
2634 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2636 snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2637 buff += ETH_GSTRING_LEN;
2642 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2647 struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2648 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2650 p[0] = hw_stats->pad_drop;
2651 p[1] = hw_stats->man_pkts;
2652 p[2] = hw_stats->rx_pkts;
2653 p[3] = hw_stats->rx_pkt_id;
2654 p[4] = hw_stats->rx_pause_frame;
2655 p[5] = hw_stats->release_buf_num;
2656 p[6] = hw_stats->sbm_drop;
2657 p[7] = hw_stats->crc_false;
2658 p[8] = hw_stats->bp_drop;
2659 p[9] = hw_stats->rslt_drop;
2660 p[10] = hw_stats->local_addr_false;
2661 p[11] = hw_stats->vlan_drop;
2662 p[12] = hw_stats->stp_drop;
2663 if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2664 for (i = 0; i < DSAF_PRIO_NR; i++) {
2665 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2666 p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2668 p[29] = hw_stats->tx_pkts;
2672 p[13] = hw_stats->tx_pkts;
2677 *hns_dsaf_get_stats - get dsaf statistic
2679 *@data:statistic value
2682 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2685 int node_num = port;
2687 /* for ge/xge node info */
2688 p = hns_dsaf_get_node_stats(ddev, p, node_num);
2690 /* for ppe node info */
2691 node_num = port + DSAF_PPE_INODE_BASE;
2692 (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2696 *hns_dsaf_get_sset_count - get dsaf string set count
2697 *@stringset: type of values in data
2698 *return dsaf string name count
2700 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2702 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2704 if (stringset == ETH_SS_STATS) {
2706 return DSAF_STATIC_NUM;
2708 return DSAF_V2_STATIC_NUM;
2714 *hns_dsaf_get_strings - get dsaf string set
2715 *@stringset:srting set index
2716 *@data:strings name value
2719 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2720 struct dsaf_device *dsaf_dev)
2722 char *buff = (char *)data;
2725 if (stringset != ETH_SS_STATS)
2728 /* for ge/xge node info */
2729 buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2731 /* for ppe node info */
2732 node = port + DSAF_PPE_INODE_BASE;
2733 (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2737 *hns_dsaf_get_sset_count - get dsaf regs count
2738 *return dsaf regs count
2740 int hns_dsaf_get_regs_count(void)
2742 return DSAF_DUMP_REGS_NUM;
2745 static int hns_dsaf_get_port_id(u8 port)
2747 if (port < DSAF_SERVICE_NW_NUM)
2750 if (port >= DSAF_BASE_INNER_PORT_NUM)
2751 return port - DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
2756 static void set_promisc_tcam_enable(struct dsaf_device *dsaf_dev, u32 port)
2758 struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 1, 0, 0, 0x80};
2759 struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2760 struct dsaf_tbl_tcam_data tbl_tcam_mask_uc = {0x01000000, 0xf};
2761 struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2762 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2763 struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, port};
2764 struct dsaf_drv_mac_single_dest_entry mask_entry;
2765 struct dsaf_drv_tbl_tcam_key temp_key, mask_key;
2766 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2767 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
2768 struct dsaf_drv_tbl_tcam_key mac_key;
2769 struct hns_mac_cb *mac_cb;
2770 u8 addr[ETH_ALEN] = {0};
2774 /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2775 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2776 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2777 if (entry_index != DSAF_INVALID_ENTRY_IDX)
2780 /* put promisc tcam entry in the end. */
2781 /* 1. set promisc unicast vague tcam entry. */
2782 entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2783 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2784 dev_err(dsaf_dev->dev,
2785 "enable uc promisc failed (port:%#x)\n",
2790 mac_cb = dsaf_dev->mac_cb[port];
2791 (void)hns_mac_get_inner_port_num(mac_cb, 0, &port_num);
2792 tbl_tcam_ucast.tbl_ucast_out_port = port_num;
2794 /* config uc vague table */
2795 hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2796 &tbl_tcam_mask_uc, &tbl_tcam_ucast);
2798 /* update software entry */
2799 soft_mac_entry = priv->soft_mac_tbl;
2800 soft_mac_entry += entry_index;
2801 soft_mac_entry->index = entry_index;
2802 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
2803 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
2804 /* step back to the START for mc. */
2805 soft_mac_entry = priv->soft_mac_tbl;
2807 /* 2. set promisc multicast vague tcam entry. */
2808 entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2809 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2810 dev_err(dsaf_dev->dev,
2811 "enable mc promisc failed (port:%#x)\n",
2816 memset(&mask_entry, 0x0, sizeof(mask_entry));
2817 memset(&mask_key, 0x0, sizeof(mask_key));
2818 memset(&temp_key, 0x0, sizeof(temp_key));
2819 mask_entry.addr[0] = 0x01;
2820 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, mask_entry.in_vlan_id,
2821 0xf, mask_entry.addr);
2822 tbl_tcam_mcast.tbl_mcast_item_vld = 1;
2823 tbl_tcam_mcast.tbl_mcast_old_en = 0;
2825 /* set MAC port to handle multicast */
2826 mskid = hns_dsaf_get_port_id(port);
2827 if (mskid == -EINVAL) {
2828 dev_err(dsaf_dev->dev, "%s,pnum(%d)error,key(%#x:%#x)\n",
2829 dsaf_dev->ae_dev.name, port,
2830 mask_key.high.val, mask_key.low.val);
2833 dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2836 /* set pool bit map to handle multicast */
2837 mskid = hns_dsaf_get_port_id(port_num);
2838 if (mskid == -EINVAL) {
2839 dev_err(dsaf_dev->dev,
2840 "%s, pool bit map pnum(%d)error,key(%#x:%#x)\n",
2841 dsaf_dev->ae_dev.name, port_num,
2842 mask_key.high.val, mask_key.low.val);
2845 dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2848 memcpy(&temp_key, &mask_key, sizeof(mask_key));
2849 hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2850 (struct dsaf_tbl_tcam_data *)(&mask_key),
2853 /* update software entry */
2854 soft_mac_entry += entry_index;
2855 soft_mac_entry->index = entry_index;
2856 soft_mac_entry->tcam_key.high.val = temp_key.high.val;
2857 soft_mac_entry->tcam_key.low.val = temp_key.low.val;
2860 static void set_promisc_tcam_disable(struct dsaf_device *dsaf_dev, u32 port)
2862 struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2863 struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 0, 0, 0, 0};
2864 struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2865 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2866 struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, 0};
2867 struct dsaf_tbl_tcam_data tbl_tcam_mask = {0, 0};
2868 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2869 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
2870 struct dsaf_drv_tbl_tcam_key mac_key;
2871 u8 addr[ETH_ALEN] = {0};
2873 /* 1. delete uc vague tcam entry. */
2874 /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2875 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2876 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2878 if (entry_index == DSAF_INVALID_ENTRY_IDX)
2881 /* config uc vague table */
2882 hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2883 &tbl_tcam_mask, &tbl_tcam_ucast);
2884 /* update soft management table. */
2885 soft_mac_entry = priv->soft_mac_tbl;
2886 soft_mac_entry += entry_index;
2887 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2888 /* step back to the START for mc. */
2889 soft_mac_entry = priv->soft_mac_tbl;
2891 /* 2. delete mc vague tcam entry. */
2893 memset(&mac_key, 0x0, sizeof(mac_key));
2894 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2895 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2897 if (entry_index == DSAF_INVALID_ENTRY_IDX)
2900 /* config mc vague table */
2901 hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2902 &tbl_tcam_mask, &tbl_tcam_mcast);
2903 /* update soft management table. */
2904 soft_mac_entry += entry_index;
2905 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2908 /* Reserve the last TCAM entry for promisc support */
2909 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
2910 u32 port, bool enable)
2913 set_promisc_tcam_enable(dsaf_dev, port);
2915 set_promisc_tcam_disable(dsaf_dev, port);
2918 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port)
2923 if (port >= DSAF_SERVICE_NW_NUM)
2927 while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
2928 val = dsaf_read_dev(dsaf_dev, DSAF_VOQ_IN_PKT_NUM_0_REG +
2929 (port + DSAF_XGE_NUM) * 0x40);
2930 val_tmp = dsaf_read_dev(dsaf_dev, DSAF_VOQ_OUT_PKT_NUM_0_REG +
2931 (port + DSAF_XGE_NUM) * 0x40);
2935 usleep_range(100, 200);
2938 if (wait_cnt >= HNS_MAX_WAIT_CNT) {
2939 dev_err(dsaf_dev->dev, "hns dsaf clean wait timeout(%u - %u).\n",
2948 * dsaf_probe - probo dsaf dev
2949 * @pdev: dasf platform device
2950 * retuen 0 - success , negative --fail
2952 static int hns_dsaf_probe(struct platform_device *pdev)
2954 struct dsaf_device *dsaf_dev;
2957 dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2958 if (IS_ERR(dsaf_dev)) {
2959 ret = PTR_ERR(dsaf_dev);
2961 "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2965 ret = hns_dsaf_get_cfg(dsaf_dev);
2969 ret = hns_dsaf_init(dsaf_dev);
2973 ret = hns_mac_init(dsaf_dev);
2977 ret = hns_ppe_init(dsaf_dev);
2981 ret = hns_dsaf_ae_init(dsaf_dev);
2988 hns_ppe_uninit(dsaf_dev);
2991 hns_mac_uninit(dsaf_dev);
2994 hns_dsaf_free(dsaf_dev);
2997 hns_dsaf_free_dev(dsaf_dev);
3003 * dsaf_remove - remove dsaf dev
3004 * @pdev: dasf platform device
3006 static int hns_dsaf_remove(struct platform_device *pdev)
3008 struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
3010 hns_dsaf_ae_uninit(dsaf_dev);
3012 hns_ppe_uninit(dsaf_dev);
3014 hns_mac_uninit(dsaf_dev);
3016 hns_dsaf_free(dsaf_dev);
3018 hns_dsaf_free_dev(dsaf_dev);
3023 static const struct of_device_id g_dsaf_match[] = {
3024 {.compatible = "hisilicon,hns-dsaf-v1"},
3025 {.compatible = "hisilicon,hns-dsaf-v2"},
3028 MODULE_DEVICE_TABLE(of, g_dsaf_match);
3030 static struct platform_driver g_dsaf_driver = {
3031 .probe = hns_dsaf_probe,
3032 .remove = hns_dsaf_remove,
3034 .name = DSAF_DRV_NAME,
3035 .of_match_table = g_dsaf_match,
3036 .acpi_match_table = hns_dsaf_acpi_match,
3040 module_platform_driver(g_dsaf_driver);
3043 * hns_dsaf_roce_reset - reset dsaf and roce
3044 * @dsaf_fwnode: Pointer to framework node for the dasf
3045 * @enable: false - request reset , true - drop reset
3046 * retuen 0 - success , negative -fail
3048 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
3050 struct dsaf_device *dsaf_dev;
3051 struct platform_device *pdev;
3056 const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3057 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3058 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3059 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3060 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3061 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3062 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3063 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3064 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3066 const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3067 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3068 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3069 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3070 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3071 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3072 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3073 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3074 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3077 /* find the platform device corresponding to fwnode */
3078 if (is_of_node(dsaf_fwnode)) {
3079 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
3080 } else if (is_acpi_device_node(dsaf_fwnode)) {
3081 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
3083 pr_err("fwnode is neither OF or ACPI type\n");
3087 /* check if we were a success in fetching pdev */
3089 pr_err("couldn't find platform device for node\n");
3093 /* retrieve the dsaf_device from the driver data */
3094 dsaf_dev = dev_get_drvdata(&pdev->dev);
3096 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
3097 put_device(&pdev->dev);
3101 /* now, make sure we are running on compatible SoC */
3102 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
3103 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
3104 dsaf_dev->ae_dev.name);
3105 put_device(&pdev->dev);
3109 /* do reset or de-reset according to the flag */
3111 /* reset rocee-channels in dsaf and rocee */
3112 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3114 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
3116 /* configure dsaf tx roce correspond to port map and sl map */
3117 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
3118 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3119 dsaf_set_field(mp, 7 << i * 3, i * 3,
3120 port_map[i][DSAF_ROCE_6PORT_MODE]);
3121 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
3122 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
3124 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
3125 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3126 dsaf_set_field(sl, 3 << i * 2, i * 2,
3127 sl_map[i][DSAF_ROCE_6PORT_MODE]);
3128 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
3130 /* de-reset rocee-channels in dsaf and rocee */
3131 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3133 msleep(SRST_TIME_INTERVAL);
3134 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
3136 /* enable dsaf channel rocee credit */
3137 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
3138 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
3139 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3141 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
3142 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3145 put_device(&pdev->dev);
3149 EXPORT_SYMBOL(hns_dsaf_roce_reset);
3151 MODULE_LICENSE("GPL");
3152 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3153 MODULE_DESCRIPTION("HNS DSAF driver");
3154 MODULE_VERSION(DSAF_MOD_VERSION);