drivers/net/ethernet/freescale/ucc_geth.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
   4  *
   5  * Author: Shlomi Gridish <gridish@freescale.com>
   6  *
   7  * Description:
   8  * Internal header file for UCC Gigabit Ethernet unit routines.
   9  *
  10  * Changelog:
  11  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  12  * - Rearrange code and style fixes
  13  */
  14 #ifndef __UCC_GETH_H__
  15 #define __UCC_GETH_H__
  16
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/if_ether.h>
  20
  21 #include <soc/fsl/qe/immap_qe.h>
  22 #include <soc/fsl/qe/qe.h>
  23
  24 #include <soc/fsl/qe/ucc.h>
  25 #include <soc/fsl/qe/ucc_fast.h>
  26
  27 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
  28 #define DRV_NAME "ucc_geth"
  29
  30 #define NUM_TX_QUEUES                   8
  31 #define NUM_RX_QUEUES                   8
  32 #define NUM_BDS_IN_PREFETCHED_BDS       4
  33 #define TX_IP_OFFSET_ENTRY_MAX          8
  34 #define NUM_OF_PADDRS                   4
  35 #define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
  36 #define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
  37
  38 struct ucc_geth {
  39         struct ucc_fast uccf;
  40         u8 res0[0x100 - sizeof(struct ucc_fast)];
  41
  42         u32 maccfg1;            /* mac configuration reg. 1 */
  43         u32 maccfg2;            /* mac configuration reg. 2 */
  44         u32 ipgifg;             /* interframe gap reg.  */
  45         u32 hafdup;             /* half-duplex reg.  */
  46         u8 res1[0x10];
  47         u8 miimng[0x18];        /* MII management structure moved to _mii.h */
  48         u32 ifctl;              /* interface control reg */
  49         u32 ifstat;             /* interface statux reg */
  50         u32 macstnaddr1;        /* mac station address part 1 reg */
  51         u32 macstnaddr2;        /* mac station address part 2 reg */
  52         u8 res2[0x8];
  53         u32 uempr;              /* UCC Ethernet Mac parameter reg */
  54         u32 utbipar;            /* UCC tbi address reg */
  55         u16 uescr;              /* UCC Ethernet statistics control reg */
  56         u8 res3[0x180 - 0x15A];
  57         u32 tx64;               /* Total number of frames (including bad
  58                                    frames) transmitted that were exactly of the
  59                                    minimal length (64 for un tagged, 68 for
  60                                    tagged, or with length exactly equal to the
  61                                    parameter MINLength */
  62         u32 tx127;              /* Total number of frames (including bad
  63                                    frames) transmitted that were between
  64                                    MINLength (Including FCS length==4) and 127
  65                                    octets */
  66         u32 tx255;              /* Total number of frames (including bad
  67                                    frames) transmitted that were between 128
  68                                    (Including FCS length==4) and 255 octets */
  69         u32 rx64;               /* Total number of frames received including
  70                                    bad frames that were exactly of the mninimal
  71                                    length (64 bytes) */
  72         u32 rx127;              /* Total number of frames (including bad
  73                                    frames) received that were between MINLength
  74                                    (Including FCS length==4) and 127 octets */
  75         u32 rx255;              /* Total number of frames (including bad
  76                                    frames) received that were between 128
  77                                    (Including FCS length==4) and 255 octets */
  78         u32 txok;               /* Total number of octets residing in frames
  79                                    that where involved in successful
  80                                    transmission */
  81         u16 txcf;               /* Total number of PAUSE control frames
  82                                    transmitted by this MAC */
  83         u8 res4[0x2];
  84         u32 tmca;               /* Total number of frames that were transmitted
  85                                    successfully with the group address bit set
  86                                    that are not broadcast frames */
  87         u32 tbca;               /* Total number of frames transmitted
  88                                    successfully that had destination address
  89                                    field equal to the broadcast address */
  90         u32 rxfok;              /* Total number of frames received OK */
  91         u32 rxbok;              /* Total number of octets received OK */
  92         u32 rbyt;               /* Total number of octets received including
  93                                    octets in bad frames. Must be implemented in
  94                                    HW because it includes octets in frames that
  95                                    never even reach the UCC */
  96         u32 rmca;               /* Total number of frames that were received
  97                                    successfully with the group address bit set
  98                                    that are not broadcast frames */
  99         u32 rbca;               /* Total number of frames received successfully
 100                                    that had destination address equal to the
 101                                    broadcast address */
 102         u32 scar;               /* Statistics carry register */
 103         u32 scam;               /* Statistics caryy mask register */
 104         u8 res5[0x200 - 0x1c4];
 105 } __packed;
 106
 107 /* UCC GETH TEMODR Register */
 108 #define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100  /* enable Tx statistics
 109                                                          */
 110 #define TEMODER_SCHEDULER_ENABLE                0x2000  /* enable scheduler */
 111 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400  /* generate IPv4
 112                                                            checksums */
 113 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200  /* enable performance
 114                                                            optimization
 115                                                            enhancement (mode1) */
 116 #define TEMODER_RMON_STATISTICS                 0x0100  /* enable tx statistics
 117                                                          */
 118 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15) /* Number of queues <<
 119                                                            shift */
 120
 121 /* UCC GETH TEMODR Register */
 122 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000      /* enable Rx
 123                                                                    statistics */
 124 #define REMODER_RX_EXTENDED_FEATURES            0x80000000      /* enable
 125                                                                    extended
 126                                                                    features */
 127 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 ) /* vlan operation
 128                                                            tagged << shift */
 129 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
 130                                                            tagged << shift */
 131 #define REMODER_RX_QOS_MODE_SHIFT               (31-15) /* rx QoS mode << shift
 132                                                          */
 133 #define REMODER_RMON_STATISTICS                 0x00001000      /* enable rx
 134                                                                    statistics */
 135 #define REMODER_RX_EXTENDED_FILTERING           0x00000800      /* extended
 136                                                                    filtering
 137                                                                    vs.
 138                                                                    mpc82xx-like
 139                                                                    filtering */
 140 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23) /* Number of queues <<
 141                                                            shift */
 142 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008      /* enable
 143                                                                    dynamic max
 144                                                                    frame length
 145                                                                  */
 146 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004      /* enable
 147                                                                    dynamic min
 148                                                                    frame length
 149                                                                  */
 150 #define REMODER_IP_CHECKSUM_CHECK               0x00000002      /* check IPv4
 151                                                                    checksums */
 152 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001      /* align ip
 153                                                                    address to
 154                                                                    4-byte
 155                                                                    boundary */
 156
 157 /* UCC GETH Event Register */
 158 #define UCCE_TXB   (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
 159                     UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
 160                     UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
 161                     UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
 162
 163 #define UCCE_RXB   (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
 164                     UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
 165                     UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
 166                     UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
 167
 168 #define UCCE_RXF   (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
 169                     UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
 170                     UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
 171                     UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
 172
 173 #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
 174                     UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
 175                     UCC_GETH_UCCE_RXC  | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
 176
 177 #define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
 178 #define UCCE_TX_EVENTS  (UCCE_TXB | UCC_GETH_UCCE_TXE)
 179
 180 /* TBI defines */
 181 #define ENET_TBI_MII_CR         0x00    /* Control */
 182 #define ENET_TBI_MII_SR         0x01    /* Status */
 183 #define ENET_TBI_MII_ANA        0x04    /* AN advertisement */
 184 #define ENET_TBI_MII_ANLPBPA    0x05    /* AN link partner base page ability */
 185 #define ENET_TBI_MII_ANEX       0x06    /* AN expansion */
 186 #define ENET_TBI_MII_ANNPT      0x07    /* AN next page transmit */
 187 #define ENET_TBI_MII_ANLPANP    0x08    /* AN link partner ability next page */
 188 #define ENET_TBI_MII_EXST       0x0F    /* Extended status */
 189 #define ENET_TBI_MII_JD         0x10    /* Jitter diagnostics */
 190 #define ENET_TBI_MII_TBICON     0x11    /* TBI control */
 191
 192 /* TBI MDIO register bit fields*/
 193 #define TBISR_LSTATUS          0x0004
 194 #define TBICON_CLK_SELECT       0x0020
 195 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
 196 #define TBIANA_SYMMETRIC_PAUSE  0x0080
 197 #define TBIANA_HALF_DUPLEX      0x0040
 198 #define TBIANA_FULL_DUPLEX      0x0020
 199 #define TBICR_PHY_RESET         0x8000
 200 #define TBICR_ANEG_ENABLE       0x1000
 201 #define TBICR_RESTART_ANEG      0x0200
 202 #define TBICR_FULL_DUPLEX       0x0100
 203 #define TBICR_SPEED1_SET        0x0040
 204
 205 #define TBIANA_SETTINGS ( \
 206                 TBIANA_ASYMMETRIC_PAUSE \
 207                 | TBIANA_SYMMETRIC_PAUSE \
 208                 | TBIANA_FULL_DUPLEX \
 209                 )
 210 #define TBICR_SETTINGS ( \
 211                 TBICR_PHY_RESET \
 212                 | TBICR_ANEG_ENABLE \
 213                 | TBICR_FULL_DUPLEX \
 214                 | TBICR_SPEED1_SET \
 215                 )
 216
 217 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
 218 #define MACCFG1_FLOW_RX                         0x00000020      /* Flow Control
 219                                                                    Rx */
 220 #define MACCFG1_FLOW_TX                         0x00000010      /* Flow Control
 221                                                                    Tx */
 222 #define MACCFG1_ENABLE_SYNCHED_RX               0x00000008      /* Rx Enable
 223                                                                    synchronized
 224                                                                    to Rx stream
 225                                                                  */
 226 #define MACCFG1_ENABLE_RX                       0x00000004      /* Enable Rx */
 227 #define MACCFG1_ENABLE_SYNCHED_TX               0x00000002      /* Tx Enable
 228                                                                    synchronized
 229                                                                    to Tx stream
 230                                                                  */
 231 #define MACCFG1_ENABLE_TX                       0x00000001      /* Enable Tx */
 232
 233 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
 234 #define MACCFG2_PREL_SHIFT                      (31 - 19)       /* Preamble
 235                                                                    Length <<
 236                                                                    shift */
 237 #define MACCFG2_PREL_MASK                       0x0000f000      /* Preamble
 238                                                                    Length mask */
 239 #define MACCFG2_SRP                             0x00000080      /* Soft Receive
 240                                                                    Preamble */
 241 #define MACCFG2_STP                             0x00000040      /* Soft
 242                                                                    Transmit
 243                                                                    Preamble */
 244 #define MACCFG2_RESERVED_1                      0x00000020      /* Reserved -
 245                                                                    must be set
 246                                                                    to 1 */
 247 #define MACCFG2_LC                              0x00000010      /* Length Check
 248                                                                  */
 249 #define MACCFG2_MPE                             0x00000008      /* Magic packet
 250                                                                    detect */
 251 #define MACCFG2_FDX                             0x00000001      /* Full Duplex */
 252 #define MACCFG2_FDX_MASK                        0x00000001      /* Full Duplex
 253                                                                    mask */
 254 #define MACCFG2_PAD_CRC                         0x00000004
 255 #define MACCFG2_CRC_EN                          0x00000002
 256 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000      /* Neither
 257                                                                    Padding
 258                                                                    short frames
 259                                                                    nor CRC */
 260 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002      /* Append CRC
 261                                                                    only */
 262 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
 263 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100      /* nibble mode
 264                                                                    (MII/RMII/RGMII
 265                                                                    10/100bps) */
 266 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200      /* byte mode
 267                                                                    (GMII/TBI/RTB/RGMII
 268                                                                    1000bps ) */
 269 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300      /* mask
 270                                                                    covering all
 271                                                                    relevant
 272                                                                    bits */
 273
 274 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
 275 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)       /* Non
 276                                                                    back-to-back
 277                                                                    inter frame
 278                                                                    gap part 1.
 279                                                                    << shift */
 280 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)       /* Non
 281                                                                    back-to-back
 282                                                                    inter frame
 283                                                                    gap part 2.
 284                                                                    << shift */
 285 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)       /* Mimimum IFG
 286                                                                    Enforcement
 287                                                                    << shift */
 288 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)       /* back-to-back
 289                                                                    inter frame
 290                                                                    gap << shift
 291                                                                  */
 292 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127     /* Non back-to-back
 293                                                            inter frame gap part
 294                                                            1. max val */
 295 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127     /* Non back-to-back
 296                                                            inter frame gap part
 297                                                            2. max val */
 298 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255     /* Mimimum IFG
 299                                                            Enforcement max val */
 300 #define IPGIFG_BACK_TO_BACK_IFG_MAX             127     /* back-to-back inter
 301                                                            frame gap max val */
 302 #define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
 303 #define IPGIFG_NBTB_IPG_MASK                    0x007F0000
 304 #define IPGIFG_MIN_IFG_MASK                     0x0000FF00
 305 #define IPGIFG_BTB_IPG_MASK                     0x0000007F
 306
 307 /* UCC GETH HAFDUP (Half Duplex Register) */
 308 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)       /* Alternate
 309                                                                    Binary
 310                                                                    Exponential
 311                                                                    Backoff
 312                                                                    Truncation
 313                                                                    << shift */
 314 #define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf     /* Alternate Binary
 315                                                            Exponential Backoff
 316                                                            Truncation max val */
 317 #define HALFDUP_ALT_BEB                         0x00080000      /* Alternate
 318                                                                    Binary
 319                                                                    Exponential
 320                                                                    Backoff */
 321 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000      /* Back
 322                                                                    pressure no
 323                                                                    backoff */
 324 #define HALFDUP_NO_BACKOFF                      0x00020000      /* No Backoff */
 325 #define HALFDUP_EXCESSIVE_DEFER                 0x00010000      /* Excessive
 326                                                                    Defer */
 327 #define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)       /* Maximum
 328                                                                    Retransmission
 329                                                                    << shift */
 330 #define HALFDUP_MAX_RETRANSMISSION_MAX          0xf     /* Maximum
 331                                                            Retransmission max
 332                                                            val */
 333 #define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)       /* Collision
 334                                                                    Window <<
 335                                                                    shift */
 336 #define HALFDUP_COLLISION_WINDOW_MAX            0x3f    /* Collision Window max
 337                                                            val */
 338 #define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
 339 #define HALFDUP_RETRANS_MASK                    0x0000F000
 340 #define HALFDUP_COL_WINDOW_MASK                 0x0000003F
 341
 342 /* UCC GETH UCCS (Ethernet Status Register) */
 343 #define UCCS_BPR                                0x02    /* Back pressure (in
 344                                                            half duplex mode) */
 345 #define UCCS_PAU                                0x02    /* Pause state (in full
 346                                                            duplex mode) */
 347 #define UCCS_MPD                                0x01    /* Magic Packet
 348                                                            Detected */
 349
 350 /* UCC GETH IFSTAT (Interface Status Register) */
 351 #define IFSTAT_EXCESS_DEFER                     0x00000200      /* Excessive
 352                                                                    transmission
 353                                                                    defer */
 354
 355 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
 356 #define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)       /* Station
 357                                                                    address 6th
 358                                                                    octet <<
 359                                                                    shift */
 360 #define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)       /* Station
 361                                                                    address 5th
 362                                                                    octet <<
 363                                                                    shift */
 364 #define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)       /* Station
 365                                                                    address 4th
 366                                                                    octet <<
 367                                                                    shift */
 368 #define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)       /* Station
 369                                                                    address 3rd
 370                                                                    octet <<
 371                                                                    shift */
 372
 373 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
 374 #define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)       /* Station
 375                                                                    address 2nd
 376                                                                    octet <<
 377                                                                    shift */
 378 #define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)       /* Station
 379                                                                    address 1st
 380                                                                    octet <<
 381                                                                    shift */
 382
 383 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
 384 #define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)       /* Pause time
 385                                                                    value <<
 386                                                                    shift */
 387 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)       /* Extended
 388                                                                    pause time
 389                                                                    value <<
 390                                                                    shift */
 391
 392 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
 393 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)       /* Phy address
 394                                                                    << shift */
 395 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f      /* Phy address
 396                                                                    mask */
 397
 398 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
 399 #define UESCR_AUTOZ                             0x8000  /* Automatically zero
 400                                                            addressed
 401                                                            statistical counter
 402                                                            values */
 403 #define UESCR_CLRCNT                            0x4000  /* Clear all statistics
 404                                                            counters */
 405 #define UESCR_MAXCOV_SHIFT                      (15 -  7)       /* Max
 406                                                                    Coalescing
 407                                                                    Value <<
 408                                                                    shift */
 409 #define UESCR_SCOV_SHIFT                        (15 - 15)       /* Status
 410                                                                    Coalescing
 411                                                                    Value <<
 412                                                                    shift */
 413
 414 /* UCC GETH UDSR (Data Synchronization Register) */
 415 #define UDSR_MAGIC                              0x067E
 416
 417 struct ucc_geth_thread_data_tx {
 418         u8 res0[104];
 419 } __packed;
 420
 421 struct ucc_geth_thread_data_rx {
 422         u8 res0[40];
 423 } __packed;
 424
 425 /* Send Queue Queue-Descriptor */
 426 struct ucc_geth_send_queue_qd {
 427         u32 bd_ring_base;       /* pointer to BD ring base address */
 428         u8 res0[0x8];
 429         u32 last_bd_completed_address;/* initialize to last entry in BD ring */
 430         u8 res1[0x30];
 431 } __packed;
 432
 433 struct ucc_geth_send_queue_mem_region {
 434         struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
 435 } __packed;
 436
 437 struct ucc_geth_thread_tx_pram {
 438         u8 res0[64];
 439 } __packed;
 440
 441 struct ucc_geth_thread_rx_pram {
 442         u8 res0[128];
 443 } __packed;
 444
 445 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
 446 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
 447 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
 448
 449 struct ucc_geth_scheduler {
 450         u16 cpucount0;          /* CPU packet counter */
 451         u16 cpucount1;          /* CPU packet counter */
 452         u16 cecount0;           /* QE packet counter */
 453         u16 cecount1;           /* QE packet counter */
 454         u16 cpucount2;          /* CPU packet counter */
 455         u16 cpucount3;          /* CPU packet counter */
 456         u16 cecount2;           /* QE packet counter */
 457         u16 cecount3;           /* QE packet counter */
 458         u16 cpucount4;          /* CPU packet counter */
 459         u16 cpucount5;          /* CPU packet counter */
 460         u16 cecount4;           /* QE packet counter */
 461         u16 cecount5;           /* QE packet counter */
 462         u16 cpucount6;          /* CPU packet counter */
 463         u16 cpucount7;          /* CPU packet counter */
 464         u16 cecount6;           /* QE packet counter */
 465         u16 cecount7;           /* QE packet counter */
 466         u32 weightstatus[NUM_TX_QUEUES];        /* accumulated weight factor */
 467         u32 rtsrshadow;         /* temporary variable handled by QE */
 468         u32 time;               /* temporary variable handled by QE */
 469         u32 ttl;                /* temporary variable handled by QE */
 470         u32 mblinterval;        /* max burst length interval */
 471         u16 nortsrbytetime;     /* normalized value of byte time in tsr units */
 472         u8 fracsiz;             /* radix 2 log value of denom. of
 473                                    NorTSRByteTime */
 474         u8 res0[1];
 475         u8 strictpriorityq;     /* Strict Priority Mask register */
 476         u8 txasap;              /* Transmit ASAP register */
 477         u8 extrabw;             /* Extra BandWidth register */
 478         u8 oldwfqmask;          /* temporary variable handled by QE */
 479         u8 weightfactor[NUM_TX_QUEUES];
 480                                       /**< weight factor for queues   */
 481         u32 minw;               /* temporary variable handled by QE */
 482         u8 res1[0x70 - 0x64];
 483 } __packed;
 484
 485 struct ucc_geth_tx_firmware_statistics_pram {
 486         u32 sicoltx;            /* single collision */
 487         u32 mulcoltx;           /* multiple collision */
 488         u32 latecoltxfr;        /* late collision */
 489         u32 frabortduecol;      /* frames aborted due to transmit collision */
 490         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 491                                    transmission that are not counted on any
 492                                    other counter */
 493         u32 carriersenseertx;   /* carrier sense error */
 494         u32 frtxok;             /* frames transmitted OK */
 495         u32 txfrexcessivedefer; /* frames with defferal time greater than
 496                                    specified threshold */
 497         u32 txpkts256;          /* total packets (including bad) between 256
 498                                    and 511 octets */
 499         u32 txpkts512;          /* total packets (including bad) between 512
 500                                    and 1023 octets */
 501         u32 txpkts1024;         /* total packets (including bad) between 1024
 502                                    and 1518 octets */
 503         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 504                                    and MAXLength octets */
 505 } __packed;
 506
 507 struct ucc_geth_rx_firmware_statistics_pram {
 508         u32 frrxfcser;          /* frames with crc error */
 509         u32 fraligner;          /* frames with alignment error */
 510         u32 inrangelenrxer;     /* in range length error */
 511         u32 outrangelenrxer;    /* out of range length error */
 512         u32 frtoolong;          /* frame too long */
 513         u32 runt;               /* runt */
 514         u32 verylongevent;      /* very long event */
 515         u32 symbolerror;        /* symbol error */
 516         u32 dropbsy;            /* drop because of BD not ready */
 517         u8 res0[0x8];
 518         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 519                                    or type mismatch) */
 520         u32 underpkts;          /* total frames less than 64 octets */
 521         u32 pkts256;            /* total frames (including bad) between 256 and
 522                                    511 octets */
 523         u32 pkts512;            /* total frames (including bad) between 512 and
 524                                    1023 octets */
 525         u32 pkts1024;           /* total frames (including bad) between 1024
 526                                    and 1518 octets */
 527         u32 pktsjumbo;          /* total frames (including bad) between 1024
 528                                    and MAXLength octets */
 529         u32 frlossinmacer;      /* frames lost because of internal MAC error
 530                                    that is not counted in any other counter */
 531         u32 pausefr;            /* pause frames */
 532         u8 res1[0x4];
 533         u32 removevlan;         /* total frames that had their VLAN tag removed
 534                                  */
 535         u32 replacevlan;        /* total frames that had their VLAN tag
 536                                    replaced */
 537         u32 insertvlan;         /* total frames that had their VLAN tag
 538                                    inserted */
 539 } __packed;
 540
 541 struct ucc_geth_rx_interrupt_coalescing_entry {
 542         u32 interruptcoalescingmaxvalue;        /* interrupt coalescing max
 543                                                    value */
 544         u32 interruptcoalescingcounter; /* interrupt coalescing counter,
 545                                            initialize to
 546                                            interruptcoalescingmaxvalue */
 547 } __packed;
 548
 549 struct ucc_geth_rx_interrupt_coalescing_table {
 550         struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
 551                                        /**< interrupt coalescing entry */
 552 } __packed;
 553
 554 struct ucc_geth_rx_prefetched_bds {
 555         struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];     /* prefetched bd */
 556 } __packed;
 557
 558 struct ucc_geth_rx_bd_queues_entry {
 559         u32 bdbaseptr;          /* BD base pointer */
 560         u32 bdptr;              /* BD pointer */
 561         u32 externalbdbaseptr;  /* external BD base pointer */
 562         u32 externalbdptr;      /* external BD pointer */
 563 } __packed;
 564
 565 struct ucc_geth_tx_global_pram {
 566         u16 temoder;
 567         u8 res0[0x38 - 0x02];
 568         u32 sqptr;              /* a base pointer to send queue memory region */
 569         u32 schedulerbasepointer;       /* a base pointer to scheduler memory
 570                                            region */
 571         u32 txrmonbaseptr;      /* base pointer to Tx RMON statistics counter */
 572         u32 tstate;             /* tx internal state. High byte contains
 573                                    function code */
 574         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
 575         u32 vtagtable[0x8];     /* 8 4-byte VLAN tags */
 576         u32 tqptr;              /* a base pointer to the Tx Queues Memory
 577                                    Region */
 578         u8 res2[0x80 - 0x74];
 579 } __packed;
 580
 581 /* structure representing Extended Filtering Global Parameters in PRAM */
 582 struct ucc_geth_exf_global_pram {
 583         u32 l2pcdptr;           /* individual address filter, high */
 584         u8 res0[0x10 - 0x04];
 585 } __packed;
 586
 587 struct ucc_geth_rx_global_pram {
 588         u32 remoder;            /* ethernet mode reg. */
 589         u32 rqptr;              /* base pointer to the Rx Queues Memory Region*/
 590         u32 res0[0x1];
 591         u8 res1[0x20 - 0xC];
 592         u16 typeorlen;          /* cutoff point less than which, type/len field
 593                                    is considered length */
 594         u8 res2[0x1];
 595         u8 rxgstpack;           /* acknowledgement on GRACEFUL STOP RX command*/
 596         u32 rxrmonbaseptr;      /* base pointer to Rx RMON statistics counter */
 597         u8 res3[0x30 - 0x28];
 598         u32 intcoalescingptr;   /* Interrupt coalescing table pointer */
 599         u8 res4[0x36 - 0x34];
 600         u8 rstate;              /* rx internal state. High byte contains
 601                                    function code */
 602         u8 res5[0x46 - 0x37];
 603         u16 mrblr;              /* max receive buffer length reg. */
 604         u32 rbdqptr;            /* base pointer to RxBD parameter table
 605                                    description */
 606         u16 mflr;               /* max frame length reg. */
 607         u16 minflr;             /* min frame length reg. */
 608         u16 maxd1;              /* max dma1 length reg. */
 609         u16 maxd2;              /* max dma2 length reg. */
 610         u32 ecamptr;            /* external CAM address */
 611         u32 l2qt;               /* VLAN priority mapping table. */
 612         u32 l3qt[0x8];          /* IP priority mapping table. */
 613         u16 vlantype;           /* vlan type */
 614         u16 vlantci;            /* default vlan tci */
 615         u8 addressfiltering[64];        /* address filtering data structure */
 616         u32 exfGlobalParam;     /* base address for extended filtering global
 617                                    parameters */
 618         u8 res6[0x100 - 0xC4];  /* Initialize to zero */
 619 } __packed;
 620
 621 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 622
 623 /* structure representing InitEnet command */
 624 struct ucc_geth_init_pram {
 625         u8 resinit1;
 626         u8 resinit2;
 627         u8 resinit3;
 628         u8 resinit4;
 629         u16 resinit5;
 630         u8 res1[0x1];
 631         u8 largestexternallookupkeysize;
 632         u32 rgftgfrxglobal;
 633         u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];   /* rx threads */
 634         u8 res2[0x38 - 0x30];
 635         u32 txglobal;           /* tx global */
 636         u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];   /* tx threads */
 637         u8 res3[0x1];
 638 } __packed;
 639
 640 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 641 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 642
 643 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 644 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 645 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 646 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 647
 648 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
 649 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
 650 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
 651 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
 652 #define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
 653
 654 /* structure representing 82xx Address Filtering Enet Address in PRAM */
 655 struct ucc_geth_82xx_enet_address {
 656         u8 res1[0x2];
 657         u16 h;                  /* address (MSB) */
 658         u16 m;                  /* address */
 659         u16 l;                  /* address (LSB) */
 660 } __packed;
 661
 662 /* structure representing 82xx Address Filtering PRAM */
 663 struct ucc_geth_82xx_address_filtering_pram {
 664         u32 iaddr_h;            /* individual address filter, high */
 665         u32 iaddr_l;            /* individual address filter, low */
 666         u32 gaddr_h;            /* group address filter, high */
 667         u32 gaddr_l;            /* group address filter, low */
 668         struct ucc_geth_82xx_enet_address __iomem taddr;
 669         struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
 670         u8 res0[0x40 - 0x38];
 671 } __packed;
 672
 673 /* GETH Tx firmware statistics structure, used when calling
 674    UCC_GETH_GetStatistics. */
 675 struct ucc_geth_tx_firmware_statistics {
 676         u32 sicoltx;            /* single collision */
 677         u32 mulcoltx;           /* multiple collision */
 678         u32 latecoltxfr;        /* late collision */
 679         u32 frabortduecol;      /* frames aborted due to transmit collision */
 680         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 681                                    transmission that are not counted on any
 682                                    other counter */
 683         u32 carriersenseertx;   /* carrier sense error */
 684         u32 frtxok;             /* frames transmitted OK */
 685         u32 txfrexcessivedefer; /* frames with defferal time greater than
 686                                    specified threshold */
 687         u32 txpkts256;          /* total packets (including bad) between 256
 688                                    and 511 octets */
 689         u32 txpkts512;          /* total packets (including bad) between 512
 690                                    and 1023 octets */
 691         u32 txpkts1024;         /* total packets (including bad) between 1024
 692                                    and 1518 octets */
 693         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 694                                    and MAXLength octets */
 695 } __packed;
 696
 697 /* GETH Rx firmware statistics structure, used when calling
 698    UCC_GETH_GetStatistics. */
 699 struct ucc_geth_rx_firmware_statistics {
 700         u32 frrxfcser;          /* frames with crc error */
 701         u32 fraligner;          /* frames with alignment error */
 702         u32 inrangelenrxer;     /* in range length error */
 703         u32 outrangelenrxer;    /* out of range length error */
 704         u32 frtoolong;          /* frame too long */
 705         u32 runt;               /* runt */
 706         u32 verylongevent;      /* very long event */
 707         u32 symbolerror;        /* symbol error */
 708         u32 dropbsy;            /* drop because of BD not ready */
 709         u8 res0[0x8];
 710         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 711                                    or type mismatch) */
 712         u32 underpkts;          /* total frames less than 64 octets */
 713         u32 pkts256;            /* total frames (including bad) between 256 and
 714                                    511 octets */
 715         u32 pkts512;            /* total frames (including bad) between 512 and
 716                                    1023 octets */
 717         u32 pkts1024;           /* total frames (including bad) between 1024
 718                                    and 1518 octets */
 719         u32 pktsjumbo;          /* total frames (including bad) between 1024
 720                                    and MAXLength octets */
 721         u32 frlossinmacer;      /* frames lost because of internal MAC error
 722                                    that is not counted in any other counter */
 723         u32 pausefr;            /* pause frames */
 724         u8 res1[0x4];
 725         u32 removevlan;         /* total frames that had their VLAN tag removed
 726                                  */
 727         u32 replacevlan;        /* total frames that had their VLAN tag
 728                                    replaced */
 729         u32 insertvlan;         /* total frames that had their VLAN tag
 730                                    inserted */
 731 } __packed;
 732
 733 /* GETH hardware statistics structure, used when calling
 734    UCC_GETH_GetStatistics. */
 735 struct ucc_geth_hardware_statistics {
 736         u32 tx64;               /* Total number of frames (including bad
 737                                    frames) transmitted that were exactly of the
 738                                    minimal length (64 for un tagged, 68 for
 739                                    tagged, or with length exactly equal to the
 740                                    parameter MINLength */
 741         u32 tx127;              /* Total number of frames (including bad
 742                                    frames) transmitted that were between
 743                                    MINLength (Including FCS length==4) and 127
 744                                    octets */
 745         u32 tx255;              /* Total number of frames (including bad
 746                                    frames) transmitted that were between 128
 747                                    (Including FCS length==4) and 255 octets */
 748         u32 rx64;               /* Total number of frames received including
 749                                    bad frames that were exactly of the mninimal
 750                                    length (64 bytes) */
 751         u32 rx127;              /* Total number of frames (including bad
 752                                    frames) received that were between MINLength
 753                                    (Including FCS length==4) and 127 octets */
 754         u32 rx255;              /* Total number of frames (including bad
 755                                    frames) received that were between 128
 756                                    (Including FCS length==4) and 255 octets */
 757         u32 txok;               /* Total number of octets residing in frames
 758                                    that where involved in successful
 759                                    transmission */
 760         u16 txcf;               /* Total number of PAUSE control frames
 761                                    transmitted by this MAC */
 762         u32 tmca;               /* Total number of frames that were transmitted
 763                                    successfully with the group address bit set
 764                                    that are not broadcast frames */
 765         u32 tbca;               /* Total number of frames transmitted
 766                                    successfully that had destination address
 767                                    field equal to the broadcast address */
 768         u32 rxfok;              /* Total number of frames received OK */
 769         u32 rxbok;              /* Total number of octets received OK */
 770         u32 rbyt;               /* Total number of octets received including
 771                                    octets in bad frames. Must be implemented in
 772                                    HW because it includes octets in frames that
 773                                    never even reach the UCC */
 774         u32 rmca;               /* Total number of frames that were received
 775                                    successfully with the group address bit set
 776                                    that are not broadcast frames */
 777         u32 rbca;               /* Total number of frames received successfully
 778                                    that had destination address equal to the
 779                                    broadcast address */
 780 } __packed;
 781
 782 /* UCC GETH Tx errors returned via TxConf callback */
 783 #define TX_ERRORS_DEF      0x0200
 784 #define TX_ERRORS_EXDEF    0x0100
 785 #define TX_ERRORS_LC       0x0080
 786 #define TX_ERRORS_RL       0x0040
 787 #define TX_ERRORS_RC_MASK  0x003C
 788 #define TX_ERRORS_RC_SHIFT 2
 789 #define TX_ERRORS_UN       0x0002
 790 #define TX_ERRORS_CSL      0x0001
 791
 792 /* UCC GETH Rx errors returned via RxStore callback */
 793 #define RX_ERRORS_CMR      0x0200
 794 #define RX_ERRORS_M        0x0100
 795 #define RX_ERRORS_BC       0x0080
 796 #define RX_ERRORS_MC       0x0040
 797
 798 /* Transmit BD. These are in addition to values defined in uccf. */
 799 #define T_VID      0x003c0000   /* insert VLAN id index mask. */
 800 #define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
 801 #define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
 802 #define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
 803 #define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
 804 #define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
 805 #define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
 806 #define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
 807 #define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
 808                 | T_UN | T_CSL) /* transmit errors to report */
 809
 810 /* Receive BD. These are in addition to values defined in uccf. */
 811 #define R_LG    0x00200000      /* Frame length violation.  */
 812 #define R_NO    0x00100000      /* Non-octet aligned frame.  */
 813 #define R_SH    0x00080000      /* Short frame.  */
 814 #define R_CR    0x00040000      /* CRC error.  */
 815 #define R_OV    0x00020000      /* Overrun.  */
 816 #define R_IPCH  0x00010000      /* IP checksum check failed. */
 817 #define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
 818 #define R_M     (((u32) RX_ERRORS_M    ) << 16)
 819 #define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
 820 #define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
 821 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)     /* receive errors to
 822                                                            report */
 823 #define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
 824                 R_OV | R_IPCH)  /* receive errors to discard */
 825
 826 /* Alignments */
 827 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT       256
 828 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
 829 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
 830 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
 831 #define UCC_GETH_THREAD_DATA_ALIGNMENT          256     /* spec gives values
 832                                                            based on num of
 833                                                            threads, but always
 834                                                            using the maximum is
 835                                                            easier */
 836 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT  32
 837 #define UCC_GETH_SCHEDULER_ALIGNMENT            8       /* This is a guess */
 838 #define UCC_GETH_TX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 839 #define UCC_GETH_RX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 840 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT      64
 841 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT         8       /* This is a guess */
 842 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT    128     /* This is a guess */
 843 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8    /* This
 844                                                                            is a
 845                                                                            guess
 846                                                                          */
 847 #define UCC_GETH_RX_BD_RING_ALIGNMENT           32
 848 #define UCC_GETH_TX_BD_RING_ALIGNMENT           32
 849 #define UCC_GETH_MRBLR_ALIGNMENT                128
 850 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT      4
 851 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT       32
 852 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT          64
 853
 854 #define UCC_GETH_TAD_EF                         0x80
 855 #define UCC_GETH_TAD_V                          0x40
 856 #define UCC_GETH_TAD_REJ                        0x20
 857 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
 858 #define UCC_GETH_TAD_VTAG_OP_SHIFT              6
 859 #define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
 860 #define UCC_GETH_TAD_RQOS_SHIFT                 0
 861 #define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
 862 #define UCC_GETH_TAD_CFI                        0x10
 863
 864 #define UCC_GETH_VLAN_PRIORITY_MAX              8
 865 #define UCC_GETH_IP_PRIORITY_MAX                64
 866 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
 867 #define UCC_GETH_RX_BD_RING_SIZE_MIN            8
 868 #define UCC_GETH_TX_BD_RING_SIZE_MIN            2
 869 #define UCC_GETH_BD_RING_SIZE_MAX               0xffff
 870
 871 #define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
 872
 873 /* Driver definitions */
 874 #define TX_BD_RING_LEN                          0x10
 875 #define RX_BD_RING_LEN                          0x20
 876
 877 #define TX_RING_MOD_MASK(size)                  (size-1)
 878 #define RX_RING_MOD_MASK(size)                  (size-1)
 879
 880 #define ENET_GROUP_ADDR                         0x01    /* Group address mask
 881                                                            for ethernet
 882                                                            addresses */
 883
 884 #define TX_TIMEOUT                              (1*HZ)
 885 #define PHY_INIT_TIMEOUT                        100000
 886 #define PHY_CHANGE_TIME                         2
 887
 888 /* Fast Ethernet (10/100 Mbps) */
 889 #define UCC_GETH_URFS_INIT                      512     /* Rx virtual FIFO size
 890                                                          */
 891 #define UCC_GETH_URFET_INIT                     256     /* 1/2 urfs */
 892 #define UCC_GETH_URFSET_INIT                    384     /* 3/4 urfs */
 893 #define UCC_GETH_UTFS_INIT                      512     /* Tx virtual FIFO size
 894                                                          */
 895 #define UCC_GETH_UTFET_INIT                     256     /* 1/2 utfs */
 896 #define UCC_GETH_UTFTT_INIT                     256     /* 1/2 utfs
 897                                                            due to errata */
 898 /* Gigabit Ethernet (1000 Mbps) */
 899 #define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/    /* Rx virtual
 900                                                                    FIFO size */
 901 #define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/    /* 1/2 urfs */
 902 #define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/    /* 3/4 urfs */
 903 #define UCC_GETH_UTFS_GIGA_INIT                 4096/*2048*/    /* Tx virtual
 904                                                                    FIFO size */
 905 #define UCC_GETH_UTFET_GIGA_INIT                2048/*1024*/    /* 1/2 utfs */
 906 #define UCC_GETH_UTFTT_GIGA_INIT                4096/*0x40*/    /* Tx virtual
 907                                                                    FIFO size */
 908
 909 #define UCC_GETH_REMODER_INIT                   0       /* bits that must be
 910                                                            set */
 911 #define UCC_GETH_TEMODER_INIT                   0xC000  /* bits that must */
 912
 913 /* Initial value for UPSMR */
 914 #define UCC_GETH_UPSMR_INIT                     UCC_GETH_UPSMR_RES1
 915
 916 #define UCC_GETH_MACCFG1_INIT                   0
 917 #define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1)
 918
 919 /* Ethernet Address Type. */
 920 enum enet_addr_type {
 921         ENET_ADDR_TYPE_INDIVIDUAL,
 922         ENET_ADDR_TYPE_GROUP,
 923         ENET_ADDR_TYPE_BROADCAST
 924 };
 925
 926 /* UCC GETH 82xx Ethernet Address Recognition Location */
 927 enum ucc_geth_enet_address_recognition_location {
 928         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
 929                                                                       address */
 930         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
 931                                                                    station
 932                                                                    address
 933                                                                    paddr1 */
 934         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,      /* additional
 935                                                                    station
 936                                                                    address
 937                                                                    paddr2 */
 938         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,      /* additional
 939                                                                    station
 940                                                                    address
 941                                                                    paddr3 */
 942         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,  /* additional
 943                                                                    station
 944                                                                    address
 945                                                                    paddr4 */
 946         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,  /* group hash */
 947         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
 948                                                                       hash */
 949 };
 950
 951 /* UCC GETH vlan operation tagged */
 952 enum ucc_geth_vlan_operation_tagged {
 953         UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,       /* Tagged - nop */
 954         UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
 955                 = 0x1,  /* Tagged - replace vid portion of q tag */
 956         UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
 957                 = 0x2,  /* Tagged - if vid0 replace vid with default value  */
 958         UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
 959                 = 0x3   /* Tagged - extract q tag from frame */
 960 };
 961
 962 /* UCC GETH vlan operation non-tagged */
 963 enum ucc_geth_vlan_operation_non_tagged {
 964         UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,   /* Non tagged - nop */
 965         UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1   /* Non tagged -
 966                                                                    q tag insert
 967                                                                  */
 968 };
 969
 970 /* UCC GETH Rx Quality of Service Mode */
 971 enum ucc_geth_qos_mode {
 972         UCC_GETH_QOS_MODE_DEFAULT = 0x0,        /* default queue */
 973         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,     /* queue
 974                                                                    determined
 975                                                                    by L2
 976                                                                    criteria */
 977         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2      /* queue
 978                                                                    determined
 979                                                                    by L3
 980                                                                    criteria */
 981 };
 982
 983 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
 984    for combined functionality */
 985 enum ucc_geth_statistics_gathering_mode {
 986         UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,   /* No
 987                                                                    statistics
 988                                                                    gathering */
 989         UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
 990                                                                     hardware
 991                                                                     statistics
 992                                                                     gathering
 993                                                                   */
 994         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
 995                                                                       firmware
 996                                                                       tx
 997                                                                       statistics
 998                                                                       gathering
 999                                                                      */
1000         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1001                                                                       firmware
1002                                                                       rx
1003                                                                       statistics
1004                                                                       gathering
1005                                                                     */
1006 };
1007
1008 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1009 enum ucc_geth_maccfg2_pad_and_crc_mode {
1010         UCC_GETH_PAD_AND_CRC_MODE_NONE
1011                 = MACCFG2_PAD_AND_CRC_MODE_NONE,        /* Neither Padding
1012                                                            short frames
1013                                                            nor CRC */
1014         UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1015                 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,    /* Append
1016                                                            CRC only */
1017         UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1018             MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1019 };
1020
1021 /* UCC GETH upsmr Flow Control Mode */
1022 enum ucc_geth_flow_control_mode {
1023         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,    /* No automatic
1024                                                                    flow control
1025                                                                  */
1026         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1027                 = 0x00004000    /* Send pause frame when RxFIFO reaches its
1028                                    emergency threshold */
1029 };
1030
1031 /* UCC GETH number of threads */
1032 enum ucc_geth_num_of_threads {
1033         UCC_GETH_NUM_OF_THREADS_1 = 0x1,        /* 1 */
1034         UCC_GETH_NUM_OF_THREADS_2 = 0x2,        /* 2 */
1035         UCC_GETH_NUM_OF_THREADS_4 = 0x0,        /* 4 */
1036         UCC_GETH_NUM_OF_THREADS_6 = 0x3,        /* 6 */
1037         UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1038 };
1039
1040 /* UCC GETH number of station addresses */
1041 enum ucc_geth_num_of_station_addresses {
1042         UCC_GETH_NUM_OF_STATION_ADDRESSES_1,    /* 1 */
1043         UCC_GETH_NUM_OF_STATION_ADDRESSES_5     /* 5 */
1044 };
1045
1046 /* UCC GETH 82xx Ethernet Address Container */
1047 struct enet_addr_container {
1048         u8 address[ETH_ALEN];   /* ethernet address */
1049         enum ucc_geth_enet_address_recognition_location location;       /* location in
1050                                                                    82xx address
1051                                                                    recognition
1052                                                                    hardware */
1053         struct list_head node;
1054 };
1055
1056 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1057
1058 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1059 struct ucc_geth_tad_params {
1060         int rx_non_dynamic_extended_features_mode;
1061         int reject_frame;
1062         enum ucc_geth_vlan_operation_tagged vtag_op;
1063         enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1064         enum ucc_geth_qos_mode rqos;
1065         u8 vpri;
1066         u16 vid;
1067 };
1068
1069 /* GETH protocol initialization structure */
1070 struct ucc_geth_info {
1071         struct ucc_fast_info uf_info;
1072         u8 numQueuesTx;
1073         u8 numQueuesRx;
1074         int ipCheckSumCheck;
1075         int ipCheckSumGenerate;
1076         int rxExtendedFiltering;
1077         u32 extendedFilteringChainPointer;
1078         u16 typeorlen;
1079         int dynamicMaxFrameLength;
1080         int dynamicMinFrameLength;
1081         u8 nonBackToBackIfgPart1;
1082         u8 nonBackToBackIfgPart2;
1083         u8 miminumInterFrameGapEnforcement;
1084         u8 backToBackInterFrameGap;
1085         int ipAddressAlignment;
1086         int lengthCheckRx;
1087         u32 mblinterval;
1088         u16 nortsrbytetime;
1089         u8 fracsiz;
1090         u8 strictpriorityq;
1091         u8 txasap;
1092         u8 extrabw;
1093         int miiPreambleSupress;
1094         u8 altBebTruncation;
1095         int altBeb;
1096         int backPressureNoBackoff;
1097         int noBackoff;
1098         int excessDefer;
1099         u8 maxRetransmission;
1100         u8 collisionWindow;
1101         int pro;
1102         int cap;
1103         int rsh;
1104         int rlpb;
1105         int cam;
1106         int bro;
1107         int ecm;
1108         int receiveFlowControl;
1109         int transmitFlowControl;
1110         u8 maxGroupAddrInHash;
1111         u8 maxIndAddrInHash;
1112         u8 prel;
1113         u16 maxFrameLength;
1114         u16 minFrameLength;
1115         u16 maxD1Length;
1116         u16 maxD2Length;
1117         u16 vlantype;
1118         u16 vlantci;
1119         u32 ecamptr;
1120         u32 eventRegMask;
1121         u16 pausePeriod;
1122         u16 extensionField;
1123         struct device_node *phy_node;
1124         struct device_node *tbi_node;
1125         u8 weightfactor[NUM_TX_QUEUES];
1126         u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1127         u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1128         u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1129         u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1130         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1131         u16 bdRingLenTx[NUM_TX_QUEUES];
1132         u16 bdRingLenRx[NUM_RX_QUEUES];
1133         enum ucc_geth_num_of_station_addresses numStationAddresses;
1134         enum qe_fltr_largest_external_tbl_lookup_key_size
1135             largestexternallookupkeysize;
1136         enum ucc_geth_statistics_gathering_mode statisticsMode;
1137         enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1138         enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1139         enum ucc_geth_qos_mode rxQoSMode;
1140         enum ucc_geth_flow_control_mode aufc;
1141         enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1142         enum ucc_geth_num_of_threads numThreadsTx;
1143         enum ucc_geth_num_of_threads numThreadsRx;
1144         unsigned int riscTx;
1145         unsigned int riscRx;
1146 };
1147
1148 /* structure representing UCC GETH */
1149 struct ucc_geth_private {
1150         struct ucc_geth_info *ug_info;
1151         struct ucc_fast_private *uccf;
1152         struct device *dev;
1153         struct net_device *ndev;
1154         struct napi_struct napi;
1155         struct work_struct timeout_work;
1156         struct ucc_geth __iomem *ug_regs;
1157         struct ucc_geth_init_pram *p_init_enet_param_shadow;
1158         struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1159         u32 exf_glbl_param_offset;
1160         struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1161         u32 rx_glbl_pram_offset;
1162         struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1163         u32 tx_glbl_pram_offset;
1164         struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1165         u32 send_q_mem_reg_offset;
1166         struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1167         u32 thread_dat_tx_offset;
1168         struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1169         u32 thread_dat_rx_offset;
1170         struct ucc_geth_scheduler __iomem *p_scheduler;
1171         u32 scheduler_offset;
1172         struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1173         u32 tx_fw_statistics_pram_offset;
1174         struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1175         u32 rx_fw_statistics_pram_offset;
1176         struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1177         u32 rx_irq_coalescing_tbl_offset;
1178         struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1179         u32 rx_bd_qs_tbl_offset;
1180         u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1181         u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1182         u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1183         u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1184         u8 __iomem *confBd[NUM_TX_QUEUES];
1185         u8 __iomem *txBd[NUM_TX_QUEUES];
1186         u8 __iomem *rxBd[NUM_RX_QUEUES];
1187         int badFrame[NUM_RX_QUEUES];
1188         u16 cpucount[NUM_TX_QUEUES];
1189         u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1190         int indAddrRegUsed[NUM_OF_PADDRS];
1191         u8 paddr[NUM_OF_PADDRS][ETH_ALEN];      /* ethernet address */
1192         u8 numGroupAddrInHash;
1193         u8 numIndAddrInHash;
1194         u8 numIndAddrInReg;
1195         int rx_extended_features;
1196         int rx_non_dynamic_extended_features;
1197         struct list_head conf_skbs;
1198         struct list_head group_hash_q;
1199         struct list_head ind_hash_q;
1200         u32 saved_uccm;
1201         spinlock_t lock;
1202         /* pointers to arrays of skbuffs for tx and rx */
1203         struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1204         struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1205         /* indices pointing to the next free sbk in skb arrays */
1206         u16 skb_curtx[NUM_TX_QUEUES];
1207         u16 skb_currx[NUM_RX_QUEUES];
1208         /* index of the first skb which hasn't been transmitted yet. */
1209         u16 skb_dirtytx[NUM_TX_QUEUES];
1210
1211         struct ugeth_mii_info *mii_info;
1212         struct phy_device *phydev;
1213         phy_interface_t phy_interface;
1214         int max_speed;
1215         uint32_t msg_enable;
1216         int oldspeed;
1217         int oldduplex;
1218         int oldlink;
1219         int wol_en;
1220
1221         struct device_node *node;
1222 };
1223
1224 void uec_set_ethtool_ops(struct net_device *netdev);
1225 int init_flow_control_params(u32 automatic_flow_control_mode,
1226                 int rx_flow_control_enable, int tx_flow_control_enable,
1227                 u16 pause_period, u16 extension_field,
1228                 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1229                 u32 __iomem *maccfg1_register);
1230
1231
1232 #endif                          /* __UCC_GETH_H__ */