drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <linux/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105
 106 #include "gianfar.h"
 107
 108 #define TX_TIMEOUT      (5*HZ)
 109
 110 const char gfar_driver_version[] = "2.0";
 111
 112 static int gfar_enet_open(struct net_device *dev);
 113 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 114 static void gfar_reset_task(struct work_struct *work);
 115 static void gfar_timeout(struct net_device *dev);
 116 static int gfar_close(struct net_device *dev);
 117 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 118                                 int alloc_cnt);
 119 static int gfar_set_mac_address(struct net_device *dev);
 120 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 121 static irqreturn_t gfar_error(int irq, void *dev_id);
 122 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 123 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 124 static void adjust_link(struct net_device *dev);
 125 static noinline void gfar_update_link_state(struct gfar_private *priv);
 126 static int init_phy(struct net_device *dev);
 127 static int gfar_probe(struct platform_device *ofdev);
 128 static int gfar_remove(struct platform_device *ofdev);
 129 static void free_skb_resources(struct gfar_private *priv);
 130 static void gfar_set_multi(struct net_device *dev);
 131 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 132 static void gfar_configure_serdes(struct net_device *dev);
 133 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 134 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 135 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 137 #ifdef CONFIG_NET_POLL_CONTROLLER
 138 static void gfar_netpoll(struct net_device *dev);
 139 #endif
 140 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 141 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 142 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 143 static void gfar_halt_nodisable(struct gfar_private *priv);
 144 static void gfar_clear_exact_match(struct net_device *dev);
 145 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 146                                   const u8 *addr);
 147 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 148
 149 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 150 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 151 MODULE_LICENSE("GPL");
 152
 153 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 154                             dma_addr_t buf)
 155 {
 156         u32 lstatus;
 157
 158         bdp->bufPtr = cpu_to_be32(buf);
 159
 160         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 161         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 162                 lstatus |= BD_LFLAG(RXBD_WRAP);
 163
 164         gfar_wmb();
 165
 166         bdp->lstatus = cpu_to_be32(lstatus);
 167 }
 168
 169 static void gfar_init_bds(struct net_device *ndev)
 170 {
 171         struct gfar_private *priv = netdev_priv(ndev);
 172         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 173         struct gfar_priv_tx_q *tx_queue = NULL;
 174         struct gfar_priv_rx_q *rx_queue = NULL;
 175         struct txbd8 *txbdp;
 176         u32 __iomem *rfbptr;
 177         int i, j;
 178
 179         for (i = 0; i < priv->num_tx_queues; i++) {
 180                 tx_queue = priv->tx_queue[i];
 181                 /* Initialize some variables in our dev structure */
 182                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 183                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 184                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 185                 tx_queue->skb_curtx = 0;
 186                 tx_queue->skb_dirtytx = 0;
 187
 188                 /* Initialize Transmit Descriptor Ring */
 189                 txbdp = tx_queue->tx_bd_base;
 190                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 191                         txbdp->lstatus = 0;
 192                         txbdp->bufPtr = 0;
 193                         txbdp++;
 194                 }
 195
 196                 /* Set the last descriptor in the ring to indicate wrap */
 197                 txbdp--;
 198                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 199                                             TXBD_WRAP);
 200         }
 201
 202         rfbptr = &regs->rfbptr0;
 203         for (i = 0; i < priv->num_rx_queues; i++) {
 204                 rx_queue = priv->rx_queue[i];
 205
 206                 rx_queue->next_to_clean = 0;
 207                 rx_queue->next_to_use = 0;
 208                 rx_queue->next_to_alloc = 0;
 209
 210                 /* make sure next_to_clean != next_to_use after this
 211                  * by leaving at least 1 unused descriptor
 212                  */
 213                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 214
 215                 rx_queue->rfbptr = rfbptr;
 216                 rfbptr += 2;
 217         }
 218 }
 219
 220 static int gfar_alloc_skb_resources(struct net_device *ndev)
 221 {
 222         void *vaddr;
 223         dma_addr_t addr;
 224         int i, j;
 225         struct gfar_private *priv = netdev_priv(ndev);
 226         struct device *dev = priv->dev;
 227         struct gfar_priv_tx_q *tx_queue = NULL;
 228         struct gfar_priv_rx_q *rx_queue = NULL;
 229
 230         priv->total_tx_ring_size = 0;
 231         for (i = 0; i < priv->num_tx_queues; i++)
 232                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 233
 234         priv->total_rx_ring_size = 0;
 235         for (i = 0; i < priv->num_rx_queues; i++)
 236                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 237
 238         /* Allocate memory for the buffer descriptors */
 239         vaddr = dma_alloc_coherent(dev,
 240                                    (priv->total_tx_ring_size *
 241                                     sizeof(struct txbd8)) +
 242                                    (priv->total_rx_ring_size *
 243                                     sizeof(struct rxbd8)),
 244                                    &addr, GFP_KERNEL);
 245         if (!vaddr)
 246                 return -ENOMEM;
 247
 248         for (i = 0; i < priv->num_tx_queues; i++) {
 249                 tx_queue = priv->tx_queue[i];
 250                 tx_queue->tx_bd_base = vaddr;
 251                 tx_queue->tx_bd_dma_base = addr;
 252                 tx_queue->dev = ndev;
 253                 /* enet DMA only understands physical addresses */
 254                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 255                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 256         }
 257
 258         /* Start the rx descriptor ring where the tx ring leaves off */
 259         for (i = 0; i < priv->num_rx_queues; i++) {
 260                 rx_queue = priv->rx_queue[i];
 261                 rx_queue->rx_bd_base = vaddr;
 262                 rx_queue->rx_bd_dma_base = addr;
 263                 rx_queue->ndev = ndev;
 264                 rx_queue->dev = dev;
 265                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 266                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 267         }
 268
 269         /* Setup the skbuff rings */
 270         for (i = 0; i < priv->num_tx_queues; i++) {
 271                 tx_queue = priv->tx_queue[i];
 272                 tx_queue->tx_skbuff =
 273                         kmalloc_array(tx_queue->tx_ring_size,
 274                                       sizeof(*tx_queue->tx_skbuff),
 275                                       GFP_KERNEL);
 276                 if (!tx_queue->tx_skbuff)
 277                         goto cleanup;
 278
 279                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 280                         tx_queue->tx_skbuff[j] = NULL;
 281         }
 282
 283         for (i = 0; i < priv->num_rx_queues; i++) {
 284                 rx_queue = priv->rx_queue[i];
 285                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 286                                             sizeof(*rx_queue->rx_buff),
 287                                             GFP_KERNEL);
 288                 if (!rx_queue->rx_buff)
 289                         goto cleanup;
 290         }
 291
 292         gfar_init_bds(ndev);
 293
 294         return 0;
 295
 296 cleanup:
 297         free_skb_resources(priv);
 298         return -ENOMEM;
 299 }
 300
 301 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 302 {
 303         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 304         u32 __iomem *baddr;
 305         int i;
 306
 307         baddr = &regs->tbase0;
 308         for (i = 0; i < priv->num_tx_queues; i++) {
 309                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 310                 baddr += 2;
 311         }
 312
 313         baddr = &regs->rbase0;
 314         for (i = 0; i < priv->num_rx_queues; i++) {
 315                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 316                 baddr += 2;
 317         }
 318 }
 319
 320 static void gfar_init_rqprm(struct gfar_private *priv)
 321 {
 322         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 323         u32 __iomem *baddr;
 324         int i;
 325
 326         baddr = &regs->rqprm0;
 327         for (i = 0; i < priv->num_rx_queues; i++) {
 328                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 329                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 330                 baddr++;
 331         }
 332 }
 333
 334 static void gfar_rx_offload_en(struct gfar_private *priv)
 335 {
 336         /* set this when rx hw offload (TOE) functions are being used */
 337         priv->uses_rxfcb = 0;
 338
 339         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 340                 priv->uses_rxfcb = 1;
 341
 342         if (priv->hwts_rx_en || priv->rx_filer_enable)
 343                 priv->uses_rxfcb = 1;
 344 }
 345
 346 static void gfar_mac_rx_config(struct gfar_private *priv)
 347 {
 348         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 349         u32 rctrl = 0;
 350
 351         if (priv->rx_filer_enable) {
 352                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 353                 /* Program the RIR0 reg with the required distribution */
 354                 if (priv->poll_mode == GFAR_SQ_POLLING)
 355                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 356                 else /* GFAR_MQ_POLLING */
 357                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 358         }
 359
 360         /* Restore PROMISC mode */
 361         if (priv->ndev->flags & IFF_PROMISC)
 362                 rctrl |= RCTRL_PROM;
 363
 364         if (priv->ndev->features & NETIF_F_RXCSUM)
 365                 rctrl |= RCTRL_CHECKSUMMING;
 366
 367         if (priv->extended_hash)
 368                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 369
 370         if (priv->padding) {
 371                 rctrl &= ~RCTRL_PAL_MASK;
 372                 rctrl |= RCTRL_PADDING(priv->padding);
 373         }
 374
 375         /* Enable HW time stamping if requested from user space */
 376         if (priv->hwts_rx_en)
 377                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 378
 379         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 380                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 381
 382         /* Clear the LFC bit */
 383         gfar_write(&regs->rctrl, rctrl);
 384         /* Init flow control threshold values */
 385         gfar_init_rqprm(priv);
 386         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 387         rctrl |= RCTRL_LFC;
 388
 389         /* Init rctrl based on our settings */
 390         gfar_write(&regs->rctrl, rctrl);
 391 }
 392
 393 static void gfar_mac_tx_config(struct gfar_private *priv)
 394 {
 395         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 396         u32 tctrl = 0;
 397
 398         if (priv->ndev->features & NETIF_F_IP_CSUM)
 399                 tctrl |= TCTRL_INIT_CSUM;
 400
 401         if (priv->prio_sched_en)
 402                 tctrl |= TCTRL_TXSCHED_PRIO;
 403         else {
 404                 tctrl |= TCTRL_TXSCHED_WRRS;
 405                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 406                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 407         }
 408
 409         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 410                 tctrl |= TCTRL_VLINS;
 411
 412         gfar_write(&regs->tctrl, tctrl);
 413 }
 414
 415 static void gfar_configure_coalescing(struct gfar_private *priv,
 416                                unsigned long tx_mask, unsigned long rx_mask)
 417 {
 418         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 419         u32 __iomem *baddr;
 420
 421         if (priv->mode == MQ_MG_MODE) {
 422                 int i = 0;
 423
 424                 baddr = &regs->txic0;
 425                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 426                         gfar_write(baddr + i, 0);
 427                         if (likely(priv->tx_queue[i]->txcoalescing))
 428                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 429                 }
 430
 431                 baddr = &regs->rxic0;
 432                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 433                         gfar_write(baddr + i, 0);
 434                         if (likely(priv->rx_queue[i]->rxcoalescing))
 435                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 436                 }
 437         } else {
 438                 /* Backward compatible case -- even if we enable
 439                  * multiple queues, there's only single reg to program
 440                  */
 441                 gfar_write(&regs->txic, 0);
 442                 if (likely(priv->tx_queue[0]->txcoalescing))
 443                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 444
 445                 gfar_write(&regs->rxic, 0);
 446                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 447                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 448         }
 449 }
 450
 451 void gfar_configure_coalescing_all(struct gfar_private *priv)
 452 {
 453         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 454 }
 455
 456 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 457 {
 458         struct gfar_private *priv = netdev_priv(dev);
 459         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 460         unsigned long tx_packets = 0, tx_bytes = 0;
 461         int i;
 462
 463         for (i = 0; i < priv->num_rx_queues; i++) {
 464                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 465                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 466                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 467         }
 468
 469         dev->stats.rx_packets = rx_packets;
 470         dev->stats.rx_bytes   = rx_bytes;
 471         dev->stats.rx_dropped = rx_dropped;
 472
 473         for (i = 0; i < priv->num_tx_queues; i++) {
 474                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 475                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 476         }
 477
 478         dev->stats.tx_bytes   = tx_bytes;
 479         dev->stats.tx_packets = tx_packets;
 480
 481         return &dev->stats;
 482 }
 483
 484 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 485 {
 486         eth_mac_addr(dev, p);
 487
 488         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 489
 490         return 0;
 491 }
 492
 493 static const struct net_device_ops gfar_netdev_ops = {
 494         .ndo_open = gfar_enet_open,
 495         .ndo_start_xmit = gfar_start_xmit,
 496         .ndo_stop = gfar_close,
 497         .ndo_change_mtu = gfar_change_mtu,
 498         .ndo_set_features = gfar_set_features,
 499         .ndo_set_rx_mode = gfar_set_multi,
 500         .ndo_tx_timeout = gfar_timeout,
 501         .ndo_do_ioctl = gfar_ioctl,
 502         .ndo_get_stats = gfar_get_stats,
 503         .ndo_set_mac_address = gfar_set_mac_addr,
 504         .ndo_validate_addr = eth_validate_addr,
 505 #ifdef CONFIG_NET_POLL_CONTROLLER
 506         .ndo_poll_controller = gfar_netpoll,
 507 #endif
 508 };
 509
 510 static void gfar_ints_disable(struct gfar_private *priv)
 511 {
 512         int i;
 513         for (i = 0; i < priv->num_grps; i++) {
 514                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 515                 /* Clear IEVENT */
 516                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 517
 518                 /* Initialize IMASK */
 519                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 520         }
 521 }
 522
 523 static void gfar_ints_enable(struct gfar_private *priv)
 524 {
 525         int i;
 526         for (i = 0; i < priv->num_grps; i++) {
 527                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 528                 /* Unmask the interrupts we look for */
 529                 gfar_write(&regs->imask, IMASK_DEFAULT);
 530         }
 531 }
 532
 533 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 534 {
 535         int i;
 536
 537         for (i = 0; i < priv->num_tx_queues; i++) {
 538                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 539                                             GFP_KERNEL);
 540                 if (!priv->tx_queue[i])
 541                         return -ENOMEM;
 542
 543                 priv->tx_queue[i]->tx_skbuff = NULL;
 544                 priv->tx_queue[i]->qindex = i;
 545                 priv->tx_queue[i]->dev = priv->ndev;
 546                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 547         }
 548         return 0;
 549 }
 550
 551 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 552 {
 553         int i;
 554
 555         for (i = 0; i < priv->num_rx_queues; i++) {
 556                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 557                                             GFP_KERNEL);
 558                 if (!priv->rx_queue[i])
 559                         return -ENOMEM;
 560
 561                 priv->rx_queue[i]->qindex = i;
 562                 priv->rx_queue[i]->ndev = priv->ndev;
 563         }
 564         return 0;
 565 }
 566
 567 static void gfar_free_tx_queues(struct gfar_private *priv)
 568 {
 569         int i;
 570
 571         for (i = 0; i < priv->num_tx_queues; i++)
 572                 kfree(priv->tx_queue[i]);
 573 }
 574
 575 static void gfar_free_rx_queues(struct gfar_private *priv)
 576 {
 577         int i;
 578
 579         for (i = 0; i < priv->num_rx_queues; i++)
 580                 kfree(priv->rx_queue[i]);
 581 }
 582
 583 static void unmap_group_regs(struct gfar_private *priv)
 584 {
 585         int i;
 586
 587         for (i = 0; i < MAXGROUPS; i++)
 588                 if (priv->gfargrp[i].regs)
 589                         iounmap(priv->gfargrp[i].regs);
 590 }
 591
 592 static void free_gfar_dev(struct gfar_private *priv)
 593 {
 594         int i, j;
 595
 596         for (i = 0; i < priv->num_grps; i++)
 597                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 598                         kfree(priv->gfargrp[i].irqinfo[j]);
 599                         priv->gfargrp[i].irqinfo[j] = NULL;
 600                 }
 601
 602         free_netdev(priv->ndev);
 603 }
 604
 605 static void disable_napi(struct gfar_private *priv)
 606 {
 607         int i;
 608
 609         for (i = 0; i < priv->num_grps; i++) {
 610                 napi_disable(&priv->gfargrp[i].napi_rx);
 611                 napi_disable(&priv->gfargrp[i].napi_tx);
 612         }
 613 }
 614
 615 static void enable_napi(struct gfar_private *priv)
 616 {
 617         int i;
 618
 619         for (i = 0; i < priv->num_grps; i++) {
 620                 napi_enable(&priv->gfargrp[i].napi_rx);
 621                 napi_enable(&priv->gfargrp[i].napi_tx);
 622         }
 623 }
 624
 625 static int gfar_parse_group(struct device_node *np,
 626                             struct gfar_private *priv, const char *model)
 627 {
 628         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 629         int i;
 630
 631         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 632                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 633                                           GFP_KERNEL);
 634                 if (!grp->irqinfo[i])
 635                         return -ENOMEM;
 636         }
 637
 638         grp->regs = of_iomap(np, 0);
 639         if (!grp->regs)
 640                 return -ENOMEM;
 641
 642         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 643
 644         /* If we aren't the FEC we have multiple interrupts */
 645         if (model && strcasecmp(model, "FEC")) {
 646                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 647                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 648                 if (!gfar_irq(grp, TX)->irq ||
 649                     !gfar_irq(grp, RX)->irq ||
 650                     !gfar_irq(grp, ER)->irq)
 651                         return -EINVAL;
 652         }
 653
 654         grp->priv = priv;
 655         spin_lock_init(&grp->grplock);
 656         if (priv->mode == MQ_MG_MODE) {
 657                 u32 rxq_mask, txq_mask;
 658                 int ret;
 659
 660                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 661                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 662
 663                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 664                 if (!ret) {
 665                         grp->rx_bit_map = rxq_mask ?
 666                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 667                 }
 668
 669                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 670                 if (!ret) {
 671                         grp->tx_bit_map = txq_mask ?
 672                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 673                 }
 674
 675                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 676                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 677                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 678                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 679                 }
 680         } else {
 681                 grp->rx_bit_map = 0xFF;
 682                 grp->tx_bit_map = 0xFF;
 683         }
 684
 685         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 686          * right to left, so we need to revert the 8 bits to get the q index
 687          */
 688         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 689         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 690
 691         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 692          * also assign queues to groups
 693          */
 694         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 695                 if (!grp->rx_queue)
 696                         grp->rx_queue = priv->rx_queue[i];
 697                 grp->num_rx_queues++;
 698                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 699                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 700                 priv->rx_queue[i]->grp = grp;
 701         }
 702
 703         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 704                 if (!grp->tx_queue)
 705                         grp->tx_queue = priv->tx_queue[i];
 706                 grp->num_tx_queues++;
 707                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 708                 priv->tqueue |= (TQUEUE_EN0 >> i);
 709                 priv->tx_queue[i]->grp = grp;
 710         }
 711
 712         priv->num_grps++;
 713
 714         return 0;
 715 }
 716
 717 static int gfar_of_group_count(struct device_node *np)
 718 {
 719         struct device_node *child;
 720         int num = 0;
 721
 722         for_each_available_child_of_node(np, child)
 723                 if (!of_node_cmp(child->name, "queue-group"))
 724                         num++;
 725
 726         return num;
 727 }
 728
 729 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 730 {
 731         const char *model;
 732         const char *ctype;
 733         const void *mac_addr;
 734         int err = 0, i;
 735         struct net_device *dev = NULL;
 736         struct gfar_private *priv = NULL;
 737         struct device_node *np = ofdev->dev.of_node;
 738         struct device_node *child = NULL;
 739         u32 stash_len = 0;
 740         u32 stash_idx = 0;
 741         unsigned int num_tx_qs, num_rx_qs;
 742         unsigned short mode, poll_mode;
 743
 744         if (!np)
 745                 return -ENODEV;
 746
 747         if (of_device_is_compatible(np, "fsl,etsec2")) {
 748                 mode = MQ_MG_MODE;
 749                 poll_mode = GFAR_SQ_POLLING;
 750         } else {
 751                 mode = SQ_SG_MODE;
 752                 poll_mode = GFAR_SQ_POLLING;
 753         }
 754
 755         if (mode == SQ_SG_MODE) {
 756                 num_tx_qs = 1;
 757                 num_rx_qs = 1;
 758         } else { /* MQ_MG_MODE */
 759                 /* get the actual number of supported groups */
 760                 unsigned int num_grps = gfar_of_group_count(np);
 761
 762                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 763                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 764                                 num_grps);
 765                         pr_err("Cannot do alloc_etherdev, aborting\n");
 766                         return -EINVAL;
 767                 }
 768
 769                 if (poll_mode == GFAR_SQ_POLLING) {
 770                         num_tx_qs = num_grps; /* one txq per int group */
 771                         num_rx_qs = num_grps; /* one rxq per int group */
 772                 } else { /* GFAR_MQ_POLLING */
 773                         u32 tx_queues, rx_queues;
 774                         int ret;
 775
 776                         /* parse the num of HW tx and rx queues */
 777                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 778                                                    &tx_queues);
 779                         num_tx_qs = ret ? 1 : tx_queues;
 780
 781                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 782                                                    &rx_queues);
 783                         num_rx_qs = ret ? 1 : rx_queues;
 784                 }
 785         }
 786
 787         if (num_tx_qs > MAX_TX_QS) {
 788                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 789                        num_tx_qs, MAX_TX_QS);
 790                 pr_err("Cannot do alloc_etherdev, aborting\n");
 791                 return -EINVAL;
 792         }
 793
 794         if (num_rx_qs > MAX_RX_QS) {
 795                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 796                        num_rx_qs, MAX_RX_QS);
 797                 pr_err("Cannot do alloc_etherdev, aborting\n");
 798                 return -EINVAL;
 799         }
 800
 801         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 802         dev = *pdev;
 803         if (NULL == dev)
 804                 return -ENOMEM;
 805
 806         priv = netdev_priv(dev);
 807         priv->ndev = dev;
 808
 809         priv->mode = mode;
 810         priv->poll_mode = poll_mode;
 811
 812         priv->num_tx_queues = num_tx_qs;
 813         netif_set_real_num_rx_queues(dev, num_rx_qs);
 814         priv->num_rx_queues = num_rx_qs;
 815
 816         err = gfar_alloc_tx_queues(priv);
 817         if (err)
 818                 goto tx_alloc_failed;
 819
 820         err = gfar_alloc_rx_queues(priv);
 821         if (err)
 822                 goto rx_alloc_failed;
 823
 824         err = of_property_read_string(np, "model", &model);
 825         if (err) {
 826                 pr_err("Device model property missing, aborting\n");
 827                 goto rx_alloc_failed;
 828         }
 829
 830         /* Init Rx queue filer rule set linked list */
 831         INIT_LIST_HEAD(&priv->rx_list.list);
 832         priv->rx_list.count = 0;
 833         mutex_init(&priv->rx_queue_access);
 834
 835         for (i = 0; i < MAXGROUPS; i++)
 836                 priv->gfargrp[i].regs = NULL;
 837
 838         /* Parse and initialize group specific information */
 839         if (priv->mode == MQ_MG_MODE) {
 840                 for_each_available_child_of_node(np, child) {
 841                         if (of_node_cmp(child->name, "queue-group"))
 842                                 continue;
 843
 844                         err = gfar_parse_group(child, priv, model);
 845                         if (err)
 846                                 goto err_grp_init;
 847                 }
 848         } else { /* SQ_SG_MODE */
 849                 err = gfar_parse_group(np, priv, model);
 850                 if (err)
 851                         goto err_grp_init;
 852         }
 853
 854         if (of_property_read_bool(np, "bd-stash")) {
 855                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 856                 priv->bd_stash_en = 1;
 857         }
 858
 859         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 860
 861         if (err == 0)
 862                 priv->rx_stash_size = stash_len;
 863
 864         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 865
 866         if (err == 0)
 867                 priv->rx_stash_index = stash_idx;
 868
 869         if (stash_len || stash_idx)
 870                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 871
 872         mac_addr = of_get_mac_address(np);
 873
 874         if (mac_addr)
 875                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 876
 877         if (model && !strcasecmp(model, "TSEC"))
 878                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 879                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 880                                      FSL_GIANFAR_DEV_HAS_RMON |
 881                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 882
 883         if (model && !strcasecmp(model, "eTSEC"))
 884                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 885                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 886                                      FSL_GIANFAR_DEV_HAS_RMON |
 887                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 888                                      FSL_GIANFAR_DEV_HAS_CSUM |
 889                                      FSL_GIANFAR_DEV_HAS_VLAN |
 890                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 891                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 892                                      FSL_GIANFAR_DEV_HAS_TIMER |
 893                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 894
 895         err = of_property_read_string(np, "phy-connection-type", &ctype);
 896
 897         /* We only care about rgmii-id.  The rest are autodetected */
 898         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 899                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 900         else
 901                 priv->interface = PHY_INTERFACE_MODE_MII;
 902
 903         if (of_find_property(np, "fsl,magic-packet", NULL))
 904                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 905
 906         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 907                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 908
 909         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 910
 911         /* In the case of a fixed PHY, the DT node associated
 912          * to the PHY is the Ethernet MAC DT node.
 913          */
 914         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 915                 err = of_phy_register_fixed_link(np);
 916                 if (err)
 917                         goto err_grp_init;
 918
 919                 priv->phy_node = of_node_get(np);
 920         }
 921
 922         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 923         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 924
 925         return 0;
 926
 927 err_grp_init:
 928         unmap_group_regs(priv);
 929 rx_alloc_failed:
 930         gfar_free_rx_queues(priv);
 931 tx_alloc_failed:
 932         gfar_free_tx_queues(priv);
 933         free_gfar_dev(priv);
 934         return err;
 935 }
 936
 937 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 938 {
 939         struct hwtstamp_config config;
 940         struct gfar_private *priv = netdev_priv(netdev);
 941
 942         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 943                 return -EFAULT;
 944
 945         /* reserved for future extensions */
 946         if (config.flags)
 947                 return -EINVAL;
 948
 949         switch (config.tx_type) {
 950         case HWTSTAMP_TX_OFF:
 951                 priv->hwts_tx_en = 0;
 952                 break;
 953         case HWTSTAMP_TX_ON:
 954                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 955                         return -ERANGE;
 956                 priv->hwts_tx_en = 1;
 957                 break;
 958         default:
 959                 return -ERANGE;
 960         }
 961
 962         switch (config.rx_filter) {
 963         case HWTSTAMP_FILTER_NONE:
 964                 if (priv->hwts_rx_en) {
 965                         priv->hwts_rx_en = 0;
 966                         reset_gfar(netdev);
 967                 }
 968                 break;
 969         default:
 970                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 971                         return -ERANGE;
 972                 if (!priv->hwts_rx_en) {
 973                         priv->hwts_rx_en = 1;
 974                         reset_gfar(netdev);
 975                 }
 976                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 977                 break;
 978         }
 979
 980         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 981                 -EFAULT : 0;
 982 }
 983
 984 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 985 {
 986         struct hwtstamp_config config;
 987         struct gfar_private *priv = netdev_priv(netdev);
 988
 989         config.flags = 0;
 990         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 991         config.rx_filter = (priv->hwts_rx_en ?
 992                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 993
 994         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 995                 -EFAULT : 0;
 996 }
 997
 998 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 999 {
1000         struct phy_device *phydev = dev->phydev;
1001
1002         if (!netif_running(dev))
1003                 return -EINVAL;
1004
1005         if (cmd == SIOCSHWTSTAMP)
1006                 return gfar_hwtstamp_set(dev, rq);
1007         if (cmd == SIOCGHWTSTAMP)
1008                 return gfar_hwtstamp_get(dev, rq);
1009
1010         if (!phydev)
1011                 return -ENODEV;
1012
1013         return phy_mii_ioctl(phydev, rq, cmd);
1014 }
1015
1016 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1017                                    u32 class)
1018 {
1019         u32 rqfpr = FPR_FILER_MASK;
1020         u32 rqfcr = 0x0;
1021
1022         rqfar--;
1023         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1024         priv->ftp_rqfpr[rqfar] = rqfpr;
1025         priv->ftp_rqfcr[rqfar] = rqfcr;
1026         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1027
1028         rqfar--;
1029         rqfcr = RQFCR_CMP_NOMATCH;
1030         priv->ftp_rqfpr[rqfar] = rqfpr;
1031         priv->ftp_rqfcr[rqfar] = rqfcr;
1032         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1033
1034         rqfar--;
1035         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1036         rqfpr = class;
1037         priv->ftp_rqfcr[rqfar] = rqfcr;
1038         priv->ftp_rqfpr[rqfar] = rqfpr;
1039         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1040
1041         rqfar--;
1042         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1043         rqfpr = class;
1044         priv->ftp_rqfcr[rqfar] = rqfcr;
1045         priv->ftp_rqfpr[rqfar] = rqfpr;
1046         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1047
1048         return rqfar;
1049 }
1050
1051 static void gfar_init_filer_table(struct gfar_private *priv)
1052 {
1053         int i = 0x0;
1054         u32 rqfar = MAX_FILER_IDX;
1055         u32 rqfcr = 0x0;
1056         u32 rqfpr = FPR_FILER_MASK;
1057
1058         /* Default rule */
1059         rqfcr = RQFCR_CMP_MATCH;
1060         priv->ftp_rqfcr[rqfar] = rqfcr;
1061         priv->ftp_rqfpr[rqfar] = rqfpr;
1062         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1063
1064         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1065         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1066         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1067         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1070
1071         /* cur_filer_idx indicated the first non-masked rule */
1072         priv->cur_filer_idx = rqfar;
1073
1074         /* Rest are masked rules */
1075         rqfcr = RQFCR_CMP_NOMATCH;
1076         for (i = 0; i < rqfar; i++) {
1077                 priv->ftp_rqfcr[i] = rqfcr;
1078                 priv->ftp_rqfpr[i] = rqfpr;
1079                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1080         }
1081 }
1082
1083 #ifdef CONFIG_PPC
1084 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1085 {
1086         unsigned int pvr = mfspr(SPRN_PVR);
1087         unsigned int svr = mfspr(SPRN_SVR);
1088         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1089         unsigned int rev = svr & 0xffff;
1090
1091         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1092         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1093             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1094                 priv->errata |= GFAR_ERRATA_74;
1095
1096         /* MPC8313 and MPC837x all rev */
1097         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1098             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1099                 priv->errata |= GFAR_ERRATA_76;
1100
1101         /* MPC8313 Rev < 2.0 */
1102         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1103                 priv->errata |= GFAR_ERRATA_12;
1104 }
1105
1106 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1107 {
1108         unsigned int svr = mfspr(SPRN_SVR);
1109
1110         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1111                 priv->errata |= GFAR_ERRATA_12;
1112         /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
1113         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1114             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1115             ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
1116                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1117 }
1118 #endif
1119
1120 static void gfar_detect_errata(struct gfar_private *priv)
1121 {
1122         struct device *dev = &priv->ofdev->dev;
1123
1124         /* no plans to fix */
1125         priv->errata |= GFAR_ERRATA_A002;
1126
1127 #ifdef CONFIG_PPC
1128         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1129                 __gfar_detect_errata_85xx(priv);
1130         else /* non-mpc85xx parts, i.e. e300 core based */
1131                 __gfar_detect_errata_83xx(priv);
1132 #endif
1133
1134         if (priv->errata)
1135                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1136                          priv->errata);
1137 }
1138
1139 void gfar_mac_reset(struct gfar_private *priv)
1140 {
1141         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1142         u32 tempval;
1143
1144         /* Reset MAC layer */
1145         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1146
1147         /* We need to delay at least 3 TX clocks */
1148         udelay(3);
1149
1150         /* the soft reset bit is not self-resetting, so we need to
1151          * clear it before resuming normal operation
1152          */
1153         gfar_write(&regs->maccfg1, 0);
1154
1155         udelay(3);
1156
1157         gfar_rx_offload_en(priv);
1158
1159         /* Initialize the max receive frame/buffer lengths */
1160         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1161         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1162
1163         /* Initialize the Minimum Frame Length Register */
1164         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1165
1166         /* Initialize MACCFG2. */
1167         tempval = MACCFG2_INIT_SETTINGS;
1168
1169         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1170          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1171          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1172          */
1173         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1174                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1175
1176         gfar_write(&regs->maccfg2, tempval);
1177
1178         /* Clear mac addr hash registers */
1179         gfar_write(&regs->igaddr0, 0);
1180         gfar_write(&regs->igaddr1, 0);
1181         gfar_write(&regs->igaddr2, 0);
1182         gfar_write(&regs->igaddr3, 0);
1183         gfar_write(&regs->igaddr4, 0);
1184         gfar_write(&regs->igaddr5, 0);
1185         gfar_write(&regs->igaddr6, 0);
1186         gfar_write(&regs->igaddr7, 0);
1187
1188         gfar_write(&regs->gaddr0, 0);
1189         gfar_write(&regs->gaddr1, 0);
1190         gfar_write(&regs->gaddr2, 0);
1191         gfar_write(&regs->gaddr3, 0);
1192         gfar_write(&regs->gaddr4, 0);
1193         gfar_write(&regs->gaddr5, 0);
1194         gfar_write(&regs->gaddr6, 0);
1195         gfar_write(&regs->gaddr7, 0);
1196
1197         if (priv->extended_hash)
1198                 gfar_clear_exact_match(priv->ndev);
1199
1200         gfar_mac_rx_config(priv);
1201
1202         gfar_mac_tx_config(priv);
1203
1204         gfar_set_mac_address(priv->ndev);
1205
1206         gfar_set_multi(priv->ndev);
1207
1208         /* clear ievent and imask before configuring coalescing */
1209         gfar_ints_disable(priv);
1210
1211         /* Configure the coalescing support */
1212         gfar_configure_coalescing_all(priv);
1213 }
1214
1215 static void gfar_hw_init(struct gfar_private *priv)
1216 {
1217         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1218         u32 attrs;
1219
1220         /* Stop the DMA engine now, in case it was running before
1221          * (The firmware could have used it, and left it running).
1222          */
1223         gfar_halt(priv);
1224
1225         gfar_mac_reset(priv);
1226
1227         /* Zero out the rmon mib registers if it has them */
1228         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1229                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1230
1231                 /* Mask off the CAM interrupts */
1232                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1233                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1234         }
1235
1236         /* Initialize ECNTRL */
1237         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1238
1239         /* Set the extraction length and index */
1240         attrs = ATTRELI_EL(priv->rx_stash_size) |
1241                 ATTRELI_EI(priv->rx_stash_index);
1242
1243         gfar_write(&regs->attreli, attrs);
1244
1245         /* Start with defaults, and add stashing
1246          * depending on driver parameters
1247          */
1248         attrs = ATTR_INIT_SETTINGS;
1249
1250         if (priv->bd_stash_en)
1251                 attrs |= ATTR_BDSTASH;
1252
1253         if (priv->rx_stash_size != 0)
1254                 attrs |= ATTR_BUFSTASH;
1255
1256         gfar_write(&regs->attr, attrs);
1257
1258         /* FIFO configs */
1259         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1260         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1261         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1262
1263         /* Program the interrupt steering regs, only for MG devices */
1264         if (priv->num_grps > 1)
1265                 gfar_write_isrg(priv);
1266 }
1267
1268 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1269 {
1270         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271
1272         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1273                 priv->extended_hash = 1;
1274                 priv->hash_width = 9;
1275
1276                 priv->hash_regs[0] = &regs->igaddr0;
1277                 priv->hash_regs[1] = &regs->igaddr1;
1278                 priv->hash_regs[2] = &regs->igaddr2;
1279                 priv->hash_regs[3] = &regs->igaddr3;
1280                 priv->hash_regs[4] = &regs->igaddr4;
1281                 priv->hash_regs[5] = &regs->igaddr5;
1282                 priv->hash_regs[6] = &regs->igaddr6;
1283                 priv->hash_regs[7] = &regs->igaddr7;
1284                 priv->hash_regs[8] = &regs->gaddr0;
1285                 priv->hash_regs[9] = &regs->gaddr1;
1286                 priv->hash_regs[10] = &regs->gaddr2;
1287                 priv->hash_regs[11] = &regs->gaddr3;
1288                 priv->hash_regs[12] = &regs->gaddr4;
1289                 priv->hash_regs[13] = &regs->gaddr5;
1290                 priv->hash_regs[14] = &regs->gaddr6;
1291                 priv->hash_regs[15] = &regs->gaddr7;
1292
1293         } else {
1294                 priv->extended_hash = 0;
1295                 priv->hash_width = 8;
1296
1297                 priv->hash_regs[0] = &regs->gaddr0;
1298                 priv->hash_regs[1] = &regs->gaddr1;
1299                 priv->hash_regs[2] = &regs->gaddr2;
1300                 priv->hash_regs[3] = &regs->gaddr3;
1301                 priv->hash_regs[4] = &regs->gaddr4;
1302                 priv->hash_regs[5] = &regs->gaddr5;
1303                 priv->hash_regs[6] = &regs->gaddr6;
1304                 priv->hash_regs[7] = &regs->gaddr7;
1305         }
1306 }
1307
1308 /* Set up the ethernet device structure, private data,
1309  * and anything else we need before we start
1310  */
1311 static int gfar_probe(struct platform_device *ofdev)
1312 {
1313         struct device_node *np = ofdev->dev.of_node;
1314         struct net_device *dev = NULL;
1315         struct gfar_private *priv = NULL;
1316         int err = 0, i;
1317
1318         err = gfar_of_init(ofdev, &dev);
1319
1320         if (err)
1321                 return err;
1322
1323         priv = netdev_priv(dev);
1324         priv->ndev = dev;
1325         priv->ofdev = ofdev;
1326         priv->dev = &ofdev->dev;
1327         SET_NETDEV_DEV(dev, &ofdev->dev);
1328
1329         INIT_WORK(&priv->reset_task, gfar_reset_task);
1330
1331         platform_set_drvdata(ofdev, priv);
1332
1333         gfar_detect_errata(priv);
1334
1335         /* Set the dev->base_addr to the gfar reg region */
1336         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1337
1338         /* Fill in the dev structure */
1339         dev->watchdog_timeo = TX_TIMEOUT;
1340         /* MTU range: 50 - 9586 */
1341         dev->mtu = 1500;
1342         dev->min_mtu = 50;
1343         dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
1344         dev->netdev_ops = &gfar_netdev_ops;
1345         dev->ethtool_ops = &gfar_ethtool_ops;
1346
1347         /* Register for napi ...We are registering NAPI for each grp */
1348         for (i = 0; i < priv->num_grps; i++) {
1349                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1350                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1351                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1352                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1353                                        gfar_poll_tx_sq, 2);
1354                 } else {
1355                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1356                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1357                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1358                                        gfar_poll_tx, 2);
1359                 }
1360         }
1361
1362         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1363                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1364                                    NETIF_F_RXCSUM;
1365                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1366                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1367         }
1368
1369         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1370                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1371                                     NETIF_F_HW_VLAN_CTAG_RX;
1372                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1373         }
1374
1375         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1376
1377         gfar_init_addr_hash_table(priv);
1378
1379         /* Insert receive time stamps into padding alignment bytes, and
1380          * plus 2 bytes padding to ensure the cpu alignment.
1381          */
1382         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1383                 priv->padding = 8 + DEFAULT_PADDING;
1384
1385         if (dev->features & NETIF_F_IP_CSUM ||
1386             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1387                 dev->needed_headroom = GMAC_FCB_LEN;
1388
1389         /* Initializing some of the rx/tx queue level parameters */
1390         for (i = 0; i < priv->num_tx_queues; i++) {
1391                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1392                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1393                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1394                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1395         }
1396
1397         for (i = 0; i < priv->num_rx_queues; i++) {
1398                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1399                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1400                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1401         }
1402
1403         /* Always enable rx filer if available */
1404         priv->rx_filer_enable =
1405             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1406         /* Enable most messages by default */
1407         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1408         /* use pritority h/w tx queue scheduling for single queue devices */
1409         if (priv->num_tx_queues == 1)
1410                 priv->prio_sched_en = 1;
1411
1412         set_bit(GFAR_DOWN, &priv->state);
1413
1414         gfar_hw_init(priv);
1415
1416         /* Carrier starts down, phylib will bring it up */
1417         netif_carrier_off(dev);
1418
1419         err = register_netdev(dev);
1420
1421         if (err) {
1422                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1423                 goto register_fail;
1424         }
1425
1426         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1427                 priv->wol_supported |= GFAR_WOL_MAGIC;
1428
1429         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1430             priv->rx_filer_enable)
1431                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1432
1433         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1434
1435         /* fill out IRQ number and name fields */
1436         for (i = 0; i < priv->num_grps; i++) {
1437                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1438                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1439                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1440                                 dev->name, "_g", '0' + i, "_tx");
1441                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1442                                 dev->name, "_g", '0' + i, "_rx");
1443                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1444                                 dev->name, "_g", '0' + i, "_er");
1445                 } else
1446                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1447         }
1448
1449         /* Initialize the filer table */
1450         gfar_init_filer_table(priv);
1451
1452         /* Print out the device info */
1453         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1454
1455         /* Even more device info helps when determining which kernel
1456          * provided which set of benchmarks.
1457          */
1458         netdev_info(dev, "Running with NAPI enabled\n");
1459         for (i = 0; i < priv->num_rx_queues; i++)
1460                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1461                             i, priv->rx_queue[i]->rx_ring_size);
1462         for (i = 0; i < priv->num_tx_queues; i++)
1463                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1464                             i, priv->tx_queue[i]->tx_ring_size);
1465
1466         return 0;
1467
1468 register_fail:
1469         if (of_phy_is_fixed_link(np))
1470                 of_phy_deregister_fixed_link(np);
1471         unmap_group_regs(priv);
1472         gfar_free_rx_queues(priv);
1473         gfar_free_tx_queues(priv);
1474         of_node_put(priv->phy_node);
1475         of_node_put(priv->tbi_node);
1476         free_gfar_dev(priv);
1477         return err;
1478 }
1479
1480 static int gfar_remove(struct platform_device *ofdev)
1481 {
1482         struct gfar_private *priv = platform_get_drvdata(ofdev);
1483         struct device_node *np = ofdev->dev.of_node;
1484
1485         of_node_put(priv->phy_node);
1486         of_node_put(priv->tbi_node);
1487
1488         unregister_netdev(priv->ndev);
1489
1490         if (of_phy_is_fixed_link(np))
1491                 of_phy_deregister_fixed_link(np);
1492
1493         unmap_group_regs(priv);
1494         gfar_free_rx_queues(priv);
1495         gfar_free_tx_queues(priv);
1496         free_gfar_dev(priv);
1497
1498         return 0;
1499 }
1500
1501 #ifdef CONFIG_PM
1502
1503 static void __gfar_filer_disable(struct gfar_private *priv)
1504 {
1505         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1506         u32 temp;
1507
1508         temp = gfar_read(&regs->rctrl);
1509         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1510         gfar_write(&regs->rctrl, temp);
1511 }
1512
1513 static void __gfar_filer_enable(struct gfar_private *priv)
1514 {
1515         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1516         u32 temp;
1517
1518         temp = gfar_read(&regs->rctrl);
1519         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1520         gfar_write(&regs->rctrl, temp);
1521 }
1522
1523 /* Filer rules implementing wol capabilities */
1524 static void gfar_filer_config_wol(struct gfar_private *priv)
1525 {
1526         unsigned int i;
1527         u32 rqfcr;
1528
1529         __gfar_filer_disable(priv);
1530
1531         /* clear the filer table, reject any packet by default */
1532         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1533         for (i = 0; i <= MAX_FILER_IDX; i++)
1534                 gfar_write_filer(priv, i, rqfcr, 0);
1535
1536         i = 0;
1537         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1538                 /* unicast packet, accept it */
1539                 struct net_device *ndev = priv->ndev;
1540                 /* get the default rx queue index */
1541                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1542                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1543                                     (ndev->dev_addr[1] << 8) |
1544                                      ndev->dev_addr[2];
1545
1546                 rqfcr = (qindex << 10) | RQFCR_AND |
1547                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1548
1549                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1550
1551                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1552                                 (ndev->dev_addr[4] << 8) |
1553                                  ndev->dev_addr[5];
1554                 rqfcr = (qindex << 10) | RQFCR_GPI |
1555                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1556                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1557         }
1558
1559         __gfar_filer_enable(priv);
1560 }
1561
1562 static void gfar_filer_restore_table(struct gfar_private *priv)
1563 {
1564         u32 rqfcr, rqfpr;
1565         unsigned int i;
1566
1567         __gfar_filer_disable(priv);
1568
1569         for (i = 0; i <= MAX_FILER_IDX; i++) {
1570                 rqfcr = priv->ftp_rqfcr[i];
1571                 rqfpr = priv->ftp_rqfpr[i];
1572                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1573         }
1574
1575         __gfar_filer_enable(priv);
1576 }
1577
1578 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1579 static void gfar_start_wol_filer(struct gfar_private *priv)
1580 {
1581         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1582         u32 tempval;
1583         int i = 0;
1584
1585         /* Enable Rx hw queues */
1586         gfar_write(&regs->rqueue, priv->rqueue);
1587
1588         /* Initialize DMACTRL to have WWR and WOP */
1589         tempval = gfar_read(&regs->dmactrl);
1590         tempval |= DMACTRL_INIT_SETTINGS;
1591         gfar_write(&regs->dmactrl, tempval);
1592
1593         /* Make sure we aren't stopped */
1594         tempval = gfar_read(&regs->dmactrl);
1595         tempval &= ~DMACTRL_GRS;
1596         gfar_write(&regs->dmactrl, tempval);
1597
1598         for (i = 0; i < priv->num_grps; i++) {
1599                 regs = priv->gfargrp[i].regs;
1600                 /* Clear RHLT, so that the DMA starts polling now */
1601                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1602                 /* enable the Filer General Purpose Interrupt */
1603                 gfar_write(&regs->imask, IMASK_FGPI);
1604         }
1605
1606         /* Enable Rx DMA */
1607         tempval = gfar_read(&regs->maccfg1);
1608         tempval |= MACCFG1_RX_EN;
1609         gfar_write(&regs->maccfg1, tempval);
1610 }
1611
1612 static int gfar_suspend(struct device *dev)
1613 {
1614         struct gfar_private *priv = dev_get_drvdata(dev);
1615         struct net_device *ndev = priv->ndev;
1616         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1617         u32 tempval;
1618         u16 wol = priv->wol_opts;
1619
1620         if (!netif_running(ndev))
1621                 return 0;
1622
1623         disable_napi(priv);
1624         netif_tx_lock(ndev);
1625         netif_device_detach(ndev);
1626         netif_tx_unlock(ndev);
1627
1628         gfar_halt(priv);
1629
1630         if (wol & GFAR_WOL_MAGIC) {
1631                 /* Enable interrupt on Magic Packet */
1632                 gfar_write(&regs->imask, IMASK_MAG);
1633
1634                 /* Enable Magic Packet mode */
1635                 tempval = gfar_read(&regs->maccfg2);
1636                 tempval |= MACCFG2_MPEN;
1637                 gfar_write(&regs->maccfg2, tempval);
1638
1639                 /* re-enable the Rx block */
1640                 tempval = gfar_read(&regs->maccfg1);
1641                 tempval |= MACCFG1_RX_EN;
1642                 gfar_write(&regs->maccfg1, tempval);
1643
1644         } else if (wol & GFAR_WOL_FILER_UCAST) {
1645                 gfar_filer_config_wol(priv);
1646                 gfar_start_wol_filer(priv);
1647
1648         } else {
1649                 phy_stop(ndev->phydev);
1650         }
1651
1652         return 0;
1653 }
1654
1655 static int gfar_resume(struct device *dev)
1656 {
1657         struct gfar_private *priv = dev_get_drvdata(dev);
1658         struct net_device *ndev = priv->ndev;
1659         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1660         u32 tempval;
1661         u16 wol = priv->wol_opts;
1662
1663         if (!netif_running(ndev))
1664                 return 0;
1665
1666         if (wol & GFAR_WOL_MAGIC) {
1667                 /* Disable Magic Packet mode */
1668                 tempval = gfar_read(&regs->maccfg2);
1669                 tempval &= ~MACCFG2_MPEN;
1670                 gfar_write(&regs->maccfg2, tempval);
1671
1672         } else if (wol & GFAR_WOL_FILER_UCAST) {
1673                 /* need to stop rx only, tx is already down */
1674                 gfar_halt(priv);
1675                 gfar_filer_restore_table(priv);
1676
1677         } else {
1678                 phy_start(ndev->phydev);
1679         }
1680
1681         gfar_start(priv);
1682
1683         netif_device_attach(ndev);
1684         enable_napi(priv);
1685
1686         return 0;
1687 }
1688
1689 static int gfar_restore(struct device *dev)
1690 {
1691         struct gfar_private *priv = dev_get_drvdata(dev);
1692         struct net_device *ndev = priv->ndev;
1693
1694         if (!netif_running(ndev)) {
1695                 netif_device_attach(ndev);
1696
1697                 return 0;
1698         }
1699
1700         gfar_init_bds(ndev);
1701
1702         gfar_mac_reset(priv);
1703
1704         gfar_init_tx_rx_base(priv);
1705
1706         gfar_start(priv);
1707
1708         priv->oldlink = 0;
1709         priv->oldspeed = 0;
1710         priv->oldduplex = -1;
1711
1712         if (ndev->phydev)
1713                 phy_start(ndev->phydev);
1714
1715         netif_device_attach(ndev);
1716         enable_napi(priv);
1717
1718         return 0;
1719 }
1720
1721 static const struct dev_pm_ops gfar_pm_ops = {
1722         .suspend = gfar_suspend,
1723         .resume = gfar_resume,
1724         .freeze = gfar_suspend,
1725         .thaw = gfar_resume,
1726         .restore = gfar_restore,
1727 };
1728
1729 #define GFAR_PM_OPS (&gfar_pm_ops)
1730
1731 #else
1732
1733 #define GFAR_PM_OPS NULL
1734
1735 #endif
1736
1737 /* Reads the controller's registers to determine what interface
1738  * connects it to the PHY.
1739  */
1740 static phy_interface_t gfar_get_interface(struct net_device *dev)
1741 {
1742         struct gfar_private *priv = netdev_priv(dev);
1743         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1744         u32 ecntrl;
1745
1746         ecntrl = gfar_read(&regs->ecntrl);
1747
1748         if (ecntrl & ECNTRL_SGMII_MODE)
1749                 return PHY_INTERFACE_MODE_SGMII;
1750
1751         if (ecntrl & ECNTRL_TBI_MODE) {
1752                 if (ecntrl & ECNTRL_REDUCED_MODE)
1753                         return PHY_INTERFACE_MODE_RTBI;
1754                 else
1755                         return PHY_INTERFACE_MODE_TBI;
1756         }
1757
1758         if (ecntrl & ECNTRL_REDUCED_MODE) {
1759                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1760                         return PHY_INTERFACE_MODE_RMII;
1761                 }
1762                 else {
1763                         phy_interface_t interface = priv->interface;
1764
1765                         /* This isn't autodetected right now, so it must
1766                          * be set by the device tree or platform code.
1767                          */
1768                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1769                                 return PHY_INTERFACE_MODE_RGMII_ID;
1770
1771                         return PHY_INTERFACE_MODE_RGMII;
1772                 }
1773         }
1774
1775         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1776                 return PHY_INTERFACE_MODE_GMII;
1777
1778         return PHY_INTERFACE_MODE_MII;
1779 }
1780
1781
1782 /* Initializes driver's PHY state, and attaches to the PHY.
1783  * Returns 0 on success.
1784  */
1785 static int init_phy(struct net_device *dev)
1786 {
1787         struct gfar_private *priv = netdev_priv(dev);
1788         uint gigabit_support =
1789                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1790                 GFAR_SUPPORTED_GBIT : 0;
1791         phy_interface_t interface;
1792         struct phy_device *phydev;
1793         struct ethtool_eee edata;
1794
1795         priv->oldlink = 0;
1796         priv->oldspeed = 0;
1797         priv->oldduplex = -1;
1798
1799         interface = gfar_get_interface(dev);
1800
1801         phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1802                                 interface);
1803         if (!phydev) {
1804                 dev_err(&dev->dev, "could not attach to PHY\n");
1805                 return -ENODEV;
1806         }
1807
1808         if (interface == PHY_INTERFACE_MODE_SGMII)
1809                 gfar_configure_serdes(dev);
1810
1811         /* Remove any features not supported by the controller */
1812         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1813         phydev->advertising = phydev->supported;
1814
1815         /* Add support for flow control */
1816         phy_support_asym_pause(phydev);
1817
1818         /* disable EEE autoneg, EEE not supported by eTSEC */
1819         memset(&edata, 0, sizeof(struct ethtool_eee));
1820         phy_ethtool_set_eee(phydev, &edata);
1821
1822         return 0;
1823 }
1824
1825 /* Initialize TBI PHY interface for communicating with the
1826  * SERDES lynx PHY on the chip.  We communicate with this PHY
1827  * through the MDIO bus on each controller, treating it as a
1828  * "normal" PHY at the address found in the TBIPA register.  We assume
1829  * that the TBIPA register is valid.  Either the MDIO bus code will set
1830  * it to a value that doesn't conflict with other PHYs on the bus, or the
1831  * value doesn't matter, as there are no other PHYs on the bus.
1832  */
1833 static void gfar_configure_serdes(struct net_device *dev)
1834 {
1835         struct gfar_private *priv = netdev_priv(dev);
1836         struct phy_device *tbiphy;
1837
1838         if (!priv->tbi_node) {
1839                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1840                                     "device tree specify a tbi-handle\n");
1841                 return;
1842         }
1843
1844         tbiphy = of_phy_find_device(priv->tbi_node);
1845         if (!tbiphy) {
1846                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1847                 return;
1848         }
1849
1850         /* If the link is already up, we must already be ok, and don't need to
1851          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1852          * everything for us?  Resetting it takes the link down and requires
1853          * several seconds for it to come back.
1854          */
1855         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1856                 put_device(&tbiphy->mdio.dev);
1857                 return;
1858         }
1859
1860         /* Single clk mode, mii mode off(for serdes communication) */
1861         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1862
1863         phy_write(tbiphy, MII_ADVERTISE,
1864                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1865                   ADVERTISE_1000XPSE_ASYM);
1866
1867         phy_write(tbiphy, MII_BMCR,
1868                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1869                   BMCR_SPEED1000);
1870
1871         put_device(&tbiphy->mdio.dev);
1872 }
1873
1874 static int __gfar_is_rx_idle(struct gfar_private *priv)
1875 {
1876         u32 res;
1877
1878         /* Normaly TSEC should not hang on GRS commands, so we should
1879          * actually wait for IEVENT_GRSC flag.
1880          */
1881         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1882                 return 0;
1883
1884         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1885          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1886          * and the Rx can be safely reset.
1887          */
1888         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1889         res &= 0x7f807f80;
1890         if ((res & 0xffff) == (res >> 16))
1891                 return 1;
1892
1893         return 0;
1894 }
1895
1896 /* Halt the receive and transmit queues */
1897 static void gfar_halt_nodisable(struct gfar_private *priv)
1898 {
1899         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1900         u32 tempval;
1901         unsigned int timeout;
1902         int stopped;
1903
1904         gfar_ints_disable(priv);
1905
1906         if (gfar_is_dma_stopped(priv))
1907                 return;
1908
1909         /* Stop the DMA, and wait for it to stop */
1910         tempval = gfar_read(&regs->dmactrl);
1911         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1912         gfar_write(&regs->dmactrl, tempval);
1913
1914 retry:
1915         timeout = 1000;
1916         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1917                 cpu_relax();
1918                 timeout--;
1919         }
1920
1921         if (!timeout)
1922                 stopped = gfar_is_dma_stopped(priv);
1923
1924         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1925             !__gfar_is_rx_idle(priv))
1926                 goto retry;
1927 }
1928
1929 /* Halt the receive and transmit queues */
1930 void gfar_halt(struct gfar_private *priv)
1931 {
1932         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1933         u32 tempval;
1934
1935         /* Dissable the Rx/Tx hw queues */
1936         gfar_write(&regs->rqueue, 0);
1937         gfar_write(&regs->tqueue, 0);
1938
1939         mdelay(10);
1940
1941         gfar_halt_nodisable(priv);
1942
1943         /* Disable Rx/Tx DMA */
1944         tempval = gfar_read(&regs->maccfg1);
1945         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1946         gfar_write(&regs->maccfg1, tempval);
1947 }
1948
1949 void stop_gfar(struct net_device *dev)
1950 {
1951         struct gfar_private *priv = netdev_priv(dev);
1952
1953         netif_tx_stop_all_queues(dev);
1954
1955         smp_mb__before_atomic();
1956         set_bit(GFAR_DOWN, &priv->state);
1957         smp_mb__after_atomic();
1958
1959         disable_napi(priv);
1960
1961         /* disable ints and gracefully shut down Rx/Tx DMA */
1962         gfar_halt(priv);
1963
1964         phy_stop(dev->phydev);
1965
1966         free_skb_resources(priv);
1967 }
1968
1969 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1970 {
1971         struct txbd8 *txbdp;
1972         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1973         int i, j;
1974
1975         txbdp = tx_queue->tx_bd_base;
1976
1977         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1978                 if (!tx_queue->tx_skbuff[i])
1979                         continue;
1980
1981                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1982                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1983                 txbdp->lstatus = 0;
1984                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1985                      j++) {
1986                         txbdp++;
1987                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1988                                        be16_to_cpu(txbdp->length),
1989                                        DMA_TO_DEVICE);
1990                 }
1991                 txbdp++;
1992                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1993                 tx_queue->tx_skbuff[i] = NULL;
1994         }
1995         kfree(tx_queue->tx_skbuff);
1996         tx_queue->tx_skbuff = NULL;
1997 }
1998
1999 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
2000 {
2001         int i;
2002
2003         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
2004
2005         if (rx_queue->skb)
2006                 dev_kfree_skb(rx_queue->skb);
2007
2008         for (i = 0; i < rx_queue->rx_ring_size; i++) {
2009                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
2010
2011                 rxbdp->lstatus = 0;
2012                 rxbdp->bufPtr = 0;
2013                 rxbdp++;
2014
2015                 if (!rxb->page)
2016                         continue;
2017
2018                 dma_unmap_page(rx_queue->dev, rxb->dma,
2019                                PAGE_SIZE, DMA_FROM_DEVICE);
2020                 __free_page(rxb->page);
2021
2022                 rxb->page = NULL;
2023         }
2024
2025         kfree(rx_queue->rx_buff);
2026         rx_queue->rx_buff = NULL;
2027 }
2028
2029 /* If there are any tx skbs or rx skbs still around, free them.
2030  * Then free tx_skbuff and rx_skbuff
2031  */
2032 static void free_skb_resources(struct gfar_private *priv)
2033 {
2034         struct gfar_priv_tx_q *tx_queue = NULL;
2035         struct gfar_priv_rx_q *rx_queue = NULL;
2036         int i;
2037
2038         /* Go through all the buffer descriptors and free their data buffers */
2039         for (i = 0; i < priv->num_tx_queues; i++) {
2040                 struct netdev_queue *txq;
2041
2042                 tx_queue = priv->tx_queue[i];
2043                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2044                 if (tx_queue->tx_skbuff)
2045                         free_skb_tx_queue(tx_queue);
2046                 netdev_tx_reset_queue(txq);
2047         }
2048
2049         for (i = 0; i < priv->num_rx_queues; i++) {
2050                 rx_queue = priv->rx_queue[i];
2051                 if (rx_queue->rx_buff)
2052                         free_skb_rx_queue(rx_queue);
2053         }
2054
2055         dma_free_coherent(priv->dev,
2056                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2057                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2058                           priv->tx_queue[0]->tx_bd_base,
2059                           priv->tx_queue[0]->tx_bd_dma_base);
2060 }
2061
2062 void gfar_start(struct gfar_private *priv)
2063 {
2064         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2065         u32 tempval;
2066         int i = 0;
2067
2068         /* Enable Rx/Tx hw queues */
2069         gfar_write(&regs->rqueue, priv->rqueue);
2070         gfar_write(&regs->tqueue, priv->tqueue);
2071
2072         /* Initialize DMACTRL to have WWR and WOP */
2073         tempval = gfar_read(&regs->dmactrl);
2074         tempval |= DMACTRL_INIT_SETTINGS;
2075         gfar_write(&regs->dmactrl, tempval);
2076
2077         /* Make sure we aren't stopped */
2078         tempval = gfar_read(&regs->dmactrl);
2079         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2080         gfar_write(&regs->dmactrl, tempval);
2081
2082         for (i = 0; i < priv->num_grps; i++) {
2083                 regs = priv->gfargrp[i].regs;
2084                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2085                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2086                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2087         }
2088
2089         /* Enable Rx/Tx DMA */
2090         tempval = gfar_read(&regs->maccfg1);
2091         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2092         gfar_write(&regs->maccfg1, tempval);
2093
2094         gfar_ints_enable(priv);
2095
2096         netif_trans_update(priv->ndev); /* prevent tx timeout */
2097 }
2098
2099 static void free_grp_irqs(struct gfar_priv_grp *grp)
2100 {
2101         free_irq(gfar_irq(grp, TX)->irq, grp);
2102         free_irq(gfar_irq(grp, RX)->irq, grp);
2103         free_irq(gfar_irq(grp, ER)->irq, grp);
2104 }
2105
2106 static int register_grp_irqs(struct gfar_priv_grp *grp)
2107 {
2108         struct gfar_private *priv = grp->priv;
2109         struct net_device *dev = priv->ndev;
2110         int err;
2111
2112         /* If the device has multiple interrupts, register for
2113          * them.  Otherwise, only register for the one
2114          */
2115         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2116                 /* Install our interrupt handlers for Error,
2117                  * Transmit, and Receive
2118                  */
2119                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2120                                   gfar_irq(grp, ER)->name, grp);
2121                 if (err < 0) {
2122                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2123                                   gfar_irq(grp, ER)->irq);
2124
2125                         goto err_irq_fail;
2126                 }
2127                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2128
2129                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2130                                   gfar_irq(grp, TX)->name, grp);
2131                 if (err < 0) {
2132                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2133                                   gfar_irq(grp, TX)->irq);
2134                         goto tx_irq_fail;
2135                 }
2136                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2137                                   gfar_irq(grp, RX)->name, grp);
2138                 if (err < 0) {
2139                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2140                                   gfar_irq(grp, RX)->irq);
2141                         goto rx_irq_fail;
2142                 }
2143                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2144
2145         } else {
2146                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2147                                   gfar_irq(grp, TX)->name, grp);
2148                 if (err < 0) {
2149                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2150                                   gfar_irq(grp, TX)->irq);
2151                         goto err_irq_fail;
2152                 }
2153                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2154         }
2155
2156         return 0;
2157
2158 rx_irq_fail:
2159         free_irq(gfar_irq(grp, TX)->irq, grp);
2160 tx_irq_fail:
2161         free_irq(gfar_irq(grp, ER)->irq, grp);
2162 err_irq_fail:
2163         return err;
2164
2165 }
2166
2167 static void gfar_free_irq(struct gfar_private *priv)
2168 {
2169         int i;
2170
2171         /* Free the IRQs */
2172         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2173                 for (i = 0; i < priv->num_grps; i++)
2174                         free_grp_irqs(&priv->gfargrp[i]);
2175         } else {
2176                 for (i = 0; i < priv->num_grps; i++)
2177                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2178                                  &priv->gfargrp[i]);
2179         }
2180 }
2181
2182 static int gfar_request_irq(struct gfar_private *priv)
2183 {
2184         int err, i, j;
2185
2186         for (i = 0; i < priv->num_grps; i++) {
2187                 err = register_grp_irqs(&priv->gfargrp[i]);
2188                 if (err) {
2189                         for (j = 0; j < i; j++)
2190                                 free_grp_irqs(&priv->gfargrp[j]);
2191                         return err;
2192                 }
2193         }
2194
2195         return 0;
2196 }
2197
2198 /* Bring the controller up and running */
2199 int startup_gfar(struct net_device *ndev)
2200 {
2201         struct gfar_private *priv = netdev_priv(ndev);
2202         int err;
2203
2204         gfar_mac_reset(priv);
2205
2206         err = gfar_alloc_skb_resources(ndev);
2207         if (err)
2208                 return err;
2209
2210         gfar_init_tx_rx_base(priv);
2211
2212         smp_mb__before_atomic();
2213         clear_bit(GFAR_DOWN, &priv->state);
2214         smp_mb__after_atomic();
2215
2216         /* Start Rx/Tx DMA and enable the interrupts */
2217         gfar_start(priv);
2218
2219         /* force link state update after mac reset */
2220         priv->oldlink = 0;
2221         priv->oldspeed = 0;
2222         priv->oldduplex = -1;
2223
2224         phy_start(ndev->phydev);
2225
2226         enable_napi(priv);
2227
2228         netif_tx_wake_all_queues(ndev);
2229
2230         return 0;
2231 }
2232
2233 /* Called when something needs to use the ethernet device
2234  * Returns 0 for success.
2235  */
2236 static int gfar_enet_open(struct net_device *dev)
2237 {
2238         struct gfar_private *priv = netdev_priv(dev);
2239         int err;
2240
2241         err = init_phy(dev);
2242         if (err)
2243                 return err;
2244
2245         err = gfar_request_irq(priv);
2246         if (err)
2247                 return err;
2248
2249         err = startup_gfar(dev);
2250         if (err)
2251                 return err;
2252
2253         return err;
2254 }
2255
2256 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2257 {
2258         struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
2259
2260         memset(fcb, 0, GMAC_FCB_LEN);
2261
2262         return fcb;
2263 }
2264
2265 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2266                                     int fcb_length)
2267 {
2268         /* If we're here, it's a IP packet with a TCP or UDP
2269          * payload.  We set it to checksum, using a pseudo-header
2270          * we provide
2271          */
2272         u8 flags = TXFCB_DEFAULT;
2273
2274         /* Tell the controller what the protocol is
2275          * And provide the already calculated phcs
2276          */
2277         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2278                 flags |= TXFCB_UDP;
2279                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2280         } else
2281                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2282
2283         /* l3os is the distance between the start of the
2284          * frame (skb->data) and the start of the IP hdr.
2285          * l4os is the distance between the start of the
2286          * l3 hdr and the l4 hdr
2287          */
2288         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2289         fcb->l4os = skb_network_header_len(skb);
2290
2291         fcb->flags = flags;
2292 }
2293
2294 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2295 {
2296         fcb->flags |= TXFCB_VLN;
2297         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2298 }
2299
2300 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2301                                       struct txbd8 *base, int ring_size)
2302 {
2303         struct txbd8 *new_bd = bdp + stride;
2304
2305         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2306 }
2307
2308 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2309                                       int ring_size)
2310 {
2311         return skip_txbd(bdp, 1, base, ring_size);
2312 }
2313
2314 /* eTSEC12: csum generation not supported for some fcb offsets */
2315 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2316                                        unsigned long fcb_addr)
2317 {
2318         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2319                (fcb_addr % 0x20) > 0x18);
2320 }
2321
2322 /* eTSEC76: csum generation for frames larger than 2500 may
2323  * cause excess delays before start of transmission
2324  */
2325 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2326                                        unsigned int len)
2327 {
2328         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2329                (len > 2500));
2330 }
2331
2332 /* This is called by the kernel when a frame is ready for transmission.
2333  * It is pointed to by the dev->hard_start_xmit function pointer
2334  */
2335 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2336 {
2337         struct gfar_private *priv = netdev_priv(dev);
2338         struct gfar_priv_tx_q *tx_queue = NULL;
2339         struct netdev_queue *txq;
2340         struct gfar __iomem *regs = NULL;
2341         struct txfcb *fcb = NULL;
2342         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2343         u32 lstatus;
2344         skb_frag_t *frag;
2345         int i, rq = 0;
2346         int do_tstamp, do_csum, do_vlan;
2347         u32 bufaddr;
2348         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2349
2350         rq = skb->queue_mapping;
2351         tx_queue = priv->tx_queue[rq];
2352         txq = netdev_get_tx_queue(dev, rq);
2353         base = tx_queue->tx_bd_base;
2354         regs = tx_queue->grp->regs;
2355
2356         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2357         do_vlan = skb_vlan_tag_present(skb);
2358         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2359                     priv->hwts_tx_en;
2360
2361         if (do_csum || do_vlan)
2362                 fcb_len = GMAC_FCB_LEN;
2363
2364         /* check if time stamp should be generated */
2365         if (unlikely(do_tstamp))
2366                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2367
2368         /* make space for additional header when fcb is needed */
2369         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2370                 struct sk_buff *skb_new;
2371
2372                 skb_new = skb_realloc_headroom(skb, fcb_len);
2373                 if (!skb_new) {
2374                         dev->stats.tx_errors++;
2375                         dev_kfree_skb_any(skb);
2376                         return NETDEV_TX_OK;
2377                 }
2378
2379                 if (skb->sk)
2380                         skb_set_owner_w(skb_new, skb->sk);
2381                 dev_consume_skb_any(skb);
2382                 skb = skb_new;
2383         }
2384
2385         /* total number of fragments in the SKB */
2386         nr_frags = skb_shinfo(skb)->nr_frags;
2387
2388         /* calculate the required number of TxBDs for this skb */
2389         if (unlikely(do_tstamp))
2390                 nr_txbds = nr_frags + 2;
2391         else
2392                 nr_txbds = nr_frags + 1;
2393
2394         /* check if there is space to queue this packet */
2395         if (nr_txbds > tx_queue->num_txbdfree) {
2396                 /* no space, stop the queue */
2397                 netif_tx_stop_queue(txq);
2398                 dev->stats.tx_fifo_errors++;
2399                 return NETDEV_TX_BUSY;
2400         }
2401
2402         /* Update transmit stats */
2403         bytes_sent = skb->len;
2404         tx_queue->stats.tx_bytes += bytes_sent;
2405         /* keep Tx bytes on wire for BQL accounting */
2406         GFAR_CB(skb)->bytes_sent = bytes_sent;
2407         tx_queue->stats.tx_packets++;
2408
2409         txbdp = txbdp_start = tx_queue->cur_tx;
2410         lstatus = be32_to_cpu(txbdp->lstatus);
2411
2412         /* Add TxPAL between FCB and frame if required */
2413         if (unlikely(do_tstamp)) {
2414                 skb_push(skb, GMAC_TXPAL_LEN);
2415                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2416         }
2417
2418         /* Add TxFCB if required */
2419         if (fcb_len) {
2420                 fcb = gfar_add_fcb(skb);
2421                 lstatus |= BD_LFLAG(TXBD_TOE);
2422         }
2423
2424         /* Set up checksumming */
2425         if (do_csum) {
2426                 gfar_tx_checksum(skb, fcb, fcb_len);
2427
2428                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2429                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2430                         __skb_pull(skb, GMAC_FCB_LEN);
2431                         skb_checksum_help(skb);
2432                         if (do_vlan || do_tstamp) {
2433                                 /* put back a new fcb for vlan/tstamp TOE */
2434                                 fcb = gfar_add_fcb(skb);
2435                         } else {
2436                                 /* Tx TOE not used */
2437                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2438                                 fcb = NULL;
2439                         }
2440                 }
2441         }
2442
2443         if (do_vlan)
2444                 gfar_tx_vlan(skb, fcb);
2445
2446         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2447                                  DMA_TO_DEVICE);
2448         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2449                 goto dma_map_err;
2450
2451         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2452
2453         /* Time stamp insertion requires one additional TxBD */
2454         if (unlikely(do_tstamp))
2455                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2456                                                  tx_queue->tx_ring_size);
2457
2458         if (likely(!nr_frags)) {
2459                 if (likely(!do_tstamp))
2460                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2461         } else {
2462                 u32 lstatus_start = lstatus;
2463
2464                 /* Place the fragment addresses and lengths into the TxBDs */
2465                 frag = &skb_shinfo(skb)->frags[0];
2466                 for (i = 0; i < nr_frags; i++, frag++) {
2467                         unsigned int size;
2468
2469                         /* Point at the next BD, wrapping as needed */
2470                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2471
2472                         size = skb_frag_size(frag);
2473
2474                         lstatus = be32_to_cpu(txbdp->lstatus) | size |
2475                                   BD_LFLAG(TXBD_READY);
2476
2477                         /* Handle the last BD specially */
2478                         if (i == nr_frags - 1)
2479                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2480
2481                         bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
2482                                                    size, DMA_TO_DEVICE);
2483                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2484                                 goto dma_map_err;
2485
2486                         /* set the TxBD length and buffer pointer */
2487                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2488                         txbdp->lstatus = cpu_to_be32(lstatus);
2489                 }
2490
2491                 lstatus = lstatus_start;
2492         }
2493
2494         /* If time stamping is requested one additional TxBD must be set up. The
2495          * first TxBD points to the FCB and must have a data length of
2496          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2497          * the full frame length.
2498          */
2499         if (unlikely(do_tstamp)) {
2500                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2501
2502                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2503                 bufaddr += fcb_len;
2504
2505                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2506                               (skb_headlen(skb) - fcb_len);
2507                 if (!nr_frags)
2508                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2509
2510                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2511                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2512                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2513
2514                 /* Setup tx hardware time stamping */
2515                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2516                 fcb->ptp = 1;
2517         } else {
2518                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2519         }
2520
2521         netdev_tx_sent_queue(txq, bytes_sent);
2522
2523         gfar_wmb();
2524
2525         txbdp_start->lstatus = cpu_to_be32(lstatus);
2526
2527         gfar_wmb(); /* force lstatus write before tx_skbuff */
2528
2529         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2530
2531         /* Update the current skb pointer to the next entry we will use
2532          * (wrapping if necessary)
2533          */
2534         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2535                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2536
2537         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2538
2539         /* We can work in parallel with gfar_clean_tx_ring(), except
2540          * when modifying num_txbdfree. Note that we didn't grab the lock
2541          * when we were reading the num_txbdfree and checking for available
2542          * space, that's because outside of this function it can only grow.
2543          */
2544         spin_lock_bh(&tx_queue->txlock);
2545         /* reduce TxBD free count */
2546         tx_queue->num_txbdfree -= (nr_txbds);
2547         spin_unlock_bh(&tx_queue->txlock);
2548
2549         /* If the next BD still needs to be cleaned up, then the bds
2550          * are full.  We need to tell the kernel to stop sending us stuff.
2551          */
2552         if (!tx_queue->num_txbdfree) {
2553                 netif_tx_stop_queue(txq);
2554
2555                 dev->stats.tx_fifo_errors++;
2556         }
2557
2558         /* Tell the DMA to go go go */
2559         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2560
2561         return NETDEV_TX_OK;
2562
2563 dma_map_err:
2564         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2565         if (do_tstamp)
2566                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2567         for (i = 0; i < nr_frags; i++) {
2568                 lstatus = be32_to_cpu(txbdp->lstatus);
2569                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2570                         break;
2571
2572                 lstatus &= ~BD_LFLAG(TXBD_READY);
2573                 txbdp->lstatus = cpu_to_be32(lstatus);
2574                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2575                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2576                                DMA_TO_DEVICE);
2577                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2578         }
2579         gfar_wmb();
2580         dev_kfree_skb_any(skb);
2581         return NETDEV_TX_OK;
2582 }
2583
2584 /* Stops the kernel queue, and halts the controller */
2585 static int gfar_close(struct net_device *dev)
2586 {
2587         struct gfar_private *priv = netdev_priv(dev);
2588
2589         cancel_work_sync(&priv->reset_task);
2590         stop_gfar(dev);
2591
2592         /* Disconnect from the PHY */
2593         phy_disconnect(dev->phydev);
2594
2595         gfar_free_irq(priv);
2596
2597         return 0;
2598 }
2599
2600 /* Changes the mac address if the controller is not running. */
2601 static int gfar_set_mac_address(struct net_device *dev)
2602 {
2603         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2604
2605         return 0;
2606 }
2607
2608 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2609 {
2610         struct gfar_private *priv = netdev_priv(dev);
2611
2612         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2613                 cpu_relax();
2614
2615         if (dev->flags & IFF_UP)
2616                 stop_gfar(dev);
2617
2618         dev->mtu = new_mtu;
2619
2620         if (dev->flags & IFF_UP)
2621                 startup_gfar(dev);
2622
2623         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2624
2625         return 0;
2626 }
2627
2628 void reset_gfar(struct net_device *ndev)
2629 {
2630         struct gfar_private *priv = netdev_priv(ndev);
2631
2632         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2633                 cpu_relax();
2634
2635         stop_gfar(ndev);
2636         startup_gfar(ndev);
2637
2638         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2639 }
2640
2641 /* gfar_reset_task gets scheduled when a packet has not been
2642  * transmitted after a set amount of time.
2643  * For now, assume that clearing out all the structures, and
2644  * starting over will fix the problem.
2645  */
2646 static void gfar_reset_task(struct work_struct *work)
2647 {
2648         struct gfar_private *priv = container_of(work, struct gfar_private,
2649                                                  reset_task);
2650         reset_gfar(priv->ndev);
2651 }
2652
2653 static void gfar_timeout(struct net_device *dev)
2654 {
2655         struct gfar_private *priv = netdev_priv(dev);
2656
2657         dev->stats.tx_errors++;
2658         schedule_work(&priv->reset_task);
2659 }
2660
2661 /* Interrupt Handler for Transmit complete */
2662 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2663 {
2664         struct net_device *dev = tx_queue->dev;
2665         struct netdev_queue *txq;
2666         struct gfar_private *priv = netdev_priv(dev);
2667         struct txbd8 *bdp, *next = NULL;
2668         struct txbd8 *lbdp = NULL;
2669         struct txbd8 *base = tx_queue->tx_bd_base;
2670         struct sk_buff *skb;
2671         int skb_dirtytx;
2672         int tx_ring_size = tx_queue->tx_ring_size;
2673         int frags = 0, nr_txbds = 0;
2674         int i;
2675         int howmany = 0;
2676         int tqi = tx_queue->qindex;
2677         unsigned int bytes_sent = 0;
2678         u32 lstatus;
2679         size_t buflen;
2680
2681         txq = netdev_get_tx_queue(dev, tqi);
2682         bdp = tx_queue->dirty_tx;
2683         skb_dirtytx = tx_queue->skb_dirtytx;
2684
2685         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2686
2687                 frags = skb_shinfo(skb)->nr_frags;
2688
2689                 /* When time stamping, one additional TxBD must be freed.
2690                  * Also, we need to dma_unmap_single() the TxPAL.
2691                  */
2692                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2693                         nr_txbds = frags + 2;
2694                 else
2695                         nr_txbds = frags + 1;
2696
2697                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2698
2699                 lstatus = be32_to_cpu(lbdp->lstatus);
2700
2701                 /* Only clean completed frames */
2702                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2703                     (lstatus & BD_LENGTH_MASK))
2704                         break;
2705
2706                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2707                         next = next_txbd(bdp, base, tx_ring_size);
2708                         buflen = be16_to_cpu(next->length) +
2709                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2710                 } else
2711                         buflen = be16_to_cpu(bdp->length);
2712
2713                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2714                                  buflen, DMA_TO_DEVICE);
2715
2716                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2717                         struct skb_shared_hwtstamps shhwtstamps;
2718                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2719                                           ~0x7UL);
2720
2721                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2722                         shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2723                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2724                         skb_tstamp_tx(skb, &shhwtstamps);
2725                         gfar_clear_txbd_status(bdp);
2726                         bdp = next;
2727                 }
2728
2729                 gfar_clear_txbd_status(bdp);
2730                 bdp = next_txbd(bdp, base, tx_ring_size);
2731
2732                 for (i = 0; i < frags; i++) {
2733                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2734                                        be16_to_cpu(bdp->length),
2735                                        DMA_TO_DEVICE);
2736                         gfar_clear_txbd_status(bdp);
2737                         bdp = next_txbd(bdp, base, tx_ring_size);
2738                 }
2739
2740                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2741
2742                 dev_kfree_skb_any(skb);
2743
2744                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2745
2746                 skb_dirtytx = (skb_dirtytx + 1) &
2747                               TX_RING_MOD_MASK(tx_ring_size);
2748
2749                 howmany++;
2750                 spin_lock(&tx_queue->txlock);
2751                 tx_queue->num_txbdfree += nr_txbds;
2752                 spin_unlock(&tx_queue->txlock);
2753         }
2754
2755         /* If we freed a buffer, we can restart transmission, if necessary */
2756         if (tx_queue->num_txbdfree &&
2757             netif_tx_queue_stopped(txq) &&
2758             !(test_bit(GFAR_DOWN, &priv->state)))
2759                 netif_wake_subqueue(priv->ndev, tqi);
2760
2761         /* Update dirty indicators */
2762         tx_queue->skb_dirtytx = skb_dirtytx;
2763         tx_queue->dirty_tx = bdp;
2764
2765         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2766 }
2767
2768 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2769 {
2770         struct page *page;
2771         dma_addr_t addr;
2772
2773         page = dev_alloc_page();
2774         if (unlikely(!page))
2775                 return false;
2776
2777         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2778         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2779                 __free_page(page);
2780
2781                 return false;
2782         }
2783
2784         rxb->dma = addr;
2785         rxb->page = page;
2786         rxb->page_offset = 0;
2787
2788         return true;
2789 }
2790
2791 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2792 {
2793         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2794         struct gfar_extra_stats *estats = &priv->extra_stats;
2795
2796         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2797         atomic64_inc(&estats->rx_alloc_err);
2798 }
2799
2800 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2801                                 int alloc_cnt)
2802 {
2803         struct rxbd8 *bdp;
2804         struct gfar_rx_buff *rxb;
2805         int i;
2806
2807         i = rx_queue->next_to_use;
2808         bdp = &rx_queue->rx_bd_base[i];
2809         rxb = &rx_queue->rx_buff[i];
2810
2811         while (alloc_cnt--) {
2812                 /* try reuse page */
2813                 if (unlikely(!rxb->page)) {
2814                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2815                                 gfar_rx_alloc_err(rx_queue);
2816                                 break;
2817                         }
2818                 }
2819
2820                 /* Setup the new RxBD */
2821                 gfar_init_rxbdp(rx_queue, bdp,
2822                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2823
2824                 /* Update to the next pointer */
2825                 bdp++;
2826                 rxb++;
2827
2828                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2829                         i = 0;
2830                         bdp = rx_queue->rx_bd_base;
2831                         rxb = rx_queue->rx_buff;
2832                 }
2833         }
2834
2835         rx_queue->next_to_use = i;
2836         rx_queue->next_to_alloc = i;
2837 }
2838
2839 static void count_errors(u32 lstatus, struct net_device *ndev)
2840 {
2841         struct gfar_private *priv = netdev_priv(ndev);
2842         struct net_device_stats *stats = &ndev->stats;
2843         struct gfar_extra_stats *estats = &priv->extra_stats;
2844
2845         /* If the packet was truncated, none of the other errors matter */
2846         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2847                 stats->rx_length_errors++;
2848
2849                 atomic64_inc(&estats->rx_trunc);
2850
2851                 return;
2852         }
2853         /* Count the errors, if there were any */
2854         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2855                 stats->rx_length_errors++;
2856
2857                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2858                         atomic64_inc(&estats->rx_large);
2859                 else
2860                         atomic64_inc(&estats->rx_short);
2861         }
2862         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2863                 stats->rx_frame_errors++;
2864                 atomic64_inc(&estats->rx_nonoctet);
2865         }
2866         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2867                 atomic64_inc(&estats->rx_crcerr);
2868                 stats->rx_crc_errors++;
2869         }
2870         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2871                 atomic64_inc(&estats->rx_overrun);
2872                 stats->rx_over_errors++;
2873         }
2874 }
2875
2876 irqreturn_t gfar_receive(int irq, void *grp_id)
2877 {
2878         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2879         unsigned long flags;
2880         u32 imask, ievent;
2881
2882         ievent = gfar_read(&grp->regs->ievent);
2883
2884         if (unlikely(ievent & IEVENT_FGPI)) {
2885                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2886                 return IRQ_HANDLED;
2887         }
2888
2889         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2890                 spin_lock_irqsave(&grp->grplock, flags);
2891                 imask = gfar_read(&grp->regs->imask);
2892                 imask &= IMASK_RX_DISABLED;
2893                 gfar_write(&grp->regs->imask, imask);
2894                 spin_unlock_irqrestore(&grp->grplock, flags);
2895                 __napi_schedule(&grp->napi_rx);
2896         } else {
2897                 /* Clear IEVENT, so interrupts aren't called again
2898                  * because of the packets that have already arrived.
2899                  */
2900                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2901         }
2902
2903         return IRQ_HANDLED;
2904 }
2905
2906 /* Interrupt Handler for Transmit complete */
2907 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2908 {
2909         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2910         unsigned long flags;
2911         u32 imask;
2912
2913         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2914                 spin_lock_irqsave(&grp->grplock, flags);
2915                 imask = gfar_read(&grp->regs->imask);
2916                 imask &= IMASK_TX_DISABLED;
2917                 gfar_write(&grp->regs->imask, imask);
2918                 spin_unlock_irqrestore(&grp->grplock, flags);
2919                 __napi_schedule(&grp->napi_tx);
2920         } else {
2921                 /* Clear IEVENT, so interrupts aren't called again
2922                  * because of the packets that have already arrived.
2923                  */
2924                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2925         }
2926
2927         return IRQ_HANDLED;
2928 }
2929
2930 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2931                              struct sk_buff *skb, bool first)
2932 {
2933         int size = lstatus & BD_LENGTH_MASK;
2934         struct page *page = rxb->page;
2935
2936         if (likely(first)) {
2937                 skb_put(skb, size);
2938         } else {
2939                 /* the last fragments' length contains the full frame length */
2940                 if (lstatus & BD_LFLAG(RXBD_LAST))
2941                         size -= skb->len;
2942
2943                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2944                                 rxb->page_offset + RXBUF_ALIGNMENT,
2945                                 size, GFAR_RXB_TRUESIZE);
2946         }
2947
2948         /* try reuse page */
2949         if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2950                 return false;
2951
2952         /* change offset to the other half */
2953         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2954
2955         page_ref_inc(page);
2956
2957         return true;
2958 }
2959
2960 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2961                                struct gfar_rx_buff *old_rxb)
2962 {
2963         struct gfar_rx_buff *new_rxb;
2964         u16 nta = rxq->next_to_alloc;
2965
2966         new_rxb = &rxq->rx_buff[nta];
2967
2968         /* find next buf that can reuse a page */
2969         nta++;
2970         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2971
2972         /* copy page reference */
2973         *new_rxb = *old_rxb;
2974
2975         /* sync for use by the device */
2976         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2977                                          old_rxb->page_offset,
2978                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2979 }
2980
2981 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2982                                             u32 lstatus, struct sk_buff *skb)
2983 {
2984         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2985         struct page *page = rxb->page;
2986         bool first = false;
2987
2988         if (likely(!skb)) {
2989                 void *buff_addr = page_address(page) + rxb->page_offset;
2990
2991                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2992                 if (unlikely(!skb)) {
2993                         gfar_rx_alloc_err(rx_queue);
2994                         return NULL;
2995                 }
2996                 skb_reserve(skb, RXBUF_ALIGNMENT);
2997                 first = true;
2998         }
2999
3000         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
3001                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
3002
3003         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
3004                 /* reuse the free half of the page */
3005                 gfar_reuse_rx_page(rx_queue, rxb);
3006         } else {
3007                 /* page cannot be reused, unmap it */
3008                 dma_unmap_page(rx_queue->dev, rxb->dma,
3009                                PAGE_SIZE, DMA_FROM_DEVICE);
3010         }
3011
3012         /* clear rxb content */
3013         rxb->page = NULL;
3014
3015         return skb;
3016 }
3017
3018 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3019 {
3020         /* If valid headers were found, and valid sums
3021          * were verified, then we tell the kernel that no
3022          * checksumming is necessary.  Otherwise, it is [FIXME]
3023          */
3024         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3025             (RXFCB_CIP | RXFCB_CTU))
3026                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3027         else
3028                 skb_checksum_none_assert(skb);
3029 }
3030
3031 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3032 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3033 {
3034         struct gfar_private *priv = netdev_priv(ndev);
3035         struct rxfcb *fcb = NULL;
3036
3037         /* fcb is at the beginning if exists */
3038         fcb = (struct rxfcb *)skb->data;
3039
3040         /* Remove the FCB from the skb
3041          * Remove the padded bytes, if there are any
3042          */
3043         if (priv->uses_rxfcb)
3044                 skb_pull(skb, GMAC_FCB_LEN);
3045
3046         /* Get receive timestamp from the skb */
3047         if (priv->hwts_rx_en) {
3048                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3049                 u64 *ns = (u64 *) skb->data;
3050
3051                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3052                 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
3053         }
3054
3055         if (priv->padding)
3056                 skb_pull(skb, priv->padding);
3057
3058         /* Trim off the FCS */
3059         pskb_trim(skb, skb->len - ETH_FCS_LEN);
3060
3061         if (ndev->features & NETIF_F_RXCSUM)
3062                 gfar_rx_checksum(skb, fcb);
3063
3064         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3065          * Even if vlan rx accel is disabled, on some chips
3066          * RXFCB_VLN is pseudo randomly set.
3067          */
3068         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3069             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3070                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3071                                        be16_to_cpu(fcb->vlctl));
3072 }
3073
3074 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3075  * until the budget/quota has been reached. Returns the number
3076  * of frames handled
3077  */
3078 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3079 {
3080         struct net_device *ndev = rx_queue->ndev;
3081         struct gfar_private *priv = netdev_priv(ndev);
3082         struct rxbd8 *bdp;
3083         int i, howmany = 0;
3084         struct sk_buff *skb = rx_queue->skb;
3085         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3086         unsigned int total_bytes = 0, total_pkts = 0;
3087
3088         /* Get the first full descriptor */
3089         i = rx_queue->next_to_clean;
3090
3091         while (rx_work_limit--) {
3092                 u32 lstatus;
3093
3094                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3095                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3096                         cleaned_cnt = 0;
3097                 }
3098
3099                 bdp = &rx_queue->rx_bd_base[i];
3100                 lstatus = be32_to_cpu(bdp->lstatus);
3101                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3102                         break;
3103
3104                 /* order rx buffer descriptor reads */
3105                 rmb();
3106
3107                 /* fetch next to clean buffer from the ring */
3108                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3109                 if (unlikely(!skb))
3110                         break;
3111
3112                 cleaned_cnt++;
3113                 howmany++;
3114
3115                 if (unlikely(++i == rx_queue->rx_ring_size))
3116                         i = 0;
3117
3118                 rx_queue->next_to_clean = i;
3119
3120                 /* fetch next buffer if not the last in frame */
3121                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3122                         continue;
3123
3124                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3125                         count_errors(lstatus, ndev);
3126
3127                         /* discard faulty buffer */
3128                         dev_kfree_skb(skb);
3129                         skb = NULL;
3130                         rx_queue->stats.rx_dropped++;
3131                         continue;
3132                 }
3133
3134                 gfar_process_frame(ndev, skb);
3135
3136                 /* Increment the number of packets */
3137                 total_pkts++;
3138                 total_bytes += skb->len;
3139
3140                 skb_record_rx_queue(skb, rx_queue->qindex);
3141
3142                 skb->protocol = eth_type_trans(skb, ndev);
3143
3144                 /* Send the packet up the stack */
3145                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3146
3147                 skb = NULL;
3148         }
3149
3150         /* Store incomplete frames for completion */
3151         rx_queue->skb = skb;
3152
3153         rx_queue->stats.rx_packets += total_pkts;
3154         rx_queue->stats.rx_bytes += total_bytes;
3155
3156         if (cleaned_cnt)
3157                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3158
3159         /* Update Last Free RxBD pointer for LFC */
3160         if (unlikely(priv->tx_actual_en)) {
3161                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3162
3163                 gfar_write(rx_queue->rfbptr, bdp_dma);
3164         }
3165
3166         return howmany;
3167 }
3168
3169 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3170 {
3171         struct gfar_priv_grp *gfargrp =
3172                 container_of(napi, struct gfar_priv_grp, napi_rx);
3173         struct gfar __iomem *regs = gfargrp->regs;
3174         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3175         int work_done = 0;
3176
3177         /* Clear IEVENT, so interrupts aren't called again
3178          * because of the packets that have already arrived
3179          */
3180         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3181
3182         work_done = gfar_clean_rx_ring(rx_queue, budget);
3183
3184         if (work_done < budget) {
3185                 u32 imask;
3186                 napi_complete_done(napi, work_done);
3187                 /* Clear the halt bit in RSTAT */
3188                 gfar_write(&regs->rstat, gfargrp->rstat);
3189
3190                 spin_lock_irq(&gfargrp->grplock);
3191                 imask = gfar_read(&regs->imask);
3192                 imask |= IMASK_RX_DEFAULT;
3193                 gfar_write(&regs->imask, imask);
3194                 spin_unlock_irq(&gfargrp->grplock);
3195         }
3196
3197         return work_done;
3198 }
3199
3200 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3201 {
3202         struct gfar_priv_grp *gfargrp =
3203                 container_of(napi, struct gfar_priv_grp, napi_tx);
3204         struct gfar __iomem *regs = gfargrp->regs;
3205         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3206         u32 imask;
3207
3208         /* Clear IEVENT, so interrupts aren't called again
3209          * because of the packets that have already arrived
3210          */
3211         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3212
3213         /* run Tx cleanup to completion */
3214         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3215                 gfar_clean_tx_ring(tx_queue);
3216
3217         napi_complete(napi);
3218
3219         spin_lock_irq(&gfargrp->grplock);
3220         imask = gfar_read(&regs->imask);
3221         imask |= IMASK_TX_DEFAULT;
3222         gfar_write(&regs->imask, imask);
3223         spin_unlock_irq(&gfargrp->grplock);
3224
3225         return 0;
3226 }
3227
3228 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3229 {
3230         struct gfar_priv_grp *gfargrp =
3231                 container_of(napi, struct gfar_priv_grp, napi_rx);
3232         struct gfar_private *priv = gfargrp->priv;
3233         struct gfar __iomem *regs = gfargrp->regs;
3234         struct gfar_priv_rx_q *rx_queue = NULL;
3235         int work_done = 0, work_done_per_q = 0;
3236         int i, budget_per_q = 0;
3237         unsigned long rstat_rxf;
3238         int num_act_queues;
3239
3240         /* Clear IEVENT, so interrupts aren't called again
3241          * because of the packets that have already arrived
3242          */
3243         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3244
3245         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3246
3247         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3248         if (num_act_queues)
3249                 budget_per_q = budget/num_act_queues;
3250
3251         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3252                 /* skip queue if not active */
3253                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3254                         continue;
3255
3256                 rx_queue = priv->rx_queue[i];
3257                 work_done_per_q =
3258                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3259                 work_done += work_done_per_q;
3260
3261                 /* finished processing this queue */
3262                 if (work_done_per_q < budget_per_q) {
3263                         /* clear active queue hw indication */
3264                         gfar_write(&regs->rstat,
3265                                    RSTAT_CLEAR_RXF0 >> i);
3266                         num_act_queues--;
3267
3268                         if (!num_act_queues)
3269                                 break;
3270                 }
3271         }
3272
3273         if (!num_act_queues) {
3274                 u32 imask;
3275                 napi_complete_done(napi, work_done);
3276
3277                 /* Clear the halt bit in RSTAT */
3278                 gfar_write(&regs->rstat, gfargrp->rstat);
3279
3280                 spin_lock_irq(&gfargrp->grplock);
3281                 imask = gfar_read(&regs->imask);
3282                 imask |= IMASK_RX_DEFAULT;
3283                 gfar_write(&regs->imask, imask);
3284                 spin_unlock_irq(&gfargrp->grplock);
3285         }
3286
3287         return work_done;
3288 }
3289
3290 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3291 {
3292         struct gfar_priv_grp *gfargrp =
3293                 container_of(napi, struct gfar_priv_grp, napi_tx);
3294         struct gfar_private *priv = gfargrp->priv;
3295         struct gfar __iomem *regs = gfargrp->regs;
3296         struct gfar_priv_tx_q *tx_queue = NULL;
3297         int has_tx_work = 0;
3298         int i;
3299
3300         /* Clear IEVENT, so interrupts aren't called again
3301          * because of the packets that have already arrived
3302          */
3303         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3304
3305         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3306                 tx_queue = priv->tx_queue[i];
3307                 /* run Tx cleanup to completion */
3308                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3309                         gfar_clean_tx_ring(tx_queue);
3310                         has_tx_work = 1;
3311                 }
3312         }
3313
3314         if (!has_tx_work) {
3315                 u32 imask;
3316                 napi_complete(napi);
3317
3318                 spin_lock_irq(&gfargrp->grplock);
3319                 imask = gfar_read(&regs->imask);
3320                 imask |= IMASK_TX_DEFAULT;
3321                 gfar_write(&regs->imask, imask);
3322                 spin_unlock_irq(&gfargrp->grplock);
3323         }
3324
3325         return 0;
3326 }
3327
3328
3329 #ifdef CONFIG_NET_POLL_CONTROLLER
3330 /* Polling 'interrupt' - used by things like netconsole to send skbs
3331  * without having to re-enable interrupts. It's not called while
3332  * the interrupt routine is executing.
3333  */
3334 static void gfar_netpoll(struct net_device *dev)
3335 {
3336         struct gfar_private *priv = netdev_priv(dev);
3337         int i;
3338
3339         /* If the device has multiple interrupts, run tx/rx */
3340         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3341                 for (i = 0; i < priv->num_grps; i++) {
3342                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3343
3344                         disable_irq(gfar_irq(grp, TX)->irq);
3345                         disable_irq(gfar_irq(grp, RX)->irq);
3346                         disable_irq(gfar_irq(grp, ER)->irq);
3347                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3348                         enable_irq(gfar_irq(grp, ER)->irq);
3349                         enable_irq(gfar_irq(grp, RX)->irq);
3350                         enable_irq(gfar_irq(grp, TX)->irq);
3351                 }
3352         } else {
3353                 for (i = 0; i < priv->num_grps; i++) {
3354                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3355
3356                         disable_irq(gfar_irq(grp, TX)->irq);
3357                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3358                         enable_irq(gfar_irq(grp, TX)->irq);
3359                 }
3360         }
3361 }
3362 #endif
3363
3364 /* The interrupt handler for devices with one interrupt */
3365 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3366 {
3367         struct gfar_priv_grp *gfargrp = grp_id;
3368
3369         /* Save ievent for future reference */
3370         u32 events = gfar_read(&gfargrp->regs->ievent);
3371
3372         /* Check for reception */
3373         if (events & IEVENT_RX_MASK)
3374                 gfar_receive(irq, grp_id);
3375
3376         /* Check for transmit completion */
3377         if (events & IEVENT_TX_MASK)
3378                 gfar_transmit(irq, grp_id);
3379
3380         /* Check for errors */
3381         if (events & IEVENT_ERR_MASK)
3382                 gfar_error(irq, grp_id);
3383
3384         return IRQ_HANDLED;
3385 }
3386
3387 /* Called every time the controller might need to be made
3388  * aware of new link state.  The PHY code conveys this
3389  * information through variables in the phydev structure, and this
3390  * function converts those variables into the appropriate
3391  * register values, and can bring down the device if needed.
3392  */
3393 static void adjust_link(struct net_device *dev)
3394 {
3395         struct gfar_private *priv = netdev_priv(dev);
3396         struct phy_device *phydev = dev->phydev;
3397
3398         if (unlikely(phydev->link != priv->oldlink ||
3399                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3400                                        phydev->speed != priv->oldspeed))))
3401                 gfar_update_link_state(priv);
3402 }
3403
3404 /* Update the hash table based on the current list of multicast
3405  * addresses we subscribe to.  Also, change the promiscuity of
3406  * the device based on the flags (this function is called
3407  * whenever dev->flags is changed
3408  */
3409 static void gfar_set_multi(struct net_device *dev)
3410 {
3411         struct netdev_hw_addr *ha;
3412         struct gfar_private *priv = netdev_priv(dev);
3413         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3414         u32 tempval;
3415
3416         if (dev->flags & IFF_PROMISC) {
3417                 /* Set RCTRL to PROM */
3418                 tempval = gfar_read(&regs->rctrl);
3419                 tempval |= RCTRL_PROM;
3420                 gfar_write(&regs->rctrl, tempval);
3421         } else {
3422                 /* Set RCTRL to not PROM */
3423                 tempval = gfar_read(&regs->rctrl);
3424                 tempval &= ~(RCTRL_PROM);
3425                 gfar_write(&regs->rctrl, tempval);
3426         }
3427
3428         if (dev->flags & IFF_ALLMULTI) {
3429                 /* Set the hash to rx all multicast frames */
3430                 gfar_write(&regs->igaddr0, 0xffffffff);
3431                 gfar_write(&regs->igaddr1, 0xffffffff);
3432                 gfar_write(&regs->igaddr2, 0xffffffff);
3433                 gfar_write(&regs->igaddr3, 0xffffffff);
3434                 gfar_write(&regs->igaddr4, 0xffffffff);
3435                 gfar_write(&regs->igaddr5, 0xffffffff);
3436                 gfar_write(&regs->igaddr6, 0xffffffff);
3437                 gfar_write(&regs->igaddr7, 0xffffffff);
3438                 gfar_write(&regs->gaddr0, 0xffffffff);
3439                 gfar_write(&regs->gaddr1, 0xffffffff);
3440                 gfar_write(&regs->gaddr2, 0xffffffff);
3441                 gfar_write(&regs->gaddr3, 0xffffffff);
3442                 gfar_write(&regs->gaddr4, 0xffffffff);
3443                 gfar_write(&regs->gaddr5, 0xffffffff);
3444                 gfar_write(&regs->gaddr6, 0xffffffff);
3445                 gfar_write(&regs->gaddr7, 0xffffffff);
3446         } else {
3447                 int em_num;
3448                 int idx;
3449
3450                 /* zero out the hash */
3451                 gfar_write(&regs->igaddr0, 0x0);
3452                 gfar_write(&regs->igaddr1, 0x0);
3453                 gfar_write(&regs->igaddr2, 0x0);
3454                 gfar_write(&regs->igaddr3, 0x0);
3455                 gfar_write(&regs->igaddr4, 0x0);
3456                 gfar_write(&regs->igaddr5, 0x0);
3457                 gfar_write(&regs->igaddr6, 0x0);
3458                 gfar_write(&regs->igaddr7, 0x0);
3459                 gfar_write(&regs->gaddr0, 0x0);
3460                 gfar_write(&regs->gaddr1, 0x0);
3461                 gfar_write(&regs->gaddr2, 0x0);
3462                 gfar_write(&regs->gaddr3, 0x0);
3463                 gfar_write(&regs->gaddr4, 0x0);
3464                 gfar_write(&regs->gaddr5, 0x0);
3465                 gfar_write(&regs->gaddr6, 0x0);
3466                 gfar_write(&regs->gaddr7, 0x0);
3467
3468                 /* If we have extended hash tables, we need to
3469                  * clear the exact match registers to prepare for
3470                  * setting them
3471                  */
3472                 if (priv->extended_hash) {
3473                         em_num = GFAR_EM_NUM + 1;
3474                         gfar_clear_exact_match(dev);
3475                         idx = 1;
3476                 } else {
3477                         idx = 0;
3478                         em_num = 0;
3479                 }
3480
3481                 if (netdev_mc_empty(dev))
3482                         return;
3483
3484                 /* Parse the list, and set the appropriate bits */
3485                 netdev_for_each_mc_addr(ha, dev) {
3486                         if (idx < em_num) {
3487                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3488                                 idx++;
3489                         } else
3490                                 gfar_set_hash_for_addr(dev, ha->addr);
3491                 }
3492         }
3493 }
3494
3495
3496 /* Clears each of the exact match registers to zero, so they
3497  * don't interfere with normal reception
3498  */
3499 static void gfar_clear_exact_match(struct net_device *dev)
3500 {
3501         int idx;
3502         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3503
3504         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3505                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3506 }
3507
3508 /* Set the appropriate hash bit for the given addr */
3509 /* The algorithm works like so:
3510  * 1) Take the Destination Address (ie the multicast address), and
3511  * do a CRC on it (little endian), and reverse the bits of the
3512  * result.
3513  * 2) Use the 8 most significant bits as a hash into a 256-entry
3514  * table.  The table is controlled through 8 32-bit registers:
3515  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3516  * gaddr7.  This means that the 3 most significant bits in the
3517  * hash index which gaddr register to use, and the 5 other bits
3518  * indicate which bit (assuming an IBM numbering scheme, which
3519  * for PowerPC (tm) is usually the case) in the register holds
3520  * the entry.
3521  */
3522 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3523 {
3524         u32 tempval;
3525         struct gfar_private *priv = netdev_priv(dev);
3526         u32 result = ether_crc(ETH_ALEN, addr);
3527         int width = priv->hash_width;
3528         u8 whichbit = (result >> (32 - width)) & 0x1f;
3529         u8 whichreg = result >> (32 - width + 5);
3530         u32 value = (1 << (31-whichbit));
3531
3532         tempval = gfar_read(priv->hash_regs[whichreg]);
3533         tempval |= value;
3534         gfar_write(priv->hash_regs[whichreg], tempval);
3535 }
3536
3537
3538 /* There are multiple MAC Address register pairs on some controllers
3539  * This function sets the numth pair to a given address
3540  */
3541 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3542                                   const u8 *addr)
3543 {
3544         struct gfar_private *priv = netdev_priv(dev);
3545         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3546         u32 tempval;
3547         u32 __iomem *macptr = &regs->macstnaddr1;
3548
3549         macptr += num*2;
3550
3551         /* For a station address of 0x12345678ABCD in transmission
3552          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3553          * MACnADDR2 is set to 0x34120000.
3554          */
3555         tempval = (addr[5] << 24) | (addr[4] << 16) |
3556                   (addr[3] << 8)  |  addr[2];
3557
3558         gfar_write(macptr, tempval);
3559
3560         tempval = (addr[1] << 24) | (addr[0] << 16);
3561
3562         gfar_write(macptr+1, tempval);
3563 }
3564
3565 /* GFAR error interrupt handler */
3566 static irqreturn_t gfar_error(int irq, void *grp_id)
3567 {
3568         struct gfar_priv_grp *gfargrp = grp_id;
3569         struct gfar __iomem *regs = gfargrp->regs;
3570         struct gfar_private *priv= gfargrp->priv;
3571         struct net_device *dev = priv->ndev;
3572
3573         /* Save ievent for future reference */
3574         u32 events = gfar_read(&regs->ievent);
3575
3576         /* Clear IEVENT */
3577         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3578
3579         /* Magic Packet is not an error. */
3580         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3581             (events & IEVENT_MAG))
3582                 events &= ~IEVENT_MAG;
3583
3584         /* Hmm... */
3585         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3586                 netdev_dbg(dev,
3587                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3588                            events, gfar_read(&regs->imask));
3589
3590         /* Update the error counters */
3591         if (events & IEVENT_TXE) {
3592                 dev->stats.tx_errors++;
3593
3594                 if (events & IEVENT_LC)
3595                         dev->stats.tx_window_errors++;
3596                 if (events & IEVENT_CRL)
3597                         dev->stats.tx_aborted_errors++;
3598                 if (events & IEVENT_XFUN) {
3599                         netif_dbg(priv, tx_err, dev,
3600                                   "TX FIFO underrun, packet dropped\n");
3601                         dev->stats.tx_dropped++;
3602                         atomic64_inc(&priv->extra_stats.tx_underrun);
3603
3604                         schedule_work(&priv->reset_task);
3605                 }
3606                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3607         }
3608         if (events & IEVENT_BSY) {
3609                 dev->stats.rx_over_errors++;
3610                 atomic64_inc(&priv->extra_stats.rx_bsy);
3611
3612                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3613                           gfar_read(&regs->rstat));
3614         }
3615         if (events & IEVENT_BABR) {
3616                 dev->stats.rx_errors++;
3617                 atomic64_inc(&priv->extra_stats.rx_babr);
3618
3619                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3620         }
3621         if (events & IEVENT_EBERR) {
3622                 atomic64_inc(&priv->extra_stats.eberr);
3623                 netif_dbg(priv, rx_err, dev, "bus error\n");
3624         }
3625         if (events & IEVENT_RXC)
3626                 netif_dbg(priv, rx_status, dev, "control frame\n");
3627
3628         if (events & IEVENT_BABT) {
3629                 atomic64_inc(&priv->extra_stats.tx_babt);
3630                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3631         }
3632         return IRQ_HANDLED;
3633 }
3634
3635 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3636 {
3637         struct net_device *ndev = priv->ndev;
3638         struct phy_device *phydev = ndev->phydev;
3639         u32 val = 0;
3640
3641         if (!phydev->duplex)
3642                 return val;
3643
3644         if (!priv->pause_aneg_en) {
3645                 if (priv->tx_pause_en)
3646                         val |= MACCFG1_TX_FLOW;
3647                 if (priv->rx_pause_en)
3648                         val |= MACCFG1_RX_FLOW;
3649         } else {
3650                 u16 lcl_adv, rmt_adv;
3651                 u8 flowctrl;
3652                 /* get link partner capabilities */
3653                 rmt_adv = 0;
3654                 if (phydev->pause)
3655                         rmt_adv = LPA_PAUSE_CAP;
3656                 if (phydev->asym_pause)
3657                         rmt_adv |= LPA_PAUSE_ASYM;
3658
3659                 lcl_adv = ethtool_adv_to_lcl_adv_t(phydev->advertising);
3660                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3661                 if (flowctrl & FLOW_CTRL_TX)
3662                         val |= MACCFG1_TX_FLOW;
3663                 if (flowctrl & FLOW_CTRL_RX)
3664                         val |= MACCFG1_RX_FLOW;
3665         }
3666
3667         return val;
3668 }
3669
3670 static noinline void gfar_update_link_state(struct gfar_private *priv)
3671 {
3672         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3673         struct net_device *ndev = priv->ndev;
3674         struct phy_device *phydev = ndev->phydev;
3675         struct gfar_priv_rx_q *rx_queue = NULL;
3676         int i;
3677
3678         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3679                 return;
3680
3681         if (phydev->link) {
3682                 u32 tempval1 = gfar_read(&regs->maccfg1);
3683                 u32 tempval = gfar_read(&regs->maccfg2);
3684                 u32 ecntrl = gfar_read(&regs->ecntrl);
3685                 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
3686
3687                 if (phydev->duplex != priv->oldduplex) {
3688                         if (!(phydev->duplex))
3689                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3690                         else
3691                                 tempval |= MACCFG2_FULL_DUPLEX;
3692
3693                         priv->oldduplex = phydev->duplex;
3694                 }
3695
3696                 if (phydev->speed != priv->oldspeed) {
3697                         switch (phydev->speed) {
3698                         case 1000:
3699                                 tempval =
3700                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3701
3702                                 ecntrl &= ~(ECNTRL_R100);
3703                                 break;
3704                         case 100:
3705                         case 10:
3706                                 tempval =
3707                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3708
3709                                 /* Reduced mode distinguishes
3710                                  * between 10 and 100
3711                                  */
3712                                 if (phydev->speed == SPEED_100)
3713                                         ecntrl |= ECNTRL_R100;
3714                                 else
3715                                         ecntrl &= ~(ECNTRL_R100);
3716                                 break;
3717                         default:
3718                                 netif_warn(priv, link, priv->ndev,
3719                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3720                                            phydev->speed);
3721                                 break;
3722                         }
3723
3724                         priv->oldspeed = phydev->speed;
3725                 }
3726
3727                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3728                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3729
3730                 /* Turn last free buffer recording on */
3731                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3732                         for (i = 0; i < priv->num_rx_queues; i++) {
3733                                 u32 bdp_dma;
3734
3735                                 rx_queue = priv->rx_queue[i];
3736                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3737                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3738                         }
3739
3740                         priv->tx_actual_en = 1;
3741                 }
3742
3743                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3744                         priv->tx_actual_en = 0;
3745
3746                 gfar_write(&regs->maccfg1, tempval1);
3747                 gfar_write(&regs->maccfg2, tempval);
3748                 gfar_write(&regs->ecntrl, ecntrl);
3749
3750                 if (!priv->oldlink)
3751                         priv->oldlink = 1;
3752
3753         } else if (priv->oldlink) {
3754                 priv->oldlink = 0;
3755                 priv->oldspeed = 0;
3756                 priv->oldduplex = -1;
3757         }
3758
3759         if (netif_msg_link(priv))
3760                 phy_print_status(phydev);
3761 }
3762
3763 static const struct of_device_id gfar_match[] =
3764 {
3765         {
3766                 .type = "network",
3767                 .compatible = "gianfar",
3768         },
3769         {
3770                 .compatible = "fsl,etsec2",
3771         },
3772         {},
3773 };
3774 MODULE_DEVICE_TABLE(of, gfar_match);
3775
3776 /* Structure for a device driver */
3777 static struct platform_driver gfar_driver = {
3778         .driver = {
3779                 .name = "fsl-gianfar",
3780                 .pm = GFAR_PM_OPS,
3781                 .of_match_table = gfar_match,
3782         },
3783         .probe = gfar_probe,
3784         .remove = gfar_remove,
3785 };
3786
3787 module_platform_driver(gfar_driver);