drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         struct mbox_list entry;
 288         u16 access = 0;
 289         u16 execute = 0;
 290         u32 v;
 291         u64 res;
 292         int i, ms, delay_idx, ret;
 293         const __be64 *p = cmd;
 294         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 295         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 296         __be64 cmd_rpl[MBOX_LEN / 8];
 297         u32 pcie_fw;
 298
 299         if ((size & 15) || size > MBOX_LEN)
 300                 return -EINVAL;
 301
 302         /*
 303          * If the device is off-line, as in EEH, commands will time out.
 304          * Fail them early so we don't waste time waiting.
 305          */
 306         if (adap->pdev->error_state != pci_channel_io_normal)
 307                 return -EIO;
 308
 309         /* If we have a negative timeout, that implies that we can't sleep. */
 310         if (timeout < 0) {
 311                 sleep_ok = false;
 312                 timeout = -timeout;
 313         }
 314
 315         /* Queue ourselves onto the mailbox access list.  When our entry is at
 316          * the front of the list, we have rights to access the mailbox.  So we
 317          * wait [for a while] till we're at the front [or bail out with an
 318          * EBUSY] ...
 319          */
 320         spin_lock(&adap->mbox_lock);
 321         list_add_tail(&entry.list, &adap->mlist.list);
 322         spin_unlock(&adap->mbox_lock);
 323
 324         delay_idx = 0;
 325         ms = delay[0];
 326
 327         for (i = 0; ; i += ms) {
 328                 /* If we've waited too long, return a busy indication.  This
 329                  * really ought to be based on our initial position in the
 330                  * mailbox access list but this is a start.  We very rearely
 331                  * contend on access to the mailbox ...
 332                  */
 333                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 334                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 335                         spin_lock(&adap->mbox_lock);
 336                         list_del(&entry.list);
 337                         spin_unlock(&adap->mbox_lock);
 338                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 339                         t4_record_mbox(adap, cmd, size, access, ret);
 340                         return ret;
 341                 }
 342
 343                 /* If we're at the head, break out and start the mailbox
 344                  * protocol.
 345                  */
 346                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 347                                      list) == &entry)
 348                         break;
 349
 350                 /* Delay for a bit before checking again ... */
 351                 if (sleep_ok) {
 352                         ms = delay[delay_idx];  /* last element may repeat */
 353                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 354                                 delay_idx++;
 355                         msleep(ms);
 356                 } else {
 357                         mdelay(ms);
 358                 }
 359         }
 360
 361         /* Loop trying to get ownership of the mailbox.  Return an error
 362          * if we can't gain ownership.
 363          */
 364         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 365         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 366                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         if (v != MBOX_OWNER_DRV) {
 368                 spin_lock(&adap->mbox_lock);
 369                 list_del(&entry.list);
 370                 spin_unlock(&adap->mbox_lock);
 371                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 372                 t4_record_mbox(adap, cmd, size, access, ret);
 373                 return ret;
 374         }
 375
 376         /* Copy in the new mailbox command and send it on its way ... */
 377         t4_record_mbox(adap, cmd, size, access, 0);
 378         for (i = 0; i < size; i += 8)
 379                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 380
 381         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 382         t4_read_reg(adap, ctl_reg);          /* flush write */
 383
 384         delay_idx = 0;
 385         ms = delay[0];
 386
 387         for (i = 0;
 388              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 389              i < timeout;
 390              i += ms) {
 391                 if (sleep_ok) {
 392                         ms = delay[delay_idx];  /* last element may repeat */
 393                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 394                                 delay_idx++;
 395                         msleep(ms);
 396                 } else
 397                         mdelay(ms);
 398
 399                 v = t4_read_reg(adap, ctl_reg);
 400                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 401                         if (!(v & MBMSGVALID_F)) {
 402                                 t4_write_reg(adap, ctl_reg, 0);
 403                                 continue;
 404                         }
 405
 406                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 407                         res = be64_to_cpu(cmd_rpl[0]);
 408
 409                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 410                                 fw_asrt(adap, data_reg);
 411                                 res = FW_CMD_RETVAL_V(EIO);
 412                         } else if (rpl) {
 413                                 memcpy(rpl, cmd_rpl, size);
 414                         }
 415
 416                         t4_write_reg(adap, ctl_reg, 0);
 417
 418                         execute = i + ms;
 419                         t4_record_mbox(adap, cmd_rpl,
 420                                        MBOX_LEN, access, execute);
 421                         spin_lock(&adap->mbox_lock);
 422                         list_del(&entry.list);
 423                         spin_unlock(&adap->mbox_lock);
 424                         return -FW_CMD_RETVAL_G((int)res);
 425                 }
 426         }
 427
 428         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 429         t4_record_mbox(adap, cmd, size, access, ret);
 430         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 431                 *(const u8 *)cmd, mbox);
 432         t4_report_fw_error(adap);
 433         spin_lock(&adap->mbox_lock);
 434         list_del(&entry.list);
 435         spin_unlock(&adap->mbox_lock);
 436         t4_fatal_err(adap);
 437         return ret;
 438 }
 439
 440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 441                     void *rpl, bool sleep_ok)
 442 {
 443         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 444                                        FW_CMD_MAX_TIMEOUT);
 445 }
 446
 447 static int t4_edc_err_read(struct adapter *adap, int idx)
 448 {
 449         u32 edc_ecc_err_addr_reg;
 450         u32 rdata_reg;
 451
 452         if (is_t4(adap->params.chip)) {
 453                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 454                 return 0;
 455         }
 456         if (idx != 0 && idx != 1) {
 457                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 458                 return 0;
 459         }
 460
 461         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 462         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 463
 464         CH_WARN(adap,
 465                 "edc%d err addr 0x%x: 0x%x.\n",
 466                 idx, edc_ecc_err_addr_reg,
 467                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 468         CH_WARN(adap,
 469                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 470                 rdata_reg,
 471                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 472                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 486  *      @adap: the adapter
 487  *      @win: PCI-E Memory Window to use
 488  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 489  *      @addr: address within indicated memory type
 490  *      @len: amount of memory to transfer
 491  *      @hbuf: host memory buffer
 492  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 493  *
 494  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 495  *      firmware memory address and host buffer must be aligned on 32-bit
 496  *      boudaries; the length may be arbitrary.  The memory is transferred as
 497  *      a raw byte sequence from/to the firmware's memory.  If this memory
 498  *      contains data structures which contain multi-byte integers, it's the
 499  *      caller's responsibility to perform appropriate byte order conversions.
 500  */
 501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 502                  u32 len, void *hbuf, int dir)
 503 {
 504         u32 pos, offset, resid, memoffset;
 505         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 506         u32 *buf;
 507
 508         /* Argument sanity checks ...
 509          */
 510         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 511                 return -EINVAL;
 512         buf = (u32 *)hbuf;
 513
 514         /* It's convenient to be able to handle lengths which aren't a
 515          * multiple of 32-bits because we often end up transferring files to
 516          * the firmware.  So we'll handle that by normalizing the length here
 517          * and then handling any residual transfer at the end.
 518          */
 519         resid = len & 0x3;
 520         len -= resid;
 521
 522         /* Offset into the region of memory which is being accessed
 523          * MEM_EDC0 = 0
 524          * MEM_EDC1 = 1
 525          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 526          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 527          */
 528         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 529         if (mtype != MEM_MC1)
 530                 memoffset = (mtype * (edc_size * 1024 * 1024));
 531         else {
 532                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 533                                                       MA_EXT_MEMORY0_BAR_A));
 534                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 535         }
 536
 537         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 538         addr = addr + memoffset;
 539
 540         /* Each PCI-E Memory Window is programmed with a window size -- or
 541          * "aperture" -- which controls the granularity of its mapping onto
 542          * adapter memory.  We need to grab that aperture in order to know
 543          * how to use the specified window.  The window is also programmed
 544          * with the base address of the Memory Window in BAR0's address
 545          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 546          * the address is relative to BAR0.
 547          */
 548         mem_reg = t4_read_reg(adap,
 549                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 550                                                   win));
 551         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 552         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 553         if (is_t4(adap->params.chip))
 554                 mem_base -= adap->t4_bar0;
 555         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 556
 557         /* Calculate our initial PCI-E Memory Window Position and Offset into
 558          * that Window.
 559          */
 560         pos = addr & ~(mem_aperture-1);
 561         offset = addr - pos;
 562
 563         /* Set up initial PCI-E Memory Window to cover the start of our
 564          * transfer.  (Read it back to ensure that changes propagate before we
 565          * attempt to use the new value.)
 566          */
 567         t4_write_reg(adap,
 568                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 569                      pos | win_pf);
 570         t4_read_reg(adap,
 571                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 572
 573         /* Transfer data to/from the adapter as long as there's an integral
 574          * number of 32-bit transfers to complete.
 575          *
 576          * A note on Endianness issues:
 577          *
 578          * The "register" reads and writes below from/to the PCI-E Memory
 579          * Window invoke the standard adapter Big-Endian to PCI-E Link
 580          * Little-Endian "swizzel."  As a result, if we have the following
 581          * data in adapter memory:
 582          *
 583          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 584          *     Address:      i+0  i+1  i+2  i+3
 585          *
 586          * Then a read of the adapter memory via the PCI-E Memory Window
 587          * will yield:
 588          *
 589          *     x = readl(i)
 590          *         31                  0
 591          *         [ b3 | b2 | b1 | b0 ]
 592          *
 593          * If this value is stored into local memory on a Little-Endian system
 594          * it will show up correctly in local memory as:
 595          *
 596          *     ( ..., b0, b1, b2, b3, ... )
 597          *
 598          * But on a Big-Endian system, the store will show up in memory
 599          * incorrectly swizzled as:
 600          *
 601          *     ( ..., b3, b2, b1, b0, ... )
 602          *
 603          * So we need to account for this in the reads and writes to the
 604          * PCI-E Memory Window below by undoing the register read/write
 605          * swizzels.
 606          */
 607         while (len > 0) {
 608                 if (dir == T4_MEMORY_READ)
 609                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 610                                                 mem_base + offset));
 611                 else
 612                         t4_write_reg(adap, mem_base + offset,
 613                                      (__force u32)cpu_to_le32(*buf++));
 614                 offset += sizeof(__be32);
 615                 len -= sizeof(__be32);
 616
 617                 /* If we've reached the end of our current window aperture,
 618                  * move the PCI-E Memory Window on to the next.  Note that
 619                  * doing this here after "len" may be 0 allows us to set up
 620                  * the PCI-E Memory Window for a possible final residual
 621                  * transfer below ...
 622                  */
 623                 if (offset == mem_aperture) {
 624                         pos += mem_aperture;
 625                         offset = 0;
 626                         t4_write_reg(adap,
 627                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 628                                                     win), pos | win_pf);
 629                         t4_read_reg(adap,
 630                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 631                                                     win));
 632                 }
 633         }
 634
 635         /* If the original transfer had a length which wasn't a multiple of
 636          * 32-bits, now's where we need to finish off the transfer of the
 637          * residual amount.  The PCI-E Memory Window has already been moved
 638          * above (if necessary) to cover this final transfer.
 639          */
 640         if (resid) {
 641                 union {
 642                         u32 word;
 643                         char byte[4];
 644                 } last;
 645                 unsigned char *bp;
 646                 int i;
 647
 648                 if (dir == T4_MEMORY_READ) {
 649                         last.word = le32_to_cpu(
 650                                         (__force __le32)t4_read_reg(adap,
 651                                                 mem_base + offset));
 652                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 653                                 bp[i] = last.byte[i];
 654                 } else {
 655                         last.word = *buf;
 656                         for (i = resid; i < 4; i++)
 657                                 last.byte[i] = 0;
 658                         t4_write_reg(adap, mem_base + offset,
 659                                      (__force u32)cpu_to_le32(last.word));
 660                 }
 661         }
 662
 663         return 0;
 664 }
 665
 666 /* Return the specified PCI-E Configuration Space register from our Physical
 667  * Function.  We try first via a Firmware LDST Command since we prefer to let
 668  * the firmware own all of these registers, but if that fails we go for it
 669  * directly ourselves.
 670  */
 671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 672 {
 673         u32 val, ldst_addrspace;
 674
 675         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 676          * retrieve the specified PCI-E Configuration Space register.
 677          */
 678         struct fw_ldst_cmd ldst_cmd;
 679         int ret;
 680
 681         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 682         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 683         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 684                                                FW_CMD_REQUEST_F |
 685                                                FW_CMD_READ_F |
 686                                                ldst_addrspace);
 687         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 688         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 689         ldst_cmd.u.pcie.ctrl_to_fn =
 690                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 691         ldst_cmd.u.pcie.r = reg;
 692
 693         /* If the LDST Command succeeds, return the result, otherwise
 694          * fall through to reading it directly ourselves ...
 695          */
 696         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 697                          &ldst_cmd);
 698         if (ret == 0)
 699                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 700         else
 701                 /* Read the desired Configuration Space register via the PCI-E
 702                  * Backdoor mechanism.
 703                  */
 704                 t4_hw_pci_read_cfg4(adap, reg, &val);
 705         return val;
 706 }
 707
 708 /* Get the window based on base passed to it.
 709  * Window aperture is currently unhandled, but there is no use case for it
 710  * right now
 711  */
 712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 713                          u32 memwin_base)
 714 {
 715         u32 ret;
 716
 717         if (is_t4(adap->params.chip)) {
 718                 u32 bar0;
 719
 720                 /* Truncation intentional: we only read the bottom 32-bits of
 721                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 722                  * mechanism to read BAR0 instead of using
 723                  * pci_resource_start() because we could be operating from
 724                  * within a Virtual Machine which is trapping our accesses to
 725                  * our Configuration Space and we need to set up the PCI-E
 726                  * Memory Window decoders with the actual addresses which will
 727                  * be coming across the PCI-E link.
 728                  */
 729                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 730                 bar0 &= pci_mask;
 731                 adap->t4_bar0 = bar0;
 732
 733                 ret = bar0 + memwin_base;
 734         } else {
 735                 /* For T5, only relative offset inside the PCIe BAR is passed */
 736                 ret = memwin_base;
 737         }
 738         return ret;
 739 }
 740
 741 /* Get the default utility window (win0) used by everyone */
 742 u32 t4_get_util_window(struct adapter *adap)
 743 {
 744         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 745                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 746 }
 747
 748 /* Set up memory window for accessing adapter memory ranges.  (Read
 749  * back MA register to ensure that changes propagate before we attempt
 750  * to use the new values.)
 751  */
 752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 753 {
 754         t4_write_reg(adap,
 755                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 756                      memwin_base | BIR_V(0) |
 757                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 758         t4_read_reg(adap,
 759                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 760 }
 761
 762 /**
 763  *      t4_get_regs_len - return the size of the chips register set
 764  *      @adapter: the adapter
 765  *
 766  *      Returns the size of the chip's BAR0 register space.
 767  */
 768 unsigned int t4_get_regs_len(struct adapter *adapter)
 769 {
 770         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 771
 772         switch (chip_version) {
 773         case CHELSIO_T4:
 774                 return T4_REGMAP_SIZE;
 775
 776         case CHELSIO_T5:
 777         case CHELSIO_T6:
 778                 return T5_REGMAP_SIZE;
 779         }
 780
 781         dev_err(adapter->pdev_dev,
 782                 "Unsupported chip version %d\n", chip_version);
 783         return 0;
 784 }
 785
 786 /**
 787  *      t4_get_regs - read chip registers into provided buffer
 788  *      @adap: the adapter
 789  *      @buf: register buffer
 790  *      @buf_size: size (in bytes) of register buffer
 791  *
 792  *      If the provided register buffer isn't large enough for the chip's
 793  *      full register range, the register dump will be truncated to the
 794  *      register buffer's size.
 795  */
 796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 797 {
 798         static const unsigned int t4_reg_ranges[] = {
 799                 0x1008, 0x1108,
 800                 0x1180, 0x1184,
 801                 0x1190, 0x1194,
 802                 0x11a0, 0x11a4,
 803                 0x11b0, 0x11b4,
 804                 0x11fc, 0x123c,
 805                 0x1300, 0x173c,
 806                 0x1800, 0x18fc,
 807                 0x3000, 0x30d8,
 808                 0x30e0, 0x30e4,
 809                 0x30ec, 0x5910,
 810                 0x5920, 0x5924,
 811                 0x5960, 0x5960,
 812                 0x5968, 0x5968,
 813                 0x5970, 0x5970,
 814                 0x5978, 0x5978,
 815                 0x5980, 0x5980,
 816                 0x5988, 0x5988,
 817                 0x5990, 0x5990,
 818                 0x5998, 0x5998,
 819                 0x59a0, 0x59d4,
 820                 0x5a00, 0x5ae0,
 821                 0x5ae8, 0x5ae8,
 822                 0x5af0, 0x5af0,
 823                 0x5af8, 0x5af8,
 824                 0x6000, 0x6098,
 825                 0x6100, 0x6150,
 826                 0x6200, 0x6208,
 827                 0x6240, 0x6248,
 828                 0x6280, 0x62b0,
 829                 0x62c0, 0x6338,
 830                 0x6370, 0x638c,
 831                 0x6400, 0x643c,
 832                 0x6500, 0x6524,
 833                 0x6a00, 0x6a04,
 834                 0x6a14, 0x6a38,
 835                 0x6a60, 0x6a70,
 836                 0x6a78, 0x6a78,
 837                 0x6b00, 0x6b0c,
 838                 0x6b1c, 0x6b84,
 839                 0x6bf0, 0x6bf8,
 840                 0x6c00, 0x6c0c,
 841                 0x6c1c, 0x6c84,
 842                 0x6cf0, 0x6cf8,
 843                 0x6d00, 0x6d0c,
 844                 0x6d1c, 0x6d84,
 845                 0x6df0, 0x6df8,
 846                 0x6e00, 0x6e0c,
 847                 0x6e1c, 0x6e84,
 848                 0x6ef0, 0x6ef8,
 849                 0x6f00, 0x6f0c,
 850                 0x6f1c, 0x6f84,
 851                 0x6ff0, 0x6ff8,
 852                 0x7000, 0x700c,
 853                 0x701c, 0x7084,
 854                 0x70f0, 0x70f8,
 855                 0x7100, 0x710c,
 856                 0x711c, 0x7184,
 857                 0x71f0, 0x71f8,
 858                 0x7200, 0x720c,
 859                 0x721c, 0x7284,
 860                 0x72f0, 0x72f8,
 861                 0x7300, 0x730c,
 862                 0x731c, 0x7384,
 863                 0x73f0, 0x73f8,
 864                 0x7400, 0x7450,
 865                 0x7500, 0x7530,
 866                 0x7600, 0x760c,
 867                 0x7614, 0x761c,
 868                 0x7680, 0x76cc,
 869                 0x7700, 0x7798,
 870                 0x77c0, 0x77fc,
 871                 0x7900, 0x79fc,
 872                 0x7b00, 0x7b58,
 873                 0x7b60, 0x7b84,
 874                 0x7b8c, 0x7c38,
 875                 0x7d00, 0x7d38,
 876                 0x7d40, 0x7d80,
 877                 0x7d8c, 0x7ddc,
 878                 0x7de4, 0x7e04,
 879                 0x7e10, 0x7e1c,
 880                 0x7e24, 0x7e38,
 881                 0x7e40, 0x7e44,
 882                 0x7e4c, 0x7e78,
 883                 0x7e80, 0x7ea4,
 884                 0x7eac, 0x7edc,
 885                 0x7ee8, 0x7efc,
 886                 0x8dc0, 0x8e04,
 887                 0x8e10, 0x8e1c,
 888                 0x8e30, 0x8e78,
 889                 0x8ea0, 0x8eb8,
 890                 0x8ec0, 0x8f6c,
 891                 0x8fc0, 0x9008,
 892                 0x9010, 0x9058,
 893                 0x9060, 0x9060,
 894                 0x9068, 0x9074,
 895                 0x90fc, 0x90fc,
 896                 0x9400, 0x9408,
 897                 0x9410, 0x9458,
 898                 0x9600, 0x9600,
 899                 0x9608, 0x9638,
 900                 0x9640, 0x96bc,
 901                 0x9800, 0x9808,
 902                 0x9820, 0x983c,
 903                 0x9850, 0x9864,
 904                 0x9c00, 0x9c6c,
 905                 0x9c80, 0x9cec,
 906                 0x9d00, 0x9d6c,
 907                 0x9d80, 0x9dec,
 908                 0x9e00, 0x9e6c,
 909                 0x9e80, 0x9eec,
 910                 0x9f00, 0x9f6c,
 911                 0x9f80, 0x9fec,
 912                 0xd004, 0xd004,
 913                 0xd010, 0xd03c,
 914                 0xdfc0, 0xdfe0,
 915                 0xe000, 0xea7c,
 916                 0xf000, 0x11110,
 917                 0x11118, 0x11190,
 918                 0x19040, 0x1906c,
 919                 0x19078, 0x19080,
 920                 0x1908c, 0x190e4,
 921                 0x190f0, 0x190f8,
 922                 0x19100, 0x19110,
 923                 0x19120, 0x19124,
 924                 0x19150, 0x19194,
 925                 0x1919c, 0x191b0,
 926                 0x191d0, 0x191e8,
 927                 0x19238, 0x1924c,
 928                 0x193f8, 0x1943c,
 929                 0x1944c, 0x19474,
 930                 0x19490, 0x194e0,
 931                 0x194f0, 0x194f8,
 932                 0x19800, 0x19c08,
 933                 0x19c10, 0x19c90,
 934                 0x19ca0, 0x19ce4,
 935                 0x19cf0, 0x19d40,
 936                 0x19d50, 0x19d94,
 937                 0x19da0, 0x19de8,
 938                 0x19df0, 0x19e40,
 939                 0x19e50, 0x19e90,
 940                 0x19ea0, 0x19f4c,
 941                 0x1a000, 0x1a004,
 942                 0x1a010, 0x1a06c,
 943                 0x1a0b0, 0x1a0e4,
 944                 0x1a0ec, 0x1a0f4,
 945                 0x1a100, 0x1a108,
 946                 0x1a114, 0x1a120,
 947                 0x1a128, 0x1a130,
 948                 0x1a138, 0x1a138,
 949                 0x1a190, 0x1a1c4,
 950                 0x1a1fc, 0x1a1fc,
 951                 0x1e040, 0x1e04c,
 952                 0x1e284, 0x1e28c,
 953                 0x1e2c0, 0x1e2c0,
 954                 0x1e2e0, 0x1e2e0,
 955                 0x1e300, 0x1e384,
 956                 0x1e3c0, 0x1e3c8,
 957                 0x1e440, 0x1e44c,
 958                 0x1e684, 0x1e68c,
 959                 0x1e6c0, 0x1e6c0,
 960                 0x1e6e0, 0x1e6e0,
 961                 0x1e700, 0x1e784,
 962                 0x1e7c0, 0x1e7c8,
 963                 0x1e840, 0x1e84c,
 964                 0x1ea84, 0x1ea8c,
 965                 0x1eac0, 0x1eac0,
 966                 0x1eae0, 0x1eae0,
 967                 0x1eb00, 0x1eb84,
 968                 0x1ebc0, 0x1ebc8,
 969                 0x1ec40, 0x1ec4c,
 970                 0x1ee84, 0x1ee8c,
 971                 0x1eec0, 0x1eec0,
 972                 0x1eee0, 0x1eee0,
 973                 0x1ef00, 0x1ef84,
 974                 0x1efc0, 0x1efc8,
 975                 0x1f040, 0x1f04c,
 976                 0x1f284, 0x1f28c,
 977                 0x1f2c0, 0x1f2c0,
 978                 0x1f2e0, 0x1f2e0,
 979                 0x1f300, 0x1f384,
 980                 0x1f3c0, 0x1f3c8,
 981                 0x1f440, 0x1f44c,
 982                 0x1f684, 0x1f68c,
 983                 0x1f6c0, 0x1f6c0,
 984                 0x1f6e0, 0x1f6e0,
 985                 0x1f700, 0x1f784,
 986                 0x1f7c0, 0x1f7c8,
 987                 0x1f840, 0x1f84c,
 988                 0x1fa84, 0x1fa8c,
 989                 0x1fac0, 0x1fac0,
 990                 0x1fae0, 0x1fae0,
 991                 0x1fb00, 0x1fb84,
 992                 0x1fbc0, 0x1fbc8,
 993                 0x1fc40, 0x1fc4c,
 994                 0x1fe84, 0x1fe8c,
 995                 0x1fec0, 0x1fec0,
 996                 0x1fee0, 0x1fee0,
 997                 0x1ff00, 0x1ff84,
 998                 0x1ffc0, 0x1ffc8,
 999                 0x20000, 0x2002c,
1000                 0x20100, 0x2013c,
1001                 0x20190, 0x201a0,
1002                 0x201a8, 0x201b8,
1003                 0x201c4, 0x201c8,
1004                 0x20200, 0x20318,
1005                 0x20400, 0x204b4,
1006                 0x204c0, 0x20528,
1007                 0x20540, 0x20614,
1008                 0x21000, 0x21040,
1009                 0x2104c, 0x21060,
1010                 0x210c0, 0x210ec,
1011                 0x21200, 0x21268,
1012                 0x21270, 0x21284,
1013                 0x212fc, 0x21388,
1014                 0x21400, 0x21404,
1015                 0x21500, 0x21500,
1016                 0x21510, 0x21518,
1017                 0x2152c, 0x21530,
1018                 0x2153c, 0x2153c,
1019                 0x21550, 0x21554,
1020                 0x21600, 0x21600,
1021                 0x21608, 0x2161c,
1022                 0x21624, 0x21628,
1023                 0x21630, 0x21634,
1024                 0x2163c, 0x2163c,
1025                 0x21700, 0x2171c,
1026                 0x21780, 0x2178c,
1027                 0x21800, 0x21818,
1028                 0x21820, 0x21828,
1029                 0x21830, 0x21848,
1030                 0x21850, 0x21854,
1031                 0x21860, 0x21868,
1032                 0x21870, 0x21870,
1033                 0x21878, 0x21898,
1034                 0x218a0, 0x218a8,
1035                 0x218b0, 0x218c8,
1036                 0x218d0, 0x218d4,
1037                 0x218e0, 0x218e8,
1038                 0x218f0, 0x218f0,
1039                 0x218f8, 0x21a18,
1040                 0x21a20, 0x21a28,
1041                 0x21a30, 0x21a48,
1042                 0x21a50, 0x21a54,
1043                 0x21a60, 0x21a68,
1044                 0x21a70, 0x21a70,
1045                 0x21a78, 0x21a98,
1046                 0x21aa0, 0x21aa8,
1047                 0x21ab0, 0x21ac8,
1048                 0x21ad0, 0x21ad4,
1049                 0x21ae0, 0x21ae8,
1050                 0x21af0, 0x21af0,
1051                 0x21af8, 0x21c18,
1052                 0x21c20, 0x21c20,
1053                 0x21c28, 0x21c30,
1054                 0x21c38, 0x21c38,
1055                 0x21c80, 0x21c98,
1056                 0x21ca0, 0x21ca8,
1057                 0x21cb0, 0x21cc8,
1058                 0x21cd0, 0x21cd4,
1059                 0x21ce0, 0x21ce8,
1060                 0x21cf0, 0x21cf0,
1061                 0x21cf8, 0x21d7c,
1062                 0x21e00, 0x21e04,
1063                 0x22000, 0x2202c,
1064                 0x22100, 0x2213c,
1065                 0x22190, 0x221a0,
1066                 0x221a8, 0x221b8,
1067                 0x221c4, 0x221c8,
1068                 0x22200, 0x22318,
1069                 0x22400, 0x224b4,
1070                 0x224c0, 0x22528,
1071                 0x22540, 0x22614,
1072                 0x23000, 0x23040,
1073                 0x2304c, 0x23060,
1074                 0x230c0, 0x230ec,
1075                 0x23200, 0x23268,
1076                 0x23270, 0x23284,
1077                 0x232fc, 0x23388,
1078                 0x23400, 0x23404,
1079                 0x23500, 0x23500,
1080                 0x23510, 0x23518,
1081                 0x2352c, 0x23530,
1082                 0x2353c, 0x2353c,
1083                 0x23550, 0x23554,
1084                 0x23600, 0x23600,
1085                 0x23608, 0x2361c,
1086                 0x23624, 0x23628,
1087                 0x23630, 0x23634,
1088                 0x2363c, 0x2363c,
1089                 0x23700, 0x2371c,
1090                 0x23780, 0x2378c,
1091                 0x23800, 0x23818,
1092                 0x23820, 0x23828,
1093                 0x23830, 0x23848,
1094                 0x23850, 0x23854,
1095                 0x23860, 0x23868,
1096                 0x23870, 0x23870,
1097                 0x23878, 0x23898,
1098                 0x238a0, 0x238a8,
1099                 0x238b0, 0x238c8,
1100                 0x238d0, 0x238d4,
1101                 0x238e0, 0x238e8,
1102                 0x238f0, 0x238f0,
1103                 0x238f8, 0x23a18,
1104                 0x23a20, 0x23a28,
1105                 0x23a30, 0x23a48,
1106                 0x23a50, 0x23a54,
1107                 0x23a60, 0x23a68,
1108                 0x23a70, 0x23a70,
1109                 0x23a78, 0x23a98,
1110                 0x23aa0, 0x23aa8,
1111                 0x23ab0, 0x23ac8,
1112                 0x23ad0, 0x23ad4,
1113                 0x23ae0, 0x23ae8,
1114                 0x23af0, 0x23af0,
1115                 0x23af8, 0x23c18,
1116                 0x23c20, 0x23c20,
1117                 0x23c28, 0x23c30,
1118                 0x23c38, 0x23c38,
1119                 0x23c80, 0x23c98,
1120                 0x23ca0, 0x23ca8,
1121                 0x23cb0, 0x23cc8,
1122                 0x23cd0, 0x23cd4,
1123                 0x23ce0, 0x23ce8,
1124                 0x23cf0, 0x23cf0,
1125                 0x23cf8, 0x23d7c,
1126                 0x23e00, 0x23e04,
1127                 0x24000, 0x2402c,
1128                 0x24100, 0x2413c,
1129                 0x24190, 0x241a0,
1130                 0x241a8, 0x241b8,
1131                 0x241c4, 0x241c8,
1132                 0x24200, 0x24318,
1133                 0x24400, 0x244b4,
1134                 0x244c0, 0x24528,
1135                 0x24540, 0x24614,
1136                 0x25000, 0x25040,
1137                 0x2504c, 0x25060,
1138                 0x250c0, 0x250ec,
1139                 0x25200, 0x25268,
1140                 0x25270, 0x25284,
1141                 0x252fc, 0x25388,
1142                 0x25400, 0x25404,
1143                 0x25500, 0x25500,
1144                 0x25510, 0x25518,
1145                 0x2552c, 0x25530,
1146                 0x2553c, 0x2553c,
1147                 0x25550, 0x25554,
1148                 0x25600, 0x25600,
1149                 0x25608, 0x2561c,
1150                 0x25624, 0x25628,
1151                 0x25630, 0x25634,
1152                 0x2563c, 0x2563c,
1153                 0x25700, 0x2571c,
1154                 0x25780, 0x2578c,
1155                 0x25800, 0x25818,
1156                 0x25820, 0x25828,
1157                 0x25830, 0x25848,
1158                 0x25850, 0x25854,
1159                 0x25860, 0x25868,
1160                 0x25870, 0x25870,
1161                 0x25878, 0x25898,
1162                 0x258a0, 0x258a8,
1163                 0x258b0, 0x258c8,
1164                 0x258d0, 0x258d4,
1165                 0x258e0, 0x258e8,
1166                 0x258f0, 0x258f0,
1167                 0x258f8, 0x25a18,
1168                 0x25a20, 0x25a28,
1169                 0x25a30, 0x25a48,
1170                 0x25a50, 0x25a54,
1171                 0x25a60, 0x25a68,
1172                 0x25a70, 0x25a70,
1173                 0x25a78, 0x25a98,
1174                 0x25aa0, 0x25aa8,
1175                 0x25ab0, 0x25ac8,
1176                 0x25ad0, 0x25ad4,
1177                 0x25ae0, 0x25ae8,
1178                 0x25af0, 0x25af0,
1179                 0x25af8, 0x25c18,
1180                 0x25c20, 0x25c20,
1181                 0x25c28, 0x25c30,
1182                 0x25c38, 0x25c38,
1183                 0x25c80, 0x25c98,
1184                 0x25ca0, 0x25ca8,
1185                 0x25cb0, 0x25cc8,
1186                 0x25cd0, 0x25cd4,
1187                 0x25ce0, 0x25ce8,
1188                 0x25cf0, 0x25cf0,
1189                 0x25cf8, 0x25d7c,
1190                 0x25e00, 0x25e04,
1191                 0x26000, 0x2602c,
1192                 0x26100, 0x2613c,
1193                 0x26190, 0x261a0,
1194                 0x261a8, 0x261b8,
1195                 0x261c4, 0x261c8,
1196                 0x26200, 0x26318,
1197                 0x26400, 0x264b4,
1198                 0x264c0, 0x26528,
1199                 0x26540, 0x26614,
1200                 0x27000, 0x27040,
1201                 0x2704c, 0x27060,
1202                 0x270c0, 0x270ec,
1203                 0x27200, 0x27268,
1204                 0x27270, 0x27284,
1205                 0x272fc, 0x27388,
1206                 0x27400, 0x27404,
1207                 0x27500, 0x27500,
1208                 0x27510, 0x27518,
1209                 0x2752c, 0x27530,
1210                 0x2753c, 0x2753c,
1211                 0x27550, 0x27554,
1212                 0x27600, 0x27600,
1213                 0x27608, 0x2761c,
1214                 0x27624, 0x27628,
1215                 0x27630, 0x27634,
1216                 0x2763c, 0x2763c,
1217                 0x27700, 0x2771c,
1218                 0x27780, 0x2778c,
1219                 0x27800, 0x27818,
1220                 0x27820, 0x27828,
1221                 0x27830, 0x27848,
1222                 0x27850, 0x27854,
1223                 0x27860, 0x27868,
1224                 0x27870, 0x27870,
1225                 0x27878, 0x27898,
1226                 0x278a0, 0x278a8,
1227                 0x278b0, 0x278c8,
1228                 0x278d0, 0x278d4,
1229                 0x278e0, 0x278e8,
1230                 0x278f0, 0x278f0,
1231                 0x278f8, 0x27a18,
1232                 0x27a20, 0x27a28,
1233                 0x27a30, 0x27a48,
1234                 0x27a50, 0x27a54,
1235                 0x27a60, 0x27a68,
1236                 0x27a70, 0x27a70,
1237                 0x27a78, 0x27a98,
1238                 0x27aa0, 0x27aa8,
1239                 0x27ab0, 0x27ac8,
1240                 0x27ad0, 0x27ad4,
1241                 0x27ae0, 0x27ae8,
1242                 0x27af0, 0x27af0,
1243                 0x27af8, 0x27c18,
1244                 0x27c20, 0x27c20,
1245                 0x27c28, 0x27c30,
1246                 0x27c38, 0x27c38,
1247                 0x27c80, 0x27c98,
1248                 0x27ca0, 0x27ca8,
1249                 0x27cb0, 0x27cc8,
1250                 0x27cd0, 0x27cd4,
1251                 0x27ce0, 0x27ce8,
1252                 0x27cf0, 0x27cf0,
1253                 0x27cf8, 0x27d7c,
1254                 0x27e00, 0x27e04,
1255         };
1256
1257         static const unsigned int t5_reg_ranges[] = {
1258                 0x1008, 0x10c0,
1259                 0x10cc, 0x10f8,
1260                 0x1100, 0x1100,
1261                 0x110c, 0x1148,
1262                 0x1180, 0x1184,
1263                 0x1190, 0x1194,
1264                 0x11a0, 0x11a4,
1265                 0x11b0, 0x11b4,
1266                 0x11fc, 0x123c,
1267                 0x1280, 0x173c,
1268                 0x1800, 0x18fc,
1269                 0x3000, 0x3028,
1270                 0x3060, 0x30b0,
1271                 0x30b8, 0x30d8,
1272                 0x30e0, 0x30fc,
1273                 0x3140, 0x357c,
1274                 0x35a8, 0x35cc,
1275                 0x35ec, 0x35ec,
1276                 0x3600, 0x5624,
1277                 0x56cc, 0x56ec,
1278                 0x56f4, 0x5720,
1279                 0x5728, 0x575c,
1280                 0x580c, 0x5814,
1281                 0x5890, 0x589c,
1282                 0x58a4, 0x58ac,
1283                 0x58b8, 0x58bc,
1284                 0x5940, 0x59c8,
1285                 0x59d0, 0x59dc,
1286                 0x59fc, 0x5a18,
1287                 0x5a60, 0x5a70,
1288                 0x5a80, 0x5a9c,
1289                 0x5b94, 0x5bfc,
1290                 0x6000, 0x6020,
1291                 0x6028, 0x6040,
1292                 0x6058, 0x609c,
1293                 0x60a8, 0x614c,
1294                 0x7700, 0x7798,
1295                 0x77c0, 0x78fc,
1296                 0x7b00, 0x7b58,
1297                 0x7b60, 0x7b84,
1298                 0x7b8c, 0x7c54,
1299                 0x7d00, 0x7d38,
1300                 0x7d40, 0x7d80,
1301                 0x7d8c, 0x7ddc,
1302                 0x7de4, 0x7e04,
1303                 0x7e10, 0x7e1c,
1304                 0x7e24, 0x7e38,
1305                 0x7e40, 0x7e44,
1306                 0x7e4c, 0x7e78,
1307                 0x7e80, 0x7edc,
1308                 0x7ee8, 0x7efc,
1309                 0x8dc0, 0x8de0,
1310                 0x8df8, 0x8e04,
1311                 0x8e10, 0x8e84,
1312                 0x8ea0, 0x8f84,
1313                 0x8fc0, 0x9058,
1314                 0x9060, 0x9060,
1315                 0x9068, 0x90f8,
1316                 0x9400, 0x9408,
1317                 0x9410, 0x9470,
1318                 0x9600, 0x9600,
1319                 0x9608, 0x9638,
1320                 0x9640, 0x96f4,
1321                 0x9800, 0x9808,
1322                 0x9820, 0x983c,
1323                 0x9850, 0x9864,
1324                 0x9c00, 0x9c6c,
1325                 0x9c80, 0x9cec,
1326                 0x9d00, 0x9d6c,
1327                 0x9d80, 0x9dec,
1328                 0x9e00, 0x9e6c,
1329                 0x9e80, 0x9eec,
1330                 0x9f00, 0x9f6c,
1331                 0x9f80, 0xa020,
1332                 0xd004, 0xd004,
1333                 0xd010, 0xd03c,
1334                 0xdfc0, 0xdfe0,
1335                 0xe000, 0x1106c,
1336                 0x11074, 0x11088,
1337                 0x1109c, 0x1117c,
1338                 0x11190, 0x11204,
1339                 0x19040, 0x1906c,
1340                 0x19078, 0x19080,
1341                 0x1908c, 0x190e8,
1342                 0x190f0, 0x190f8,
1343                 0x19100, 0x19110,
1344                 0x19120, 0x19124,
1345                 0x19150, 0x19194,
1346                 0x1919c, 0x191b0,
1347                 0x191d0, 0x191e8,
1348                 0x19238, 0x19290,
1349                 0x193f8, 0x19428,
1350                 0x19430, 0x19444,
1351                 0x1944c, 0x1946c,
1352                 0x19474, 0x19474,
1353                 0x19490, 0x194cc,
1354                 0x194f0, 0x194f8,
1355                 0x19c00, 0x19c08,
1356                 0x19c10, 0x19c60,
1357                 0x19c94, 0x19ce4,
1358                 0x19cf0, 0x19d40,
1359                 0x19d50, 0x19d94,
1360                 0x19da0, 0x19de8,
1361                 0x19df0, 0x19e10,
1362                 0x19e50, 0x19e90,
1363                 0x19ea0, 0x19f24,
1364                 0x19f34, 0x19f34,
1365                 0x19f40, 0x19f50,
1366                 0x19f90, 0x19fb4,
1367                 0x19fc4, 0x19fe4,
1368                 0x1a000, 0x1a004,
1369                 0x1a010, 0x1a06c,
1370                 0x1a0b0, 0x1a0e4,
1371                 0x1a0ec, 0x1a0f8,
1372                 0x1a100, 0x1a108,
1373                 0x1a114, 0x1a120,
1374                 0x1a128, 0x1a130,
1375                 0x1a138, 0x1a138,
1376                 0x1a190, 0x1a1c4,
1377                 0x1a1fc, 0x1a1fc,
1378                 0x1e008, 0x1e00c,
1379                 0x1e040, 0x1e044,
1380                 0x1e04c, 0x1e04c,
1381                 0x1e284, 0x1e290,
1382                 0x1e2c0, 0x1e2c0,
1383                 0x1e2e0, 0x1e2e0,
1384                 0x1e300, 0x1e384,
1385                 0x1e3c0, 0x1e3c8,
1386                 0x1e408, 0x1e40c,
1387                 0x1e440, 0x1e444,
1388                 0x1e44c, 0x1e44c,
1389                 0x1e684, 0x1e690,
1390                 0x1e6c0, 0x1e6c0,
1391                 0x1e6e0, 0x1e6e0,
1392                 0x1e700, 0x1e784,
1393                 0x1e7c0, 0x1e7c8,
1394                 0x1e808, 0x1e80c,
1395                 0x1e840, 0x1e844,
1396                 0x1e84c, 0x1e84c,
1397                 0x1ea84, 0x1ea90,
1398                 0x1eac0, 0x1eac0,
1399                 0x1eae0, 0x1eae0,
1400                 0x1eb00, 0x1eb84,
1401                 0x1ebc0, 0x1ebc8,
1402                 0x1ec08, 0x1ec0c,
1403                 0x1ec40, 0x1ec44,
1404                 0x1ec4c, 0x1ec4c,
1405                 0x1ee84, 0x1ee90,
1406                 0x1eec0, 0x1eec0,
1407                 0x1eee0, 0x1eee0,
1408                 0x1ef00, 0x1ef84,
1409                 0x1efc0, 0x1efc8,
1410                 0x1f008, 0x1f00c,
1411                 0x1f040, 0x1f044,
1412                 0x1f04c, 0x1f04c,
1413                 0x1f284, 0x1f290,
1414                 0x1f2c0, 0x1f2c0,
1415                 0x1f2e0, 0x1f2e0,
1416                 0x1f300, 0x1f384,
1417                 0x1f3c0, 0x1f3c8,
1418                 0x1f408, 0x1f40c,
1419                 0x1f440, 0x1f444,
1420                 0x1f44c, 0x1f44c,
1421                 0x1f684, 0x1f690,
1422                 0x1f6c0, 0x1f6c0,
1423                 0x1f6e0, 0x1f6e0,
1424                 0x1f700, 0x1f784,
1425                 0x1f7c0, 0x1f7c8,
1426                 0x1f808, 0x1f80c,
1427                 0x1f840, 0x1f844,
1428                 0x1f84c, 0x1f84c,
1429                 0x1fa84, 0x1fa90,
1430                 0x1fac0, 0x1fac0,
1431                 0x1fae0, 0x1fae0,
1432                 0x1fb00, 0x1fb84,
1433                 0x1fbc0, 0x1fbc8,
1434                 0x1fc08, 0x1fc0c,
1435                 0x1fc40, 0x1fc44,
1436                 0x1fc4c, 0x1fc4c,
1437                 0x1fe84, 0x1fe90,
1438                 0x1fec0, 0x1fec0,
1439                 0x1fee0, 0x1fee0,
1440                 0x1ff00, 0x1ff84,
1441                 0x1ffc0, 0x1ffc8,
1442                 0x30000, 0x30030,
1443                 0x30100, 0x30144,
1444                 0x30190, 0x301a0,
1445                 0x301a8, 0x301b8,
1446                 0x301c4, 0x301c8,
1447                 0x301d0, 0x301d0,
1448                 0x30200, 0x30318,
1449                 0x30400, 0x304b4,
1450                 0x304c0, 0x3052c,
1451                 0x30540, 0x3061c,
1452                 0x30800, 0x30828,
1453                 0x30834, 0x30834,
1454                 0x308c0, 0x30908,
1455                 0x30910, 0x309ac,
1456                 0x30a00, 0x30a14,
1457                 0x30a1c, 0x30a2c,
1458                 0x30a44, 0x30a50,
1459                 0x30a74, 0x30a74,
1460                 0x30a7c, 0x30afc,
1461                 0x30b08, 0x30c24,
1462                 0x30d00, 0x30d00,
1463                 0x30d08, 0x30d14,
1464                 0x30d1c, 0x30d20,
1465                 0x30d3c, 0x30d3c,
1466                 0x30d48, 0x30d50,
1467                 0x31200, 0x3120c,
1468                 0x31220, 0x31220,
1469                 0x31240, 0x31240,
1470                 0x31600, 0x3160c,
1471                 0x31a00, 0x31a1c,
1472                 0x31e00, 0x31e20,
1473                 0x31e38, 0x31e3c,
1474                 0x31e80, 0x31e80,
1475                 0x31e88, 0x31ea8,
1476                 0x31eb0, 0x31eb4,
1477                 0x31ec8, 0x31ed4,
1478                 0x31fb8, 0x32004,
1479                 0x32200, 0x32200,
1480                 0x32208, 0x32240,
1481                 0x32248, 0x32280,
1482                 0x32288, 0x322c0,
1483                 0x322c8, 0x322fc,
1484                 0x32600, 0x32630,
1485                 0x32a00, 0x32abc,
1486                 0x32b00, 0x32b10,
1487                 0x32b20, 0x32b30,
1488                 0x32b40, 0x32b50,
1489                 0x32b60, 0x32b70,
1490                 0x33000, 0x33028,
1491                 0x33030, 0x33048,
1492                 0x33060, 0x33068,
1493                 0x33070, 0x3309c,
1494                 0x330f0, 0x33128,
1495                 0x33130, 0x33148,
1496                 0x33160, 0x33168,
1497                 0x33170, 0x3319c,
1498                 0x331f0, 0x33238,
1499                 0x33240, 0x33240,
1500                 0x33248, 0x33250,
1501                 0x3325c, 0x33264,
1502                 0x33270, 0x332b8,
1503                 0x332c0, 0x332e4,
1504                 0x332f8, 0x33338,
1505                 0x33340, 0x33340,
1506                 0x33348, 0x33350,
1507                 0x3335c, 0x33364,
1508                 0x33370, 0x333b8,
1509                 0x333c0, 0x333e4,
1510                 0x333f8, 0x33428,
1511                 0x33430, 0x33448,
1512                 0x33460, 0x33468,
1513                 0x33470, 0x3349c,
1514                 0x334f0, 0x33528,
1515                 0x33530, 0x33548,
1516                 0x33560, 0x33568,
1517                 0x33570, 0x3359c,
1518                 0x335f0, 0x33638,
1519                 0x33640, 0x33640,
1520                 0x33648, 0x33650,
1521                 0x3365c, 0x33664,
1522                 0x33670, 0x336b8,
1523                 0x336c0, 0x336e4,
1524                 0x336f8, 0x33738,
1525                 0x33740, 0x33740,
1526                 0x33748, 0x33750,
1527                 0x3375c, 0x33764,
1528                 0x33770, 0x337b8,
1529                 0x337c0, 0x337e4,
1530                 0x337f8, 0x337fc,
1531                 0x33814, 0x33814,
1532                 0x3382c, 0x3382c,
1533                 0x33880, 0x3388c,
1534                 0x338e8, 0x338ec,
1535                 0x33900, 0x33928,
1536                 0x33930, 0x33948,
1537                 0x33960, 0x33968,
1538                 0x33970, 0x3399c,
1539                 0x339f0, 0x33a38,
1540                 0x33a40, 0x33a40,
1541                 0x33a48, 0x33a50,
1542                 0x33a5c, 0x33a64,
1543                 0x33a70, 0x33ab8,
1544                 0x33ac0, 0x33ae4,
1545                 0x33af8, 0x33b10,
1546                 0x33b28, 0x33b28,
1547                 0x33b3c, 0x33b50,
1548                 0x33bf0, 0x33c10,
1549                 0x33c28, 0x33c28,
1550                 0x33c3c, 0x33c50,
1551                 0x33cf0, 0x33cfc,
1552                 0x34000, 0x34030,
1553                 0x34100, 0x34144,
1554                 0x34190, 0x341a0,
1555                 0x341a8, 0x341b8,
1556                 0x341c4, 0x341c8,
1557                 0x341d0, 0x341d0,
1558                 0x34200, 0x34318,
1559                 0x34400, 0x344b4,
1560                 0x344c0, 0x3452c,
1561                 0x34540, 0x3461c,
1562                 0x34800, 0x34828,
1563                 0x34834, 0x34834,
1564                 0x348c0, 0x34908,
1565                 0x34910, 0x349ac,
1566                 0x34a00, 0x34a14,
1567                 0x34a1c, 0x34a2c,
1568                 0x34a44, 0x34a50,
1569                 0x34a74, 0x34a74,
1570                 0x34a7c, 0x34afc,
1571                 0x34b08, 0x34c24,
1572                 0x34d00, 0x34d00,
1573                 0x34d08, 0x34d14,
1574                 0x34d1c, 0x34d20,
1575                 0x34d3c, 0x34d3c,
1576                 0x34d48, 0x34d50,
1577                 0x35200, 0x3520c,
1578                 0x35220, 0x35220,
1579                 0x35240, 0x35240,
1580                 0x35600, 0x3560c,
1581                 0x35a00, 0x35a1c,
1582                 0x35e00, 0x35e20,
1583                 0x35e38, 0x35e3c,
1584                 0x35e80, 0x35e80,
1585                 0x35e88, 0x35ea8,
1586                 0x35eb0, 0x35eb4,
1587                 0x35ec8, 0x35ed4,
1588                 0x35fb8, 0x36004,
1589                 0x36200, 0x36200,
1590                 0x36208, 0x36240,
1591                 0x36248, 0x36280,
1592                 0x36288, 0x362c0,
1593                 0x362c8, 0x362fc,
1594                 0x36600, 0x36630,
1595                 0x36a00, 0x36abc,
1596                 0x36b00, 0x36b10,
1597                 0x36b20, 0x36b30,
1598                 0x36b40, 0x36b50,
1599                 0x36b60, 0x36b70,
1600                 0x37000, 0x37028,
1601                 0x37030, 0x37048,
1602                 0x37060, 0x37068,
1603                 0x37070, 0x3709c,
1604                 0x370f0, 0x37128,
1605                 0x37130, 0x37148,
1606                 0x37160, 0x37168,
1607                 0x37170, 0x3719c,
1608                 0x371f0, 0x37238,
1609                 0x37240, 0x37240,
1610                 0x37248, 0x37250,
1611                 0x3725c, 0x37264,
1612                 0x37270, 0x372b8,
1613                 0x372c0, 0x372e4,
1614                 0x372f8, 0x37338,
1615                 0x37340, 0x37340,
1616                 0x37348, 0x37350,
1617                 0x3735c, 0x37364,
1618                 0x37370, 0x373b8,
1619                 0x373c0, 0x373e4,
1620                 0x373f8, 0x37428,
1621                 0x37430, 0x37448,
1622                 0x37460, 0x37468,
1623                 0x37470, 0x3749c,
1624                 0x374f0, 0x37528,
1625                 0x37530, 0x37548,
1626                 0x37560, 0x37568,
1627                 0x37570, 0x3759c,
1628                 0x375f0, 0x37638,
1629                 0x37640, 0x37640,
1630                 0x37648, 0x37650,
1631                 0x3765c, 0x37664,
1632                 0x37670, 0x376b8,
1633                 0x376c0, 0x376e4,
1634                 0x376f8, 0x37738,
1635                 0x37740, 0x37740,
1636                 0x37748, 0x37750,
1637                 0x3775c, 0x37764,
1638                 0x37770, 0x377b8,
1639                 0x377c0, 0x377e4,
1640                 0x377f8, 0x377fc,
1641                 0x37814, 0x37814,
1642                 0x3782c, 0x3782c,
1643                 0x37880, 0x3788c,
1644                 0x378e8, 0x378ec,
1645                 0x37900, 0x37928,
1646                 0x37930, 0x37948,
1647                 0x37960, 0x37968,
1648                 0x37970, 0x3799c,
1649                 0x379f0, 0x37a38,
1650                 0x37a40, 0x37a40,
1651                 0x37a48, 0x37a50,
1652                 0x37a5c, 0x37a64,
1653                 0x37a70, 0x37ab8,
1654                 0x37ac0, 0x37ae4,
1655                 0x37af8, 0x37b10,
1656                 0x37b28, 0x37b28,
1657                 0x37b3c, 0x37b50,
1658                 0x37bf0, 0x37c10,
1659                 0x37c28, 0x37c28,
1660                 0x37c3c, 0x37c50,
1661                 0x37cf0, 0x37cfc,
1662                 0x38000, 0x38030,
1663                 0x38100, 0x38144,
1664                 0x38190, 0x381a0,
1665                 0x381a8, 0x381b8,
1666                 0x381c4, 0x381c8,
1667                 0x381d0, 0x381d0,
1668                 0x38200, 0x38318,
1669                 0x38400, 0x384b4,
1670                 0x384c0, 0x3852c,
1671                 0x38540, 0x3861c,
1672                 0x38800, 0x38828,
1673                 0x38834, 0x38834,
1674                 0x388c0, 0x38908,
1675                 0x38910, 0x389ac,
1676                 0x38a00, 0x38a14,
1677                 0x38a1c, 0x38a2c,
1678                 0x38a44, 0x38a50,
1679                 0x38a74, 0x38a74,
1680                 0x38a7c, 0x38afc,
1681                 0x38b08, 0x38c24,
1682                 0x38d00, 0x38d00,
1683                 0x38d08, 0x38d14,
1684                 0x38d1c, 0x38d20,
1685                 0x38d3c, 0x38d3c,
1686                 0x38d48, 0x38d50,
1687                 0x39200, 0x3920c,
1688                 0x39220, 0x39220,
1689                 0x39240, 0x39240,
1690                 0x39600, 0x3960c,
1691                 0x39a00, 0x39a1c,
1692                 0x39e00, 0x39e20,
1693                 0x39e38, 0x39e3c,
1694                 0x39e80, 0x39e80,
1695                 0x39e88, 0x39ea8,
1696                 0x39eb0, 0x39eb4,
1697                 0x39ec8, 0x39ed4,
1698                 0x39fb8, 0x3a004,
1699                 0x3a200, 0x3a200,
1700                 0x3a208, 0x3a240,
1701                 0x3a248, 0x3a280,
1702                 0x3a288, 0x3a2c0,
1703                 0x3a2c8, 0x3a2fc,
1704                 0x3a600, 0x3a630,
1705                 0x3aa00, 0x3aabc,
1706                 0x3ab00, 0x3ab10,
1707                 0x3ab20, 0x3ab30,
1708                 0x3ab40, 0x3ab50,
1709                 0x3ab60, 0x3ab70,
1710                 0x3b000, 0x3b028,
1711                 0x3b030, 0x3b048,
1712                 0x3b060, 0x3b068,
1713                 0x3b070, 0x3b09c,
1714                 0x3b0f0, 0x3b128,
1715                 0x3b130, 0x3b148,
1716                 0x3b160, 0x3b168,
1717                 0x3b170, 0x3b19c,
1718                 0x3b1f0, 0x3b238,
1719                 0x3b240, 0x3b240,
1720                 0x3b248, 0x3b250,
1721                 0x3b25c, 0x3b264,
1722                 0x3b270, 0x3b2b8,
1723                 0x3b2c0, 0x3b2e4,
1724                 0x3b2f8, 0x3b338,
1725                 0x3b340, 0x3b340,
1726                 0x3b348, 0x3b350,
1727                 0x3b35c, 0x3b364,
1728                 0x3b370, 0x3b3b8,
1729                 0x3b3c0, 0x3b3e4,
1730                 0x3b3f8, 0x3b428,
1731                 0x3b430, 0x3b448,
1732                 0x3b460, 0x3b468,
1733                 0x3b470, 0x3b49c,
1734                 0x3b4f0, 0x3b528,
1735                 0x3b530, 0x3b548,
1736                 0x3b560, 0x3b568,
1737                 0x3b570, 0x3b59c,
1738                 0x3b5f0, 0x3b638,
1739                 0x3b640, 0x3b640,
1740                 0x3b648, 0x3b650,
1741                 0x3b65c, 0x3b664,
1742                 0x3b670, 0x3b6b8,
1743                 0x3b6c0, 0x3b6e4,
1744                 0x3b6f8, 0x3b738,
1745                 0x3b740, 0x3b740,
1746                 0x3b748, 0x3b750,
1747                 0x3b75c, 0x3b764,
1748                 0x3b770, 0x3b7b8,
1749                 0x3b7c0, 0x3b7e4,
1750                 0x3b7f8, 0x3b7fc,
1751                 0x3b814, 0x3b814,
1752                 0x3b82c, 0x3b82c,
1753                 0x3b880, 0x3b88c,
1754                 0x3b8e8, 0x3b8ec,
1755                 0x3b900, 0x3b928,
1756                 0x3b930, 0x3b948,
1757                 0x3b960, 0x3b968,
1758                 0x3b970, 0x3b99c,
1759                 0x3b9f0, 0x3ba38,
1760                 0x3ba40, 0x3ba40,
1761                 0x3ba48, 0x3ba50,
1762                 0x3ba5c, 0x3ba64,
1763                 0x3ba70, 0x3bab8,
1764                 0x3bac0, 0x3bae4,
1765                 0x3baf8, 0x3bb10,
1766                 0x3bb28, 0x3bb28,
1767                 0x3bb3c, 0x3bb50,
1768                 0x3bbf0, 0x3bc10,
1769                 0x3bc28, 0x3bc28,
1770                 0x3bc3c, 0x3bc50,
1771                 0x3bcf0, 0x3bcfc,
1772                 0x3c000, 0x3c030,
1773                 0x3c100, 0x3c144,
1774                 0x3c190, 0x3c1a0,
1775                 0x3c1a8, 0x3c1b8,
1776                 0x3c1c4, 0x3c1c8,
1777                 0x3c1d0, 0x3c1d0,
1778                 0x3c200, 0x3c318,
1779                 0x3c400, 0x3c4b4,
1780                 0x3c4c0, 0x3c52c,
1781                 0x3c540, 0x3c61c,
1782                 0x3c800, 0x3c828,
1783                 0x3c834, 0x3c834,
1784                 0x3c8c0, 0x3c908,
1785                 0x3c910, 0x3c9ac,
1786                 0x3ca00, 0x3ca14,
1787                 0x3ca1c, 0x3ca2c,
1788                 0x3ca44, 0x3ca50,
1789                 0x3ca74, 0x3ca74,
1790                 0x3ca7c, 0x3cafc,
1791                 0x3cb08, 0x3cc24,
1792                 0x3cd00, 0x3cd00,
1793                 0x3cd08, 0x3cd14,
1794                 0x3cd1c, 0x3cd20,
1795                 0x3cd3c, 0x3cd3c,
1796                 0x3cd48, 0x3cd50,
1797                 0x3d200, 0x3d20c,
1798                 0x3d220, 0x3d220,
1799                 0x3d240, 0x3d240,
1800                 0x3d600, 0x3d60c,
1801                 0x3da00, 0x3da1c,
1802                 0x3de00, 0x3de20,
1803                 0x3de38, 0x3de3c,
1804                 0x3de80, 0x3de80,
1805                 0x3de88, 0x3dea8,
1806                 0x3deb0, 0x3deb4,
1807                 0x3dec8, 0x3ded4,
1808                 0x3dfb8, 0x3e004,
1809                 0x3e200, 0x3e200,
1810                 0x3e208, 0x3e240,
1811                 0x3e248, 0x3e280,
1812                 0x3e288, 0x3e2c0,
1813                 0x3e2c8, 0x3e2fc,
1814                 0x3e600, 0x3e630,
1815                 0x3ea00, 0x3eabc,
1816                 0x3eb00, 0x3eb10,
1817                 0x3eb20, 0x3eb30,
1818                 0x3eb40, 0x3eb50,
1819                 0x3eb60, 0x3eb70,
1820                 0x3f000, 0x3f028,
1821                 0x3f030, 0x3f048,
1822                 0x3f060, 0x3f068,
1823                 0x3f070, 0x3f09c,
1824                 0x3f0f0, 0x3f128,
1825                 0x3f130, 0x3f148,
1826                 0x3f160, 0x3f168,
1827                 0x3f170, 0x3f19c,
1828                 0x3f1f0, 0x3f238,
1829                 0x3f240, 0x3f240,
1830                 0x3f248, 0x3f250,
1831                 0x3f25c, 0x3f264,
1832                 0x3f270, 0x3f2b8,
1833                 0x3f2c0, 0x3f2e4,
1834                 0x3f2f8, 0x3f338,
1835                 0x3f340, 0x3f340,
1836                 0x3f348, 0x3f350,
1837                 0x3f35c, 0x3f364,
1838                 0x3f370, 0x3f3b8,
1839                 0x3f3c0, 0x3f3e4,
1840                 0x3f3f8, 0x3f428,
1841                 0x3f430, 0x3f448,
1842                 0x3f460, 0x3f468,
1843                 0x3f470, 0x3f49c,
1844                 0x3f4f0, 0x3f528,
1845                 0x3f530, 0x3f548,
1846                 0x3f560, 0x3f568,
1847                 0x3f570, 0x3f59c,
1848                 0x3f5f0, 0x3f638,
1849                 0x3f640, 0x3f640,
1850                 0x3f648, 0x3f650,
1851                 0x3f65c, 0x3f664,
1852                 0x3f670, 0x3f6b8,
1853                 0x3f6c0, 0x3f6e4,
1854                 0x3f6f8, 0x3f738,
1855                 0x3f740, 0x3f740,
1856                 0x3f748, 0x3f750,
1857                 0x3f75c, 0x3f764,
1858                 0x3f770, 0x3f7b8,
1859                 0x3f7c0, 0x3f7e4,
1860                 0x3f7f8, 0x3f7fc,
1861                 0x3f814, 0x3f814,
1862                 0x3f82c, 0x3f82c,
1863                 0x3f880, 0x3f88c,
1864                 0x3f8e8, 0x3f8ec,
1865                 0x3f900, 0x3f928,
1866                 0x3f930, 0x3f948,
1867                 0x3f960, 0x3f968,
1868                 0x3f970, 0x3f99c,
1869                 0x3f9f0, 0x3fa38,
1870                 0x3fa40, 0x3fa40,
1871                 0x3fa48, 0x3fa50,
1872                 0x3fa5c, 0x3fa64,
1873                 0x3fa70, 0x3fab8,
1874                 0x3fac0, 0x3fae4,
1875                 0x3faf8, 0x3fb10,
1876                 0x3fb28, 0x3fb28,
1877                 0x3fb3c, 0x3fb50,
1878                 0x3fbf0, 0x3fc10,
1879                 0x3fc28, 0x3fc28,
1880                 0x3fc3c, 0x3fc50,
1881                 0x3fcf0, 0x3fcfc,
1882                 0x40000, 0x4000c,
1883                 0x40040, 0x40050,
1884                 0x40060, 0x40068,
1885                 0x4007c, 0x4008c,
1886                 0x40094, 0x400b0,
1887                 0x400c0, 0x40144,
1888                 0x40180, 0x4018c,
1889                 0x40200, 0x40254,
1890                 0x40260, 0x40264,
1891                 0x40270, 0x40288,
1892                 0x40290, 0x40298,
1893                 0x402ac, 0x402c8,
1894                 0x402d0, 0x402e0,
1895                 0x402f0, 0x402f0,
1896                 0x40300, 0x4033c,
1897                 0x403f8, 0x403fc,
1898                 0x41304, 0x413c4,
1899                 0x41400, 0x4140c,
1900                 0x41414, 0x4141c,
1901                 0x41480, 0x414d0,
1902                 0x44000, 0x44054,
1903                 0x4405c, 0x44078,
1904                 0x440c0, 0x44174,
1905                 0x44180, 0x441ac,
1906                 0x441b4, 0x441b8,
1907                 0x441c0, 0x44254,
1908                 0x4425c, 0x44278,
1909                 0x442c0, 0x44374,
1910                 0x44380, 0x443ac,
1911                 0x443b4, 0x443b8,
1912                 0x443c0, 0x44454,
1913                 0x4445c, 0x44478,
1914                 0x444c0, 0x44574,
1915                 0x44580, 0x445ac,
1916                 0x445b4, 0x445b8,
1917                 0x445c0, 0x44654,
1918                 0x4465c, 0x44678,
1919                 0x446c0, 0x44774,
1920                 0x44780, 0x447ac,
1921                 0x447b4, 0x447b8,
1922                 0x447c0, 0x44854,
1923                 0x4485c, 0x44878,
1924                 0x448c0, 0x44974,
1925                 0x44980, 0x449ac,
1926                 0x449b4, 0x449b8,
1927                 0x449c0, 0x449fc,
1928                 0x45000, 0x45004,
1929                 0x45010, 0x45030,
1930                 0x45040, 0x45060,
1931                 0x45068, 0x45068,
1932                 0x45080, 0x45084,
1933                 0x450a0, 0x450b0,
1934                 0x45200, 0x45204,
1935                 0x45210, 0x45230,
1936                 0x45240, 0x45260,
1937                 0x45268, 0x45268,
1938                 0x45280, 0x45284,
1939                 0x452a0, 0x452b0,
1940                 0x460c0, 0x460e4,
1941                 0x47000, 0x4703c,
1942                 0x47044, 0x4708c,
1943                 0x47200, 0x47250,
1944                 0x47400, 0x47408,
1945                 0x47414, 0x47420,
1946                 0x47600, 0x47618,
1947                 0x47800, 0x47814,
1948                 0x48000, 0x4800c,
1949                 0x48040, 0x48050,
1950                 0x48060, 0x48068,
1951                 0x4807c, 0x4808c,
1952                 0x48094, 0x480b0,
1953                 0x480c0, 0x48144,
1954                 0x48180, 0x4818c,
1955                 0x48200, 0x48254,
1956                 0x48260, 0x48264,
1957                 0x48270, 0x48288,
1958                 0x48290, 0x48298,
1959                 0x482ac, 0x482c8,
1960                 0x482d0, 0x482e0,
1961                 0x482f0, 0x482f0,
1962                 0x48300, 0x4833c,
1963                 0x483f8, 0x483fc,
1964                 0x49304, 0x493c4,
1965                 0x49400, 0x4940c,
1966                 0x49414, 0x4941c,
1967                 0x49480, 0x494d0,
1968                 0x4c000, 0x4c054,
1969                 0x4c05c, 0x4c078,
1970                 0x4c0c0, 0x4c174,
1971                 0x4c180, 0x4c1ac,
1972                 0x4c1b4, 0x4c1b8,
1973                 0x4c1c0, 0x4c254,
1974                 0x4c25c, 0x4c278,
1975                 0x4c2c0, 0x4c374,
1976                 0x4c380, 0x4c3ac,
1977                 0x4c3b4, 0x4c3b8,
1978                 0x4c3c0, 0x4c454,
1979                 0x4c45c, 0x4c478,
1980                 0x4c4c0, 0x4c574,
1981                 0x4c580, 0x4c5ac,
1982                 0x4c5b4, 0x4c5b8,
1983                 0x4c5c0, 0x4c654,
1984                 0x4c65c, 0x4c678,
1985                 0x4c6c0, 0x4c774,
1986                 0x4c780, 0x4c7ac,
1987                 0x4c7b4, 0x4c7b8,
1988                 0x4c7c0, 0x4c854,
1989                 0x4c85c, 0x4c878,
1990                 0x4c8c0, 0x4c974,
1991                 0x4c980, 0x4c9ac,
1992                 0x4c9b4, 0x4c9b8,
1993                 0x4c9c0, 0x4c9fc,
1994                 0x4d000, 0x4d004,
1995                 0x4d010, 0x4d030,
1996                 0x4d040, 0x4d060,
1997                 0x4d068, 0x4d068,
1998                 0x4d080, 0x4d084,
1999                 0x4d0a0, 0x4d0b0,
2000                 0x4d200, 0x4d204,
2001                 0x4d210, 0x4d230,
2002                 0x4d240, 0x4d260,
2003                 0x4d268, 0x4d268,
2004                 0x4d280, 0x4d284,
2005                 0x4d2a0, 0x4d2b0,
2006                 0x4e0c0, 0x4e0e4,
2007                 0x4f000, 0x4f03c,
2008                 0x4f044, 0x4f08c,
2009                 0x4f200, 0x4f250,
2010                 0x4f400, 0x4f408,
2011                 0x4f414, 0x4f420,
2012                 0x4f600, 0x4f618,
2013                 0x4f800, 0x4f814,
2014                 0x50000, 0x50084,
2015                 0x50090, 0x500cc,
2016                 0x50400, 0x50400,
2017                 0x50800, 0x50884,
2018                 0x50890, 0x508cc,
2019                 0x50c00, 0x50c00,
2020                 0x51000, 0x5101c,
2021                 0x51300, 0x51308,
2022         };
2023
2024         static const unsigned int t6_reg_ranges[] = {
2025                 0x1008, 0x101c,
2026                 0x1024, 0x10a8,
2027                 0x10b4, 0x10f8,
2028                 0x1100, 0x1114,
2029                 0x111c, 0x112c,
2030                 0x1138, 0x113c,
2031                 0x1144, 0x114c,
2032                 0x1180, 0x1184,
2033                 0x1190, 0x1194,
2034                 0x11a0, 0x11a4,
2035                 0x11b0, 0x11b4,
2036                 0x11fc, 0x1274,
2037                 0x1280, 0x133c,
2038                 0x1800, 0x18fc,
2039                 0x3000, 0x302c,
2040                 0x3060, 0x30b0,
2041                 0x30b8, 0x30d8,
2042                 0x30e0, 0x30fc,
2043                 0x3140, 0x357c,
2044                 0x35a8, 0x35cc,
2045                 0x35ec, 0x35ec,
2046                 0x3600, 0x5624,
2047                 0x56cc, 0x56ec,
2048                 0x56f4, 0x5720,
2049                 0x5728, 0x575c,
2050                 0x580c, 0x5814,
2051                 0x5890, 0x589c,
2052                 0x58a4, 0x58ac,
2053                 0x58b8, 0x58bc,
2054                 0x5940, 0x595c,
2055                 0x5980, 0x598c,
2056                 0x59b0, 0x59c8,
2057                 0x59d0, 0x59dc,
2058                 0x59fc, 0x5a18,
2059                 0x5a60, 0x5a6c,
2060                 0x5a80, 0x5a8c,
2061                 0x5a94, 0x5a9c,
2062                 0x5b94, 0x5bfc,
2063                 0x5c10, 0x5e48,
2064                 0x5e50, 0x5e94,
2065                 0x5ea0, 0x5eb0,
2066                 0x5ec0, 0x5ec0,
2067                 0x5ec8, 0x5ed0,
2068                 0x5ee0, 0x5ee0,
2069                 0x5ef0, 0x5ef0,
2070                 0x5f00, 0x5f00,
2071                 0x6000, 0x6020,
2072                 0x6028, 0x6040,
2073                 0x6058, 0x609c,
2074                 0x60a8, 0x619c,
2075                 0x7700, 0x7798,
2076                 0x77c0, 0x7880,
2077                 0x78cc, 0x78fc,
2078                 0x7b00, 0x7b58,
2079                 0x7b60, 0x7b84,
2080                 0x7b8c, 0x7c54,
2081                 0x7d00, 0x7d38,
2082                 0x7d40, 0x7d84,
2083                 0x7d8c, 0x7ddc,
2084                 0x7de4, 0x7e04,
2085                 0x7e10, 0x7e1c,
2086                 0x7e24, 0x7e38,
2087                 0x7e40, 0x7e44,
2088                 0x7e4c, 0x7e78,
2089                 0x7e80, 0x7edc,
2090                 0x7ee8, 0x7efc,
2091                 0x8dc0, 0x8de4,
2092                 0x8df8, 0x8e04,
2093                 0x8e10, 0x8e84,
2094                 0x8ea0, 0x8f88,
2095                 0x8fb8, 0x9058,
2096                 0x9060, 0x9060,
2097                 0x9068, 0x90f8,
2098                 0x9100, 0x9124,
2099                 0x9400, 0x9470,
2100                 0x9600, 0x9600,
2101                 0x9608, 0x9638,
2102                 0x9640, 0x9704,
2103                 0x9710, 0x971c,
2104                 0x9800, 0x9808,
2105                 0x9820, 0x983c,
2106                 0x9850, 0x9864,
2107                 0x9c00, 0x9c6c,
2108                 0x9c80, 0x9cec,
2109                 0x9d00, 0x9d6c,
2110                 0x9d80, 0x9dec,
2111                 0x9e00, 0x9e6c,
2112                 0x9e80, 0x9eec,
2113                 0x9f00, 0x9f6c,
2114                 0x9f80, 0xa020,
2115                 0xd004, 0xd03c,
2116                 0xd100, 0xd118,
2117                 0xd200, 0xd214,
2118                 0xd220, 0xd234,
2119                 0xd240, 0xd254,
2120                 0xd260, 0xd274,
2121                 0xd280, 0xd294,
2122                 0xd2a0, 0xd2b4,
2123                 0xd2c0, 0xd2d4,
2124                 0xd2e0, 0xd2f4,
2125                 0xd300, 0xd31c,
2126                 0xdfc0, 0xdfe0,
2127                 0xe000, 0xf008,
2128                 0xf010, 0xf018,
2129                 0xf020, 0xf028,
2130                 0x11000, 0x11014,
2131                 0x11048, 0x1106c,
2132                 0x11074, 0x11088,
2133                 0x11098, 0x11120,
2134                 0x1112c, 0x1117c,
2135                 0x11190, 0x112e0,
2136                 0x11300, 0x1130c,
2137                 0x12000, 0x1206c,
2138                 0x19040, 0x1906c,
2139                 0x19078, 0x19080,
2140                 0x1908c, 0x190e8,
2141                 0x190f0, 0x190f8,
2142                 0x19100, 0x19110,
2143                 0x19120, 0x19124,
2144                 0x19150, 0x19194,
2145                 0x1919c, 0x191b0,
2146                 0x191d0, 0x191e8,
2147                 0x19238, 0x19290,
2148                 0x192a4, 0x192b0,
2149                 0x192bc, 0x192bc,
2150                 0x19348, 0x1934c,
2151                 0x193f8, 0x19418,
2152                 0x19420, 0x19428,
2153                 0x19430, 0x19444,
2154                 0x1944c, 0x1946c,
2155                 0x19474, 0x19474,
2156                 0x19490, 0x194cc,
2157                 0x194f0, 0x194f8,
2158                 0x19c00, 0x19c48,
2159                 0x19c50, 0x19c80,
2160                 0x19c94, 0x19c98,
2161                 0x19ca0, 0x19cbc,
2162                 0x19ce4, 0x19ce4,
2163                 0x19cf0, 0x19cf8,
2164                 0x19d00, 0x19d28,
2165                 0x19d50, 0x19d78,
2166                 0x19d94, 0x19d98,
2167                 0x19da0, 0x19dc8,
2168                 0x19df0, 0x19e10,
2169                 0x19e50, 0x19e6c,
2170                 0x19ea0, 0x19ebc,
2171                 0x19ec4, 0x19ef4,
2172                 0x19f04, 0x19f2c,
2173                 0x19f34, 0x19f34,
2174                 0x19f40, 0x19f50,
2175                 0x19f90, 0x19fac,
2176                 0x19fc4, 0x19fc8,
2177                 0x19fd0, 0x19fe4,
2178                 0x1a000, 0x1a004,
2179                 0x1a010, 0x1a06c,
2180                 0x1a0b0, 0x1a0e4,
2181                 0x1a0ec, 0x1a0f8,
2182                 0x1a100, 0x1a108,
2183                 0x1a114, 0x1a120,
2184                 0x1a128, 0x1a130,
2185                 0x1a138, 0x1a138,
2186                 0x1a190, 0x1a1c4,
2187                 0x1a1fc, 0x1a1fc,
2188                 0x1e008, 0x1e00c,
2189                 0x1e040, 0x1e044,
2190                 0x1e04c, 0x1e04c,
2191                 0x1e284, 0x1e290,
2192                 0x1e2c0, 0x1e2c0,
2193                 0x1e2e0, 0x1e2e0,
2194                 0x1e300, 0x1e384,
2195                 0x1e3c0, 0x1e3c8,
2196                 0x1e408, 0x1e40c,
2197                 0x1e440, 0x1e444,
2198                 0x1e44c, 0x1e44c,
2199                 0x1e684, 0x1e690,
2200                 0x1e6c0, 0x1e6c0,
2201                 0x1e6e0, 0x1e6e0,
2202                 0x1e700, 0x1e784,
2203                 0x1e7c0, 0x1e7c8,
2204                 0x1e808, 0x1e80c,
2205                 0x1e840, 0x1e844,
2206                 0x1e84c, 0x1e84c,
2207                 0x1ea84, 0x1ea90,
2208                 0x1eac0, 0x1eac0,
2209                 0x1eae0, 0x1eae0,
2210                 0x1eb00, 0x1eb84,
2211                 0x1ebc0, 0x1ebc8,
2212                 0x1ec08, 0x1ec0c,
2213                 0x1ec40, 0x1ec44,
2214                 0x1ec4c, 0x1ec4c,
2215                 0x1ee84, 0x1ee90,
2216                 0x1eec0, 0x1eec0,
2217                 0x1eee0, 0x1eee0,
2218                 0x1ef00, 0x1ef84,
2219                 0x1efc0, 0x1efc8,
2220                 0x1f008, 0x1f00c,
2221                 0x1f040, 0x1f044,
2222                 0x1f04c, 0x1f04c,
2223                 0x1f284, 0x1f290,
2224                 0x1f2c0, 0x1f2c0,
2225                 0x1f2e0, 0x1f2e0,
2226                 0x1f300, 0x1f384,
2227                 0x1f3c0, 0x1f3c8,
2228                 0x1f408, 0x1f40c,
2229                 0x1f440, 0x1f444,
2230                 0x1f44c, 0x1f44c,
2231                 0x1f684, 0x1f690,
2232                 0x1f6c0, 0x1f6c0,
2233                 0x1f6e0, 0x1f6e0,
2234                 0x1f700, 0x1f784,
2235                 0x1f7c0, 0x1f7c8,
2236                 0x1f808, 0x1f80c,
2237                 0x1f840, 0x1f844,
2238                 0x1f84c, 0x1f84c,
2239                 0x1fa84, 0x1fa90,
2240                 0x1fac0, 0x1fac0,
2241                 0x1fae0, 0x1fae0,
2242                 0x1fb00, 0x1fb84,
2243                 0x1fbc0, 0x1fbc8,
2244                 0x1fc08, 0x1fc0c,
2245                 0x1fc40, 0x1fc44,
2246                 0x1fc4c, 0x1fc4c,
2247                 0x1fe84, 0x1fe90,
2248                 0x1fec0, 0x1fec0,
2249                 0x1fee0, 0x1fee0,
2250                 0x1ff00, 0x1ff84,
2251                 0x1ffc0, 0x1ffc8,
2252                 0x30000, 0x30030,
2253                 0x30100, 0x30168,
2254                 0x30190, 0x301a0,
2255                 0x301a8, 0x301b8,
2256                 0x301c4, 0x301c8,
2257                 0x301d0, 0x301d0,
2258                 0x30200, 0x30320,
2259                 0x30400, 0x304b4,
2260                 0x304c0, 0x3052c,
2261                 0x30540, 0x3061c,
2262                 0x30800, 0x308a0,
2263                 0x308c0, 0x30908,
2264                 0x30910, 0x309b8,
2265                 0x30a00, 0x30a04,
2266                 0x30a0c, 0x30a14,
2267                 0x30a1c, 0x30a2c,
2268                 0x30a44, 0x30a50,
2269                 0x30a74, 0x30a74,
2270                 0x30a7c, 0x30afc,
2271                 0x30b08, 0x30c24,
2272                 0x30d00, 0x30d14,
2273                 0x30d1c, 0x30d3c,
2274                 0x30d44, 0x30d4c,
2275                 0x30d54, 0x30d74,
2276                 0x30d7c, 0x30d7c,
2277                 0x30de0, 0x30de0,
2278                 0x30e00, 0x30ed4,
2279                 0x30f00, 0x30fa4,
2280                 0x30fc0, 0x30fc4,
2281                 0x31000, 0x31004,
2282                 0x31080, 0x310fc,
2283                 0x31208, 0x31220,
2284                 0x3123c, 0x31254,
2285                 0x31300, 0x31300,
2286                 0x31308, 0x3131c,
2287                 0x31338, 0x3133c,
2288                 0x31380, 0x31380,
2289                 0x31388, 0x313a8,
2290                 0x313b4, 0x313b4,
2291                 0x31400, 0x31420,
2292                 0x31438, 0x3143c,
2293                 0x31480, 0x31480,
2294                 0x314a8, 0x314a8,
2295                 0x314b0, 0x314b4,
2296                 0x314c8, 0x314d4,
2297                 0x31a40, 0x31a4c,
2298                 0x31af0, 0x31b20,
2299                 0x31b38, 0x31b3c,
2300                 0x31b80, 0x31b80,
2301                 0x31ba8, 0x31ba8,
2302                 0x31bb0, 0x31bb4,
2303                 0x31bc8, 0x31bd4,
2304                 0x32140, 0x3218c,
2305                 0x321f0, 0x321f4,
2306                 0x32200, 0x32200,
2307                 0x32218, 0x32218,
2308                 0x32400, 0x32400,
2309                 0x32408, 0x3241c,
2310                 0x32618, 0x32620,
2311                 0x32664, 0x32664,
2312                 0x326a8, 0x326a8,
2313                 0x326ec, 0x326ec,
2314                 0x32a00, 0x32abc,
2315                 0x32b00, 0x32b18,
2316                 0x32b20, 0x32b38,
2317                 0x32b40, 0x32b58,
2318                 0x32b60, 0x32b78,
2319                 0x32c00, 0x32c00,
2320                 0x32c08, 0x32c3c,
2321                 0x33000, 0x3302c,
2322                 0x33034, 0x33050,
2323                 0x33058, 0x33058,
2324                 0x33060, 0x3308c,
2325                 0x3309c, 0x330ac,
2326                 0x330c0, 0x330c0,
2327                 0x330c8, 0x330d0,
2328                 0x330d8, 0x330e0,
2329                 0x330ec, 0x3312c,
2330                 0x33134, 0x33150,
2331                 0x33158, 0x33158,
2332                 0x33160, 0x3318c,
2333                 0x3319c, 0x331ac,
2334                 0x331c0, 0x331c0,
2335                 0x331c8, 0x331d0,
2336                 0x331d8, 0x331e0,
2337                 0x331ec, 0x33290,
2338                 0x33298, 0x332c4,
2339                 0x332e4, 0x33390,
2340                 0x33398, 0x333c4,
2341                 0x333e4, 0x3342c,
2342                 0x33434, 0x33450,
2343                 0x33458, 0x33458,
2344                 0x33460, 0x3348c,
2345                 0x3349c, 0x334ac,
2346                 0x334c0, 0x334c0,
2347                 0x334c8, 0x334d0,
2348                 0x334d8, 0x334e0,
2349                 0x334ec, 0x3352c,
2350                 0x33534, 0x33550,
2351                 0x33558, 0x33558,
2352                 0x33560, 0x3358c,
2353                 0x3359c, 0x335ac,
2354                 0x335c0, 0x335c0,
2355                 0x335c8, 0x335d0,
2356                 0x335d8, 0x335e0,
2357                 0x335ec, 0x33690,
2358                 0x33698, 0x336c4,
2359                 0x336e4, 0x33790,
2360                 0x33798, 0x337c4,
2361                 0x337e4, 0x337fc,
2362                 0x33814, 0x33814,
2363                 0x33854, 0x33868,
2364                 0x33880, 0x3388c,
2365                 0x338c0, 0x338d0,
2366                 0x338e8, 0x338ec,
2367                 0x33900, 0x3392c,
2368                 0x33934, 0x33950,
2369                 0x33958, 0x33958,
2370                 0x33960, 0x3398c,
2371                 0x3399c, 0x339ac,
2372                 0x339c0, 0x339c0,
2373                 0x339c8, 0x339d0,
2374                 0x339d8, 0x339e0,
2375                 0x339ec, 0x33a90,
2376                 0x33a98, 0x33ac4,
2377                 0x33ae4, 0x33b10,
2378                 0x33b24, 0x33b28,
2379                 0x33b38, 0x33b50,
2380                 0x33bf0, 0x33c10,
2381                 0x33c24, 0x33c28,
2382                 0x33c38, 0x33c50,
2383                 0x33cf0, 0x33cfc,
2384                 0x34000, 0x34030,
2385                 0x34100, 0x34168,
2386                 0x34190, 0x341a0,
2387                 0x341a8, 0x341b8,
2388                 0x341c4, 0x341c8,
2389                 0x341d0, 0x341d0,
2390                 0x34200, 0x34320,
2391                 0x34400, 0x344b4,
2392                 0x344c0, 0x3452c,
2393                 0x34540, 0x3461c,
2394                 0x34800, 0x348a0,
2395                 0x348c0, 0x34908,
2396                 0x34910, 0x349b8,
2397                 0x34a00, 0x34a04,
2398                 0x34a0c, 0x34a14,
2399                 0x34a1c, 0x34a2c,
2400                 0x34a44, 0x34a50,
2401                 0x34a74, 0x34a74,
2402                 0x34a7c, 0x34afc,
2403                 0x34b08, 0x34c24,
2404                 0x34d00, 0x34d14,
2405                 0x34d1c, 0x34d3c,
2406                 0x34d44, 0x34d4c,
2407                 0x34d54, 0x34d74,
2408                 0x34d7c, 0x34d7c,
2409                 0x34de0, 0x34de0,
2410                 0x34e00, 0x34ed4,
2411                 0x34f00, 0x34fa4,
2412                 0x34fc0, 0x34fc4,
2413                 0x35000, 0x35004,
2414                 0x35080, 0x350fc,
2415                 0x35208, 0x35220,
2416                 0x3523c, 0x35254,
2417                 0x35300, 0x35300,
2418                 0x35308, 0x3531c,
2419                 0x35338, 0x3533c,
2420                 0x35380, 0x35380,
2421                 0x35388, 0x353a8,
2422                 0x353b4, 0x353b4,
2423                 0x35400, 0x35420,
2424                 0x35438, 0x3543c,
2425                 0x35480, 0x35480,
2426                 0x354a8, 0x354a8,
2427                 0x354b0, 0x354b4,
2428                 0x354c8, 0x354d4,
2429                 0x35a40, 0x35a4c,
2430                 0x35af0, 0x35b20,
2431                 0x35b38, 0x35b3c,
2432                 0x35b80, 0x35b80,
2433                 0x35ba8, 0x35ba8,
2434                 0x35bb0, 0x35bb4,
2435                 0x35bc8, 0x35bd4,
2436                 0x36140, 0x3618c,
2437                 0x361f0, 0x361f4,
2438                 0x36200, 0x36200,
2439                 0x36218, 0x36218,
2440                 0x36400, 0x36400,
2441                 0x36408, 0x3641c,
2442                 0x36618, 0x36620,
2443                 0x36664, 0x36664,
2444                 0x366a8, 0x366a8,
2445                 0x366ec, 0x366ec,
2446                 0x36a00, 0x36abc,
2447                 0x36b00, 0x36b18,
2448                 0x36b20, 0x36b38,
2449                 0x36b40, 0x36b58,
2450                 0x36b60, 0x36b78,
2451                 0x36c00, 0x36c00,
2452                 0x36c08, 0x36c3c,
2453                 0x37000, 0x3702c,
2454                 0x37034, 0x37050,
2455                 0x37058, 0x37058,
2456                 0x37060, 0x3708c,
2457                 0x3709c, 0x370ac,
2458                 0x370c0, 0x370c0,
2459                 0x370c8, 0x370d0,
2460                 0x370d8, 0x370e0,
2461                 0x370ec, 0x3712c,
2462                 0x37134, 0x37150,
2463                 0x37158, 0x37158,
2464                 0x37160, 0x3718c,
2465                 0x3719c, 0x371ac,
2466                 0x371c0, 0x371c0,
2467                 0x371c8, 0x371d0,
2468                 0x371d8, 0x371e0,
2469                 0x371ec, 0x37290,
2470                 0x37298, 0x372c4,
2471                 0x372e4, 0x37390,
2472                 0x37398, 0x373c4,
2473                 0x373e4, 0x3742c,
2474                 0x37434, 0x37450,
2475                 0x37458, 0x37458,
2476                 0x37460, 0x3748c,
2477                 0x3749c, 0x374ac,
2478                 0x374c0, 0x374c0,
2479                 0x374c8, 0x374d0,
2480                 0x374d8, 0x374e0,
2481                 0x374ec, 0x3752c,
2482                 0x37534, 0x37550,
2483                 0x37558, 0x37558,
2484                 0x37560, 0x3758c,
2485                 0x3759c, 0x375ac,
2486                 0x375c0, 0x375c0,
2487                 0x375c8, 0x375d0,
2488                 0x375d8, 0x375e0,
2489                 0x375ec, 0x37690,
2490                 0x37698, 0x376c4,
2491                 0x376e4, 0x37790,
2492                 0x37798, 0x377c4,
2493                 0x377e4, 0x377fc,
2494                 0x37814, 0x37814,
2495                 0x37854, 0x37868,
2496                 0x37880, 0x3788c,
2497                 0x378c0, 0x378d0,
2498                 0x378e8, 0x378ec,
2499                 0x37900, 0x3792c,
2500                 0x37934, 0x37950,
2501                 0x37958, 0x37958,
2502                 0x37960, 0x3798c,
2503                 0x3799c, 0x379ac,
2504                 0x379c0, 0x379c0,
2505                 0x379c8, 0x379d0,
2506                 0x379d8, 0x379e0,
2507                 0x379ec, 0x37a90,
2508                 0x37a98, 0x37ac4,
2509                 0x37ae4, 0x37b10,
2510                 0x37b24, 0x37b28,
2511                 0x37b38, 0x37b50,
2512                 0x37bf0, 0x37c10,
2513                 0x37c24, 0x37c28,
2514                 0x37c38, 0x37c50,
2515                 0x37cf0, 0x37cfc,
2516                 0x40040, 0x40040,
2517                 0x40080, 0x40084,
2518                 0x40100, 0x40100,
2519                 0x40140, 0x401bc,
2520                 0x40200, 0x40214,
2521                 0x40228, 0x40228,
2522                 0x40240, 0x40258,
2523                 0x40280, 0x40280,
2524                 0x40304, 0x40304,
2525                 0x40330, 0x4033c,
2526                 0x41304, 0x413c8,
2527                 0x413d0, 0x413dc,
2528                 0x413f0, 0x413f0,
2529                 0x41400, 0x4140c,
2530                 0x41414, 0x4141c,
2531                 0x41480, 0x414d0,
2532                 0x44000, 0x4407c,
2533                 0x440c0, 0x441ac,
2534                 0x441b4, 0x4427c,
2535                 0x442c0, 0x443ac,
2536                 0x443b4, 0x4447c,
2537                 0x444c0, 0x445ac,
2538                 0x445b4, 0x4467c,
2539                 0x446c0, 0x447ac,
2540                 0x447b4, 0x4487c,
2541                 0x448c0, 0x449ac,
2542                 0x449b4, 0x44a7c,
2543                 0x44ac0, 0x44bac,
2544                 0x44bb4, 0x44c7c,
2545                 0x44cc0, 0x44dac,
2546                 0x44db4, 0x44e7c,
2547                 0x44ec0, 0x44fac,
2548                 0x44fb4, 0x4507c,
2549                 0x450c0, 0x451ac,
2550                 0x451b4, 0x451fc,
2551                 0x45800, 0x45804,
2552                 0x45810, 0x45830,
2553                 0x45840, 0x45860,
2554                 0x45868, 0x45868,
2555                 0x45880, 0x45884,
2556                 0x458a0, 0x458b0,
2557                 0x45a00, 0x45a04,
2558                 0x45a10, 0x45a30,
2559                 0x45a40, 0x45a60,
2560                 0x45a68, 0x45a68,
2561                 0x45a80, 0x45a84,
2562                 0x45aa0, 0x45ab0,
2563                 0x460c0, 0x460e4,
2564                 0x47000, 0x4703c,
2565                 0x47044, 0x4708c,
2566                 0x47200, 0x47250,
2567                 0x47400, 0x47408,
2568                 0x47414, 0x47420,
2569                 0x47600, 0x47618,
2570                 0x47800, 0x47814,
2571                 0x47820, 0x4782c,
2572                 0x50000, 0x50084,
2573                 0x50090, 0x500cc,
2574                 0x50300, 0x50384,
2575                 0x50400, 0x50400,
2576                 0x50800, 0x50884,
2577                 0x50890, 0x508cc,
2578                 0x50b00, 0x50b84,
2579                 0x50c00, 0x50c00,
2580                 0x51000, 0x51020,
2581                 0x51028, 0x510b0,
2582                 0x51300, 0x51324,
2583         };
2584
2585         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2586         const unsigned int *reg_ranges;
2587         int reg_ranges_size, range;
2588         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2589
2590         /* Select the right set of register ranges to dump depending on the
2591          * adapter chip type.
2592          */
2593         switch (chip_version) {
2594         case CHELSIO_T4:
2595                 reg_ranges = t4_reg_ranges;
2596                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2597                 break;
2598
2599         case CHELSIO_T5:
2600                 reg_ranges = t5_reg_ranges;
2601                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2602                 break;
2603
2604         case CHELSIO_T6:
2605                 reg_ranges = t6_reg_ranges;
2606                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2607                 break;
2608
2609         default:
2610                 dev_err(adap->pdev_dev,
2611                         "Unsupported chip version %d\n", chip_version);
2612                 return;
2613         }
2614
2615         /* Clear the register buffer and insert the appropriate register
2616          * values selected by the above register ranges.
2617          */
2618         memset(buf, 0, buf_size);
2619         for (range = 0; range < reg_ranges_size; range += 2) {
2620                 unsigned int reg = reg_ranges[range];
2621                 unsigned int last_reg = reg_ranges[range + 1];
2622                 u32 *bufp = (u32 *)((char *)buf + reg);
2623
2624                 /* Iterate across the register range filling in the register
2625                  * buffer but don't write past the end of the register buffer.
2626                  */
2627                 while (reg <= last_reg && bufp < buf_end) {
2628                         *bufp++ = t4_read_reg(adap, reg);
2629                         reg += sizeof(u32);
2630                 }
2631         }
2632 }
2633
2634 #define EEPROM_STAT_ADDR   0x7bfc
2635 #define VPD_SIZE           0x800
2636 #define VPD_BASE           0x400
2637 #define VPD_BASE_OLD       0
2638 #define VPD_LEN            1024
2639 #define CHELSIO_VPD_UNIQUE_ID 0x82
2640
2641 /**
2642  * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2643  * @phys_addr: the physical EEPROM address
2644  * @fn: the PCI function number
2645  * @sz: size of function-specific area
2646  *
2647  * Translate a physical EEPROM address to virtual.  The first 1K is
2648  * accessed through virtual addresses starting at 31K, the rest is
2649  * accessed through virtual addresses starting at 0.
2650  *
2651  * The mapping is as follows:
2652  * [0..1K) -> [31K..32K)
2653  * [1K..1K+A) -> [31K-A..31K)
2654  * [1K+A..ES) -> [0..ES-A-1K)
2655  *
2656  * where A = @fn * @sz, and ES = EEPROM size.
2657  */
2658 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2659 {
2660         fn *= sz;
2661         if (phys_addr < 1024)
2662                 return phys_addr + (31 << 10);
2663         if (phys_addr < 1024 + fn)
2664                 return 31744 - fn + phys_addr - 1024;
2665         if (phys_addr < EEPROMSIZE)
2666                 return phys_addr - 1024 - fn;
2667         return -EINVAL;
2668 }
2669
2670 /**
2671  *      t4_seeprom_wp - enable/disable EEPROM write protection
2672  *      @adapter: the adapter
2673  *      @enable: whether to enable or disable write protection
2674  *
2675  *      Enables or disables write protection on the serial EEPROM.
2676  */
2677 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2678 {
2679         unsigned int v = enable ? 0xc : 0;
2680         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2681         return ret < 0 ? ret : 0;
2682 }
2683
2684 /**
2685  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2686  *      @adapter: adapter to read
2687  *      @p: where to store the parameters
2688  *
2689  *      Reads card parameters stored in VPD EEPROM.
2690  */
2691 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2692 {
2693         int i, ret = 0, addr;
2694         int ec, sn, pn, na;
2695         u8 *vpd, csum;
2696         unsigned int vpdr_len, kw_offset, id_len;
2697
2698         vpd = vmalloc(VPD_LEN);
2699         if (!vpd)
2700                 return -ENOMEM;
2701
2702         /* We have two VPD data structures stored in the adapter VPD area.
2703          * By default, Linux calculates the size of the VPD area by traversing
2704          * the first VPD area at offset 0x0, so we need to tell the OS what
2705          * our real VPD size is.
2706          */
2707         ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2708         if (ret < 0)
2709                 goto out;
2710
2711         /* Card information normally starts at VPD_BASE but early cards had
2712          * it at 0.
2713          */
2714         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2715         if (ret < 0)
2716                 goto out;
2717
2718         /* The VPD shall have a unique identifier specified by the PCI SIG.
2719          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2720          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2721          * is expected to automatically put this entry at the
2722          * beginning of the VPD.
2723          */
2724         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2725
2726         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2727         if (ret < 0)
2728                 goto out;
2729
2730         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2731                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2732                 ret = -EINVAL;
2733                 goto out;
2734         }
2735
2736         id_len = pci_vpd_lrdt_size(vpd);
2737         if (id_len > ID_LEN)
2738                 id_len = ID_LEN;
2739
2740         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2741         if (i < 0) {
2742                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2743                 ret = -EINVAL;
2744                 goto out;
2745         }
2746
2747         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2748         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2749         if (vpdr_len + kw_offset > VPD_LEN) {
2750                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2751                 ret = -EINVAL;
2752                 goto out;
2753         }
2754
2755 #define FIND_VPD_KW(var, name) do { \
2756         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2757         if (var < 0) { \
2758                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2759                 ret = -EINVAL; \
2760                 goto out; \
2761         } \
2762         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2763 } while (0)
2764
2765         FIND_VPD_KW(i, "RV");
2766         for (csum = 0; i >= 0; i--)
2767                 csum += vpd[i];
2768
2769         if (csum) {
2770                 dev_err(adapter->pdev_dev,
2771                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2772                 ret = -EINVAL;
2773                 goto out;
2774         }
2775
2776         FIND_VPD_KW(ec, "EC");
2777         FIND_VPD_KW(sn, "SN");
2778         FIND_VPD_KW(pn, "PN");
2779         FIND_VPD_KW(na, "NA");
2780 #undef FIND_VPD_KW
2781
2782         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2783         strim(p->id);
2784         memcpy(p->ec, vpd + ec, EC_LEN);
2785         strim(p->ec);
2786         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2787         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2788         strim(p->sn);
2789         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2790         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2791         strim(p->pn);
2792         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2793         strim((char *)p->na);
2794
2795 out:
2796         vfree(vpd);
2797         return ret < 0 ? ret : 0;
2798 }
2799
2800 /**
2801  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2802  *      @adapter: adapter to read
2803  *      @p: where to store the parameters
2804  *
2805  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2806  *      Clock.  This can only be called after a connection to the firmware
2807  *      is established.
2808  */
2809 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2810 {
2811         u32 cclk_param, cclk_val;
2812         int ret;
2813
2814         /* Grab the raw VPD parameters.
2815          */
2816         ret = t4_get_raw_vpd_params(adapter, p);
2817         if (ret)
2818                 return ret;
2819
2820         /* Ask firmware for the Core Clock since it knows how to translate the
2821          * Reference Clock ('V2') VPD field into a Core Clock value ...
2822          */
2823         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2824                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2825         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2826                               1, &cclk_param, &cclk_val);
2827
2828         if (ret)
2829                 return ret;
2830         p->cclk = cclk_val;
2831
2832         return 0;
2833 }
2834
2835 /* serial flash and firmware constants */
2836 enum {
2837         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2838
2839         /* flash command opcodes */
2840         SF_PROG_PAGE    = 2,          /* program page */
2841         SF_WR_DISABLE   = 4,          /* disable writes */
2842         SF_RD_STATUS    = 5,          /* read status register */
2843         SF_WR_ENABLE    = 6,          /* enable writes */
2844         SF_RD_DATA_FAST = 0xb,        /* read flash */
2845         SF_RD_ID        = 0x9f,       /* read ID */
2846         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2847
2848         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2849 };
2850
2851 /**
2852  *      sf1_read - read data from the serial flash
2853  *      @adapter: the adapter
2854  *      @byte_cnt: number of bytes to read
2855  *      @cont: whether another operation will be chained
2856  *      @lock: whether to lock SF for PL access only
2857  *      @valp: where to store the read data
2858  *
2859  *      Reads up to 4 bytes of data from the serial flash.  The location of
2860  *      the read needs to be specified prior to calling this by issuing the
2861  *      appropriate commands to the serial flash.
2862  */
2863 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2864                     int lock, u32 *valp)
2865 {
2866         int ret;
2867
2868         if (!byte_cnt || byte_cnt > 4)
2869                 return -EINVAL;
2870         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2871                 return -EBUSY;
2872         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2873                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2874         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2875         if (!ret)
2876                 *valp = t4_read_reg(adapter, SF_DATA_A);
2877         return ret;
2878 }
2879
2880 /**
2881  *      sf1_write - write data to the serial flash
2882  *      @adapter: the adapter
2883  *      @byte_cnt: number of bytes to write
2884  *      @cont: whether another operation will be chained
2885  *      @lock: whether to lock SF for PL access only
2886  *      @val: value to write
2887  *
2888  *      Writes up to 4 bytes of data to the serial flash.  The location of
2889  *      the write needs to be specified prior to calling this by issuing the
2890  *      appropriate commands to the serial flash.
2891  */
2892 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2893                      int lock, u32 val)
2894 {
2895         if (!byte_cnt || byte_cnt > 4)
2896                 return -EINVAL;
2897         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2898                 return -EBUSY;
2899         t4_write_reg(adapter, SF_DATA_A, val);
2900         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2901                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2902         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2903 }
2904
2905 /**
2906  *      flash_wait_op - wait for a flash operation to complete
2907  *      @adapter: the adapter
2908  *      @attempts: max number of polls of the status register
2909  *      @delay: delay between polls in ms
2910  *
2911  *      Wait for a flash operation to complete by polling the status register.
2912  */
2913 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2914 {
2915         int ret;
2916         u32 status;
2917
2918         while (1) {
2919                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2920                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2921                         return ret;
2922                 if (!(status & 1))
2923                         return 0;
2924                 if (--attempts == 0)
2925                         return -EAGAIN;
2926                 if (delay)
2927                         msleep(delay);
2928         }
2929 }
2930
2931 /**
2932  *      t4_read_flash - read words from serial flash
2933  *      @adapter: the adapter
2934  *      @addr: the start address for the read
2935  *      @nwords: how many 32-bit words to read
2936  *      @data: where to store the read data
2937  *      @byte_oriented: whether to store data as bytes or as words
2938  *
2939  *      Read the specified number of 32-bit words from the serial flash.
2940  *      If @byte_oriented is set the read data is stored as a byte array
2941  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2942  *      natural endianness.
2943  */
2944 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2945                   unsigned int nwords, u32 *data, int byte_oriented)
2946 {
2947         int ret;
2948
2949         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2950                 return -EINVAL;
2951
2952         addr = swab32(addr) | SF_RD_DATA_FAST;
2953
2954         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2955             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2956                 return ret;
2957
2958         for ( ; nwords; nwords--, data++) {
2959                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2960                 if (nwords == 1)
2961                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2962                 if (ret)
2963                         return ret;
2964                 if (byte_oriented)
2965                         *data = (__force __u32)(cpu_to_be32(*data));
2966         }
2967         return 0;
2968 }
2969
2970 /**
2971  *      t4_write_flash - write up to a page of data to the serial flash
2972  *      @adapter: the adapter
2973  *      @addr: the start address to write
2974  *      @n: length of data to write in bytes
2975  *      @data: the data to write
2976  *
2977  *      Writes up to a page of data (256 bytes) to the serial flash starting
2978  *      at the given address.  All the data must be written to the same page.
2979  */
2980 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2981                           unsigned int n, const u8 *data)
2982 {
2983         int ret;
2984         u32 buf[64];
2985         unsigned int i, c, left, val, offset = addr & 0xff;
2986
2987         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2988                 return -EINVAL;
2989
2990         val = swab32(addr) | SF_PROG_PAGE;
2991
2992         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2993             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2994                 goto unlock;
2995
2996         for (left = n; left; left -= c) {
2997                 c = min(left, 4U);
2998                 for (val = 0, i = 0; i < c; ++i)
2999                         val = (val << 8) + *data++;
3000
3001                 ret = sf1_write(adapter, c, c != left, 1, val);
3002                 if (ret)
3003                         goto unlock;
3004         }
3005         ret = flash_wait_op(adapter, 8, 1);
3006         if (ret)
3007                 goto unlock;
3008
3009         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3010
3011         /* Read the page to verify the write succeeded */
3012         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3013         if (ret)
3014                 return ret;
3015
3016         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3017                 dev_err(adapter->pdev_dev,
3018                         "failed to correctly write the flash page at %#x\n",
3019                         addr);
3020                 return -EIO;
3021         }
3022         return 0;
3023
3024 unlock:
3025         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3026         return ret;
3027 }
3028
3029 /**
3030  *      t4_get_fw_version - read the firmware version
3031  *      @adapter: the adapter
3032  *      @vers: where to place the version
3033  *
3034  *      Reads the FW version from flash.
3035  */
3036 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3037 {
3038         return t4_read_flash(adapter, FLASH_FW_START +
3039                              offsetof(struct fw_hdr, fw_ver), 1,
3040                              vers, 0);
3041 }
3042
3043 /**
3044  *      t4_get_bs_version - read the firmware bootstrap version
3045  *      @adapter: the adapter
3046  *      @vers: where to place the version
3047  *
3048  *      Reads the FW Bootstrap version from flash.
3049  */
3050 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3051 {
3052         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3053                              offsetof(struct fw_hdr, fw_ver), 1,
3054                              vers, 0);
3055 }
3056
3057 /**
3058  *      t4_get_tp_version - read the TP microcode version
3059  *      @adapter: the adapter
3060  *      @vers: where to place the version
3061  *
3062  *      Reads the TP microcode version from flash.
3063  */
3064 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3065 {
3066         return t4_read_flash(adapter, FLASH_FW_START +
3067                              offsetof(struct fw_hdr, tp_microcode_ver),
3068                              1, vers, 0);
3069 }
3070
3071 /**
3072  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3073  *      @adapter: the adapter
3074  *      @vers: where to place the version
3075  *
3076  *      Reads the Expansion ROM header from FLASH and returns the version
3077  *      number (if present) through the @vers return value pointer.  We return
3078  *      this in the Firmware Version Format since it's convenient.  Return
3079  *      0 on success, -ENOENT if no Expansion ROM is present.
3080  */
3081 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3082 {
3083         struct exprom_header {
3084                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3085                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3086         } *hdr;
3087         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3088                                            sizeof(u32))];
3089         int ret;
3090
3091         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3092                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3093                             0);
3094         if (ret)
3095                 return ret;
3096
3097         hdr = (struct exprom_header *)exprom_header_buf;
3098         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3099                 return -ENOENT;
3100
3101         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3102                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3103                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3104                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3105         return 0;
3106 }
3107
3108 /**
3109  *      t4_get_vpd_version - return the VPD version
3110  *      @adapter: the adapter
3111  *      @vers: where to place the version
3112  *
3113  *      Reads the VPD via the Firmware interface (thus this can only be called
3114  *      once we're ready to issue Firmware commands).  The format of the
3115  *      VPD version is adapter specific.  Returns 0 on success, an error on
3116  *      failure.
3117  *
3118  *      Note that early versions of the Firmware didn't include the ability
3119  *      to retrieve the VPD version, so we zero-out the return-value parameter
3120  *      in that case to avoid leaving it with garbage in it.
3121  *
3122  *      Also note that the Firmware will return its cached copy of the VPD
3123  *      Revision ID, not the actual Revision ID as written in the Serial
3124  *      EEPROM.  This is only an issue if a new VPD has been written and the
3125  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3126  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3127  *      if the Host Driver will be performing a full adapter initialization.
3128  */
3129 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3130 {
3131         u32 vpdrev_param;
3132         int ret;
3133
3134         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3135                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3136         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3137                               1, &vpdrev_param, vers);
3138         if (ret)
3139                 *vers = 0;
3140         return ret;
3141 }
3142
3143 /**
3144  *      t4_get_scfg_version - return the Serial Configuration version
3145  *      @adapter: the adapter
3146  *      @vers: where to place the version
3147  *
3148  *      Reads the Serial Configuration Version via the Firmware interface
3149  *      (thus this can only be called once we're ready to issue Firmware
3150  *      commands).  The format of the Serial Configuration version is
3151  *      adapter specific.  Returns 0 on success, an error on failure.
3152  *
3153  *      Note that early versions of the Firmware didn't include the ability
3154  *      to retrieve the Serial Configuration version, so we zero-out the
3155  *      return-value parameter in that case to avoid leaving it with
3156  *      garbage in it.
3157  *
3158  *      Also note that the Firmware will return its cached copy of the Serial
3159  *      Initialization Revision ID, not the actual Revision ID as written in
3160  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3161  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3162  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3163  *      been issued if the Host Driver will be performing a full adapter
3164  *      initialization.
3165  */
3166 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3167 {
3168         u32 scfgrev_param;
3169         int ret;
3170
3171         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3172                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3173         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3174                               1, &scfgrev_param, vers);
3175         if (ret)
3176                 *vers = 0;
3177         return ret;
3178 }
3179
3180 /**
3181  *      t4_get_version_info - extract various chip/firmware version information
3182  *      @adapter: the adapter
3183  *
3184  *      Reads various chip/firmware version numbers and stores them into the
3185  *      adapter Adapter Parameters structure.  If any of the efforts fails
3186  *      the first failure will be returned, but all of the version numbers
3187  *      will be read.
3188  */
3189 int t4_get_version_info(struct adapter *adapter)
3190 {
3191         int ret = 0;
3192
3193         #define FIRST_RET(__getvinfo) \
3194         do { \
3195                 int __ret = __getvinfo; \
3196                 if (__ret && !ret) \
3197                         ret = __ret; \
3198         } while (0)
3199
3200         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3201         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3202         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3203         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3204         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3205         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3206
3207         #undef FIRST_RET
3208         return ret;
3209 }
3210
3211 /**
3212  *      t4_dump_version_info - dump all of the adapter configuration IDs
3213  *      @adapter: the adapter
3214  *
3215  *      Dumps all of the various bits of adapter configuration version/revision
3216  *      IDs information.  This is typically called at some point after
3217  *      t4_get_version_info() has been called.
3218  */
3219 void t4_dump_version_info(struct adapter *adapter)
3220 {
3221         /* Device information */
3222         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3223                  adapter->params.vpd.id,
3224                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3225         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3226                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3227
3228         /* Firmware Version */
3229         if (!adapter->params.fw_vers)
3230                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3231         else
3232                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3233                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3234                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3235                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3236                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3237
3238         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3239          * Firmware, so dev_info() is more appropriate here.)
3240          */
3241         if (!adapter->params.bs_vers)
3242                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3243         else
3244                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3245                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3246                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3247                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3248                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3249
3250         /* TP Microcode Version */
3251         if (!adapter->params.tp_vers)
3252                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3253         else
3254                 dev_info(adapter->pdev_dev,
3255                          "TP Microcode version: %u.%u.%u.%u\n",
3256                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3257                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3258                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3259                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3260
3261         /* Expansion ROM version */
3262         if (!adapter->params.er_vers)
3263                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3264         else
3265                 dev_info(adapter->pdev_dev,
3266                          "Expansion ROM version: %u.%u.%u.%u\n",
3267                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3268                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3269                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3270                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3271
3272         /* Serial Configuration version */
3273         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3274                  adapter->params.scfg_vers);
3275
3276         /* VPD Version */
3277         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3278                  adapter->params.vpd_vers);
3279 }
3280
3281 /**
3282  *      t4_check_fw_version - check if the FW is supported with this driver
3283  *      @adap: the adapter
3284  *
3285  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3286  *      if there's exact match, a negative error if the version could not be
3287  *      read or there's a major version mismatch
3288  */
3289 int t4_check_fw_version(struct adapter *adap)
3290 {
3291         int i, ret, major, minor, micro;
3292         int exp_major, exp_minor, exp_micro;
3293         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3294
3295         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3296         /* Try multiple times before returning error */
3297         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3298                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3299
3300         if (ret)
3301                 return ret;
3302
3303         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3304         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3305         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3306
3307         switch (chip_version) {
3308         case CHELSIO_T4:
3309                 exp_major = T4FW_MIN_VERSION_MAJOR;
3310                 exp_minor = T4FW_MIN_VERSION_MINOR;
3311                 exp_micro = T4FW_MIN_VERSION_MICRO;
3312                 break;
3313         case CHELSIO_T5:
3314                 exp_major = T5FW_MIN_VERSION_MAJOR;
3315                 exp_minor = T5FW_MIN_VERSION_MINOR;
3316                 exp_micro = T5FW_MIN_VERSION_MICRO;
3317                 break;
3318         case CHELSIO_T6:
3319                 exp_major = T6FW_MIN_VERSION_MAJOR;
3320                 exp_minor = T6FW_MIN_VERSION_MINOR;
3321                 exp_micro = T6FW_MIN_VERSION_MICRO;
3322                 break;
3323         default:
3324                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3325                         adap->chip);
3326                 return -EINVAL;
3327         }
3328
3329         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3330             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3331                 dev_err(adap->pdev_dev,
3332                         "Card has firmware version %u.%u.%u, minimum "
3333                         "supported firmware is %u.%u.%u.\n", major, minor,
3334                         micro, exp_major, exp_minor, exp_micro);
3335                 return -EFAULT;
3336         }
3337         return 0;
3338 }
3339
3340 /* Is the given firmware API compatible with the one the driver was compiled
3341  * with?
3342  */
3343 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3344 {
3345
3346         /* short circuit if it's the exact same firmware version */
3347         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3348                 return 1;
3349
3350 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3351         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3352             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3353                 return 1;
3354 #undef SAME_INTF
3355
3356         return 0;
3357 }
3358
3359 /* The firmware in the filesystem is usable, but should it be installed?
3360  * This routine explains itself in detail if it indicates the filesystem
3361  * firmware should be installed.
3362  */
3363 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3364                                 int k, int c)
3365 {
3366         const char *reason;
3367
3368         if (!card_fw_usable) {
3369                 reason = "incompatible or unusable";
3370                 goto install;
3371         }
3372
3373         if (k > c) {
3374                 reason = "older than the version supported with this driver";
3375                 goto install;
3376         }
3377
3378         return 0;
3379
3380 install:
3381         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3382                 "installing firmware %u.%u.%u.%u on card.\n",
3383                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3384                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3385                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3386                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3387
3388         return 1;
3389 }
3390
3391 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3392                const u8 *fw_data, unsigned int fw_size,
3393                struct fw_hdr *card_fw, enum dev_state state,
3394                int *reset)
3395 {
3396         int ret, card_fw_usable, fs_fw_usable;
3397         const struct fw_hdr *fs_fw;
3398         const struct fw_hdr *drv_fw;
3399
3400         drv_fw = &fw_info->fw_hdr;
3401
3402         /* Read the header of the firmware on the card */
3403         ret = -t4_read_flash(adap, FLASH_FW_START,
3404                             sizeof(*card_fw) / sizeof(uint32_t),
3405                             (uint32_t *)card_fw, 1);
3406         if (ret == 0) {
3407                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3408         } else {
3409                 dev_err(adap->pdev_dev,
3410                         "Unable to read card's firmware header: %d\n", ret);
3411                 card_fw_usable = 0;
3412         }
3413
3414         if (fw_data != NULL) {
3415                 fs_fw = (const void *)fw_data;
3416                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3417         } else {
3418                 fs_fw = NULL;
3419                 fs_fw_usable = 0;
3420         }
3421
3422         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3423             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3424                 /* Common case: the firmware on the card is an exact match and
3425                  * the filesystem one is an exact match too, or the filesystem
3426                  * one is absent/incompatible.
3427                  */
3428         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3429                    should_install_fs_fw(adap, card_fw_usable,
3430                                         be32_to_cpu(fs_fw->fw_ver),
3431                                         be32_to_cpu(card_fw->fw_ver))) {
3432                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3433                                      fw_size, 0);
3434                 if (ret != 0) {
3435                         dev_err(adap->pdev_dev,
3436                                 "failed to install firmware: %d\n", ret);
3437                         goto bye;
3438                 }
3439
3440                 /* Installed successfully, update the cached header too. */
3441                 *card_fw = *fs_fw;
3442                 card_fw_usable = 1;
3443                 *reset = 0;     /* already reset as part of load_fw */
3444         }
3445
3446         if (!card_fw_usable) {
3447                 uint32_t d, c, k;
3448
3449                 d = be32_to_cpu(drv_fw->fw_ver);
3450                 c = be32_to_cpu(card_fw->fw_ver);
3451                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3452
3453                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3454                         "chip state %d, "
3455                         "driver compiled with %d.%d.%d.%d, "
3456                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3457                         state,
3458                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3459                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3460                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3461                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3462                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3463                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3464                 ret = EINVAL;
3465                 goto bye;
3466         }
3467
3468         /* We're using whatever's on the card and it's known to be good. */
3469         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3470         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3471
3472 bye:
3473         return ret;
3474 }
3475
3476 /**
3477  *      t4_flash_erase_sectors - erase a range of flash sectors
3478  *      @adapter: the adapter
3479  *      @start: the first sector to erase
3480  *      @end: the last sector to erase
3481  *
3482  *      Erases the sectors in the given inclusive range.
3483  */
3484 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3485 {
3486         int ret = 0;
3487
3488         if (end >= adapter->params.sf_nsec)
3489                 return -EINVAL;
3490
3491         while (start <= end) {
3492                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3493                     (ret = sf1_write(adapter, 4, 0, 1,
3494                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3495                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3496                         dev_err(adapter->pdev_dev,
3497                                 "erase of flash sector %d failed, error %d\n",
3498                                 start, ret);
3499                         break;
3500                 }
3501                 start++;
3502         }
3503         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3504         return ret;
3505 }
3506
3507 /**
3508  *      t4_flash_cfg_addr - return the address of the flash configuration file
3509  *      @adapter: the adapter
3510  *
3511  *      Return the address within the flash where the Firmware Configuration
3512  *      File is stored.
3513  */
3514 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3515 {
3516         if (adapter->params.sf_size == 0x100000)
3517                 return FLASH_FPGA_CFG_START;
3518         else
3519                 return FLASH_CFG_START;
3520 }
3521
3522 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3523  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3524  * and emit an error message for mismatched firmware to save our caller the
3525  * effort ...
3526  */
3527 static bool t4_fw_matches_chip(const struct adapter *adap,
3528                                const struct fw_hdr *hdr)
3529 {
3530         /* The expression below will return FALSE for any unsupported adapter
3531          * which will keep us "honest" in the future ...
3532          */
3533         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3534             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3535             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3536                 return true;
3537
3538         dev_err(adap->pdev_dev,
3539                 "FW image (%d) is not suitable for this adapter (%d)\n",
3540                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3541         return false;
3542 }
3543
3544 /**
3545  *      t4_load_fw - download firmware
3546  *      @adap: the adapter
3547  *      @fw_data: the firmware image to write
3548  *      @size: image size
3549  *
3550  *      Write the supplied firmware image to the card's serial flash.
3551  */
3552 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3553 {
3554         u32 csum;
3555         int ret, addr;
3556         unsigned int i;
3557         u8 first_page[SF_PAGE_SIZE];
3558         const __be32 *p = (const __be32 *)fw_data;
3559         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3560         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3561         unsigned int fw_img_start = adap->params.sf_fw_start;
3562         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3563
3564         if (!size) {
3565                 dev_err(adap->pdev_dev, "FW image has no data\n");
3566                 return -EINVAL;
3567         }
3568         if (size & 511) {
3569                 dev_err(adap->pdev_dev,
3570                         "FW image size not multiple of 512 bytes\n");
3571                 return -EINVAL;
3572         }
3573         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3574                 dev_err(adap->pdev_dev,
3575                         "FW image size differs from size in FW header\n");
3576                 return -EINVAL;
3577         }
3578         if (size > FW_MAX_SIZE) {
3579                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3580                         FW_MAX_SIZE);
3581                 return -EFBIG;
3582         }
3583         if (!t4_fw_matches_chip(adap, hdr))
3584                 return -EINVAL;
3585
3586         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3587                 csum += be32_to_cpu(p[i]);
3588
3589         if (csum != 0xffffffff) {
3590                 dev_err(adap->pdev_dev,
3591                         "corrupted firmware image, checksum %#x\n", csum);
3592                 return -EINVAL;
3593         }
3594
3595         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3596         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3597         if (ret)
3598                 goto out;
3599
3600         /*
3601          * We write the correct version at the end so the driver can see a bad
3602          * version if the FW write fails.  Start by writing a copy of the
3603          * first page with a bad version.
3604          */
3605         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3606         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3607         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3608         if (ret)
3609                 goto out;
3610
3611         addr = fw_img_start;
3612         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3613                 addr += SF_PAGE_SIZE;
3614                 fw_data += SF_PAGE_SIZE;
3615                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3616                 if (ret)
3617                         goto out;
3618         }
3619
3620         ret = t4_write_flash(adap,
3621                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3622                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3623 out:
3624         if (ret)
3625                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3626                         ret);
3627         else
3628                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3629         return ret;
3630 }
3631
3632 /**
3633  *      t4_phy_fw_ver - return current PHY firmware version
3634  *      @adap: the adapter
3635  *      @phy_fw_ver: return value buffer for PHY firmware version
3636  *
3637  *      Returns the current version of external PHY firmware on the
3638  *      adapter.
3639  */
3640 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3641 {
3642         u32 param, val;
3643         int ret;
3644
3645         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3646                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3647                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3648                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3649         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3650                               &param, &val);
3651         if (ret < 0)
3652                 return ret;
3653         *phy_fw_ver = val;
3654         return 0;
3655 }
3656
3657 /**
3658  *      t4_load_phy_fw - download port PHY firmware
3659  *      @adap: the adapter
3660  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3661  *      @win_lock: the lock to use to guard the memory copy
3662  *      @phy_fw_version: function to check PHY firmware versions
3663  *      @phy_fw_data: the PHY firmware image to write
3664  *      @phy_fw_size: image size
3665  *
3666  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3667  *      @phy_fw_version is supplied, then it will be used to determine if
3668  *      it's necessary to perform the transfer by comparing the version
3669  *      of any existing adapter PHY firmware with that of the passed in
3670  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3671  *      around the call to t4_memory_rw() which transfers the PHY firmware
3672  *      to the adapter.
3673  *
3674  *      A negative error number will be returned if an error occurs.  If
3675  *      version number support is available and there's no need to upgrade
3676  *      the firmware, 0 will be returned.  If firmware is successfully
3677  *      transferred to the adapter, 1 will be retured.
3678  *
3679  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3680  *      a result, a RESET of the adapter would cause that RAM to lose its
3681  *      contents.  Thus, loading PHY firmware on such adapters must happen
3682  *      after any FW_RESET_CMDs ...
3683  */
3684 int t4_load_phy_fw(struct adapter *adap,
3685                    int win, spinlock_t *win_lock,
3686                    int (*phy_fw_version)(const u8 *, size_t),
3687                    const u8 *phy_fw_data, size_t phy_fw_size)
3688 {
3689         unsigned long mtype = 0, maddr = 0;
3690         u32 param, val;
3691         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3692         int ret;
3693
3694         /* If we have version number support, then check to see if the adapter
3695          * already has up-to-date PHY firmware loaded.
3696          */
3697          if (phy_fw_version) {
3698                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3699                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3700                 if (ret < 0)
3701                         return ret;
3702
3703                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3704                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3705                                 "version %#x\n", cur_phy_fw_ver);
3706                         return 0;
3707                 }
3708         }
3709
3710         /* Ask the firmware where it wants us to copy the PHY firmware image.
3711          * The size of the file requires a special version of the READ coommand
3712          * which will pass the file size via the values field in PARAMS_CMD and
3713          * retrieve the return value from firmware and place it in the same
3714          * buffer values
3715          */
3716         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3717                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3718                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3719                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3720         val = phy_fw_size;
3721         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3722                                  &param, &val, 1, true);
3723         if (ret < 0)
3724                 return ret;
3725         mtype = val >> 8;
3726         maddr = (val & 0xff) << 16;
3727
3728         /* Copy the supplied PHY Firmware image to the adapter memory location
3729          * allocated by the adapter firmware.
3730          */
3731         if (win_lock)
3732                 spin_lock_bh(win_lock);
3733         ret = t4_memory_rw(adap, win, mtype, maddr,
3734                            phy_fw_size, (__be32 *)phy_fw_data,
3735                            T4_MEMORY_WRITE);
3736         if (win_lock)
3737                 spin_unlock_bh(win_lock);
3738         if (ret)
3739                 return ret;
3740
3741         /* Tell the firmware that the PHY firmware image has been written to
3742          * RAM and it can now start copying it over to the PHYs.  The chip
3743          * firmware will RESET the affected PHYs as part of this operation
3744          * leaving them running the new PHY firmware image.
3745          */
3746         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3747                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3748                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3749                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3750         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3751                                     &param, &val, 30000);
3752
3753         /* If we have version number support, then check to see that the new
3754          * firmware got loaded properly.
3755          */
3756         if (phy_fw_version) {
3757                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3758                 if (ret < 0)
3759                         return ret;
3760
3761                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3762                         CH_WARN(adap, "PHY Firmware did not update: "
3763                                 "version on adapter %#x, "
3764                                 "version flashed %#x\n",
3765                                 cur_phy_fw_ver, new_phy_fw_vers);
3766                         return -ENXIO;
3767                 }
3768         }
3769
3770         return 1;
3771 }
3772
3773 /**
3774  *      t4_fwcache - firmware cache operation
3775  *      @adap: the adapter
3776  *      @op  : the operation (flush or flush and invalidate)
3777  */
3778 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3779 {
3780         struct fw_params_cmd c;
3781
3782         memset(&c, 0, sizeof(c));
3783         c.op_to_vfn =
3784                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3785                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3786                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3787                             FW_PARAMS_CMD_VFN_V(0));
3788         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3789         c.param[0].mnem =
3790                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3791                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3792         c.param[0].val = (__force __be32)op;
3793
3794         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3795 }
3796
3797 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3798                         unsigned int *pif_req_wrptr,
3799                         unsigned int *pif_rsp_wrptr)
3800 {
3801         int i, j;
3802         u32 cfg, val, req, rsp;
3803
3804         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3805         if (cfg & LADBGEN_F)
3806                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3807
3808         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3809         req = POLADBGWRPTR_G(val);
3810         rsp = PILADBGWRPTR_G(val);
3811         if (pif_req_wrptr)
3812                 *pif_req_wrptr = req;
3813         if (pif_rsp_wrptr)
3814                 *pif_rsp_wrptr = rsp;
3815
3816         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3817                 for (j = 0; j < 6; j++) {
3818                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3819                                      PILADBGRDPTR_V(rsp));
3820                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3821                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3822                         req++;
3823                         rsp++;
3824                 }
3825                 req = (req + 2) & POLADBGRDPTR_M;
3826                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3827         }
3828         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3829 }
3830
3831 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3832 {
3833         u32 cfg;
3834         int i, j, idx;
3835
3836         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3837         if (cfg & LADBGEN_F)
3838                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3839
3840         for (i = 0; i < CIM_MALA_SIZE; i++) {
3841                 for (j = 0; j < 5; j++) {
3842                         idx = 8 * i + j;
3843                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3844                                      PILADBGRDPTR_V(idx));
3845                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3846                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3847                 }
3848         }
3849         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3850 }
3851
3852 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3853 {
3854         unsigned int i, j;
3855
3856         for (i = 0; i < 8; i++) {
3857                 u32 *p = la_buf + i;
3858
3859                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3860                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3861                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3862                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3863                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3864         }
3865 }
3866
3867 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3868                      FW_PORT_CAP32_ANEG)
3869
3870 /**
3871  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3872  *      @caps16: a 16-bit Port Capabilities value
3873  *
3874  *      Returns the equivalent 32-bit Port Capabilities value.
3875  */
3876 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3877 {
3878         fw_port_cap32_t caps32 = 0;
3879
3880         #define CAP16_TO_CAP32(__cap) \
3881                 do { \
3882                         if (caps16 & FW_PORT_CAP_##__cap) \
3883                                 caps32 |= FW_PORT_CAP32_##__cap; \
3884                 } while (0)
3885
3886         CAP16_TO_CAP32(SPEED_100M);
3887         CAP16_TO_CAP32(SPEED_1G);
3888         CAP16_TO_CAP32(SPEED_25G);
3889         CAP16_TO_CAP32(SPEED_10G);
3890         CAP16_TO_CAP32(SPEED_40G);
3891         CAP16_TO_CAP32(SPEED_100G);
3892         CAP16_TO_CAP32(FC_RX);
3893         CAP16_TO_CAP32(FC_TX);
3894         CAP16_TO_CAP32(ANEG);
3895         CAP16_TO_CAP32(MDIX);
3896         CAP16_TO_CAP32(MDIAUTO);
3897         CAP16_TO_CAP32(FEC_RS);
3898         CAP16_TO_CAP32(FEC_BASER_RS);
3899         CAP16_TO_CAP32(802_3_PAUSE);
3900         CAP16_TO_CAP32(802_3_ASM_DIR);
3901
3902         #undef CAP16_TO_CAP32
3903
3904         return caps32;
3905 }
3906
3907 /**
3908  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3909  *      @caps32: a 32-bit Port Capabilities value
3910  *
3911  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
3912  *      not all 32-bit Port Capabilities can be represented in the 16-bit
3913  *      Port Capabilities and some fields/values may not make it.
3914  */
3915 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3916 {
3917         fw_port_cap16_t caps16 = 0;
3918
3919         #define CAP32_TO_CAP16(__cap) \
3920                 do { \
3921                         if (caps32 & FW_PORT_CAP32_##__cap) \
3922                                 caps16 |= FW_PORT_CAP_##__cap; \
3923                 } while (0)
3924
3925         CAP32_TO_CAP16(SPEED_100M);
3926         CAP32_TO_CAP16(SPEED_1G);
3927         CAP32_TO_CAP16(SPEED_10G);
3928         CAP32_TO_CAP16(SPEED_25G);
3929         CAP32_TO_CAP16(SPEED_40G);
3930         CAP32_TO_CAP16(SPEED_100G);
3931         CAP32_TO_CAP16(FC_RX);
3932         CAP32_TO_CAP16(FC_TX);
3933         CAP32_TO_CAP16(802_3_PAUSE);
3934         CAP32_TO_CAP16(802_3_ASM_DIR);
3935         CAP32_TO_CAP16(ANEG);
3936         CAP32_TO_CAP16(MDIX);
3937         CAP32_TO_CAP16(MDIAUTO);
3938         CAP32_TO_CAP16(FEC_RS);
3939         CAP32_TO_CAP16(FEC_BASER_RS);
3940
3941         #undef CAP32_TO_CAP16
3942
3943         return caps16;
3944 }
3945
3946 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3947 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
3948 {
3949         enum cc_pause cc_pause = 0;
3950
3951         if (fw_pause & FW_PORT_CAP32_FC_RX)
3952                 cc_pause |= PAUSE_RX;
3953         if (fw_pause & FW_PORT_CAP32_FC_TX)
3954                 cc_pause |= PAUSE_TX;
3955
3956         return cc_pause;
3957 }
3958
3959 /* Translate Common Code Pause specification into Firmware Port Capabilities */
3960 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
3961 {
3962         fw_port_cap32_t fw_pause = 0;
3963
3964         if (cc_pause & PAUSE_RX)
3965                 fw_pause |= FW_PORT_CAP32_FC_RX;
3966         if (cc_pause & PAUSE_TX)
3967                 fw_pause |= FW_PORT_CAP32_FC_TX;
3968
3969         return fw_pause;
3970 }
3971
3972 /* Translate Firmware Forward Error Correction specification to Common Code */
3973 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
3974 {
3975         enum cc_fec cc_fec = 0;
3976
3977         if (fw_fec & FW_PORT_CAP32_FEC_RS)
3978                 cc_fec |= FEC_RS;
3979         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
3980                 cc_fec |= FEC_BASER_RS;
3981
3982         return cc_fec;
3983 }
3984
3985 /* Translate Common Code Forward Error Correction specification to Firmware */
3986 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
3987 {
3988         fw_port_cap32_t fw_fec = 0;
3989
3990         if (cc_fec & FEC_RS)
3991                 fw_fec |= FW_PORT_CAP32_FEC_RS;
3992         if (cc_fec & FEC_BASER_RS)
3993                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
3994
3995         return fw_fec;
3996 }
3997
3998 /**
3999  *      t4_link_l1cfg - apply link configuration to MAC/PHY
4000  *      @adapter: the adapter
4001  *      @mbox: the Firmware Mailbox to use
4002  *      @port: the Port ID
4003  *      @lc: the Port's Link Configuration
4004  *
4005  *      Set up a port's MAC and PHY according to a desired link configuration.
4006  *      - If the PHY can auto-negotiate first decide what to advertise, then
4007  *        enable/disable auto-negotiation as desired, and reset.
4008  *      - If the PHY does not auto-negotiate just reset it.
4009  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4010  *        otherwise do it later based on the outcome of auto-negotiation.
4011  */
4012 int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
4013                   unsigned int port, struct link_config *lc)
4014 {
4015         unsigned int fw_caps = adapter->params.fw_caps_support;
4016         struct fw_port_cmd cmd;
4017         unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
4018         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
4019
4020         lc->link_ok = 0;
4021
4022         /* Convert driver coding of Pause Frame Flow Control settings into the
4023          * Firmware's API.
4024          */
4025         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4026
4027         /* Convert Common Code Forward Error Control settings into the
4028          * Firmware's API.  If the current Requested FEC has "Automatic"
4029          * (IEEE 802.3) specified, then we use whatever the Firmware
4030          * sent us as part of it's IEEE 802.3-based interpratation of
4031          * the Transceiver Module EPROM FEC parameters.  Otherwise we
4032          * use whatever is in the current Requested FEC settings.
4033          */
4034         if (lc->requested_fec & FEC_AUTO)
4035                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4036         else
4037                 cc_fec = lc->requested_fec;
4038         fw_fec = cc_to_fwcap_fec(cc_fec);
4039
4040         /* Figure out what our Requested Port Capabilities are going to be.
4041          */
4042         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4043                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
4044                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4045                 lc->fec = cc_fec;
4046         } else if (lc->autoneg == AUTONEG_DISABLE) {
4047                 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4048                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4049                 lc->fec = cc_fec;
4050         } else {
4051                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4052         }
4053
4054         /* And send that on to the Firmware ...
4055          */
4056         memset(&cmd, 0, sizeof(cmd));
4057         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4058                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4059                                        FW_PORT_CMD_PORTID_V(port));
4060         cmd.action_to_len16 =
4061                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4062                                                  ? FW_PORT_ACTION_L1_CFG
4063                                                  : FW_PORT_ACTION_L1_CFG32) |
4064                             FW_LEN16(cmd));
4065         if (fw_caps == FW_CAPS16)
4066                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4067         else
4068                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4069         return t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4070 }
4071
4072 /**
4073  *      t4_restart_aneg - restart autonegotiation
4074  *      @adap: the adapter
4075  *      @mbox: mbox to use for the FW command
4076  *      @port: the port id
4077  *
4078  *      Restarts autonegotiation for the selected port.
4079  */
4080 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4081 {
4082         struct fw_port_cmd c;
4083
4084         memset(&c, 0, sizeof(c));
4085         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4086                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4087                                      FW_PORT_CMD_PORTID_V(port));
4088         c.action_to_len16 =
4089                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4090                             FW_LEN16(c));
4091         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4092         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4093 }
4094
4095 typedef void (*int_handler_t)(struct adapter *adap);
4096
4097 struct intr_info {
4098         unsigned int mask;       /* bits to check in interrupt status */
4099         const char *msg;         /* message to print or NULL */
4100         short stat_idx;          /* stat counter to increment or -1 */
4101         unsigned short fatal;    /* whether the condition reported is fatal */
4102         int_handler_t int_handler; /* platform-specific int handler */
4103 };
4104
4105 /**
4106  *      t4_handle_intr_status - table driven interrupt handler
4107  *      @adapter: the adapter that generated the interrupt
4108  *      @reg: the interrupt status register to process
4109  *      @acts: table of interrupt actions
4110  *
4111  *      A table driven interrupt handler that applies a set of masks to an
4112  *      interrupt status word and performs the corresponding actions if the
4113  *      interrupts described by the mask have occurred.  The actions include
4114  *      optionally emitting a warning or alert message.  The table is terminated
4115  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4116  *      conditions.
4117  */
4118 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4119                                  const struct intr_info *acts)
4120 {
4121         int fatal = 0;
4122         unsigned int mask = 0;
4123         unsigned int status = t4_read_reg(adapter, reg);
4124
4125         for ( ; acts->mask; ++acts) {
4126                 if (!(status & acts->mask))
4127                         continue;
4128                 if (acts->fatal) {
4129                         fatal++;
4130                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4131                                   status & acts->mask);
4132                 } else if (acts->msg && printk_ratelimit())
4133                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4134                                  status & acts->mask);
4135                 if (acts->int_handler)
4136                         acts->int_handler(adapter);
4137                 mask |= acts->mask;
4138         }
4139         status &= mask;
4140         if (status)                           /* clear processed interrupts */
4141                 t4_write_reg(adapter, reg, status);
4142         return fatal;
4143 }
4144
4145 /*
4146  * Interrupt handler for the PCIE module.
4147  */
4148 static void pcie_intr_handler(struct adapter *adapter)
4149 {
4150         static const struct intr_info sysbus_intr_info[] = {
4151                 { RNPP_F, "RXNP array parity error", -1, 1 },
4152                 { RPCP_F, "RXPC array parity error", -1, 1 },
4153                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4154                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4155                 { RFTP_F, "RXFT array parity error", -1, 1 },
4156                 { 0 }
4157         };
4158         static const struct intr_info pcie_port_intr_info[] = {
4159                 { TPCP_F, "TXPC array parity error", -1, 1 },
4160                 { TNPP_F, "TXNP array parity error", -1, 1 },
4161                 { TFTP_F, "TXFT array parity error", -1, 1 },
4162                 { TCAP_F, "TXCA array parity error", -1, 1 },
4163                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4164                 { RCAP_F, "RXCA array parity error", -1, 1 },
4165                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4166                 { RDPE_F, "Rx data parity error", -1, 1 },
4167                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4168                 { 0 }
4169         };
4170         static const struct intr_info pcie_intr_info[] = {
4171                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4172                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4173                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4174                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4175                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4176                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4177                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4178                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4179                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4180                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4181                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4182                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4183                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4184                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4185                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4186                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4187                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4188                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4189                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4190                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4191                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4192                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4193                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4194                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4195                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4196                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4197                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4198                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4199                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4200                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4201                   -1, 0 },
4202                 { 0 }
4203         };
4204
4205         static struct intr_info t5_pcie_intr_info[] = {
4206                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4207                   -1, 1 },
4208                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4209                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4210                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4211                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4212                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4213                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4214                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4215                   -1, 1 },
4216                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4217                   -1, 1 },
4218                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4219                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4220                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4221                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4222                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4223                   -1, 1 },
4224                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4225                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4226                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4227                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4228                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4229                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4230                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4231                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4232                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4233                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4234                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4235                   -1, 1 },
4236                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4237                   -1, 1 },
4238                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4239                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4240                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4241                 { READRSPERR_F, "Outbound read error", -1, 0 },
4242                 { 0 }
4243         };
4244
4245         int fat;
4246
4247         if (is_t4(adapter->params.chip))
4248                 fat = t4_handle_intr_status(adapter,
4249                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4250                                 sysbus_intr_info) +
4251                         t4_handle_intr_status(adapter,
4252                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4253                                         pcie_port_intr_info) +
4254                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4255                                               pcie_intr_info);
4256         else
4257                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4258                                             t5_pcie_intr_info);
4259
4260         if (fat)
4261                 t4_fatal_err(adapter);
4262 }
4263
4264 /*
4265  * TP interrupt handler.
4266  */
4267 static void tp_intr_handler(struct adapter *adapter)
4268 {
4269         static const struct intr_info tp_intr_info[] = {
4270                 { 0x3fffffff, "TP parity error", -1, 1 },
4271                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4272                 { 0 }
4273         };
4274
4275         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4276                 t4_fatal_err(adapter);
4277 }
4278
4279 /*
4280  * SGE interrupt handler.
4281  */
4282 static void sge_intr_handler(struct adapter *adapter)
4283 {
4284         u64 v;
4285         u32 err;
4286
4287         static const struct intr_info sge_intr_info[] = {
4288                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4289                   "SGE received CPL exceeding IQE size", -1, 1 },
4290                 { ERR_INVALID_CIDX_INC_F,
4291                   "SGE GTS CIDX increment too large", -1, 0 },
4292                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4293                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4294                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4295                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4296                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4297                   0 },
4298                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4299                   0 },
4300                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4301                   0 },
4302                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4303                   0 },
4304                 { ERR_ING_CTXT_PRIO_F,
4305                   "SGE too many priority ingress contexts", -1, 0 },
4306                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4307                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4308                 { 0 }
4309         };
4310
4311         static struct intr_info t4t5_sge_intr_info[] = {
4312                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4313                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4314                 { ERR_EGR_CTXT_PRIO_F,
4315                   "SGE too many priority egress contexts", -1, 0 },
4316                 { 0 }
4317         };
4318
4319         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4320                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4321         if (v) {
4322                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4323                                 (unsigned long long)v);
4324                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4325                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4326         }
4327
4328         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4329         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4330                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4331                                            t4t5_sge_intr_info);
4332
4333         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4334         if (err & ERROR_QID_VALID_F) {
4335                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4336                         ERROR_QID_G(err));
4337                 if (err & UNCAPTURED_ERROR_F)
4338                         dev_err(adapter->pdev_dev,
4339                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4340                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4341                              UNCAPTURED_ERROR_F);
4342         }
4343
4344         if (v != 0)
4345                 t4_fatal_err(adapter);
4346 }
4347
4348 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4349                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4350 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4351                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4352
4353 /*
4354  * CIM interrupt handler.
4355  */
4356 static void cim_intr_handler(struct adapter *adapter)
4357 {
4358         static const struct intr_info cim_intr_info[] = {
4359                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4360                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4361                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4362                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4363                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4364                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4365                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4366                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4367                 { 0 }
4368         };
4369         static const struct intr_info cim_upintr_info[] = {
4370                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4371                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4372                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4373                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4374                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4375                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4376                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4377                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4378                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4379                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4380                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4381                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4382                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4383                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4384                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4385                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4386                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4387                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4388                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4389                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4390                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4391                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4392                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4393                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4394                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4395                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4396                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4397                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4398                 { 0 }
4399         };
4400
4401         u32 val, fw_err;
4402         int fat;
4403
4404         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4405         if (fw_err & PCIE_FW_ERR_F)
4406                 t4_report_fw_error(adapter);
4407
4408         /* When the Firmware detects an internal error which normally
4409          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4410          * in order to make sure the Host sees the Firmware Crash.  So
4411          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4412          * ignore the Timer0 interrupt.
4413          */
4414
4415         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4416         if (val & TIMER0INT_F)
4417                 if (!(fw_err & PCIE_FW_ERR_F) ||
4418                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4419                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4420                                      TIMER0INT_F);
4421
4422         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4423                                     cim_intr_info) +
4424               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4425                                     cim_upintr_info);
4426         if (fat)
4427                 t4_fatal_err(adapter);
4428 }
4429
4430 /*
4431  * ULP RX interrupt handler.
4432  */
4433 static void ulprx_intr_handler(struct adapter *adapter)
4434 {
4435         static const struct intr_info ulprx_intr_info[] = {
4436                 { 0x1800000, "ULPRX context error", -1, 1 },
4437                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4438                 { 0 }
4439         };
4440
4441         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4442                 t4_fatal_err(adapter);
4443 }
4444
4445 /*
4446  * ULP TX interrupt handler.
4447  */
4448 static void ulptx_intr_handler(struct adapter *adapter)
4449 {
4450         static const struct intr_info ulptx_intr_info[] = {
4451                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4452                   0 },
4453                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4454                   0 },
4455                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4456                   0 },
4457                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4458                   0 },
4459                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4460                 { 0 }
4461         };
4462
4463         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4464                 t4_fatal_err(adapter);
4465 }
4466
4467 /*
4468  * PM TX interrupt handler.
4469  */
4470 static void pmtx_intr_handler(struct adapter *adapter)
4471 {
4472         static const struct intr_info pmtx_intr_info[] = {
4473                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4474                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4475                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4476                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4477                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4478                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4479                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4480                   -1, 1 },
4481                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4482                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4483                 { 0 }
4484         };
4485
4486         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4487                 t4_fatal_err(adapter);
4488 }
4489
4490 /*
4491  * PM RX interrupt handler.
4492  */
4493 static void pmrx_intr_handler(struct adapter *adapter)
4494 {
4495         static const struct intr_info pmrx_intr_info[] = {
4496                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4497                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4498                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4499                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4500                   -1, 1 },
4501                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4502                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4503                 { 0 }
4504         };
4505
4506         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4507                 t4_fatal_err(adapter);
4508 }
4509
4510 /*
4511  * CPL switch interrupt handler.
4512  */
4513 static void cplsw_intr_handler(struct adapter *adapter)
4514 {
4515         static const struct intr_info cplsw_intr_info[] = {
4516                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4517                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4518                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4519                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4520                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4521                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4522                 { 0 }
4523         };
4524
4525         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4526                 t4_fatal_err(adapter);
4527 }
4528
4529 /*
4530  * LE interrupt handler.
4531  */
4532 static void le_intr_handler(struct adapter *adap)
4533 {
4534         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4535         static const struct intr_info le_intr_info[] = {
4536                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4537                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4538                 { PARITYERR_F, "LE parity error", -1, 1 },
4539                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4540                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4541                 { 0 }
4542         };
4543
4544         static struct intr_info t6_le_intr_info[] = {
4545                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4546                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4547                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4548                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4549                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4550                 { 0 }
4551         };
4552
4553         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4554                                   (chip <= CHELSIO_T5) ?
4555                                   le_intr_info : t6_le_intr_info))
4556                 t4_fatal_err(adap);
4557 }
4558
4559 /*
4560  * MPS interrupt handler.
4561  */
4562 static void mps_intr_handler(struct adapter *adapter)
4563 {
4564         static const struct intr_info mps_rx_intr_info[] = {
4565                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4566                 { 0 }
4567         };
4568         static const struct intr_info mps_tx_intr_info[] = {
4569                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4570                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4571                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4572                   -1, 1 },
4573                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4574                   -1, 1 },
4575                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4576                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4577                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4578                 { 0 }
4579         };
4580         static const struct intr_info t6_mps_tx_intr_info[] = {
4581                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4582                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4583                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4584                   -1, 1 },
4585                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4586                   -1, 1 },
4587                 /* MPS Tx Bubble is normal for T6 */
4588                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4589                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4590                 { 0 }
4591         };
4592         static const struct intr_info mps_trc_intr_info[] = {
4593                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4594                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4595                   -1, 1 },
4596                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4597                 { 0 }
4598         };
4599         static const struct intr_info mps_stat_sram_intr_info[] = {
4600                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4601                 { 0 }
4602         };
4603         static const struct intr_info mps_stat_tx_intr_info[] = {
4604                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4605                 { 0 }
4606         };
4607         static const struct intr_info mps_stat_rx_intr_info[] = {
4608                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4609                 { 0 }
4610         };
4611         static const struct intr_info mps_cls_intr_info[] = {
4612                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4613                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4614                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4615                 { 0 }
4616         };
4617
4618         int fat;
4619
4620         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4621                                     mps_rx_intr_info) +
4622               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4623                                     is_t6(adapter->params.chip)
4624                                     ? t6_mps_tx_intr_info
4625                                     : mps_tx_intr_info) +
4626               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4627                                     mps_trc_intr_info) +
4628               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4629                                     mps_stat_sram_intr_info) +
4630               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4631                                     mps_stat_tx_intr_info) +
4632               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4633                                     mps_stat_rx_intr_info) +
4634               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4635                                     mps_cls_intr_info);
4636
4637         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4638         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4639         if (fat)
4640                 t4_fatal_err(adapter);
4641 }
4642
4643 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4644                       ECC_UE_INT_CAUSE_F)
4645
4646 /*
4647  * EDC/MC interrupt handler.
4648  */
4649 static void mem_intr_handler(struct adapter *adapter, int idx)
4650 {
4651         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4652
4653         unsigned int addr, cnt_addr, v;
4654
4655         if (idx <= MEM_EDC1) {
4656                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4657                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4658         } else if (idx == MEM_MC) {
4659                 if (is_t4(adapter->params.chip)) {
4660                         addr = MC_INT_CAUSE_A;
4661                         cnt_addr = MC_ECC_STATUS_A;
4662                 } else {
4663                         addr = MC_P_INT_CAUSE_A;
4664                         cnt_addr = MC_P_ECC_STATUS_A;
4665                 }
4666         } else {
4667                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4668                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4669         }
4670
4671         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4672         if (v & PERR_INT_CAUSE_F)
4673                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4674                           name[idx]);
4675         if (v & ECC_CE_INT_CAUSE_F) {
4676                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4677
4678                 t4_edc_err_read(adapter, idx);
4679
4680                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4681                 if (printk_ratelimit())
4682                         dev_warn(adapter->pdev_dev,
4683                                  "%u %s correctable ECC data error%s\n",
4684                                  cnt, name[idx], cnt > 1 ? "s" : "");
4685         }
4686         if (v & ECC_UE_INT_CAUSE_F)
4687                 dev_alert(adapter->pdev_dev,
4688                           "%s uncorrectable ECC data error\n", name[idx]);
4689
4690         t4_write_reg(adapter, addr, v);
4691         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4692                 t4_fatal_err(adapter);
4693 }
4694
4695 /*
4696  * MA interrupt handler.
4697  */
4698 static void ma_intr_handler(struct adapter *adap)
4699 {
4700         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4701
4702         if (status & MEM_PERR_INT_CAUSE_F) {
4703                 dev_alert(adap->pdev_dev,
4704                           "MA parity error, parity status %#x\n",
4705                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4706                 if (is_t5(adap->params.chip))
4707                         dev_alert(adap->pdev_dev,
4708                                   "MA parity error, parity status %#x\n",
4709                                   t4_read_reg(adap,
4710                                               MA_PARITY_ERROR_STATUS2_A));
4711         }
4712         if (status & MEM_WRAP_INT_CAUSE_F) {
4713                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4714                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4715                           "client %u to address %#x\n",
4716                           MEM_WRAP_CLIENT_NUM_G(v),
4717                           MEM_WRAP_ADDRESS_G(v) << 4);
4718         }
4719         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4720         t4_fatal_err(adap);
4721 }
4722
4723 /*
4724  * SMB interrupt handler.
4725  */
4726 static void smb_intr_handler(struct adapter *adap)
4727 {
4728         static const struct intr_info smb_intr_info[] = {
4729                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4730                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4731                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4732                 { 0 }
4733         };
4734
4735         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4736                 t4_fatal_err(adap);
4737 }
4738
4739 /*
4740  * NC-SI interrupt handler.
4741  */
4742 static void ncsi_intr_handler(struct adapter *adap)
4743 {
4744         static const struct intr_info ncsi_intr_info[] = {
4745                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4746                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4747                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4748                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4749                 { 0 }
4750         };
4751
4752         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4753                 t4_fatal_err(adap);
4754 }
4755
4756 /*
4757  * XGMAC interrupt handler.
4758  */
4759 static void xgmac_intr_handler(struct adapter *adap, int port)
4760 {
4761         u32 v, int_cause_reg;
4762
4763         if (is_t4(adap->params.chip))
4764                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4765         else
4766                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4767
4768         v = t4_read_reg(adap, int_cause_reg);
4769
4770         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4771         if (!v)
4772                 return;
4773
4774         if (v & TXFIFO_PRTY_ERR_F)
4775                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4776                           port);
4777         if (v & RXFIFO_PRTY_ERR_F)
4778                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4779                           port);
4780         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4781         t4_fatal_err(adap);
4782 }
4783
4784 /*
4785  * PL interrupt handler.
4786  */
4787 static void pl_intr_handler(struct adapter *adap)
4788 {
4789         static const struct intr_info pl_intr_info[] = {
4790                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4791                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4792                 { 0 }
4793         };
4794
4795         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4796                 t4_fatal_err(adap);
4797 }
4798
4799 #define PF_INTR_MASK (PFSW_F)
4800 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4801                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4802                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4803
4804 /**
4805  *      t4_slow_intr_handler - control path interrupt handler
4806  *      @adapter: the adapter
4807  *
4808  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4809  *      The designation 'slow' is because it involves register reads, while
4810  *      data interrupts typically don't involve any MMIOs.
4811  */
4812 int t4_slow_intr_handler(struct adapter *adapter)
4813 {
4814         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4815
4816         if (!(cause & GLBL_INTR_MASK))
4817                 return 0;
4818         if (cause & CIM_F)
4819                 cim_intr_handler(adapter);
4820         if (cause & MPS_F)
4821                 mps_intr_handler(adapter);
4822         if (cause & NCSI_F)
4823                 ncsi_intr_handler(adapter);
4824         if (cause & PL_F)
4825                 pl_intr_handler(adapter);
4826         if (cause & SMB_F)
4827                 smb_intr_handler(adapter);
4828         if (cause & XGMAC0_F)
4829                 xgmac_intr_handler(adapter, 0);
4830         if (cause & XGMAC1_F)
4831                 xgmac_intr_handler(adapter, 1);
4832         if (cause & XGMAC_KR0_F)
4833                 xgmac_intr_handler(adapter, 2);
4834         if (cause & XGMAC_KR1_F)
4835                 xgmac_intr_handler(adapter, 3);
4836         if (cause & PCIE_F)
4837                 pcie_intr_handler(adapter);
4838         if (cause & MC_F)
4839                 mem_intr_handler(adapter, MEM_MC);
4840         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4841                 mem_intr_handler(adapter, MEM_MC1);
4842         if (cause & EDC0_F)
4843                 mem_intr_handler(adapter, MEM_EDC0);
4844         if (cause & EDC1_F)
4845                 mem_intr_handler(adapter, MEM_EDC1);
4846         if (cause & LE_F)
4847                 le_intr_handler(adapter);
4848         if (cause & TP_F)
4849                 tp_intr_handler(adapter);
4850         if (cause & MA_F)
4851                 ma_intr_handler(adapter);
4852         if (cause & PM_TX_F)
4853                 pmtx_intr_handler(adapter);
4854         if (cause & PM_RX_F)
4855                 pmrx_intr_handler(adapter);
4856         if (cause & ULP_RX_F)
4857                 ulprx_intr_handler(adapter);
4858         if (cause & CPL_SWITCH_F)
4859                 cplsw_intr_handler(adapter);
4860         if (cause & SGE_F)
4861                 sge_intr_handler(adapter);
4862         if (cause & ULP_TX_F)
4863                 ulptx_intr_handler(adapter);
4864
4865         /* Clear the interrupts just processed for which we are the master. */
4866         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4867         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4868         return 1;
4869 }
4870
4871 /**
4872  *      t4_intr_enable - enable interrupts
4873  *      @adapter: the adapter whose interrupts should be enabled
4874  *
4875  *      Enable PF-specific interrupts for the calling function and the top-level
4876  *      interrupt concentrator for global interrupts.  Interrupts are already
4877  *      enabled at each module, here we just enable the roots of the interrupt
4878  *      hierarchies.
4879  *
4880  *      Note: this function should be called only when the driver manages
4881  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4882  *      function at a time should be doing this.
4883  */
4884 void t4_intr_enable(struct adapter *adapter)
4885 {
4886         u32 val = 0;
4887         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4888         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4889                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4890
4891         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4892                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4893         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4894                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4895                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4896                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4897                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4898                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4899                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4900         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4901         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4902 }
4903
4904 /**
4905  *      t4_intr_disable - disable interrupts
4906  *      @adapter: the adapter whose interrupts should be disabled
4907  *
4908  *      Disable interrupts.  We only disable the top-level interrupt
4909  *      concentrators.  The caller must be a PCI function managing global
4910  *      interrupts.
4911  */
4912 void t4_intr_disable(struct adapter *adapter)
4913 {
4914         u32 whoami, pf;
4915
4916         if (pci_channel_offline(adapter->pdev))
4917                 return;
4918
4919         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4920         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4921                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4922
4923         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4924         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4925 }
4926
4927 /**
4928  *      t4_config_rss_range - configure a portion of the RSS mapping table
4929  *      @adapter: the adapter
4930  *      @mbox: mbox to use for the FW command
4931  *      @viid: virtual interface whose RSS subtable is to be written
4932  *      @start: start entry in the table to write
4933  *      @n: how many table entries to write
4934  *      @rspq: values for the response queue lookup table
4935  *      @nrspq: number of values in @rspq
4936  *
4937  *      Programs the selected part of the VI's RSS mapping table with the
4938  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4939  *      until the full table range is populated.
4940  *
4941  *      The caller must ensure the values in @rspq are in the range allowed for
4942  *      @viid.
4943  */
4944 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4945                         int start, int n, const u16 *rspq, unsigned int nrspq)
4946 {
4947         int ret;
4948         const u16 *rsp = rspq;
4949         const u16 *rsp_end = rspq + nrspq;
4950         struct fw_rss_ind_tbl_cmd cmd;
4951
4952         memset(&cmd, 0, sizeof(cmd));
4953         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4954                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4955                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4956         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4957
4958         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4959         while (n > 0) {
4960                 int nq = min(n, 32);
4961                 __be32 *qp = &cmd.iq0_to_iq2;
4962
4963                 cmd.niqid = cpu_to_be16(nq);
4964                 cmd.startidx = cpu_to_be16(start);
4965
4966                 start += nq;
4967                 n -= nq;
4968
4969                 while (nq > 0) {
4970                         unsigned int v;
4971
4972                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4973                         if (++rsp >= rsp_end)
4974                                 rsp = rspq;
4975                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4976                         if (++rsp >= rsp_end)
4977                                 rsp = rspq;
4978                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4979                         if (++rsp >= rsp_end)
4980                                 rsp = rspq;
4981
4982                         *qp++ = cpu_to_be32(v);
4983                         nq -= 3;
4984                 }
4985
4986                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4987                 if (ret)
4988                         return ret;
4989         }
4990         return 0;
4991 }
4992
4993 /**
4994  *      t4_config_glbl_rss - configure the global RSS mode
4995  *      @adapter: the adapter
4996  *      @mbox: mbox to use for the FW command
4997  *      @mode: global RSS mode
4998  *      @flags: mode-specific flags
4999  *
5000  *      Sets the global RSS mode.
5001  */
5002 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5003                        unsigned int flags)
5004 {
5005         struct fw_rss_glb_config_cmd c;
5006
5007         memset(&c, 0, sizeof(c));
5008         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5009                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5010         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5011         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5012                 c.u.manual.mode_pkd =
5013                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5014         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5015                 c.u.basicvirtual.mode_pkd =
5016                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5017                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5018         } else
5019                 return -EINVAL;
5020         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5021 }
5022
5023 /**
5024  *      t4_config_vi_rss - configure per VI RSS settings
5025  *      @adapter: the adapter
5026  *      @mbox: mbox to use for the FW command
5027  *      @viid: the VI id
5028  *      @flags: RSS flags
5029  *      @defq: id of the default RSS queue for the VI.
5030  *
5031  *      Configures VI-specific RSS properties.
5032  */
5033 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5034                      unsigned int flags, unsigned int defq)
5035 {
5036         struct fw_rss_vi_config_cmd c;
5037
5038         memset(&c, 0, sizeof(c));
5039         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5040                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5041                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5042         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5043         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5044                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5045         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5046 }
5047
5048 /* Read an RSS table row */
5049 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5050 {
5051         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5052         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5053                                    5, 0, val);
5054 }
5055
5056 /**
5057  *      t4_read_rss - read the contents of the RSS mapping table
5058  *      @adapter: the adapter
5059  *      @map: holds the contents of the RSS mapping table
5060  *
5061  *      Reads the contents of the RSS hash->queue mapping table.
5062  */
5063 int t4_read_rss(struct adapter *adapter, u16 *map)
5064 {
5065         u32 val;
5066         int i, ret;
5067
5068         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5069                 ret = rd_rss_row(adapter, i, &val);
5070                 if (ret)
5071                         return ret;
5072                 *map++ = LKPTBLQUEUE0_G(val);
5073                 *map++ = LKPTBLQUEUE1_G(val);
5074         }
5075         return 0;
5076 }
5077
5078 static unsigned int t4_use_ldst(struct adapter *adap)
5079 {
5080         return (adap->flags & FW_OK) || !adap->use_bd;
5081 }
5082
5083 /**
5084  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5085  * @adap: the adapter
5086  * @cmd: TP fw ldst address space type
5087  * @vals: where the indirect register values are stored/written
5088  * @nregs: how many indirect registers to read/write
5089  * @start_idx: index of first indirect register to read/write
5090  * @rw: Read (1) or Write (0)
5091  * @sleep_ok: if true we may sleep while awaiting command completion
5092  *
5093  * Access TP indirect registers through LDST
5094  */
5095 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5096                             unsigned int nregs, unsigned int start_index,
5097                             unsigned int rw, bool sleep_ok)
5098 {
5099         int ret = 0;
5100         unsigned int i;
5101         struct fw_ldst_cmd c;
5102
5103         for (i = 0; i < nregs; i++) {
5104                 memset(&c, 0, sizeof(c));
5105                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5106                                                 FW_CMD_REQUEST_F |
5107                                                 (rw ? FW_CMD_READ_F :
5108                                                       FW_CMD_WRITE_F) |
5109                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5110                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5111
5112                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5113                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5114                 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5115                                       sleep_ok);
5116                 if (ret)
5117                         return ret;
5118
5119                 if (rw)
5120                         vals[i] = be32_to_cpu(c.u.addrval.val);
5121         }
5122         return 0;
5123 }
5124
5125 /**
5126  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5127  * @adap: the adapter
5128  * @reg_addr: Address Register
5129  * @reg_data: Data register
5130  * @buff: where the indirect register values are stored/written
5131  * @nregs: how many indirect registers to read/write
5132  * @start_index: index of first indirect register to read/write
5133  * @rw: READ(1) or WRITE(0)
5134  * @sleep_ok: if true we may sleep while awaiting command completion
5135  *
5136  * Read/Write TP indirect registers through LDST if possible.
5137  * Else, use backdoor access
5138  **/
5139 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5140                               u32 *buff, u32 nregs, u32 start_index, int rw,
5141                               bool sleep_ok)
5142 {
5143         int rc = -EINVAL;
5144         int cmd;
5145
5146         switch (reg_addr) {
5147         case TP_PIO_ADDR_A:
5148                 cmd = FW_LDST_ADDRSPC_TP_PIO;
5149                 break;
5150         case TP_TM_PIO_ADDR_A:
5151                 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5152                 break;
5153         case TP_MIB_INDEX_A:
5154                 cmd = FW_LDST_ADDRSPC_TP_MIB;
5155                 break;
5156         default:
5157                 goto indirect_access;
5158         }
5159
5160         if (t4_use_ldst(adap))
5161                 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5162                                       sleep_ok);
5163
5164 indirect_access:
5165
5166         if (rc) {
5167                 if (rw)
5168                         t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5169                                          start_index);
5170                 else
5171                         t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5172                                           start_index);
5173         }
5174 }
5175
5176 /**
5177  * t4_tp_pio_read - Read TP PIO registers
5178  * @adap: the adapter
5179  * @buff: where the indirect register values are written
5180  * @nregs: how many indirect registers to read
5181  * @start_index: index of first indirect register to read
5182  * @sleep_ok: if true we may sleep while awaiting command completion
5183  *
5184  * Read TP PIO Registers
5185  **/
5186 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5187                     u32 start_index, bool sleep_ok)
5188 {
5189         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5190                           start_index, 1, sleep_ok);
5191 }
5192
5193 /**
5194  * t4_tp_pio_write - Write TP PIO registers
5195  * @adap: the adapter
5196  * @buff: where the indirect register values are stored
5197  * @nregs: how many indirect registers to write
5198  * @start_index: index of first indirect register to write
5199  * @sleep_ok: if true we may sleep while awaiting command completion
5200  *
5201  * Write TP PIO Registers
5202  **/
5203 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5204                             u32 start_index, bool sleep_ok)
5205 {
5206         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5207                           start_index, 0, sleep_ok);
5208 }
5209
5210 /**
5211  * t4_tp_tm_pio_read - Read TP TM PIO registers
5212  * @adap: the adapter
5213  * @buff: where the indirect register values are written
5214  * @nregs: how many indirect registers to read
5215  * @start_index: index of first indirect register to read
5216  * @sleep_ok: if true we may sleep while awaiting command completion
5217  *
5218  * Read TP TM PIO Registers
5219  **/
5220 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5221                        u32 start_index, bool sleep_ok)
5222 {
5223         t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5224                           nregs, start_index, 1, sleep_ok);
5225 }
5226
5227 /**
5228  * t4_tp_mib_read - Read TP MIB registers
5229  * @adap: the adapter
5230  * @buff: where the indirect register values are written
5231  * @nregs: how many indirect registers to read
5232  * @start_index: index of first indirect register to read
5233  * @sleep_ok: if true we may sleep while awaiting command completion
5234  *
5235  * Read TP MIB Registers
5236  **/
5237 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5238                     bool sleep_ok)
5239 {
5240         t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5241                           start_index, 1, sleep_ok);
5242 }
5243
5244 /**
5245  *      t4_read_rss_key - read the global RSS key
5246  *      @adap: the adapter
5247  *      @key: 10-entry array holding the 320-bit RSS key
5248  *      @sleep_ok: if true we may sleep while awaiting command completion
5249  *
5250  *      Reads the global 320-bit RSS key.
5251  */
5252 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5253 {
5254         t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5255 }
5256
5257 /**
5258  *      t4_write_rss_key - program one of the RSS keys
5259  *      @adap: the adapter
5260  *      @key: 10-entry array holding the 320-bit RSS key
5261  *      @idx: which RSS key to write
5262  *      @sleep_ok: if true we may sleep while awaiting command completion
5263  *
5264  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5265  *      0..15 the corresponding entry in the RSS key table is written,
5266  *      otherwise the global RSS key is written.
5267  */
5268 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5269                       bool sleep_ok)
5270 {
5271         u8 rss_key_addr_cnt = 16;
5272         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5273
5274         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5275          * allows access to key addresses 16-63 by using KeyWrAddrX
5276          * as index[5:4](upper 2) into key table
5277          */
5278         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5279             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5280                 rss_key_addr_cnt = 32;
5281
5282         t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5283
5284         if (idx >= 0 && idx < rss_key_addr_cnt) {
5285                 if (rss_key_addr_cnt > 16)
5286                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5287                                      KEYWRADDRX_V(idx >> 4) |
5288                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5289                 else
5290                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5291                                      KEYWRADDR_V(idx) | KEYWREN_F);
5292         }
5293 }
5294
5295 /**
5296  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5297  *      @adapter: the adapter
5298  *      @index: the entry in the PF RSS table to read
5299  *      @valp: where to store the returned value
5300  *      @sleep_ok: if true we may sleep while awaiting command completion
5301  *
5302  *      Reads the PF RSS Configuration Table at the specified index and returns
5303  *      the value found there.
5304  */
5305 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5306                            u32 *valp, bool sleep_ok)
5307 {
5308         t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5309 }
5310
5311 /**
5312  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5313  *      @adapter: the adapter
5314  *      @index: the entry in the VF RSS table to read
5315  *      @vfl: where to store the returned VFL
5316  *      @vfh: where to store the returned VFH
5317  *      @sleep_ok: if true we may sleep while awaiting command completion
5318  *
5319  *      Reads the VF RSS Configuration Table at the specified index and returns
5320  *      the (VFL, VFH) values found there.
5321  */
5322 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5323                            u32 *vfl, u32 *vfh, bool sleep_ok)
5324 {
5325         u32 vrt, mask, data;
5326
5327         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5328                 mask = VFWRADDR_V(VFWRADDR_M);
5329                 data = VFWRADDR_V(index);
5330         } else {
5331                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5332                  data = T6_VFWRADDR_V(index);
5333         }
5334
5335         /* Request that the index'th VF Table values be read into VFL/VFH.
5336          */
5337         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5338         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5339         vrt |= data | VFRDEN_F;
5340         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5341
5342         /* Grab the VFL/VFH values ...
5343          */
5344         t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5345         t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5346 }
5347
5348 /**
5349  *      t4_read_rss_pf_map - read PF RSS Map
5350  *      @adapter: the adapter
5351  *      @sleep_ok: if true we may sleep while awaiting command completion
5352  *
5353  *      Reads the PF RSS Map register and returns its value.
5354  */
5355 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5356 {
5357         u32 pfmap;
5358
5359         t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5360         return pfmap;
5361 }
5362
5363 /**
5364  *      t4_read_rss_pf_mask - read PF RSS Mask
5365  *      @adapter: the adapter
5366  *      @sleep_ok: if true we may sleep while awaiting command completion
5367  *
5368  *      Reads the PF RSS Mask register and returns its value.
5369  */
5370 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5371 {
5372         u32 pfmask;
5373
5374         t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5375         return pfmask;
5376 }
5377
5378 /**
5379  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5380  *      @adap: the adapter
5381  *      @v4: holds the TCP/IP counter values
5382  *      @v6: holds the TCP/IPv6 counter values
5383  *      @sleep_ok: if true we may sleep while awaiting command completion
5384  *
5385  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5386  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5387  */
5388 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5389                          struct tp_tcp_stats *v6, bool sleep_ok)
5390 {
5391         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5392
5393 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5394 #define STAT(x)     val[STAT_IDX(x)]
5395 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5396
5397         if (v4) {
5398                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5399                                TP_MIB_TCP_OUT_RST_A, sleep_ok);
5400                 v4->tcp_out_rsts = STAT(OUT_RST);
5401                 v4->tcp_in_segs  = STAT64(IN_SEG);
5402                 v4->tcp_out_segs = STAT64(OUT_SEG);
5403                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5404         }
5405         if (v6) {
5406                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5407                                TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5408                 v6->tcp_out_rsts = STAT(OUT_RST);
5409                 v6->tcp_in_segs  = STAT64(IN_SEG);
5410                 v6->tcp_out_segs = STAT64(OUT_SEG);
5411                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5412         }
5413 #undef STAT64
5414 #undef STAT
5415 #undef STAT_IDX
5416 }
5417
5418 /**
5419  *      t4_tp_get_err_stats - read TP's error MIB counters
5420  *      @adap: the adapter
5421  *      @st: holds the counter values
5422  *      @sleep_ok: if true we may sleep while awaiting command completion
5423  *
5424  *      Returns the values of TP's error counters.
5425  */
5426 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5427                          bool sleep_ok)
5428 {
5429         int nchan = adap->params.arch.nchan;
5430
5431         t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5432                        sleep_ok);
5433         t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5434                        sleep_ok);
5435         t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5436                        sleep_ok);
5437         t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5438                        TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5439         t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5440                        TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5441         t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5442                        sleep_ok);
5443         t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5444                        TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5445         t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5446                        TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5447         t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5448                        sleep_ok);
5449 }
5450
5451 /**
5452  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5453  *      @adap: the adapter
5454  *      @st: holds the counter values
5455  *      @sleep_ok: if true we may sleep while awaiting command completion
5456  *
5457  *      Returns the values of TP's CPL counters.
5458  */
5459 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5460                          bool sleep_ok)
5461 {
5462         int nchan = adap->params.arch.nchan;
5463
5464         t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5465
5466         t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5467 }
5468
5469 /**
5470  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5471  *      @adap: the adapter
5472  *      @st: holds the counter values
5473  *      @sleep_ok: if true we may sleep while awaiting command completion
5474  *
5475  *      Returns the values of TP's RDMA counters.
5476  */
5477 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5478                           bool sleep_ok)
5479 {
5480         t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5481                        sleep_ok);
5482 }
5483
5484 /**
5485  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5486  *      @adap: the adapter
5487  *      @idx: the port index
5488  *      @st: holds the counter values
5489  *      @sleep_ok: if true we may sleep while awaiting command completion
5490  *
5491  *      Returns the values of TP's FCoE counters for the selected port.
5492  */
5493 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5494                        struct tp_fcoe_stats *st, bool sleep_ok)
5495 {
5496         u32 val[2];
5497
5498         t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5499                        sleep_ok);
5500
5501         t4_tp_mib_read(adap, &st->frames_drop, 1,
5502                        TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5503
5504         t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5505                        sleep_ok);
5506
5507         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5508 }
5509
5510 /**
5511  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5512  *      @adap: the adapter
5513  *      @st: holds the counter values
5514  *      @sleep_ok: if true we may sleep while awaiting command completion
5515  *
5516  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5517  */
5518 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5519                       bool sleep_ok)
5520 {
5521         u32 val[4];
5522
5523         t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5524         st->frames = val[0];
5525         st->drops = val[1];
5526         st->octets = ((u64)val[2] << 32) | val[3];
5527 }
5528
5529 /**
5530  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5531  *      @adap: the adapter
5532  *      @mtus: where to store the MTU values
5533  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5534  *
5535  *      Reads the HW path MTU table.
5536  */
5537 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5538 {
5539         u32 v;
5540         int i;
5541
5542         for (i = 0; i < NMTUS; ++i) {
5543                 t4_write_reg(adap, TP_MTU_TABLE_A,
5544                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5545                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5546                 mtus[i] = MTUVALUE_G(v);
5547                 if (mtu_log)
5548                         mtu_log[i] = MTUWIDTH_G(v);
5549         }
5550 }
5551
5552 /**
5553  *      t4_read_cong_tbl - reads the congestion control table
5554  *      @adap: the adapter
5555  *      @incr: where to store the alpha values
5556  *
5557  *      Reads the additive increments programmed into the HW congestion
5558  *      control table.
5559  */
5560 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5561 {
5562         unsigned int mtu, w;
5563
5564         for (mtu = 0; mtu < NMTUS; ++mtu)
5565                 for (w = 0; w < NCCTRL_WIN; ++w) {
5566                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5567                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5568                         incr[mtu][w] = (u16)t4_read_reg(adap,
5569                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5570                 }
5571 }
5572
5573 /**
5574  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5575  *      @adap: the adapter
5576  *      @addr: the indirect TP register address
5577  *      @mask: specifies the field within the register to modify
5578  *      @val: new value for the field
5579  *
5580  *      Sets a field of an indirect TP register to the given value.
5581  */
5582 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5583                             unsigned int mask, unsigned int val)
5584 {
5585         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5586         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5587         t4_write_reg(adap, TP_PIO_DATA_A, val);
5588 }
5589
5590 /**
5591  *      init_cong_ctrl - initialize congestion control parameters
5592  *      @a: the alpha values for congestion control
5593  *      @b: the beta values for congestion control
5594  *
5595  *      Initialize the congestion control parameters.
5596  */
5597 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5598 {
5599         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5600         a[9] = 2;
5601         a[10] = 3;
5602         a[11] = 4;
5603         a[12] = 5;
5604         a[13] = 6;
5605         a[14] = 7;
5606         a[15] = 8;
5607         a[16] = 9;
5608         a[17] = 10;
5609         a[18] = 14;
5610         a[19] = 17;
5611         a[20] = 21;
5612         a[21] = 25;
5613         a[22] = 30;
5614         a[23] = 35;
5615         a[24] = 45;
5616         a[25] = 60;
5617         a[26] = 80;
5618         a[27] = 100;
5619         a[28] = 200;
5620         a[29] = 300;
5621         a[30] = 400;
5622         a[31] = 500;
5623
5624         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5625         b[9] = b[10] = 1;
5626         b[11] = b[12] = 2;
5627         b[13] = b[14] = b[15] = b[16] = 3;
5628         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5629         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5630         b[28] = b[29] = 6;
5631         b[30] = b[31] = 7;
5632 }
5633
5634 /* The minimum additive increment value for the congestion control table */
5635 #define CC_MIN_INCR 2U
5636
5637 /**
5638  *      t4_load_mtus - write the MTU and congestion control HW tables
5639  *      @adap: the adapter
5640  *      @mtus: the values for the MTU table
5641  *      @alpha: the values for the congestion control alpha parameter
5642  *      @beta: the values for the congestion control beta parameter
5643  *
5644  *      Write the HW MTU table with the supplied MTUs and the high-speed
5645  *      congestion control table with the supplied alpha, beta, and MTUs.
5646  *      We write the two tables together because the additive increments
5647  *      depend on the MTUs.
5648  */
5649 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5650                   const unsigned short *alpha, const unsigned short *beta)
5651 {
5652         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5653                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5654                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5655                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5656         };
5657
5658         unsigned int i, w;
5659
5660         for (i = 0; i < NMTUS; ++i) {
5661                 unsigned int mtu = mtus[i];
5662                 unsigned int log2 = fls(mtu);
5663
5664                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5665                         log2--;
5666                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5667                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5668
5669                 for (w = 0; w < NCCTRL_WIN; ++w) {
5670                         unsigned int inc;
5671
5672                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5673                                   CC_MIN_INCR);
5674
5675                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5676                                      (w << 16) | (beta[w] << 13) | inc);
5677                 }
5678         }
5679 }
5680
5681 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5682  * clocks.  The formula is
5683  *
5684  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5685  *
5686  * which is equivalent to
5687  *
5688  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5689  */
5690 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5691 {
5692         u64 v = bytes256 * adap->params.vpd.cclk;
5693
5694         return v * 62 + v / 2;
5695 }
5696
5697 /**
5698  *      t4_get_chan_txrate - get the current per channel Tx rates
5699  *      @adap: the adapter
5700  *      @nic_rate: rates for NIC traffic
5701  *      @ofld_rate: rates for offloaded traffic
5702  *
5703  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5704  *      for each channel.
5705  */
5706 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5707 {
5708         u32 v;
5709
5710         v = t4_read_reg(adap, TP_TX_TRATE_A);
5711         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5712         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5713         if (adap->params.arch.nchan == NCHAN) {
5714                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5715                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5716         }
5717
5718         v = t4_read_reg(adap, TP_TX_ORATE_A);
5719         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5720         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5721         if (adap->params.arch.nchan == NCHAN) {
5722                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5723                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5724         }
5725 }
5726
5727 /**
5728  *      t4_set_trace_filter - configure one of the tracing filters
5729  *      @adap: the adapter
5730  *      @tp: the desired trace filter parameters
5731  *      @idx: which filter to configure
5732  *      @enable: whether to enable or disable the filter
5733  *
5734  *      Configures one of the tracing filters available in HW.  If @enable is
5735  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5736  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5737  */
5738 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5739                         int idx, int enable)
5740 {
5741         int i, ofst = idx * 4;
5742         u32 data_reg, mask_reg, cfg;
5743         u32 multitrc = TRCMULTIFILTER_F;
5744
5745         if (!enable) {
5746                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5747                 return 0;
5748         }
5749
5750         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5751         if (cfg & TRCMULTIFILTER_F) {
5752                 /* If multiple tracers are enabled, then maximum
5753                  * capture size is 2.5KB (FIFO size of a single channel)
5754                  * minus 2 flits for CPL_TRACE_PKT header.
5755                  */
5756                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5757                         return -EINVAL;
5758         } else {
5759                 /* If multiple tracers are disabled, to avoid deadlocks
5760                  * maximum packet capture size of 9600 bytes is recommended.
5761                  * Also in this mode, only trace0 can be enabled and running.
5762                  */
5763                 multitrc = 0;
5764                 if (tp->snap_len > 9600 || idx)
5765                         return -EINVAL;
5766         }
5767
5768         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5769             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5770             tp->min_len > TFMINPKTSIZE_M)
5771                 return -EINVAL;
5772
5773         /* stop the tracer we'll be changing */
5774         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5775
5776         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5777         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5778         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5779
5780         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5781                 t4_write_reg(adap, data_reg, tp->data[i]);
5782                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5783         }
5784         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5785                      TFCAPTUREMAX_V(tp->snap_len) |
5786                      TFMINPKTSIZE_V(tp->min_len));
5787         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5788                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5789                      (is_t4(adap->params.chip) ?
5790                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5791                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5792                      T5_TFINVERTMATCH_V(tp->invert)));
5793
5794         return 0;
5795 }
5796
5797 /**
5798  *      t4_get_trace_filter - query one of the tracing filters
5799  *      @adap: the adapter
5800  *      @tp: the current trace filter parameters
5801  *      @idx: which trace filter to query
5802  *      @enabled: non-zero if the filter is enabled
5803  *
5804  *      Returns the current settings of one of the HW tracing filters.
5805  */
5806 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5807                          int *enabled)
5808 {
5809         u32 ctla, ctlb;
5810         int i, ofst = idx * 4;
5811         u32 data_reg, mask_reg;
5812
5813         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5814         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5815
5816         if (is_t4(adap->params.chip)) {
5817                 *enabled = !!(ctla & TFEN_F);
5818                 tp->port =  TFPORT_G(ctla);
5819                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5820         } else {
5821                 *enabled = !!(ctla & T5_TFEN_F);
5822                 tp->port = T5_TFPORT_G(ctla);
5823                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5824         }
5825         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5826         tp->min_len = TFMINPKTSIZE_G(ctlb);
5827         tp->skip_ofst = TFOFFSET_G(ctla);
5828         tp->skip_len = TFLENGTH_G(ctla);
5829
5830         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5831         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5832         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5833
5834         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5835                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5836                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5837         }
5838 }
5839
5840 /**
5841  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5842  *      @adap: the adapter
5843  *      @cnt: where to store the count statistics
5844  *      @cycles: where to store the cycle statistics
5845  *
5846  *      Returns performance statistics from PMTX.
5847  */
5848 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5849 {
5850         int i;
5851         u32 data[2];
5852
5853         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5854                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5855                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5856                 if (is_t4(adap->params.chip)) {
5857                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5858                 } else {
5859                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5860                                          PM_TX_DBG_DATA_A, data, 2,
5861                                          PM_TX_DBG_STAT_MSB_A);
5862                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5863                 }
5864         }
5865 }
5866
5867 /**
5868  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5869  *      @adap: the adapter
5870  *      @cnt: where to store the count statistics
5871  *      @cycles: where to store the cycle statistics
5872  *
5873  *      Returns performance statistics from PMRX.
5874  */
5875 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5876 {
5877         int i;
5878         u32 data[2];
5879
5880         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5881                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5882                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5883                 if (is_t4(adap->params.chip)) {
5884                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5885                 } else {
5886                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5887                                          PM_RX_DBG_DATA_A, data, 2,
5888                                          PM_RX_DBG_STAT_MSB_A);
5889                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5890                 }
5891         }
5892 }
5893
5894 /**
5895  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5896  *      @adap: the adapter
5897  *      @pidx: the port index
5898  *
5899  *      Computes and returns a bitmap indicating which MPS buffer groups are
5900  *      associated with the given Port.  Bit i is set if buffer group i is
5901  *      used by the Port.
5902  */
5903 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5904                                               int pidx)
5905 {
5906         unsigned int chip_version, nports;
5907
5908         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5909         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5910
5911         switch (chip_version) {
5912         case CHELSIO_T4:
5913         case CHELSIO_T5:
5914                 switch (nports) {
5915                 case 1: return 0xf;
5916                 case 2: return 3 << (2 * pidx);
5917                 case 4: return 1 << pidx;
5918                 }
5919                 break;
5920
5921         case CHELSIO_T6:
5922                 switch (nports) {
5923                 case 2: return 1 << (2 * pidx);
5924                 }
5925                 break;
5926         }
5927
5928         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5929                 chip_version, nports);
5930
5931         return 0;
5932 }
5933
5934 /**
5935  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5936  *      @adapter: the adapter
5937  *      @pidx: the port index
5938  *
5939  *      Returns a bitmap indicating which MPS buffer groups are associated
5940  *      with the given Port.  Bit i is set if buffer group i is used by the
5941  *      Port.
5942  */
5943 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
5944 {
5945         u8 *mps_bg_map;
5946         unsigned int nports;
5947
5948         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5949         if (pidx >= nports) {
5950                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
5951                         pidx, nports);
5952                 return 0;
5953         }
5954
5955         /* If we've already retrieved/computed this, just return the result.
5956          */
5957         mps_bg_map = adapter->params.mps_bg_map;
5958         if (mps_bg_map[pidx])
5959                 return mps_bg_map[pidx];
5960
5961         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
5962          * If we're talking to such Firmware, let it tell us.  If the new
5963          * API isn't supported, revert back to old hardcoded way.  The value
5964          * obtained from Firmware is encoded in below format:
5965          *
5966          * val = (( MPSBGMAP[Port 3] << 24 ) |
5967          *        ( MPSBGMAP[Port 2] << 16 ) |
5968          *        ( MPSBGMAP[Port 1] <<  8 ) |
5969          *        ( MPSBGMAP[Port 0] <<  0 ))
5970          */
5971         if (adapter->flags & FW_OK) {
5972                 u32 param, val;
5973                 int ret;
5974
5975                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5976                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
5977                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
5978                                          0, 1, &param, &val);
5979                 if (!ret) {
5980                         int p;
5981
5982                         /* Store the BG Map for all of the Ports in order to
5983                          * avoid more calls to the Firmware in the future.
5984                          */
5985                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
5986                                 mps_bg_map[p] = val & 0xff;
5987
5988                         return mps_bg_map[pidx];
5989                 }
5990         }
5991
5992         /* Either we're not talking to the Firmware or we're dealing with
5993          * older Firmware which doesn't support the new API to get the MPS
5994          * Buffer Group Map.  Fall back to computing it ourselves.
5995          */
5996         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
5997         return mps_bg_map[pidx];
5998 }
5999
6000 /**
6001  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
6002  *      @adapter: the adapter
6003  *      @pidx: the port index
6004  *
6005  *      Returns a bitmap indicating which TP Ingress Channels are associated
6006  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
6007  *      the Port.
6008  */
6009 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6010 {
6011         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6012         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6013
6014         if (pidx >= nports) {
6015                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6016                          pidx, nports);
6017                 return 0;
6018         }
6019
6020         switch (chip_version) {
6021         case CHELSIO_T4:
6022         case CHELSIO_T5:
6023                 /* Note that this happens to be the same values as the MPS
6024                  * Buffer Group Map for these Chips.  But we replicate the code
6025                  * here because they're really separate concepts.
6026                  */
6027                 switch (nports) {
6028                 case 1: return 0xf;
6029                 case 2: return 3 << (2 * pidx);
6030                 case 4: return 1 << pidx;
6031                 }
6032                 break;
6033
6034         case CHELSIO_T6:
6035                 switch (nports) {
6036                 case 2: return 1 << pidx;
6037                 }
6038                 break;
6039         }
6040
6041         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6042                 chip_version, nports);
6043         return 0;
6044 }
6045
6046 /**
6047  *      t4_get_port_type_description - return Port Type string description
6048  *      @port_type: firmware Port Type enumeration
6049  */
6050 const char *t4_get_port_type_description(enum fw_port_type port_type)
6051 {
6052         static const char *const port_type_description[] = {
6053                 "Fiber_XFI",
6054                 "Fiber_XAUI",
6055                 "BT_SGMII",
6056                 "BT_XFI",
6057                 "BT_XAUI",
6058                 "KX4",
6059                 "CX4",
6060                 "KX",
6061                 "KR",
6062                 "SFP",
6063                 "BP_AP",
6064                 "BP4_AP",
6065                 "QSFP_10G",
6066                 "QSA",
6067                 "QSFP",
6068                 "BP40_BA",
6069                 "KR4_100G",
6070                 "CR4_QSFP",
6071                 "CR_QSFP",
6072                 "CR2_QSFP",
6073                 "SFP28",
6074                 "KR_SFP28",
6075         };
6076
6077         if (port_type < ARRAY_SIZE(port_type_description))
6078                 return port_type_description[port_type];
6079         return "UNKNOWN";
6080 }
6081
6082 /**
6083  *      t4_get_port_stats_offset - collect port stats relative to a previous
6084  *                                 snapshot
6085  *      @adap: The adapter
6086  *      @idx: The port
6087  *      @stats: Current stats to fill
6088  *      @offset: Previous stats snapshot
6089  */
6090 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6091                               struct port_stats *stats,
6092                               struct port_stats *offset)
6093 {
6094         u64 *s, *o;
6095         int i;
6096
6097         t4_get_port_stats(adap, idx, stats);
6098         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6099                         i < (sizeof(struct port_stats) / sizeof(u64));
6100                         i++, s++, o++)
6101                 *s -= *o;
6102 }
6103
6104 /**
6105  *      t4_get_port_stats - collect port statistics
6106  *      @adap: the adapter
6107  *      @idx: the port index
6108  *      @p: the stats structure to fill
6109  *
6110  *      Collect statistics related to the given port from HW.
6111  */
6112 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6113 {
6114         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6115         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6116
6117 #define GET_STAT(name) \
6118         t4_read_reg64(adap, \
6119         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6120         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6121 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6122
6123         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
6124         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
6125         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
6126         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
6127         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
6128         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
6129         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
6130         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
6131         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
6132         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
6133         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
6134         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6135         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
6136         p->tx_drop             = GET_STAT(TX_PORT_DROP);
6137         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
6138         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
6139         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
6140         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
6141         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
6142         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
6143         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6144         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6145         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6146
6147         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6148                 if (stat_ctl & COUNTPAUSESTATTX_F)
6149                         p->tx_frames_64 -= p->tx_pause;
6150                 if (stat_ctl & COUNTPAUSEMCTX_F)
6151                         p->tx_mcast_frames -= p->tx_pause;
6152         }
6153         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6154         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6155         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6156         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6157         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6158         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6159         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6160         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6161         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6162         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6163         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6164         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6165         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6166         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6167         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6168         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6169         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6170         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6171         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6172         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6173         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6174         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6175         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6176         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6177         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6178         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6179         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6180
6181         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6182                 if (stat_ctl & COUNTPAUSESTATRX_F)
6183                         p->rx_frames_64 -= p->rx_pause;
6184                 if (stat_ctl & COUNTPAUSEMCRX_F)
6185                         p->rx_mcast_frames -= p->rx_pause;
6186         }
6187
6188         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6189         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6190         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6191         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6192         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6193         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6194         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6195         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6196
6197 #undef GET_STAT
6198 #undef GET_STAT_COM
6199 }
6200
6201 /**
6202  *      t4_get_lb_stats - collect loopback port statistics
6203  *      @adap: the adapter
6204  *      @idx: the loopback port index
6205  *      @p: the stats structure to fill
6206  *
6207  *      Return HW statistics for the given loopback port.
6208  */
6209 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6210 {
6211         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6212
6213 #define GET_STAT(name) \
6214         t4_read_reg64(adap, \
6215         (is_t4(adap->params.chip) ? \
6216         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6217         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6218 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6219
6220         p->octets           = GET_STAT(BYTES);
6221         p->frames           = GET_STAT(FRAMES);
6222         p->bcast_frames     = GET_STAT(BCAST);
6223         p->mcast_frames     = GET_STAT(MCAST);
6224         p->ucast_frames     = GET_STAT(UCAST);
6225         p->error_frames     = GET_STAT(ERROR);
6226
6227         p->frames_64        = GET_STAT(64B);
6228         p->frames_65_127    = GET_STAT(65B_127B);
6229         p->frames_128_255   = GET_STAT(128B_255B);
6230         p->frames_256_511   = GET_STAT(256B_511B);
6231         p->frames_512_1023  = GET_STAT(512B_1023B);
6232         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6233         p->frames_1519_max  = GET_STAT(1519B_MAX);
6234         p->drop             = GET_STAT(DROP_FRAMES);
6235
6236         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6237         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6238         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6239         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6240         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6241         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6242         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6243         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6244
6245 #undef GET_STAT
6246 #undef GET_STAT_COM
6247 }
6248
6249 /*     t4_mk_filtdelwr - create a delete filter WR
6250  *     @ftid: the filter ID
6251  *     @wr: the filter work request to populate
6252  *     @qid: ingress queue to receive the delete notification
6253  *
6254  *     Creates a filter work request to delete the supplied filter.  If @qid is
6255  *     negative the delete notification is suppressed.
6256  */
6257 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6258 {
6259         memset(wr, 0, sizeof(*wr));
6260         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6261         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6262         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6263                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6264         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6265         if (qid >= 0)
6266                 wr->rx_chan_rx_rpl_iq =
6267                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6268 }
6269
6270 #define INIT_CMD(var, cmd, rd_wr) do { \
6271         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6272                                         FW_CMD_REQUEST_F | \
6273                                         FW_CMD_##rd_wr##_F); \
6274         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6275 } while (0)
6276
6277 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6278                           u32 addr, u32 val)
6279 {
6280         u32 ldst_addrspace;
6281         struct fw_ldst_cmd c;
6282
6283         memset(&c, 0, sizeof(c));
6284         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6285         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6286                                         FW_CMD_REQUEST_F |
6287                                         FW_CMD_WRITE_F |
6288                                         ldst_addrspace);
6289         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6290         c.u.addrval.addr = cpu_to_be32(addr);
6291         c.u.addrval.val = cpu_to_be32(val);
6292
6293         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6294 }
6295
6296 /**
6297  *      t4_mdio_rd - read a PHY register through MDIO
6298  *      @adap: the adapter
6299  *      @mbox: mailbox to use for the FW command
6300  *      @phy_addr: the PHY address
6301  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6302  *      @reg: the register to read
6303  *      @valp: where to store the value
6304  *
6305  *      Issues a FW command through the given mailbox to read a PHY register.
6306  */
6307 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6308                unsigned int mmd, unsigned int reg, u16 *valp)
6309 {
6310         int ret;
6311         u32 ldst_addrspace;
6312         struct fw_ldst_cmd c;
6313
6314         memset(&c, 0, sizeof(c));
6315         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6316         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6317                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6318                                         ldst_addrspace);
6319         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6320         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6321                                          FW_LDST_CMD_MMD_V(mmd));
6322         c.u.mdio.raddr = cpu_to_be16(reg);
6323
6324         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6325         if (ret == 0)
6326                 *valp = be16_to_cpu(c.u.mdio.rval);
6327         return ret;
6328 }
6329
6330 /**
6331  *      t4_mdio_wr - write a PHY register through MDIO
6332  *      @adap: the adapter
6333  *      @mbox: mailbox to use for the FW command
6334  *      @phy_addr: the PHY address
6335  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6336  *      @reg: the register to write
6337  *      @valp: value to write
6338  *
6339  *      Issues a FW command through the given mailbox to write a PHY register.
6340  */
6341 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6342                unsigned int mmd, unsigned int reg, u16 val)
6343 {
6344         u32 ldst_addrspace;
6345         struct fw_ldst_cmd c;
6346
6347         memset(&c, 0, sizeof(c));
6348         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6349         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6350                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6351                                         ldst_addrspace);
6352         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6353         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6354                                          FW_LDST_CMD_MMD_V(mmd));
6355         c.u.mdio.raddr = cpu_to_be16(reg);
6356         c.u.mdio.rval = cpu_to_be16(val);
6357
6358         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6359 }
6360
6361 /**
6362  *      t4_sge_decode_idma_state - decode the idma state
6363  *      @adap: the adapter
6364  *      @state: the state idma is stuck in
6365  */
6366 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6367 {
6368         static const char * const t4_decode[] = {
6369                 "IDMA_IDLE",
6370                 "IDMA_PUSH_MORE_CPL_FIFO",
6371                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6372                 "Not used",
6373                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6374                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6375                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6376                 "IDMA_SEND_FIFO_TO_IMSG",
6377                 "IDMA_FL_REQ_DATA_FL_PREP",
6378                 "IDMA_FL_REQ_DATA_FL",
6379                 "IDMA_FL_DROP",
6380                 "IDMA_FL_H_REQ_HEADER_FL",
6381                 "IDMA_FL_H_SEND_PCIEHDR",
6382                 "IDMA_FL_H_PUSH_CPL_FIFO",
6383                 "IDMA_FL_H_SEND_CPL",
6384                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6385                 "IDMA_FL_H_SEND_IP_HDR",
6386                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6387                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6388                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6389                 "IDMA_FL_D_SEND_PCIEHDR",
6390                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6391                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6392                 "IDMA_FL_SEND_PCIEHDR",
6393                 "IDMA_FL_PUSH_CPL_FIFO",
6394                 "IDMA_FL_SEND_CPL",
6395                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6396                 "IDMA_FL_SEND_PAYLOAD",
6397                 "IDMA_FL_REQ_NEXT_DATA_FL",
6398                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6399                 "IDMA_FL_SEND_PADDING",
6400                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6401                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6402                 "IDMA_FL_REQ_DATAFL_DONE",
6403                 "IDMA_FL_REQ_HEADERFL_DONE",
6404         };
6405         static const char * const t5_decode[] = {
6406                 "IDMA_IDLE",
6407                 "IDMA_ALMOST_IDLE",
6408                 "IDMA_PUSH_MORE_CPL_FIFO",
6409                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6410                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6411                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6412                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6413                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6414                 "IDMA_SEND_FIFO_TO_IMSG",
6415                 "IDMA_FL_REQ_DATA_FL",
6416                 "IDMA_FL_DROP",
6417                 "IDMA_FL_DROP_SEND_INC",
6418                 "IDMA_FL_H_REQ_HEADER_FL",
6419                 "IDMA_FL_H_SEND_PCIEHDR",
6420                 "IDMA_FL_H_PUSH_CPL_FIFO",
6421                 "IDMA_FL_H_SEND_CPL",
6422                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6423                 "IDMA_FL_H_SEND_IP_HDR",
6424                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6425                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6426                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6427                 "IDMA_FL_D_SEND_PCIEHDR",
6428                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6429                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6430                 "IDMA_FL_SEND_PCIEHDR",
6431                 "IDMA_FL_PUSH_CPL_FIFO",
6432                 "IDMA_FL_SEND_CPL",
6433                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6434                 "IDMA_FL_SEND_PAYLOAD",
6435                 "IDMA_FL_REQ_NEXT_DATA_FL",
6436                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6437                 "IDMA_FL_SEND_PADDING",
6438                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6439         };
6440         static const char * const t6_decode[] = {
6441                 "IDMA_IDLE",
6442                 "IDMA_PUSH_MORE_CPL_FIFO",
6443                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6444                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6445                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6446                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6447                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6448                 "IDMA_FL_REQ_DATA_FL",
6449                 "IDMA_FL_DROP",
6450                 "IDMA_FL_DROP_SEND_INC",
6451                 "IDMA_FL_H_REQ_HEADER_FL",
6452                 "IDMA_FL_H_SEND_PCIEHDR",
6453                 "IDMA_FL_H_PUSH_CPL_FIFO",
6454                 "IDMA_FL_H_SEND_CPL",
6455                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6456                 "IDMA_FL_H_SEND_IP_HDR",
6457                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6458                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6459                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6460                 "IDMA_FL_D_SEND_PCIEHDR",
6461                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6462                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6463                 "IDMA_FL_SEND_PCIEHDR",
6464                 "IDMA_FL_PUSH_CPL_FIFO",
6465                 "IDMA_FL_SEND_CPL",
6466                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6467                 "IDMA_FL_SEND_PAYLOAD",
6468                 "IDMA_FL_REQ_NEXT_DATA_FL",
6469                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6470                 "IDMA_FL_SEND_PADDING",
6471                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6472         };
6473         static const u32 sge_regs[] = {
6474                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6475                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6476                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6477         };
6478         const char **sge_idma_decode;
6479         int sge_idma_decode_nstates;
6480         int i;
6481         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6482
6483         /* Select the right set of decode strings to dump depending on the
6484          * adapter chip type.
6485          */
6486         switch (chip_version) {
6487         case CHELSIO_T4:
6488                 sge_idma_decode = (const char **)t4_decode;
6489                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6490                 break;
6491
6492         case CHELSIO_T5:
6493                 sge_idma_decode = (const char **)t5_decode;
6494                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6495                 break;
6496
6497         case CHELSIO_T6:
6498                 sge_idma_decode = (const char **)t6_decode;
6499                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6500                 break;
6501
6502         default:
6503                 dev_err(adapter->pdev_dev,
6504                         "Unsupported chip version %d\n", chip_version);
6505                 return;
6506         }
6507
6508         if (is_t4(adapter->params.chip)) {
6509                 sge_idma_decode = (const char **)t4_decode;
6510                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6511         } else {
6512                 sge_idma_decode = (const char **)t5_decode;
6513                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6514         }
6515
6516         if (state < sge_idma_decode_nstates)
6517                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6518         else
6519                 CH_WARN(adapter, "idma state %d unknown\n", state);
6520
6521         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6522                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6523                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6524 }
6525
6526 /**
6527  *      t4_sge_ctxt_flush - flush the SGE context cache
6528  *      @adap: the adapter
6529  *      @mbox: mailbox to use for the FW command
6530  *
6531  *      Issues a FW command through the given mailbox to flush the
6532  *      SGE context cache.
6533  */
6534 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6535 {
6536         int ret;
6537         u32 ldst_addrspace;
6538         struct fw_ldst_cmd c;
6539
6540         memset(&c, 0, sizeof(c));
6541         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
6542         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6543                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6544                                         ldst_addrspace);
6545         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6546         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6547
6548         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6549         return ret;
6550 }
6551
6552 /**
6553  *      t4_fw_hello - establish communication with FW
6554  *      @adap: the adapter
6555  *      @mbox: mailbox to use for the FW command
6556  *      @evt_mbox: mailbox to receive async FW events
6557  *      @master: specifies the caller's willingness to be the device master
6558  *      @state: returns the current device state (if non-NULL)
6559  *
6560  *      Issues a command to establish communication with FW.  Returns either
6561  *      an error (negative integer) or the mailbox of the Master PF.
6562  */
6563 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6564                 enum dev_master master, enum dev_state *state)
6565 {
6566         int ret;
6567         struct fw_hello_cmd c;
6568         u32 v;
6569         unsigned int master_mbox;
6570         int retries = FW_CMD_HELLO_RETRIES;
6571
6572 retry:
6573         memset(&c, 0, sizeof(c));
6574         INIT_CMD(c, HELLO, WRITE);
6575         c.err_to_clearinit = cpu_to_be32(
6576                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6577                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6578                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6579                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6580                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6581                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6582                 FW_HELLO_CMD_CLEARINIT_F);
6583
6584         /*
6585          * Issue the HELLO command to the firmware.  If it's not successful
6586          * but indicates that we got a "busy" or "timeout" condition, retry
6587          * the HELLO until we exhaust our retry limit.  If we do exceed our
6588          * retry limit, check to see if the firmware left us any error
6589          * information and report that if so.
6590          */
6591         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6592         if (ret < 0) {
6593                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6594                         goto retry;
6595                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6596                         t4_report_fw_error(adap);
6597                 return ret;
6598         }
6599
6600         v = be32_to_cpu(c.err_to_clearinit);
6601         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6602         if (state) {
6603                 if (v & FW_HELLO_CMD_ERR_F)
6604                         *state = DEV_STATE_ERR;
6605                 else if (v & FW_HELLO_CMD_INIT_F)
6606                         *state = DEV_STATE_INIT;
6607                 else
6608                         *state = DEV_STATE_UNINIT;
6609         }
6610
6611         /*
6612          * If we're not the Master PF then we need to wait around for the
6613          * Master PF Driver to finish setting up the adapter.
6614          *
6615          * Note that we also do this wait if we're a non-Master-capable PF and
6616          * there is no current Master PF; a Master PF may show up momentarily
6617          * and we wouldn't want to fail pointlessly.  (This can happen when an
6618          * OS loads lots of different drivers rapidly at the same time).  In
6619          * this case, the Master PF returned by the firmware will be
6620          * PCIE_FW_MASTER_M so the test below will work ...
6621          */
6622         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6623             master_mbox != mbox) {
6624                 int waiting = FW_CMD_HELLO_TIMEOUT;
6625
6626                 /*
6627                  * Wait for the firmware to either indicate an error or
6628                  * initialized state.  If we see either of these we bail out
6629                  * and report the issue to the caller.  If we exhaust the
6630                  * "hello timeout" and we haven't exhausted our retries, try
6631                  * again.  Otherwise bail with a timeout error.
6632                  */
6633                 for (;;) {
6634                         u32 pcie_fw;
6635
6636                         msleep(50);
6637                         waiting -= 50;
6638
6639                         /*
6640                          * If neither Error nor Initialialized are indicated
6641                          * by the firmware keep waiting till we exaust our
6642                          * timeout ... and then retry if we haven't exhausted
6643                          * our retries ...
6644                          */
6645                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6646                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6647                                 if (waiting <= 0) {
6648                                         if (retries-- > 0)
6649                                                 goto retry;
6650
6651                                         return -ETIMEDOUT;
6652                                 }
6653                                 continue;
6654                         }
6655
6656                         /*
6657                          * We either have an Error or Initialized condition
6658                          * report errors preferentially.
6659                          */
6660                         if (state) {
6661                                 if (pcie_fw & PCIE_FW_ERR_F)
6662                                         *state = DEV_STATE_ERR;
6663                                 else if (pcie_fw & PCIE_FW_INIT_F)
6664                                         *state = DEV_STATE_INIT;
6665                         }
6666
6667                         /*
6668                          * If we arrived before a Master PF was selected and
6669                          * there's not a valid Master PF, grab its identity
6670                          * for our caller.
6671                          */
6672                         if (master_mbox == PCIE_FW_MASTER_M &&
6673                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6674                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6675                         break;
6676                 }
6677         }
6678
6679         return master_mbox;
6680 }
6681
6682 /**
6683  *      t4_fw_bye - end communication with FW
6684  *      @adap: the adapter
6685  *      @mbox: mailbox to use for the FW command
6686  *
6687  *      Issues a command to terminate communication with FW.
6688  */
6689 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6690 {
6691         struct fw_bye_cmd c;
6692
6693         memset(&c, 0, sizeof(c));
6694         INIT_CMD(c, BYE, WRITE);
6695         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6696 }
6697
6698 /**
6699  *      t4_init_cmd - ask FW to initialize the device
6700  *      @adap: the adapter
6701  *      @mbox: mailbox to use for the FW command
6702  *
6703  *      Issues a command to FW to partially initialize the device.  This
6704  *      performs initialization that generally doesn't depend on user input.
6705  */
6706 int t4_early_init(struct adapter *adap, unsigned int mbox)
6707 {
6708         struct fw_initialize_cmd c;
6709
6710         memset(&c, 0, sizeof(c));
6711         INIT_CMD(c, INITIALIZE, WRITE);
6712         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6713 }
6714
6715 /**
6716  *      t4_fw_reset - issue a reset to FW
6717  *      @adap: the adapter
6718  *      @mbox: mailbox to use for the FW command
6719  *      @reset: specifies the type of reset to perform
6720  *
6721  *      Issues a reset command of the specified type to FW.
6722  */
6723 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6724 {
6725         struct fw_reset_cmd c;
6726
6727         memset(&c, 0, sizeof(c));
6728         INIT_CMD(c, RESET, WRITE);
6729         c.val = cpu_to_be32(reset);
6730         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6731 }
6732
6733 /**
6734  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6735  *      @adap: the adapter
6736  *      @mbox: mailbox to use for the FW RESET command (if desired)
6737  *      @force: force uP into RESET even if FW RESET command fails
6738  *
6739  *      Issues a RESET command to firmware (if desired) with a HALT indication
6740  *      and then puts the microprocessor into RESET state.  The RESET command
6741  *      will only be issued if a legitimate mailbox is provided (mbox <=
6742  *      PCIE_FW_MASTER_M).
6743  *
6744  *      This is generally used in order for the host to safely manipulate the
6745  *      adapter without fear of conflicting with whatever the firmware might
6746  *      be doing.  The only way out of this state is to RESTART the firmware
6747  *      ...
6748  */
6749 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6750 {
6751         int ret = 0;
6752
6753         /*
6754          * If a legitimate mailbox is provided, issue a RESET command
6755          * with a HALT indication.
6756          */
6757         if (mbox <= PCIE_FW_MASTER_M) {
6758                 struct fw_reset_cmd c;
6759
6760                 memset(&c, 0, sizeof(c));
6761                 INIT_CMD(c, RESET, WRITE);
6762                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6763                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6764                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6765         }
6766
6767         /*
6768          * Normally we won't complete the operation if the firmware RESET
6769          * command fails but if our caller insists we'll go ahead and put the
6770          * uP into RESET.  This can be useful if the firmware is hung or even
6771          * missing ...  We'll have to take the risk of putting the uP into
6772          * RESET without the cooperation of firmware in that case.
6773          *
6774          * We also force the firmware's HALT flag to be on in case we bypassed
6775          * the firmware RESET command above or we're dealing with old firmware
6776          * which doesn't have the HALT capability.  This will serve as a flag
6777          * for the incoming firmware to know that it's coming out of a HALT
6778          * rather than a RESET ... if it's new enough to understand that ...
6779          */
6780         if (ret == 0 || force) {
6781                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6782                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6783                                  PCIE_FW_HALT_F);
6784         }
6785
6786         /*
6787          * And we always return the result of the firmware RESET command
6788          * even when we force the uP into RESET ...
6789          */
6790         return ret;
6791 }
6792
6793 /**
6794  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6795  *      @adap: the adapter
6796  *      @reset: if we want to do a RESET to restart things
6797  *
6798  *      Restart firmware previously halted by t4_fw_halt().  On successful
6799  *      return the previous PF Master remains as the new PF Master and there
6800  *      is no need to issue a new HELLO command, etc.
6801  *
6802  *      We do this in two ways:
6803  *
6804  *       1. If we're dealing with newer firmware we'll simply want to take
6805  *          the chip's microprocessor out of RESET.  This will cause the
6806  *          firmware to start up from its start vector.  And then we'll loop
6807  *          until the firmware indicates it's started again (PCIE_FW.HALT
6808  *          reset to 0) or we timeout.
6809  *
6810  *       2. If we're dealing with older firmware then we'll need to RESET
6811  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6812  *          flag and automatically RESET itself on startup.
6813  */
6814 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6815 {
6816         if (reset) {
6817                 /*
6818                  * Since we're directing the RESET instead of the firmware
6819                  * doing it automatically, we need to clear the PCIE_FW.HALT
6820                  * bit.
6821                  */
6822                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6823
6824                 /*
6825                  * If we've been given a valid mailbox, first try to get the
6826                  * firmware to do the RESET.  If that works, great and we can
6827                  * return success.  Otherwise, if we haven't been given a
6828                  * valid mailbox or the RESET command failed, fall back to
6829                  * hitting the chip with a hammer.
6830                  */
6831                 if (mbox <= PCIE_FW_MASTER_M) {
6832                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6833                         msleep(100);
6834                         if (t4_fw_reset(adap, mbox,
6835                                         PIORST_F | PIORSTMODE_F) == 0)
6836                                 return 0;
6837                 }
6838
6839                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6840                 msleep(2000);
6841         } else {
6842                 int ms;
6843
6844                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6845                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6846                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6847                                 return 0;
6848                         msleep(100);
6849                         ms += 100;
6850                 }
6851                 return -ETIMEDOUT;
6852         }
6853         return 0;
6854 }
6855
6856 /**
6857  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6858  *      @adap: the adapter
6859  *      @mbox: mailbox to use for the FW RESET command (if desired)
6860  *      @fw_data: the firmware image to write
6861  *      @size: image size
6862  *      @force: force upgrade even if firmware doesn't cooperate
6863  *
6864  *      Perform all of the steps necessary for upgrading an adapter's
6865  *      firmware image.  Normally this requires the cooperation of the
6866  *      existing firmware in order to halt all existing activities
6867  *      but if an invalid mailbox token is passed in we skip that step
6868  *      (though we'll still put the adapter microprocessor into RESET in
6869  *      that case).
6870  *
6871  *      On successful return the new firmware will have been loaded and
6872  *      the adapter will have been fully RESET losing all previous setup
6873  *      state.  On unsuccessful return the adapter may be completely hosed ...
6874  *      positive errno indicates that the adapter is ~probably~ intact, a
6875  *      negative errno indicates that things are looking bad ...
6876  */
6877 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6878                   const u8 *fw_data, unsigned int size, int force)
6879 {
6880         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6881         int reset, ret;
6882
6883         if (!t4_fw_matches_chip(adap, fw_hdr))
6884                 return -EINVAL;
6885
6886         /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6887          * wont be sent when we are flashing FW.
6888          */
6889         adap->flags &= ~FW_OK;
6890
6891         ret = t4_fw_halt(adap, mbox, force);
6892         if (ret < 0 && !force)
6893                 goto out;
6894
6895         ret = t4_load_fw(adap, fw_data, size);
6896         if (ret < 0)
6897                 goto out;
6898
6899         /*
6900          * If there was a Firmware Configuration File stored in FLASH,
6901          * there's a good chance that it won't be compatible with the new
6902          * Firmware.  In order to prevent difficult to diagnose adapter
6903          * initialization issues, we clear out the Firmware Configuration File
6904          * portion of the FLASH .  The user will need to re-FLASH a new
6905          * Firmware Configuration File which is compatible with the new
6906          * Firmware if that's desired.
6907          */
6908         (void)t4_load_cfg(adap, NULL, 0);
6909
6910         /*
6911          * Older versions of the firmware don't understand the new
6912          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6913          * restart.  So for newly loaded older firmware we'll have to do the
6914          * RESET for it so it starts up on a clean slate.  We can tell if
6915          * the newly loaded firmware will handle this right by checking
6916          * its header flags to see if it advertises the capability.
6917          */
6918         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6919         ret = t4_fw_restart(adap, mbox, reset);
6920
6921         /* Grab potentially new Firmware Device Log parameters so we can see
6922          * how healthy the new Firmware is.  It's okay to contact the new
6923          * Firmware for these parameters even though, as far as it's
6924          * concerned, we've never said "HELLO" to it ...
6925          */
6926         (void)t4_init_devlog_params(adap);
6927 out:
6928         adap->flags |= FW_OK;
6929         return ret;
6930 }
6931
6932 /**
6933  *      t4_fl_pkt_align - return the fl packet alignment
6934  *      @adap: the adapter
6935  *
6936  *      T4 has a single field to specify the packing and padding boundary.
6937  *      T5 onwards has separate fields for this and hence the alignment for
6938  *      next packet offset is maximum of these two.
6939  *
6940  */
6941 int t4_fl_pkt_align(struct adapter *adap)
6942 {
6943         u32 sge_control, sge_control2;
6944         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6945
6946         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6947
6948         /* T4 uses a single control field to specify both the PCIe Padding and
6949          * Packing Boundary.  T5 introduced the ability to specify these
6950          * separately.  The actual Ingress Packet Data alignment boundary
6951          * within Packed Buffer Mode is the maximum of these two
6952          * specifications.  (Note that it makes no real practical sense to
6953          * have the Pading Boudary be larger than the Packing Boundary but you
6954          * could set the chip up that way and, in fact, legacy T4 code would
6955          * end doing this because it would initialize the Padding Boundary and
6956          * leave the Packing Boundary initialized to 0 (16 bytes).)
6957          * Padding Boundary values in T6 starts from 8B,
6958          * where as it is 32B for T4 and T5.
6959          */
6960         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6961                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6962         else
6963                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6964
6965         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6966
6967         fl_align = ingpadboundary;
6968         if (!is_t4(adap->params.chip)) {
6969                 /* T5 has a weird interpretation of one of the PCIe Packing
6970                  * Boundary values.  No idea why ...
6971                  */
6972                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6973                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6974                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6975                         ingpackboundary = 16;
6976                 else
6977                         ingpackboundary = 1 << (ingpackboundary +
6978                                                 INGPACKBOUNDARY_SHIFT_X);
6979
6980                 fl_align = max(ingpadboundary, ingpackboundary);
6981         }
6982         return fl_align;
6983 }
6984
6985 /**
6986  *      t4_fixup_host_params - fix up host-dependent parameters
6987  *      @adap: the adapter
6988  *      @page_size: the host's Base Page Size
6989  *      @cache_line_size: the host's Cache Line Size
6990  *
6991  *      Various registers in T4 contain values which are dependent on the
6992  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6993  *      those registers with the appropriate values as passed in ...
6994  */
6995 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6996                          unsigned int cache_line_size)
6997 {
6998         unsigned int page_shift = fls(page_size) - 1;
6999         unsigned int sge_hps = page_shift - 10;
7000         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7001         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7002         unsigned int fl_align_log = fls(fl_align) - 1;
7003
7004         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7005                      HOSTPAGESIZEPF0_V(sge_hps) |
7006                      HOSTPAGESIZEPF1_V(sge_hps) |
7007                      HOSTPAGESIZEPF2_V(sge_hps) |
7008                      HOSTPAGESIZEPF3_V(sge_hps) |
7009                      HOSTPAGESIZEPF4_V(sge_hps) |
7010                      HOSTPAGESIZEPF5_V(sge_hps) |
7011                      HOSTPAGESIZEPF6_V(sge_hps) |
7012                      HOSTPAGESIZEPF7_V(sge_hps));
7013
7014         if (is_t4(adap->params.chip)) {
7015                 t4_set_reg_field(adap, SGE_CONTROL_A,
7016                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7017                                  EGRSTATUSPAGESIZE_F,
7018                                  INGPADBOUNDARY_V(fl_align_log -
7019                                                   INGPADBOUNDARY_SHIFT_X) |
7020                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7021         } else {
7022                 unsigned int pack_align;
7023                 unsigned int ingpad, ingpack;
7024                 unsigned int pcie_cap;
7025
7026                 /* T5 introduced the separation of the Free List Padding and
7027                  * Packing Boundaries.  Thus, we can select a smaller Padding
7028                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
7029                  * Bandwidth, and use a Packing Boundary which is large enough
7030                  * to avoid false sharing between CPUs, etc.
7031                  *
7032                  * For the PCI Link, the smaller the Padding Boundary the
7033                  * better.  For the Memory Controller, a smaller Padding
7034                  * Boundary is better until we cross under the Memory Line
7035                  * Size (the minimum unit of transfer to/from Memory).  If we
7036                  * have a Padding Boundary which is smaller than the Memory
7037                  * Line Size, that'll involve a Read-Modify-Write cycle on the
7038                  * Memory Controller which is never good.
7039                  */
7040
7041                 /* We want the Packing Boundary to be based on the Cache Line
7042                  * Size in order to help avoid False Sharing performance
7043                  * issues between CPUs, etc.  We also want the Packing
7044                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
7045                  * get best performance when the Packing Boundary is a
7046                  * multiple of the Maximum Payload Size.
7047                  */
7048                 pack_align = fl_align;
7049                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
7050                 if (pcie_cap) {
7051                         unsigned int mps, mps_log;
7052                         u16 devctl;
7053
7054                         /* The PCIe Device Control Maximum Payload Size field
7055                          * [bits 7:5] encodes sizes as powers of 2 starting at
7056                          * 128 bytes.
7057                          */
7058                         pci_read_config_word(adap->pdev,
7059                                              pcie_cap + PCI_EXP_DEVCTL,
7060                                              &devctl);
7061                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7062                         mps = 1 << mps_log;
7063                         if (mps > pack_align)
7064                                 pack_align = mps;
7065                 }
7066
7067                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7068                  * value for the Packing Boundary.  This corresponds to 16
7069                  * bytes instead of the expected 32 bytes.  So if we want 32
7070                  * bytes, the best we can really do is 64 bytes ...
7071                  */
7072                 if (pack_align <= 16) {
7073                         ingpack = INGPACKBOUNDARY_16B_X;
7074                         fl_align = 16;
7075                 } else if (pack_align == 32) {
7076                         ingpack = INGPACKBOUNDARY_64B_X;
7077                         fl_align = 64;
7078                 } else {
7079                         unsigned int pack_align_log = fls(pack_align) - 1;
7080
7081                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7082                         fl_align = pack_align;
7083                 }
7084
7085                 /* Use the smallest Ingress Padding which isn't smaller than
7086                  * the Memory Controller Read/Write Size.  We'll take that as
7087                  * being 8 bytes since we don't know of any system with a
7088                  * wider Memory Controller Bus Width.
7089                  */
7090                 if (is_t5(adap->params.chip))
7091                         ingpad = INGPADBOUNDARY_32B_X;
7092                 else
7093                         ingpad = T6_INGPADBOUNDARY_8B_X;
7094
7095                 t4_set_reg_field(adap, SGE_CONTROL_A,
7096                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7097                                  EGRSTATUSPAGESIZE_F,
7098                                  INGPADBOUNDARY_V(ingpad) |
7099                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7100                 t4_set_reg_field(adap, SGE_CONTROL2_A,
7101                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7102                                  INGPACKBOUNDARY_V(ingpack));
7103         }
7104         /*
7105          * Adjust various SGE Free List Host Buffer Sizes.
7106          *
7107          * This is something of a crock since we're using fixed indices into
7108          * the array which are also known by the sge.c code and the T4
7109          * Firmware Configuration File.  We need to come up with a much better
7110          * approach to managing this array.  For now, the first four entries
7111          * are:
7112          *
7113          *   0: Host Page Size
7114          *   1: 64KB
7115          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7116          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7117          *
7118          * For the single-MTU buffers in unpacked mode we need to include
7119          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7120          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7121          * Padding boundary.  All of these are accommodated in the Factory
7122          * Default Firmware Configuration File but we need to adjust it for
7123          * this host's cache line size.
7124          */
7125         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7126         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7127                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7128                      & ~(fl_align-1));
7129         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7130                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7131                      & ~(fl_align-1));
7132
7133         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7134
7135         return 0;
7136 }
7137
7138 /**
7139  *      t4_fw_initialize - ask FW to initialize the device
7140  *      @adap: the adapter
7141  *      @mbox: mailbox to use for the FW command
7142  *
7143  *      Issues a command to FW to partially initialize the device.  This
7144  *      performs initialization that generally doesn't depend on user input.
7145  */
7146 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7147 {
7148         struct fw_initialize_cmd c;
7149
7150         memset(&c, 0, sizeof(c));
7151         INIT_CMD(c, INITIALIZE, WRITE);
7152         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7153 }
7154
7155 /**
7156  *      t4_query_params_rw - query FW or device parameters
7157  *      @adap: the adapter
7158  *      @mbox: mailbox to use for the FW command
7159  *      @pf: the PF
7160  *      @vf: the VF
7161  *      @nparams: the number of parameters
7162  *      @params: the parameter names
7163  *      @val: the parameter values
7164  *      @rw: Write and read flag
7165  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7166  *
7167  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7168  *      queried at once.
7169  */
7170 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7171                        unsigned int vf, unsigned int nparams, const u32 *params,
7172                        u32 *val, int rw, bool sleep_ok)
7173 {
7174         int i, ret;
7175         struct fw_params_cmd c;
7176         __be32 *p = &c.param[0].mnem;
7177
7178         if (nparams > 7)
7179                 return -EINVAL;
7180
7181         memset(&c, 0, sizeof(c));
7182         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7183                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7184                                   FW_PARAMS_CMD_PFN_V(pf) |
7185                                   FW_PARAMS_CMD_VFN_V(vf));
7186         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7187
7188         for (i = 0; i < nparams; i++) {
7189                 *p++ = cpu_to_be32(*params++);
7190                 if (rw)
7191                         *p = cpu_to_be32(*(val + i));
7192                 p++;
7193         }
7194
7195         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7196         if (ret == 0)
7197                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7198                         *val++ = be32_to_cpu(*p);
7199         return ret;
7200 }
7201
7202 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7203                     unsigned int vf, unsigned int nparams, const u32 *params,
7204                     u32 *val)
7205 {
7206         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7207                                   true);
7208 }
7209
7210 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7211                        unsigned int vf, unsigned int nparams, const u32 *params,
7212                        u32 *val)
7213 {
7214         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7215                                   false);
7216 }
7217
7218 /**
7219  *      t4_set_params_timeout - sets FW or device parameters
7220  *      @adap: the adapter
7221  *      @mbox: mailbox to use for the FW command
7222  *      @pf: the PF
7223  *      @vf: the VF
7224  *      @nparams: the number of parameters
7225  *      @params: the parameter names
7226  *      @val: the parameter values
7227  *      @timeout: the timeout time
7228  *
7229  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7230  *      specified at once.
7231  */
7232 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7233                           unsigned int pf, unsigned int vf,
7234                           unsigned int nparams, const u32 *params,
7235                           const u32 *val, int timeout)
7236 {
7237         struct fw_params_cmd c;
7238         __be32 *p = &c.param[0].mnem;
7239
7240         if (nparams > 7)
7241                 return -EINVAL;
7242
7243         memset(&c, 0, sizeof(c));
7244         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7245                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7246                                   FW_PARAMS_CMD_PFN_V(pf) |
7247                                   FW_PARAMS_CMD_VFN_V(vf));
7248         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7249
7250         while (nparams--) {
7251                 *p++ = cpu_to_be32(*params++);
7252                 *p++ = cpu_to_be32(*val++);
7253         }
7254
7255         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7256 }
7257
7258 /**
7259  *      t4_set_params - sets FW or device parameters
7260  *      @adap: the adapter
7261  *      @mbox: mailbox to use for the FW command
7262  *      @pf: the PF
7263  *      @vf: the VF
7264  *      @nparams: the number of parameters
7265  *      @params: the parameter names
7266  *      @val: the parameter values
7267  *
7268  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7269  *      specified at once.
7270  */
7271 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7272                   unsigned int vf, unsigned int nparams, const u32 *params,
7273                   const u32 *val)
7274 {
7275         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7276                                      FW_CMD_MAX_TIMEOUT);
7277 }
7278
7279 /**
7280  *      t4_cfg_pfvf - configure PF/VF resource limits
7281  *      @adap: the adapter
7282  *      @mbox: mailbox to use for the FW command
7283  *      @pf: the PF being configured
7284  *      @vf: the VF being configured
7285  *      @txq: the max number of egress queues
7286  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7287  *      @rxqi: the max number of interrupt-capable ingress queues
7288  *      @rxq: the max number of interruptless ingress queues
7289  *      @tc: the PCI traffic class
7290  *      @vi: the max number of virtual interfaces
7291  *      @cmask: the channel access rights mask for the PF/VF
7292  *      @pmask: the port access rights mask for the PF/VF
7293  *      @nexact: the maximum number of exact MPS filters
7294  *      @rcaps: read capabilities
7295  *      @wxcaps: write/execute capabilities
7296  *
7297  *      Configures resource limits and capabilities for a physical or virtual
7298  *      function.
7299  */
7300 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7301                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7302                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7303                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7304                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7305 {
7306         struct fw_pfvf_cmd c;
7307
7308         memset(&c, 0, sizeof(c));
7309         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7310                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7311                                   FW_PFVF_CMD_VFN_V(vf));
7312         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7313         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7314                                      FW_PFVF_CMD_NIQ_V(rxq));
7315         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7316                                     FW_PFVF_CMD_PMASK_V(pmask) |
7317                                     FW_PFVF_CMD_NEQ_V(txq));
7318         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7319                                       FW_PFVF_CMD_NVI_V(vi) |
7320                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7321         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7322                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7323                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7324         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7325 }
7326
7327 /**
7328  *      t4_alloc_vi - allocate a virtual interface
7329  *      @adap: the adapter
7330  *      @mbox: mailbox to use for the FW command
7331  *      @port: physical port associated with the VI
7332  *      @pf: the PF owning the VI
7333  *      @vf: the VF owning the VI
7334  *      @nmac: number of MAC addresses needed (1 to 5)
7335  *      @mac: the MAC addresses of the VI
7336  *      @rss_size: size of RSS table slice associated with this VI
7337  *
7338  *      Allocates a virtual interface for the given physical port.  If @mac is
7339  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7340  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7341  *      stored consecutively so the space needed is @nmac * 6 bytes.
7342  *      Returns a negative error number or the non-negative VI id.
7343  */
7344 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7345                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7346                 unsigned int *rss_size)
7347 {
7348         int ret;
7349         struct fw_vi_cmd c;
7350
7351         memset(&c, 0, sizeof(c));
7352         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7353                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7354                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7355         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7356         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7357         c.nmac = nmac - 1;
7358
7359         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7360         if (ret)
7361                 return ret;
7362
7363         if (mac) {
7364                 memcpy(mac, c.mac, sizeof(c.mac));
7365                 switch (nmac) {
7366                 case 5:
7367                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7368                 case 4:
7369                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7370                 case 3:
7371                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7372                 case 2:
7373                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7374                 }
7375         }
7376         if (rss_size)
7377                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7378         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7379 }
7380
7381 /**
7382  *      t4_free_vi - free a virtual interface
7383  *      @adap: the adapter
7384  *      @mbox: mailbox to use for the FW command
7385  *      @pf: the PF owning the VI
7386  *      @vf: the VF owning the VI
7387  *      @viid: virtual interface identifiler
7388  *
7389  *      Free a previously allocated virtual interface.
7390  */
7391 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7392                unsigned int vf, unsigned int viid)
7393 {
7394         struct fw_vi_cmd c;
7395
7396         memset(&c, 0, sizeof(c));
7397         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7398                                   FW_CMD_REQUEST_F |
7399                                   FW_CMD_EXEC_F |
7400                                   FW_VI_CMD_PFN_V(pf) |
7401                                   FW_VI_CMD_VFN_V(vf));
7402         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7403         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7404
7405         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7406 }
7407
7408 /**
7409  *      t4_set_rxmode - set Rx properties of a virtual interface
7410  *      @adap: the adapter
7411  *      @mbox: mailbox to use for the FW command
7412  *      @viid: the VI id
7413  *      @mtu: the new MTU or -1
7414  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7415  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7416  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7417  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7418  *      @sleep_ok: if true we may sleep while awaiting command completion
7419  *
7420  *      Sets Rx properties of a virtual interface.
7421  */
7422 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7423                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7424                   bool sleep_ok)
7425 {
7426         struct fw_vi_rxmode_cmd c;
7427
7428         /* convert to FW values */
7429         if (mtu < 0)
7430                 mtu = FW_RXMODE_MTU_NO_CHG;
7431         if (promisc < 0)
7432                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7433         if (all_multi < 0)
7434                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7435         if (bcast < 0)
7436                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7437         if (vlanex < 0)
7438                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7439
7440         memset(&c, 0, sizeof(c));
7441         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7442                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7443                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7444         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7445         c.mtu_to_vlanexen =
7446                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7447                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7448                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7449                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7450                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7451         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7452 }
7453
7454 /**
7455  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7456  *      @adap: the adapter
7457  *      @mbox: mailbox to use for the FW command
7458  *      @viid: the VI id
7459  *      @free: if true any existing filters for this VI id are first removed
7460  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7461  *      @addr: the MAC address(es)
7462  *      @idx: where to store the index of each allocated filter
7463  *      @hash: pointer to hash address filter bitmap
7464  *      @sleep_ok: call is allowed to sleep
7465  *
7466  *      Allocates an exact-match filter for each of the supplied addresses and
7467  *      sets it to the corresponding address.  If @idx is not %NULL it should
7468  *      have at least @naddr entries, each of which will be set to the index of
7469  *      the filter allocated for the corresponding MAC address.  If a filter
7470  *      could not be allocated for an address its index is set to 0xffff.
7471  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7472  *      are hashed and update the hash filter bitmap pointed at by @hash.
7473  *
7474  *      Returns a negative error number or the number of filters allocated.
7475  */
7476 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7477                       unsigned int viid, bool free, unsigned int naddr,
7478                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7479 {
7480         int offset, ret = 0;
7481         struct fw_vi_mac_cmd c;
7482         unsigned int nfilters = 0;
7483         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7484         unsigned int rem = naddr;
7485
7486         if (naddr > max_naddr)
7487                 return -EINVAL;
7488
7489         for (offset = 0; offset < naddr ; /**/) {
7490                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7491                                          rem : ARRAY_SIZE(c.u.exact));
7492                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7493                                                      u.exact[fw_naddr]), 16);
7494                 struct fw_vi_mac_exact *p;
7495                 int i;
7496
7497                 memset(&c, 0, sizeof(c));
7498                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7499                                            FW_CMD_REQUEST_F |
7500                                            FW_CMD_WRITE_F |
7501                                            FW_CMD_EXEC_V(free) |
7502                                            FW_VI_MAC_CMD_VIID_V(viid));
7503                 c.freemacs_to_len16 =
7504                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7505                                     FW_CMD_LEN16_V(len16));
7506
7507                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7508                         p->valid_to_idx =
7509                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7510                                             FW_VI_MAC_CMD_IDX_V(
7511                                                     FW_VI_MAC_ADD_MAC));
7512                         memcpy(p->macaddr, addr[offset + i],
7513                                sizeof(p->macaddr));
7514                 }
7515
7516                 /* It's okay if we run out of space in our MAC address arena.
7517                  * Some of the addresses we submit may get stored so we need
7518                  * to run through the reply to see what the results were ...
7519                  */
7520                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7521                 if (ret && ret != -FW_ENOMEM)
7522                         break;
7523
7524                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7525                         u16 index = FW_VI_MAC_CMD_IDX_G(
7526                                         be16_to_cpu(p->valid_to_idx));
7527
7528                         if (idx)
7529                                 idx[offset + i] = (index >= max_naddr ?
7530                                                    0xffff : index);
7531                         if (index < max_naddr)
7532                                 nfilters++;
7533                         else if (hash)
7534                                 *hash |= (1ULL <<
7535                                           hash_mac_addr(addr[offset + i]));
7536                 }
7537
7538                 free = false;
7539                 offset += fw_naddr;
7540                 rem -= fw_naddr;
7541         }
7542
7543         if (ret == 0 || ret == -FW_ENOMEM)
7544                 ret = nfilters;
7545         return ret;
7546 }
7547
7548 /**
7549  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
7550  *      @adap: the adapter
7551  *      @mbox: mailbox to use for the FW command
7552  *      @viid: the VI id
7553  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7554  *      @addr: the MAC address(es)
7555  *      @sleep_ok: call is allowed to sleep
7556  *
7557  *      Frees the exact-match filter for each of the supplied addresses
7558  *
7559  *      Returns a negative error number or the number of filters freed.
7560  */
7561 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7562                      unsigned int viid, unsigned int naddr,
7563                      const u8 **addr, bool sleep_ok)
7564 {
7565         int offset, ret = 0;
7566         struct fw_vi_mac_cmd c;
7567         unsigned int nfilters = 0;
7568         unsigned int max_naddr = is_t4(adap->params.chip) ?
7569                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
7570                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7571         unsigned int rem = naddr;
7572
7573         if (naddr > max_naddr)
7574                 return -EINVAL;
7575
7576         for (offset = 0; offset < (int)naddr ; /**/) {
7577                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7578                                          ? rem
7579                                          : ARRAY_SIZE(c.u.exact));
7580                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7581                                                      u.exact[fw_naddr]), 16);
7582                 struct fw_vi_mac_exact *p;
7583                 int i;
7584
7585                 memset(&c, 0, sizeof(c));
7586                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7587                                      FW_CMD_REQUEST_F |
7588                                      FW_CMD_WRITE_F |
7589                                      FW_CMD_EXEC_V(0) |
7590                                      FW_VI_MAC_CMD_VIID_V(viid));
7591                 c.freemacs_to_len16 =
7592                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7593                                             FW_CMD_LEN16_V(len16));
7594
7595                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7596                         p->valid_to_idx = cpu_to_be16(
7597                                 FW_VI_MAC_CMD_VALID_F |
7598                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7599                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7600                 }
7601
7602                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7603                 if (ret)
7604                         break;
7605
7606                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7607                         u16 index = FW_VI_MAC_CMD_IDX_G(
7608                                                 be16_to_cpu(p->valid_to_idx));
7609
7610                         if (index < max_naddr)
7611                                 nfilters++;
7612                 }
7613
7614                 offset += fw_naddr;
7615                 rem -= fw_naddr;
7616         }
7617
7618         if (ret == 0)
7619                 ret = nfilters;
7620         return ret;
7621 }
7622
7623 /**
7624  *      t4_change_mac - modifies the exact-match filter for a MAC address
7625  *      @adap: the adapter
7626  *      @mbox: mailbox to use for the FW command
7627  *      @viid: the VI id
7628  *      @idx: index of existing filter for old value of MAC address, or -1
7629  *      @addr: the new MAC address value
7630  *      @persist: whether a new MAC allocation should be persistent
7631  *      @add_smt: if true also add the address to the HW SMT
7632  *
7633  *      Modifies an exact-match filter and sets it to the new MAC address.
7634  *      Note that in general it is not possible to modify the value of a given
7635  *      filter so the generic way to modify an address filter is to free the one
7636  *      being used by the old address value and allocate a new filter for the
7637  *      new address value.  @idx can be -1 if the address is a new addition.
7638  *
7639  *      Returns a negative error number or the index of the filter with the new
7640  *      MAC value.
7641  */
7642 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7643                   int idx, const u8 *addr, bool persist, bool add_smt)
7644 {
7645         int ret, mode;
7646         struct fw_vi_mac_cmd c;
7647         struct fw_vi_mac_exact *p = c.u.exact;
7648         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7649
7650         if (idx < 0)                             /* new allocation */
7651                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7652         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7653
7654         memset(&c, 0, sizeof(c));
7655         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7656                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7657                                    FW_VI_MAC_CMD_VIID_V(viid));
7658         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7659         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7660                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7661                                       FW_VI_MAC_CMD_IDX_V(idx));
7662         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7663
7664         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7665         if (ret == 0) {
7666                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7667                 if (ret >= max_mac_addr)
7668                         ret = -ENOMEM;
7669         }
7670         return ret;
7671 }
7672
7673 /**
7674  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7675  *      @adap: the adapter
7676  *      @mbox: mailbox to use for the FW command
7677  *      @viid: the VI id
7678  *      @ucast: whether the hash filter should also match unicast addresses
7679  *      @vec: the value to be written to the hash filter
7680  *      @sleep_ok: call is allowed to sleep
7681  *
7682  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7683  */
7684 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7685                      bool ucast, u64 vec, bool sleep_ok)
7686 {
7687         struct fw_vi_mac_cmd c;
7688
7689         memset(&c, 0, sizeof(c));
7690         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7691                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7692                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7693         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7694                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7695                                           FW_CMD_LEN16_V(1));
7696         c.u.hash.hashvec = cpu_to_be64(vec);
7697         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7698 }
7699
7700 /**
7701  *      t4_enable_vi_params - enable/disable a virtual interface
7702  *      @adap: the adapter
7703  *      @mbox: mailbox to use for the FW command
7704  *      @viid: the VI id
7705  *      @rx_en: 1=enable Rx, 0=disable Rx
7706  *      @tx_en: 1=enable Tx, 0=disable Tx
7707  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7708  *
7709  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7710  *      only makes sense when enabling a Virtual Interface ...
7711  */
7712 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7713                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7714 {
7715         struct fw_vi_enable_cmd c;
7716
7717         memset(&c, 0, sizeof(c));
7718         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7719                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7720                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7721         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7722                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7723                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7724                                      FW_LEN16(c));
7725         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7726 }
7727
7728 /**
7729  *      t4_enable_vi - enable/disable a virtual interface
7730  *      @adap: the adapter
7731  *      @mbox: mailbox to use for the FW command
7732  *      @viid: the VI id
7733  *      @rx_en: 1=enable Rx, 0=disable Rx
7734  *      @tx_en: 1=enable Tx, 0=disable Tx
7735  *
7736  *      Enables/disables a virtual interface.
7737  */
7738 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7739                  bool rx_en, bool tx_en)
7740 {
7741         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7742 }
7743
7744 /**
7745  *      t4_identify_port - identify a VI's port by blinking its LED
7746  *      @adap: the adapter
7747  *      @mbox: mailbox to use for the FW command
7748  *      @viid: the VI id
7749  *      @nblinks: how many times to blink LED at 2.5 Hz
7750  *
7751  *      Identifies a VI's port by blinking its LED.
7752  */
7753 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7754                      unsigned int nblinks)
7755 {
7756         struct fw_vi_enable_cmd c;
7757
7758         memset(&c, 0, sizeof(c));
7759         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7760                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7761                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7762         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7763         c.blinkdur = cpu_to_be16(nblinks);
7764         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7765 }
7766
7767 /**
7768  *      t4_iq_stop - stop an ingress queue and its FLs
7769  *      @adap: the adapter
7770  *      @mbox: mailbox to use for the FW command
7771  *      @pf: the PF owning the queues
7772  *      @vf: the VF owning the queues
7773  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7774  *      @iqid: ingress queue id
7775  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7776  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7777  *
7778  *      Stops an ingress queue and its associated FLs, if any.  This causes
7779  *      any current or future data/messages destined for these queues to be
7780  *      tossed.
7781  */
7782 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7783                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7784                unsigned int fl0id, unsigned int fl1id)
7785 {
7786         struct fw_iq_cmd c;
7787
7788         memset(&c, 0, sizeof(c));
7789         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7790                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7791                                   FW_IQ_CMD_VFN_V(vf));
7792         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7793         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7794         c.iqid = cpu_to_be16(iqid);
7795         c.fl0id = cpu_to_be16(fl0id);
7796         c.fl1id = cpu_to_be16(fl1id);
7797         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7798 }
7799
7800 /**
7801  *      t4_iq_free - free an ingress queue and its FLs
7802  *      @adap: the adapter
7803  *      @mbox: mailbox to use for the FW command
7804  *      @pf: the PF owning the queues
7805  *      @vf: the VF owning the queues
7806  *      @iqtype: the ingress queue type
7807  *      @iqid: ingress queue id
7808  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7809  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7810  *
7811  *      Frees an ingress queue and its associated FLs, if any.
7812  */
7813 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7814                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7815                unsigned int fl0id, unsigned int fl1id)
7816 {
7817         struct fw_iq_cmd c;
7818
7819         memset(&c, 0, sizeof(c));
7820         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7821                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7822                                   FW_IQ_CMD_VFN_V(vf));
7823         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7824         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7825         c.iqid = cpu_to_be16(iqid);
7826         c.fl0id = cpu_to_be16(fl0id);
7827         c.fl1id = cpu_to_be16(fl1id);
7828         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7829 }
7830
7831 /**
7832  *      t4_eth_eq_free - free an Ethernet egress queue
7833  *      @adap: the adapter
7834  *      @mbox: mailbox to use for the FW command
7835  *      @pf: the PF owning the queue
7836  *      @vf: the VF owning the queue
7837  *      @eqid: egress queue id
7838  *
7839  *      Frees an Ethernet egress queue.
7840  */
7841 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7842                    unsigned int vf, unsigned int eqid)
7843 {
7844         struct fw_eq_eth_cmd c;
7845
7846         memset(&c, 0, sizeof(c));
7847         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7848                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7849                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7850                                   FW_EQ_ETH_CMD_VFN_V(vf));
7851         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7852         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7853         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7854 }
7855
7856 /**
7857  *      t4_ctrl_eq_free - free a control egress queue
7858  *      @adap: the adapter
7859  *      @mbox: mailbox to use for the FW command
7860  *      @pf: the PF owning the queue
7861  *      @vf: the VF owning the queue
7862  *      @eqid: egress queue id
7863  *
7864  *      Frees a control egress queue.
7865  */
7866 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7867                     unsigned int vf, unsigned int eqid)
7868 {
7869         struct fw_eq_ctrl_cmd c;
7870
7871         memset(&c, 0, sizeof(c));
7872         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7873                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7874                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7875                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7876         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7877         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7878         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7879 }
7880
7881 /**
7882  *      t4_ofld_eq_free - free an offload egress queue
7883  *      @adap: the adapter
7884  *      @mbox: mailbox to use for the FW command
7885  *      @pf: the PF owning the queue
7886  *      @vf: the VF owning the queue
7887  *      @eqid: egress queue id
7888  *
7889  *      Frees a control egress queue.
7890  */
7891 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7892                     unsigned int vf, unsigned int eqid)
7893 {
7894         struct fw_eq_ofld_cmd c;
7895
7896         memset(&c, 0, sizeof(c));
7897         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7898                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7899                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7900                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7901         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7902         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7903         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7904 }
7905
7906 /**
7907  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7908  *      @adap: the adapter
7909  *      @link_down_rc: Link Down Reason Code
7910  *
7911  *      Returns a string representation of the Link Down Reason Code.
7912  */
7913 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7914 {
7915         static const char * const reason[] = {
7916                 "Link Down",
7917                 "Remote Fault",
7918                 "Auto-negotiation Failure",
7919                 "Reserved",
7920                 "Insufficient Airflow",
7921                 "Unable To Determine Reason",
7922                 "No RX Signal Detected",
7923                 "Reserved",
7924         };
7925
7926         if (link_down_rc >= ARRAY_SIZE(reason))
7927                 return "Bad Reason Code";
7928
7929         return reason[link_down_rc];
7930 }
7931
7932 /**
7933  * Return the highest speed set in the port capabilities, in Mb/s.
7934  */
7935 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
7936 {
7937         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
7938                 do { \
7939                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7940                                 return __speed; \
7941                 } while (0)
7942
7943         TEST_SPEED_RETURN(400G, 400000);
7944         TEST_SPEED_RETURN(200G, 200000);
7945         TEST_SPEED_RETURN(100G, 100000);
7946         TEST_SPEED_RETURN(50G,   50000);
7947         TEST_SPEED_RETURN(40G,   40000);
7948         TEST_SPEED_RETURN(25G,   25000);
7949         TEST_SPEED_RETURN(10G,   10000);
7950         TEST_SPEED_RETURN(1G,     1000);
7951         TEST_SPEED_RETURN(100M,    100);
7952
7953         #undef TEST_SPEED_RETURN
7954
7955         return 0;
7956 }
7957
7958 /**
7959  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
7960  *      @acaps: advertised Port Capabilities
7961  *
7962  *      Get the highest speed for the port from the advertised Port
7963  *      Capabilities.  It will be either the highest speed from the list of
7964  *      speeds or whatever user has set using ethtool.
7965  */
7966 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
7967 {
7968         #define TEST_SPEED_RETURN(__caps_speed) \
7969                 do { \
7970                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7971                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
7972                 } while (0)
7973
7974         TEST_SPEED_RETURN(400G);
7975         TEST_SPEED_RETURN(200G);
7976         TEST_SPEED_RETURN(100G);
7977         TEST_SPEED_RETURN(50G);
7978         TEST_SPEED_RETURN(40G);
7979         TEST_SPEED_RETURN(25G);
7980         TEST_SPEED_RETURN(10G);
7981         TEST_SPEED_RETURN(1G);
7982         TEST_SPEED_RETURN(100M);
7983
7984         #undef TEST_SPEED_RETURN
7985
7986         return 0;
7987 }
7988
7989 /**
7990  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
7991  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
7992  *
7993  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
7994  *      32-bit Port Capabilities value.
7995  */
7996 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
7997 {
7998         fw_port_cap32_t linkattr = 0;
7999
8000         /* Unfortunately the format of the Link Status in the old
8001          * 16-bit Port Information message isn't the same as the
8002          * 16-bit Port Capabilities bitfield used everywhere else ...
8003          */
8004         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8005                 linkattr |= FW_PORT_CAP32_FC_RX;
8006         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8007                 linkattr |= FW_PORT_CAP32_FC_TX;
8008         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8009                 linkattr |= FW_PORT_CAP32_SPEED_100M;
8010         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8011                 linkattr |= FW_PORT_CAP32_SPEED_1G;
8012         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8013                 linkattr |= FW_PORT_CAP32_SPEED_10G;
8014         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8015                 linkattr |= FW_PORT_CAP32_SPEED_25G;
8016         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8017                 linkattr |= FW_PORT_CAP32_SPEED_40G;
8018         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8019                 linkattr |= FW_PORT_CAP32_SPEED_100G;
8020
8021         return linkattr;
8022 }
8023
8024 /**
8025  *      t4_handle_get_port_info - process a FW reply message
8026  *      @pi: the port info
8027  *      @rpl: start of the FW message
8028  *
8029  *      Processes a GET_PORT_INFO FW reply message.
8030  */
8031 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8032 {
8033         const struct fw_port_cmd *cmd = (const void *)rpl;
8034         int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8035         struct adapter *adapter = pi->adapter;
8036         struct link_config *lc = &pi->link_cfg;
8037         int link_ok, linkdnrc;
8038         enum fw_port_type port_type;
8039         enum fw_port_module_type mod_type;
8040         unsigned int speed, fc, fec;
8041         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8042
8043         /* Extract the various fields from the Port Information message.
8044          */
8045         switch (action) {
8046         case FW_PORT_ACTION_GET_PORT_INFO: {
8047                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8048
8049                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8050                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8051                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8052                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8053                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8054                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8055                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8056                 linkattr = lstatus_to_fwcap(lstatus);
8057                 break;
8058         }
8059
8060         case FW_PORT_ACTION_GET_PORT_INFO32: {
8061                 u32 lstatus32;
8062
8063                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8064                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8065                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8066                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8067                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8068                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8069                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8070                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8071                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8072                 break;
8073         }
8074
8075         default:
8076                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8077                         be32_to_cpu(cmd->action_to_len16));
8078                 return;
8079         }
8080
8081         fec = fwcap_to_cc_fec(acaps);
8082         fc = fwcap_to_cc_pause(linkattr);
8083         speed = fwcap_to_speed(linkattr);
8084
8085         if (mod_type != pi->mod_type) {
8086                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8087                  * various fundamental Port Capabilities which used to be
8088                  * immutable can now change radically.  We can now have
8089                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8090                  * all change based on what Transceiver Module is inserted.
8091                  * So we need to record the Physical "Port" Capabilities on
8092                  * every Transceiver Module change.
8093                  */
8094                 lc->pcaps = pcaps;
8095
8096                 /* When a new Transceiver Module is inserted, the Firmware
8097                  * will examine its i2c EPROM to determine its type and
8098                  * general operating parameters including things like Forward
8099                  * Error Control, etc.  Various IEEE 802.3 standards dictate
8100                  * how to interpret these i2c values to determine default
8101                  * "sutomatic" settings.  We record these for future use when
8102                  * the user explicitly requests these standards-based values.
8103                  */
8104                 lc->def_acaps = acaps;
8105
8106                 /* Some versions of the early T6 Firmware "cheated" when
8107                  * handling different Transceiver Modules by changing the
8108                  * underlaying Port Type reported to the Host Drivers.  As
8109                  * such we need to capture whatever Port Type the Firmware
8110                  * sends us and record it in case it's different from what we
8111                  * were told earlier.  Unfortunately, since Firmware is
8112                  * forever, we'll need to keep this code here forever, but in
8113                  * later T6 Firmware it should just be an assignment of the
8114                  * same value already recorded.
8115                  */
8116                 pi->port_type = port_type;
8117
8118                 pi->mod_type = mod_type;
8119                 t4_os_portmod_changed(adapter, pi->port_id);
8120         }
8121
8122         if (link_ok != lc->link_ok || speed != lc->speed ||
8123             fc != lc->fc || fec != lc->fec) {   /* something changed */
8124                 if (!link_ok && lc->link_ok) {
8125                         lc->link_down_rc = linkdnrc;
8126                         dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
8127                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
8128                 }
8129                 lc->link_ok = link_ok;
8130                 lc->speed = speed;
8131                 lc->fc = fc;
8132                 lc->fec = fec;
8133
8134                 lc->lpacaps = lpacaps;
8135                 lc->acaps = acaps & ADVERT_MASK;
8136
8137                 if (lc->acaps & FW_PORT_CAP32_ANEG) {
8138                         lc->autoneg = AUTONEG_ENABLE;
8139                 } else {
8140                         /* When Autoneg is disabled, user needs to set
8141                          * single speed.
8142                          * Similar to cxgb4_ethtool.c: set_link_ksettings
8143                          */
8144                         lc->acaps = 0;
8145                         lc->speed_caps = fwcap_to_fwspeed(acaps);
8146                         lc->autoneg = AUTONEG_DISABLE;
8147                 }
8148
8149                 t4_os_link_changed(adapter, pi->port_id, link_ok);
8150         }
8151 }
8152
8153 /**
8154  *      t4_update_port_info - retrieve and update port information if changed
8155  *      @pi: the port_info
8156  *
8157  *      We issue a Get Port Information Command to the Firmware and, if
8158  *      successful, we check to see if anything is different from what we
8159  *      last recorded and update things accordingly.
8160  */
8161 int t4_update_port_info(struct port_info *pi)
8162 {
8163         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8164         struct fw_port_cmd port_cmd;
8165         int ret;
8166
8167         memset(&port_cmd, 0, sizeof(port_cmd));
8168         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8169                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8170                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8171         port_cmd.action_to_len16 = cpu_to_be32(
8172                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8173                                      ? FW_PORT_ACTION_GET_PORT_INFO
8174                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8175                 FW_LEN16(port_cmd));
8176         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8177                          &port_cmd, sizeof(port_cmd), &port_cmd);
8178         if (ret)
8179                 return ret;
8180
8181         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8182         return 0;
8183 }
8184
8185 /**
8186  *      t4_get_link_params - retrieve basic link parameters for given port
8187  *      @pi: the port
8188  *      @link_okp: value return pointer for link up/down
8189  *      @speedp: value return pointer for speed (Mb/s)
8190  *      @mtup: value return pointer for mtu
8191  *
8192  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8193  *      and MTU for a specified port.  A negative error is returned on
8194  *      failure; 0 on success.
8195  */
8196 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8197                        unsigned int *speedp, unsigned int *mtup)
8198 {
8199         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8200         struct fw_port_cmd port_cmd;
8201         unsigned int action, link_ok, speed, mtu;
8202         fw_port_cap32_t linkattr;
8203         int ret;
8204
8205         memset(&port_cmd, 0, sizeof(port_cmd));
8206         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8207                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8208                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8209         action = (fw_caps == FW_CAPS16
8210                   ? FW_PORT_ACTION_GET_PORT_INFO
8211                   : FW_PORT_ACTION_GET_PORT_INFO32);
8212         port_cmd.action_to_len16 = cpu_to_be32(
8213                 FW_PORT_CMD_ACTION_V(action) |
8214                 FW_LEN16(port_cmd));
8215         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8216                          &port_cmd, sizeof(port_cmd), &port_cmd);
8217         if (ret)
8218                 return ret;
8219
8220         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8221                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8222
8223                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8224                 linkattr = lstatus_to_fwcap(lstatus);
8225                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8226         } else {
8227                 u32 lstatus32 =
8228                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8229
8230                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8231                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8232                 mtu = FW_PORT_CMD_MTU32_G(
8233                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8234         }
8235         speed = fwcap_to_speed(linkattr);
8236
8237         *link_okp = link_ok;
8238         *speedp = fwcap_to_speed(linkattr);
8239         *mtup = mtu;
8240
8241         return 0;
8242 }
8243
8244 /**
8245  *      t4_handle_fw_rpl - process a FW reply message
8246  *      @adap: the adapter
8247  *      @rpl: start of the FW message
8248  *
8249  *      Processes a FW message, such as link state change messages.
8250  */
8251 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8252 {
8253         u8 opcode = *(const u8 *)rpl;
8254
8255         /* This might be a port command ... this simplifies the following
8256          * conditionals ...  We can get away with pre-dereferencing
8257          * action_to_len16 because it's in the first 16 bytes and all messages
8258          * will be at least that long.
8259          */
8260         const struct fw_port_cmd *p = (const void *)rpl;
8261         unsigned int action =
8262                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8263
8264         if (opcode == FW_PORT_CMD &&
8265             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8266              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8267                 int i;
8268                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8269                 struct port_info *pi = NULL;
8270
8271                 for_each_port(adap, i) {
8272                         pi = adap2pinfo(adap, i);
8273                         if (pi->tx_chan == chan)
8274                                 break;
8275                 }
8276
8277                 t4_handle_get_port_info(pi, rpl);
8278         } else {
8279                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8280                          opcode);
8281                 return -EINVAL;
8282         }
8283         return 0;
8284 }
8285
8286 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8287 {
8288         u16 val;
8289
8290         if (pci_is_pcie(adapter->pdev)) {
8291                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8292                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8293                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8294         }
8295 }
8296
8297 /**
8298  *      init_link_config - initialize a link's SW state
8299  *      @lc: pointer to structure holding the link state
8300  *      @pcaps: link Port Capabilities
8301  *      @acaps: link current Advertised Port Capabilities
8302  *
8303  *      Initializes the SW state maintained for each link, including the link's
8304  *      capabilities and default speed/flow-control/autonegotiation settings.
8305  */
8306 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8307                              fw_port_cap32_t acaps)
8308 {
8309         lc->pcaps = pcaps;
8310         lc->def_acaps = acaps;
8311         lc->lpacaps = 0;
8312         lc->speed_caps = 0;
8313         lc->speed = 0;
8314         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8315
8316         /* For Forward Error Control, we default to whatever the Firmware
8317          * tells us the Link is currently advertising.
8318          */
8319         lc->requested_fec = FEC_AUTO;
8320         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8321
8322         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8323                 lc->acaps = lc->pcaps & ADVERT_MASK;
8324                 lc->autoneg = AUTONEG_ENABLE;
8325                 lc->requested_fc |= PAUSE_AUTONEG;
8326         } else {
8327                 lc->acaps = 0;
8328                 lc->autoneg = AUTONEG_DISABLE;
8329         }
8330 }
8331
8332 #define CIM_PF_NOACCESS 0xeeeeeeee
8333
8334 int t4_wait_dev_ready(void __iomem *regs)
8335 {
8336         u32 whoami;
8337
8338         whoami = readl(regs + PL_WHOAMI_A);
8339         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8340                 return 0;
8341
8342         msleep(500);
8343         whoami = readl(regs + PL_WHOAMI_A);
8344         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8345 }
8346
8347 struct flash_desc {
8348         u32 vendor_and_model_id;
8349         u32 size_mb;
8350 };
8351
8352 static int t4_get_flash_params(struct adapter *adap)
8353 {
8354         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8355          * to the preexisting code.  All flash parts have 64KB sectors.
8356          */
8357         static struct flash_desc supported_flash[] = {
8358                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8359         };
8360
8361         unsigned int part, manufacturer;
8362         unsigned int density, size;
8363         u32 flashid = 0;
8364         int ret;
8365
8366         /* Issue a Read ID Command to the Flash part.  We decode supported
8367          * Flash parts and their sizes from this.  There's a newer Query
8368          * Command which can retrieve detailed geometry information but many
8369          * Flash parts don't support it.
8370          */
8371
8372         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8373         if (!ret)
8374                 ret = sf1_read(adap, 3, 0, 1, &flashid);
8375         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8376         if (ret)
8377                 return ret;
8378
8379         /* Check to see if it's one of our non-standard supported Flash parts.
8380          */
8381         for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8382                 if (supported_flash[part].vendor_and_model_id == flashid) {
8383                         adap->params.sf_size = supported_flash[part].size_mb;
8384                         adap->params.sf_nsec =
8385                                 adap->params.sf_size / SF_SEC_SIZE;
8386                         goto found;
8387                 }
8388
8389         /* Decode Flash part size.  The code below looks repetative with
8390          * common encodings, but that's not guaranteed in the JEDEC
8391          * specification for the Read JADEC ID command.  The only thing that
8392          * we're guaranteed by the JADEC specification is where the
8393          * Manufacturer ID is in the returned result.  After that each
8394          * Manufacturer ~could~ encode things completely differently.
8395          * Note, all Flash parts must have 64KB sectors.
8396          */
8397         manufacturer = flashid & 0xff;
8398         switch (manufacturer) {
8399         case 0x20: { /* Micron/Numonix */
8400                 /* This Density -> Size decoding table is taken from Micron
8401                  * Data Sheets.
8402                  */
8403                 density = (flashid >> 16) & 0xff;
8404                 switch (density) {
8405                 case 0x14: /* 1MB */
8406                         size = 1 << 20;
8407                         break;
8408                 case 0x15: /* 2MB */
8409                         size = 1 << 21;
8410                         break;
8411                 case 0x16: /* 4MB */
8412                         size = 1 << 22;
8413                         break;
8414                 case 0x17: /* 8MB */
8415                         size = 1 << 23;
8416                         break;
8417                 case 0x18: /* 16MB */
8418                         size = 1 << 24;
8419                         break;
8420                 case 0x19: /* 32MB */
8421                         size = 1 << 25;
8422                         break;
8423                 case 0x20: /* 64MB */
8424                         size = 1 << 26;
8425                         break;
8426                 case 0x21: /* 128MB */
8427                         size = 1 << 27;
8428                         break;
8429                 case 0x22: /* 256MB */
8430                         size = 1 << 28;
8431                         break;
8432
8433                 default:
8434                         dev_err(adap->pdev_dev, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
8435                                 flashid, density);
8436                         return -EINVAL;
8437                 }
8438                 break;
8439         }
8440         case 0xc2: { /* Macronix */
8441                 /* This Density -> Size decoding table is taken from Macronix
8442                  * Data Sheets.
8443                  */
8444                 density = (flashid >> 16) & 0xff;
8445                 switch (density) {
8446                 case 0x17: /* 8MB */
8447                         size = 1 << 23;
8448                         break;
8449                 case 0x18: /* 16MB */
8450                         size = 1 << 24;
8451                         break;
8452                 default:
8453                         dev_err(adap->pdev_dev, "Macronix Flash Part has bad size, ID = %#x, Density code = %#x\n",
8454                                 flashid, density);
8455                         return -EINVAL;
8456                 }
8457                 break;
8458         }
8459         case 0xef: { /* Winbond */
8460                 /* This Density -> Size decoding table is taken from Winbond
8461                  * Data Sheets.
8462                  */
8463                 density = (flashid >> 16) & 0xff;
8464                 switch (density) {
8465                 case 0x17: /* 8MB */
8466                         size = 1 << 23;
8467                         break;
8468                 case 0x18: /* 16MB */
8469                         size = 1 << 24;
8470                         break;
8471                 default:
8472                         dev_err(adap->pdev_dev, "Winbond Flash Part has bad size, ID = %#x, Density code = %#x\n",
8473                                 flashid, density);
8474                         return -EINVAL;
8475                 }
8476                 break;
8477         }
8478         default:
8479                 dev_err(adap->pdev_dev, "Unsupported Flash Part, ID = %#x\n",
8480                         flashid);
8481                 return -EINVAL;
8482         }
8483
8484         /* Store decoded Flash size and fall through into vetting code. */
8485         adap->params.sf_size = size;
8486         adap->params.sf_nsec = size / SF_SEC_SIZE;
8487
8488 found:
8489         if (adap->params.sf_size < FLASH_MIN_SIZE)
8490                 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8491                          flashid, adap->params.sf_size, FLASH_MIN_SIZE);
8492         return 0;
8493 }
8494
8495 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
8496 {
8497         u16 val;
8498         u32 pcie_cap;
8499
8500         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
8501         if (pcie_cap) {
8502                 pci_read_config_word(adapter->pdev,
8503                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
8504                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
8505                 val |= range;
8506                 pci_write_config_word(adapter->pdev,
8507                                       pcie_cap + PCI_EXP_DEVCTL2, val);
8508         }
8509 }
8510
8511 /**
8512  *      t4_prep_adapter - prepare SW and HW for operation
8513  *      @adapter: the adapter
8514  *      @reset: if true perform a HW reset
8515  *
8516  *      Initialize adapter SW state for the various HW modules, set initial
8517  *      values for some adapter tunables, take PHYs out of reset, and
8518  *      initialize the MDIO interface.
8519  */
8520 int t4_prep_adapter(struct adapter *adapter)
8521 {
8522         int ret, ver;
8523         uint16_t device_id;
8524         u32 pl_rev;
8525
8526         get_pci_mode(adapter, &adapter->params.pci);
8527         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8528
8529         ret = t4_get_flash_params(adapter);
8530         if (ret < 0) {
8531                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8532                 return ret;
8533         }
8534
8535         /* Retrieve adapter's device ID
8536          */
8537         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8538         ver = device_id >> 12;
8539         adapter->params.chip = 0;
8540         switch (ver) {
8541         case CHELSIO_T4:
8542                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8543                 adapter->params.arch.sge_fl_db = DBPRIO_F;
8544                 adapter->params.arch.mps_tcam_size =
8545                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
8546                 adapter->params.arch.mps_rplc_size = 128;
8547                 adapter->params.arch.nchan = NCHAN;
8548                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8549                 adapter->params.arch.vfcount = 128;
8550                 /* Congestion map is for 4 channels so that
8551                  * MPS can have 4 priority per port.
8552                  */
8553                 adapter->params.arch.cng_ch_bits_log = 2;
8554                 break;
8555         case CHELSIO_T5:
8556                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8557                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8558                 adapter->params.arch.mps_tcam_size =
8559                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8560                 adapter->params.arch.mps_rplc_size = 128;
8561                 adapter->params.arch.nchan = NCHAN;
8562                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8563                 adapter->params.arch.vfcount = 128;
8564                 adapter->params.arch.cng_ch_bits_log = 2;
8565                 break;
8566         case CHELSIO_T6:
8567                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8568                 adapter->params.arch.sge_fl_db = 0;
8569                 adapter->params.arch.mps_tcam_size =
8570                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8571                 adapter->params.arch.mps_rplc_size = 256;
8572                 adapter->params.arch.nchan = 2;
8573                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8574                 adapter->params.arch.vfcount = 256;
8575                 /* Congestion map will be for 2 channels so that
8576                  * MPS can have 8 priority per port.
8577                  */
8578                 adapter->params.arch.cng_ch_bits_log = 3;
8579                 break;
8580         default:
8581                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8582                         device_id);
8583                 return -EINVAL;
8584         }
8585
8586         adapter->params.cim_la_size = CIMLA_SIZE;
8587         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8588
8589         /*
8590          * Default port for debugging in case we can't reach FW.
8591          */
8592         adapter->params.nports = 1;
8593         adapter->params.portvec = 1;
8594         adapter->params.vpd.cclk = 50000;
8595
8596         /* Set pci completion timeout value to 4 seconds. */
8597         set_pcie_completion_timeout(adapter, 0xd);
8598         return 0;
8599 }
8600
8601 /**
8602  *      t4_shutdown_adapter - shut down adapter, host & wire
8603  *      @adapter: the adapter
8604  *
8605  *      Perform an emergency shutdown of the adapter and stop it from
8606  *      continuing any further communication on the ports or DMA to the
8607  *      host.  This is typically used when the adapter and/or firmware
8608  *      have crashed and we want to prevent any further accidental
8609  *      communication with the rest of the world.  This will also force
8610  *      the port Link Status to go down -- if register writes work --
8611  *      which should help our peers figure out that we're down.
8612  */
8613 int t4_shutdown_adapter(struct adapter *adapter)
8614 {
8615         int port;
8616
8617         t4_intr_disable(adapter);
8618         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8619         for_each_port(adapter, port) {
8620                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8621                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
8622                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
8623
8624                 t4_write_reg(adapter, a_port_cfg,
8625                              t4_read_reg(adapter, a_port_cfg)
8626                              & ~SIGNAL_DET_V(1));
8627         }
8628         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8629
8630         return 0;
8631 }
8632
8633 /**
8634  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8635  *      @adapter: the adapter
8636  *      @qid: the Queue ID
8637  *      @qtype: the Ingress or Egress type for @qid
8638  *      @user: true if this request is for a user mode queue
8639  *      @pbar2_qoffset: BAR2 Queue Offset
8640  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8641  *
8642  *      Returns the BAR2 SGE Queue Registers information associated with the
8643  *      indicated Absolute Queue ID.  These are passed back in return value
8644  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8645  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8646  *
8647  *      This may return an error which indicates that BAR2 SGE Queue
8648  *      registers aren't available.  If an error is not returned, then the
8649  *      following values are returned:
8650  *
8651  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8652  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8653  *
8654  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8655  *      require the "Inferred Queue ID" ability may be used.  E.g. the
8656  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8657  *      then these "Inferred Queue ID" register may not be used.
8658  */
8659 int t4_bar2_sge_qregs(struct adapter *adapter,
8660                       unsigned int qid,
8661                       enum t4_bar2_qtype qtype,
8662                       int user,
8663                       u64 *pbar2_qoffset,
8664                       unsigned int *pbar2_qid)
8665 {
8666         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
8667         u64 bar2_page_offset, bar2_qoffset;
8668         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
8669
8670         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8671         if (!user && is_t4(adapter->params.chip))
8672                 return -EINVAL;
8673
8674         /* Get our SGE Page Size parameters.
8675          */
8676         page_shift = adapter->params.sge.hps + 10;
8677         page_size = 1 << page_shift;
8678
8679         /* Get the right Queues per Page parameters for our Queue.
8680          */
8681         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
8682                      ? adapter->params.sge.eq_qpp
8683                      : adapter->params.sge.iq_qpp);
8684         qpp_mask = (1 << qpp_shift) - 1;
8685
8686         /*  Calculate the basics of the BAR2 SGE Queue register area:
8687          *  o The BAR2 page the Queue registers will be in.
8688          *  o The BAR2 Queue ID.
8689          *  o The BAR2 Queue ID Offset into the BAR2 page.
8690          */
8691         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
8692         bar2_qid = qid & qpp_mask;
8693         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
8694
8695         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8696          * hardware will infer the Absolute Queue ID simply from the writes to
8697          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8698          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
8699          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8700          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8701          * from the BAR2 Page and BAR2 Queue ID.
8702          *
8703          * One important censequence of this is that some BAR2 SGE registers
8704          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8705          * there.  But other registers synthesize the SGE Queue ID purely
8706          * from the writes to the registers -- the Write Combined Doorbell
8707          * Buffer is a good example.  These BAR2 SGE Registers are only
8708          * available for those BAR2 SGE Register areas where the SGE Absolute
8709          * Queue ID can be inferred from simple writes.
8710          */
8711         bar2_qoffset = bar2_page_offset;
8712         bar2_qinferred = (bar2_qid_offset < page_size);
8713         if (bar2_qinferred) {
8714                 bar2_qoffset += bar2_qid_offset;
8715                 bar2_qid = 0;
8716         }
8717
8718         *pbar2_qoffset = bar2_qoffset;
8719         *pbar2_qid = bar2_qid;
8720         return 0;
8721 }
8722
8723 /**
8724  *      t4_init_devlog_params - initialize adapter->params.devlog
8725  *      @adap: the adapter
8726  *
8727  *      Initialize various fields of the adapter's Firmware Device Log
8728  *      Parameters structure.
8729  */
8730 int t4_init_devlog_params(struct adapter *adap)
8731 {
8732         struct devlog_params *dparams = &adap->params.devlog;
8733         u32 pf_dparams;
8734         unsigned int devlog_meminfo;
8735         struct fw_devlog_cmd devlog_cmd;
8736         int ret;
8737
8738         /* If we're dealing with newer firmware, the Device Log Paramerters
8739          * are stored in a designated register which allows us to access the
8740          * Device Log even if we can't talk to the firmware.
8741          */
8742         pf_dparams =
8743                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
8744         if (pf_dparams) {
8745                 unsigned int nentries, nentries128;
8746
8747                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
8748                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
8749
8750                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
8751                 nentries = (nentries128 + 1) * 128;
8752                 dparams->size = nentries * sizeof(struct fw_devlog_e);
8753
8754                 return 0;
8755         }
8756
8757         /* Otherwise, ask the firmware for it's Device Log Parameters.
8758          */
8759         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
8760         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
8761                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
8762         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
8763         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
8764                          &devlog_cmd);
8765         if (ret)
8766                 return ret;
8767
8768         devlog_meminfo =
8769                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
8770         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
8771         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
8772         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8773
8774         return 0;
8775 }
8776
8777 /**
8778  *      t4_init_sge_params - initialize adap->params.sge
8779  *      @adapter: the adapter
8780  *
8781  *      Initialize various fields of the adapter's SGE Parameters structure.
8782  */
8783 int t4_init_sge_params(struct adapter *adapter)
8784 {
8785         struct sge_params *sge_params = &adapter->params.sge;
8786         u32 hps, qpp;
8787         unsigned int s_hps, s_qpp;
8788
8789         /* Extract the SGE Page Size for our PF.
8790          */
8791         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
8792         s_hps = (HOSTPAGESIZEPF0_S +
8793                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
8794         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
8795
8796         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8797          */
8798         s_qpp = (QUEUESPERPAGEPF0_S +
8799                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
8800         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
8801         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8802         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
8803         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8804
8805         return 0;
8806 }
8807
8808 /**
8809  *      t4_init_tp_params - initialize adap->params.tp
8810  *      @adap: the adapter
8811  *      @sleep_ok: if true we may sleep while awaiting command completion
8812  *
8813  *      Initialize various fields of the adapter's TP Parameters structure.
8814  */
8815 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
8816 {
8817         int chan;
8818         u32 v;
8819
8820         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
8821         adap->params.tp.tre = TIMERRESOLUTION_G(v);
8822         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
8823
8824         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8825         for (chan = 0; chan < NCHAN; chan++)
8826                 adap->params.tp.tx_modq[chan] = chan;
8827
8828         /* Cache the adapter's Compressed Filter Mode and global Incress
8829          * Configuration.
8830          */
8831         t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
8832                        TP_VLAN_PRI_MAP_A, sleep_ok);
8833         t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
8834                        TP_INGRESS_CONFIG_A, sleep_ok);
8835
8836         /* For T6, cache the adapter's compressed error vector
8837          * and passing outer header info for encapsulated packets.
8838          */
8839         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
8840                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
8841                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
8842         }
8843
8844         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8845          * shift positions of several elements of the Compressed Filter Tuple
8846          * for this adapter which we need frequently ...
8847          */
8848         adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
8849         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
8850         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
8851         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
8852         adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
8853         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
8854                                                                PROTOCOL_F);
8855         adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
8856                                                                 ETHERTYPE_F);
8857         adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
8858                                                                MACMATCH_F);
8859         adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
8860                                                                 MPSHITTYPE_F);
8861         adap->params.tp.frag_shift = t4_filter_field_shift(adap,
8862                                                            FRAGMENTATION_F);
8863
8864         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8865          * represents the presence of an Outer VLAN instead of a VNIC ID.
8866          */
8867         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
8868                 adap->params.tp.vnic_shift = -1;
8869
8870         v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
8871         adap->params.tp.hash_filter_mask = v;
8872         v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
8873         adap->params.tp.hash_filter_mask |= ((u64)v << 32);
8874         return 0;
8875 }
8876
8877 /**
8878  *      t4_filter_field_shift - calculate filter field shift
8879  *      @adap: the adapter
8880  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8881  *
8882  *      Return the shift position of a filter field within the Compressed
8883  *      Filter Tuple.  The filter field is specified via its selection bit
8884  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8885  */
8886 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8887 {
8888         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8889         unsigned int sel;
8890         int field_shift;
8891
8892         if ((filter_mode & filter_sel) == 0)
8893                 return -1;
8894
8895         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8896                 switch (filter_mode & sel) {
8897                 case FCOE_F:
8898                         field_shift += FT_FCOE_W;
8899                         break;
8900                 case PORT_F:
8901                         field_shift += FT_PORT_W;
8902                         break;
8903                 case VNIC_ID_F:
8904                         field_shift += FT_VNIC_ID_W;
8905                         break;
8906                 case VLAN_F:
8907                         field_shift += FT_VLAN_W;
8908                         break;
8909                 case TOS_F:
8910                         field_shift += FT_TOS_W;
8911                         break;
8912                 case PROTOCOL_F:
8913                         field_shift += FT_PROTOCOL_W;
8914                         break;
8915                 case ETHERTYPE_F:
8916                         field_shift += FT_ETHERTYPE_W;
8917                         break;
8918                 case MACMATCH_F:
8919                         field_shift += FT_MACMATCH_W;
8920                         break;
8921                 case MPSHITTYPE_F:
8922                         field_shift += FT_MPSHITTYPE_W;
8923                         break;
8924                 case FRAGMENTATION_F:
8925                         field_shift += FT_FRAGMENTATION_W;
8926                         break;
8927                 }
8928         }
8929         return field_shift;
8930 }
8931
8932 int t4_init_rss_mode(struct adapter *adap, int mbox)
8933 {
8934         int i, ret;
8935         struct fw_rss_vi_config_cmd rvc;
8936
8937         memset(&rvc, 0, sizeof(rvc));
8938
8939         for_each_port(adap, i) {
8940                 struct port_info *p = adap2pinfo(adap, i);
8941
8942                 rvc.op_to_viid =
8943                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
8944                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
8945                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
8946                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
8947                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
8948                 if (ret)
8949                         return ret;
8950                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
8951         }
8952         return 0;
8953 }
8954
8955 /**
8956  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
8957  *      @pi: the port_info
8958  *      @mbox: mailbox to use for the FW command
8959  *      @port: physical port associated with the VI
8960  *      @pf: the PF owning the VI
8961  *      @vf: the VF owning the VI
8962  *      @mac: the MAC address of the VI
8963  *
8964  *      Allocates a virtual interface for the given physical port.  If @mac is
8965  *      not %NULL it contains the MAC address of the VI as assigned by FW.
8966  *      @mac should be large enough to hold an Ethernet address.
8967  *      Returns < 0 on error.
8968  */
8969 int t4_init_portinfo(struct port_info *pi, int mbox,
8970                      int port, int pf, int vf, u8 mac[])
8971 {
8972         struct adapter *adapter = pi->adapter;
8973         unsigned int fw_caps = adapter->params.fw_caps_support;
8974         struct fw_port_cmd cmd;
8975         unsigned int rss_size;
8976         enum fw_port_type port_type;
8977         int mdio_addr;
8978         fw_port_cap32_t pcaps, acaps;
8979         int ret;
8980
8981         /* If we haven't yet determined whether we're talking to Firmware
8982          * which knows the new 32-bit Port Capabilities, it's time to find
8983          * out now.  This will also tell new Firmware to send us Port Status
8984          * Updates using the new 32-bit Port Capabilities version of the
8985          * Port Information message.
8986          */
8987         if (fw_caps == FW_CAPS_UNKNOWN) {
8988                 u32 param, val;
8989
8990                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
8991                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
8992                 val = 1;
8993                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
8994                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
8995                 adapter->params.fw_caps_support = fw_caps;
8996         }
8997
8998         memset(&cmd, 0, sizeof(cmd));
8999         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9000                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
9001                                        FW_PORT_CMD_PORTID_V(port));
9002         cmd.action_to_len16 = cpu_to_be32(
9003                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9004                                      ? FW_PORT_ACTION_GET_PORT_INFO
9005                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
9006                 FW_LEN16(cmd));
9007         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9008         if (ret)
9009                 return ret;
9010
9011         /* Extract the various fields from the Port Information message.
9012          */
9013         if (fw_caps == FW_CAPS16) {
9014                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9015
9016                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9017                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9018                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9019                              : -1);
9020                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9021                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9022         } else {
9023                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9024
9025                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9026                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9027                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9028                              : -1);
9029                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9030                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9031         }
9032
9033         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
9034         if (ret < 0)
9035                 return ret;
9036
9037         pi->viid = ret;
9038         pi->tx_chan = port;
9039         pi->lport = port;
9040         pi->rss_size = rss_size;
9041
9042         pi->port_type = port_type;
9043         pi->mdio_addr = mdio_addr;
9044         pi->mod_type = FW_PORT_MOD_TYPE_NA;
9045
9046         init_link_config(&pi->link_cfg, pcaps, acaps);
9047         return 0;
9048 }
9049
9050 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9051 {
9052         u8 addr[6];
9053         int ret, i, j = 0;
9054
9055         for_each_port(adap, i) {
9056                 struct port_info *pi = adap2pinfo(adap, i);
9057
9058                 while ((adap->params.portvec & (1 << j)) == 0)
9059                         j++;
9060
9061                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9062                 if (ret)
9063                         return ret;
9064
9065                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9066                 j++;
9067         }
9068         return 0;
9069 }
9070
9071 /**
9072  *      t4_read_cimq_cfg - read CIM queue configuration
9073  *      @adap: the adapter
9074  *      @base: holds the queue base addresses in bytes
9075  *      @size: holds the queue sizes in bytes
9076  *      @thres: holds the queue full thresholds in bytes
9077  *
9078  *      Returns the current configuration of the CIM queues, starting with
9079  *      the IBQs, then the OBQs.
9080  */
9081 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9082 {
9083         unsigned int i, v;
9084         int cim_num_obq = is_t4(adap->params.chip) ?
9085                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9086
9087         for (i = 0; i < CIM_NUM_IBQ; i++) {
9088                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9089                              QUENUMSELECT_V(i));
9090                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9091                 /* value is in 256-byte units */
9092                 *base++ = CIMQBASE_G(v) * 256;
9093                 *size++ = CIMQSIZE_G(v) * 256;
9094                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9095         }
9096         for (i = 0; i < cim_num_obq; i++) {
9097                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9098                              QUENUMSELECT_V(i));
9099                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9100                 /* value is in 256-byte units */
9101                 *base++ = CIMQBASE_G(v) * 256;
9102                 *size++ = CIMQSIZE_G(v) * 256;
9103         }
9104 }
9105
9106 /**
9107  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
9108  *      @adap: the adapter
9109  *      @qid: the queue index
9110  *      @data: where to store the queue contents
9111  *      @n: capacity of @data in 32-bit words
9112  *
9113  *      Reads the contents of the selected CIM queue starting at address 0 up
9114  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9115  *      error and the number of 32-bit words actually read on success.
9116  */
9117 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9118 {
9119         int i, err, attempts;
9120         unsigned int addr;
9121         const unsigned int nwords = CIM_IBQ_SIZE * 4;
9122
9123         if (qid > 5 || (n & 3))
9124                 return -EINVAL;
9125
9126         addr = qid * nwords;
9127         if (n > nwords)
9128                 n = nwords;
9129
9130         /* It might take 3-10ms before the IBQ debug read access is allowed.
9131          * Wait for 1 Sec with a delay of 1 usec.
9132          */
9133         attempts = 1000000;
9134
9135         for (i = 0; i < n; i++, addr++) {
9136                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9137                              IBQDBGEN_F);
9138                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9139                                       attempts, 1);
9140                 if (err)
9141                         return err;
9142                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9143         }
9144         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9145         return i;
9146 }
9147
9148 /**
9149  *      t4_read_cim_obq - read the contents of a CIM outbound queue
9150  *      @adap: the adapter
9151  *      @qid: the queue index
9152  *      @data: where to store the queue contents
9153  *      @n: capacity of @data in 32-bit words
9154  *
9155  *      Reads the contents of the selected CIM queue starting at address 0 up
9156  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9157  *      error and the number of 32-bit words actually read on success.
9158  */
9159 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9160 {
9161         int i, err;
9162         unsigned int addr, v, nwords;
9163         int cim_num_obq = is_t4(adap->params.chip) ?
9164                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9165
9166         if ((qid > (cim_num_obq - 1)) || (n & 3))
9167                 return -EINVAL;
9168
9169         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9170                      QUENUMSELECT_V(qid));
9171         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9172
9173         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9174         nwords = CIMQSIZE_G(v) * 64;  /* same */
9175         if (n > nwords)
9176                 n = nwords;
9177
9178         for (i = 0; i < n; i++, addr++) {
9179                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9180                              OBQDBGEN_F);
9181                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9182                                       2, 1);
9183                 if (err)
9184                         return err;
9185                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9186         }
9187         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9188         return i;
9189 }
9190
9191 /**
9192  *      t4_cim_read - read a block from CIM internal address space
9193  *      @adap: the adapter
9194  *      @addr: the start address within the CIM address space
9195  *      @n: number of words to read
9196  *      @valp: where to store the result
9197  *
9198  *      Reads a block of 4-byte words from the CIM intenal address space.
9199  */
9200 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9201                 unsigned int *valp)
9202 {
9203         int ret = 0;
9204
9205         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9206                 return -EBUSY;
9207
9208         for ( ; !ret && n--; addr += 4) {
9209                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9210                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9211                                       0, 5, 2);
9212                 if (!ret)
9213                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9214         }
9215         return ret;
9216 }
9217
9218 /**
9219  *      t4_cim_write - write a block into CIM internal address space
9220  *      @adap: the adapter
9221  *      @addr: the start address within the CIM address space
9222  *      @n: number of words to write
9223  *      @valp: set of values to write
9224  *
9225  *      Writes a block of 4-byte words into the CIM intenal address space.
9226  */
9227 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9228                  const unsigned int *valp)
9229 {
9230         int ret = 0;
9231
9232         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9233                 return -EBUSY;
9234
9235         for ( ; !ret && n--; addr += 4) {
9236                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9237                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9238                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9239                                       0, 5, 2);
9240         }
9241         return ret;
9242 }
9243
9244 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9245                          unsigned int val)
9246 {
9247         return t4_cim_write(adap, addr, 1, &val);
9248 }
9249
9250 /**
9251  *      t4_cim_read_la - read CIM LA capture buffer
9252  *      @adap: the adapter
9253  *      @la_buf: where to store the LA data
9254  *      @wrptr: the HW write pointer within the capture buffer
9255  *
9256  *      Reads the contents of the CIM LA buffer with the most recent entry at
9257  *      the end of the returned data and with the entry at @wrptr first.
9258  *      We try to leave the LA in the running state we find it in.
9259  */
9260 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9261 {
9262         int i, ret;
9263         unsigned int cfg, val, idx;
9264
9265         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9266         if (ret)
9267                 return ret;
9268
9269         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9270                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9271                 if (ret)
9272                         return ret;
9273         }
9274
9275         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9276         if (ret)
9277                 goto restart;
9278
9279         idx = UPDBGLAWRPTR_G(val);
9280         if (wrptr)
9281                 *wrptr = idx;
9282
9283         for (i = 0; i < adap->params.cim_la_size; i++) {
9284                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9285                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9286                 if (ret)
9287                         break;
9288                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9289                 if (ret)
9290                         break;
9291                 if (val & UPDBGLARDEN_F) {
9292                         ret = -ETIMEDOUT;
9293                         break;
9294                 }
9295                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9296                 if (ret)
9297                         break;
9298
9299                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9300                  * identify the 32-bit portion of the full 312-bit data
9301                  */
9302                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9303                         idx = (idx & 0xff0) + 0x10;
9304                 else
9305                         idx++;
9306                 /* address can't exceed 0xfff */
9307                 idx &= UPDBGLARDPTR_M;
9308         }
9309 restart:
9310         if (cfg & UPDBGLAEN_F) {
9311                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9312                                       cfg & ~UPDBGLARDEN_F);
9313                 if (!ret)
9314                         ret = r;
9315         }
9316         return ret;
9317 }
9318
9319 /**
9320  *      t4_tp_read_la - read TP LA capture buffer
9321  *      @adap: the adapter
9322  *      @la_buf: where to store the LA data
9323  *      @wrptr: the HW write pointer within the capture buffer
9324  *
9325  *      Reads the contents of the TP LA buffer with the most recent entry at
9326  *      the end of the returned data and with the entry at @wrptr first.
9327  *      We leave the LA in the running state we find it in.
9328  */
9329 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9330 {
9331         bool last_incomplete;
9332         unsigned int i, cfg, val, idx;
9333
9334         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9335         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9336                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9337                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9338
9339         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9340         idx = DBGLAWPTR_G(val);
9341         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9342         if (last_incomplete)
9343                 idx = (idx + 1) & DBGLARPTR_M;
9344         if (wrptr)
9345                 *wrptr = idx;
9346
9347         val &= 0xffff;
9348         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9349         val |= adap->params.tp.la_mask;
9350
9351         for (i = 0; i < TPLA_SIZE; i++) {
9352                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9353                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9354                 idx = (idx + 1) & DBGLARPTR_M;
9355         }
9356
9357         /* Wipe out last entry if it isn't valid */
9358         if (last_incomplete)
9359                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9360
9361         if (cfg & DBGLAENABLE_F)                    /* restore running state */
9362                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9363                              cfg | adap->params.tp.la_mask);
9364 }
9365
9366 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9367  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9368  * state for more than the Warning Threshold then we'll issue a warning about
9369  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9370  * appears to be hung every Warning Repeat second till the situation clears.
9371  * If the situation clears, we'll note that as well.
9372  */
9373 #define SGE_IDMA_WARN_THRESH 1
9374 #define SGE_IDMA_WARN_REPEAT 300
9375
9376 /**
9377  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9378  *      @adapter: the adapter
9379  *      @idma: the adapter IDMA Monitor state
9380  *
9381  *      Initialize the state of an SGE Ingress DMA Monitor.
9382  */
9383 void t4_idma_monitor_init(struct adapter *adapter,
9384                           struct sge_idma_monitor_state *idma)
9385 {
9386         /* Initialize the state variables for detecting an SGE Ingress DMA
9387          * hang.  The SGE has internal counters which count up on each clock
9388          * tick whenever the SGE finds its Ingress DMA State Engines in the
9389          * same state they were on the previous clock tick.  The clock used is
9390          * the Core Clock so we have a limit on the maximum "time" they can
9391          * record; typically a very small number of seconds.  For instance,
9392          * with a 600MHz Core Clock, we can only count up to a bit more than
9393          * 7s.  So we'll synthesize a larger counter in order to not run the
9394          * risk of having the "timers" overflow and give us the flexibility to
9395          * maintain a Hung SGE State Machine of our own which operates across
9396          * a longer time frame.
9397          */
9398         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9399         idma->idma_stalled[0] = 0;
9400         idma->idma_stalled[1] = 0;
9401 }
9402
9403 /**
9404  *      t4_idma_monitor - monitor SGE Ingress DMA state
9405  *      @adapter: the adapter
9406  *      @idma: the adapter IDMA Monitor state
9407  *      @hz: number of ticks/second
9408  *      @ticks: number of ticks since the last IDMA Monitor call
9409  */
9410 void t4_idma_monitor(struct adapter *adapter,
9411                      struct sge_idma_monitor_state *idma,
9412                      int hz, int ticks)
9413 {
9414         int i, idma_same_state_cnt[2];
9415
9416          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9417           * are counters inside the SGE which count up on each clock when the
9418           * SGE finds its Ingress DMA State Engines in the same states they
9419           * were in the previous clock.  The counters will peg out at
9420           * 0xffffffff without wrapping around so once they pass the 1s
9421           * threshold they'll stay above that till the IDMA state changes.
9422           */
9423         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9424         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9425         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9426
9427         for (i = 0; i < 2; i++) {
9428                 u32 debug0, debug11;
9429
9430                 /* If the Ingress DMA Same State Counter ("timer") is less
9431                  * than 1s, then we can reset our synthesized Stall Timer and
9432                  * continue.  If we have previously emitted warnings about a
9433                  * potential stalled Ingress Queue, issue a note indicating
9434                  * that the Ingress Queue has resumed forward progress.
9435                  */
9436                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9437                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9438                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9439                                          "resumed after %d seconds\n",
9440                                          i, idma->idma_qid[i],
9441                                          idma->idma_stalled[i] / hz);
9442                         idma->idma_stalled[i] = 0;
9443                         continue;
9444                 }
9445
9446                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9447                  * domain.  The first time we get here it'll be because we
9448                  * passed the 1s Threshold; each additional time it'll be
9449                  * because the RX Timer Callback is being fired on its regular
9450                  * schedule.
9451                  *
9452                  * If the stall is below our Potential Hung Ingress Queue
9453                  * Warning Threshold, continue.
9454                  */
9455                 if (idma->idma_stalled[i] == 0) {
9456                         idma->idma_stalled[i] = hz;
9457                         idma->idma_warn[i] = 0;
9458                 } else {
9459                         idma->idma_stalled[i] += ticks;
9460                         idma->idma_warn[i] -= ticks;
9461                 }
9462
9463                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9464                         continue;
9465
9466                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9467                  */
9468                 if (idma->idma_warn[i] > 0)
9469                         continue;
9470                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9471
9472                 /* Read and save the SGE IDMA State and Queue ID information.
9473                  * We do this every time in case it changes across time ...
9474                  * can't be too careful ...
9475                  */
9476                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9477                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9478                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9479
9480                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9481                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9482                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9483
9484                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9485                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9486                          i, idma->idma_qid[i], idma->idma_state[i],
9487                          idma->idma_stalled[i] / hz,
9488                          debug0, debug11);
9489                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9490         }
9491 }
9492
9493 /**
9494  *      t4_load_cfg - download config file
9495  *      @adap: the adapter
9496  *      @cfg_data: the cfg text file to write
9497  *      @size: text file size
9498  *
9499  *      Write the supplied config text file to the card's serial flash.
9500  */
9501 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9502 {
9503         int ret, i, n, cfg_addr;
9504         unsigned int addr;
9505         unsigned int flash_cfg_start_sec;
9506         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9507
9508         cfg_addr = t4_flash_cfg_addr(adap);
9509         if (cfg_addr < 0)
9510                 return cfg_addr;
9511
9512         addr = cfg_addr;
9513         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9514
9515         if (size > FLASH_CFG_MAX_SIZE) {
9516                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9517                         FLASH_CFG_MAX_SIZE);
9518                 return -EFBIG;
9519         }
9520
9521         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
9522                          sf_sec_size);
9523         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9524                                      flash_cfg_start_sec + i - 1);
9525         /* If size == 0 then we're simply erasing the FLASH sectors associated
9526          * with the on-adapter Firmware Configuration File.
9527          */
9528         if (ret || size == 0)
9529                 goto out;
9530
9531         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9532         for (i = 0; i < size; i += SF_PAGE_SIZE) {
9533                 if ((size - i) <  SF_PAGE_SIZE)
9534                         n = size - i;
9535                 else
9536                         n = SF_PAGE_SIZE;
9537                 ret = t4_write_flash(adap, addr, n, cfg_data);
9538                 if (ret)
9539                         goto out;
9540
9541                 addr += SF_PAGE_SIZE;
9542                 cfg_data += SF_PAGE_SIZE;
9543         }
9544
9545 out:
9546         if (ret)
9547                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9548                         (size == 0 ? "clear" : "download"), ret);
9549         return ret;
9550 }
9551
9552 /**
9553  *      t4_set_vf_mac - Set MAC address for the specified VF
9554  *      @adapter: The adapter
9555  *      @vf: one of the VFs instantiated by the specified PF
9556  *      @naddr: the number of MAC addresses
9557  *      @addr: the MAC address(es) to be set to the specified VF
9558  */
9559 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9560                       unsigned int naddr, u8 *addr)
9561 {
9562         struct fw_acl_mac_cmd cmd;
9563
9564         memset(&cmd, 0, sizeof(cmd));
9565         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9566                                     FW_CMD_REQUEST_F |
9567                                     FW_CMD_WRITE_F |
9568                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9569                                     FW_ACL_MAC_CMD_VFN_V(vf));
9570
9571         /* Note: Do not enable the ACL */
9572         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9573         cmd.nmac = naddr;
9574
9575         switch (adapter->pf) {
9576         case 3:
9577                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9578                 break;
9579         case 2:
9580                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9581                 break;
9582         case 1:
9583                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9584                 break;
9585         case 0:
9586                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9587                 break;
9588         }
9589
9590         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9591 }
9592
9593 /**
9594  * t4_read_pace_tbl - read the pace table
9595  * @adap: the adapter
9596  * @pace_vals: holds the returned values
9597  *
9598  * Returns the values of TP's pace table in microseconds.
9599  */
9600 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9601 {
9602         unsigned int i, v;
9603
9604         for (i = 0; i < NTX_SCHED; i++) {
9605                 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
9606                 v = t4_read_reg(adap, TP_PACE_TABLE_A);
9607                 pace_vals[i] = dack_ticks_to_usec(adap, v);
9608         }
9609 }
9610
9611 /**
9612  * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9613  * @adap: the adapter
9614  * @sched: the scheduler index
9615  * @kbps: the byte rate in Kbps
9616  * @ipg: the interpacket delay in tenths of nanoseconds
9617  * @sleep_ok: if true we may sleep while awaiting command completion
9618  *
9619  * Return the current configuration of a HW Tx scheduler.
9620  */
9621 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
9622                      unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
9623 {
9624         unsigned int v, addr, bpt, cpt;
9625
9626         if (kbps) {
9627                 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
9628                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9629                 if (sched & 1)
9630                         v >>= 16;
9631                 bpt = (v >> 8) & 0xff;
9632                 cpt = v & 0xff;
9633                 if (!cpt) {
9634                         *kbps = 0;      /* scheduler disabled */
9635                 } else {
9636                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9637                         *kbps = (v * bpt) / 125;
9638                 }
9639         }
9640         if (ipg) {
9641                 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
9642                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9643                 if (sched & 1)
9644                         v >>= 16;
9645                 v &= 0xffff;
9646                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
9647         }
9648 }
9649
9650 /* t4_sge_ctxt_rd - read an SGE context through FW
9651  * @adap: the adapter
9652  * @mbox: mailbox to use for the FW command
9653  * @cid: the context id
9654  * @ctype: the context type
9655  * @data: where to store the context data
9656  *
9657  * Issues a FW command through the given mailbox to read an SGE context.
9658  */
9659 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9660                    enum ctxt_type ctype, u32 *data)
9661 {
9662         struct fw_ldst_cmd c;
9663         int ret;
9664
9665         if (ctype == CTXT_FLM)
9666                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
9667         else
9668                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
9669
9670         memset(&c, 0, sizeof(c));
9671         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
9672                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
9673                                         FW_LDST_CMD_ADDRSPACE_V(ret));
9674         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9675         c.u.idctxt.physid = cpu_to_be32(cid);
9676
9677         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9678         if (ret == 0) {
9679                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9680                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9681                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9682                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9683                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9684                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9685         }
9686         return ret;
9687 }
9688
9689 /**
9690  * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9691  * @adap: the adapter
9692  * @cid: the context id
9693  * @ctype: the context type
9694  * @data: where to store the context data
9695  *
9696  * Reads an SGE context directly, bypassing FW.  This is only for
9697  * debugging when FW is unavailable.
9698  */
9699 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
9700                       enum ctxt_type ctype, u32 *data)
9701 {
9702         int i, ret;
9703
9704         t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
9705         ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
9706         if (!ret)
9707                 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
9708                         *data++ = t4_read_reg(adap, i);
9709         return ret;
9710 }
9711
9712 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9713                     int rateunit, int ratemode, int channel, int class,
9714                     int minrate, int maxrate, int weight, int pktsize)
9715 {
9716         struct fw_sched_cmd cmd;
9717
9718         memset(&cmd, 0, sizeof(cmd));
9719         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
9720                                       FW_CMD_REQUEST_F |
9721                                       FW_CMD_WRITE_F);
9722         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9723
9724         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9725         cmd.u.params.type = type;
9726         cmd.u.params.level = level;
9727         cmd.u.params.mode = mode;
9728         cmd.u.params.ch = channel;
9729         cmd.u.params.cl = class;
9730         cmd.u.params.unit = rateunit;
9731         cmd.u.params.rate = ratemode;
9732         cmd.u.params.min = cpu_to_be32(minrate);
9733         cmd.u.params.max = cpu_to_be32(maxrate);
9734         cmd.u.params.weight = cpu_to_be16(weight);
9735         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9736
9737         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
9738                                NULL, 1);
9739 }