2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F) {
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 adap->flags &= ~FW_OK;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
211 for ( ; nflit; nflit--, mbox_addr += 8)
212 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
220 struct fw_debug_cmd asrt;
222 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
223 dev_alert(adap->pdev_dev,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
226 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter *adapter,
238 const __be64 *cmd, unsigned int size,
239 int access, int execute)
241 struct mbox_cmd_log *log = adapter->mbox_log;
242 struct mbox_cmd *entry;
245 entry = mbox_cmd_log_entry(log, log->cursor++);
246 if (log->cursor == log->size)
249 for (i = 0; i < size / 8; i++)
250 entry->cmd[i] = be64_to_cpu(cmd[i]);
251 while (i < MBOX_LEN / 8)
253 entry->timestamp = jiffies;
254 entry->seqno = log->seqno++;
255 entry->access = access;
256 entry->execute = execute;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
283 int size, void *rpl, bool sleep_ok, int timeout)
285 static const int delay[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry;
294 int i, ms, delay_idx, ret;
295 const __be64 *p = cmd;
296 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
297 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
298 __be64 cmd_rpl[MBOX_LEN / 8];
301 if ((size & 15) || size > MBOX_LEN)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap->pdev->error_state != pci_channel_io_normal)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap->mbox_lock);
323 list_add_tail(&entry.list, &adap->mlist.list);
324 spin_unlock_bh(&adap->mbox_lock);
329 for (i = 0; ; i += ms) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rearely
333 * contend on access to the mailbox ...
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
336 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
337 spin_lock_bh(&adap->mbox_lock);
338 list_del(&entry.list);
339 spin_unlock_bh(&adap->mbox_lock);
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
341 t4_record_mbox(adap, cmd, size, access, ret);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap->mlist.list, struct mbox_list,
352 /* Delay for a bit before checking again ... */
354 ms = delay[delay_idx]; /* last element may repeat */
355 if (delay_idx < ARRAY_SIZE(delay) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
369 if (v != MBOX_OWNER_DRV) {
370 spin_lock_bh(&adap->mbox_lock);
371 list_del(&entry.list);
372 spin_unlock_bh(&adap->mbox_lock);
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, size, access, ret);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap, cmd, size, access, 0);
380 for (i = 0; i < size; i += 8)
381 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
384 t4_read_reg(adap, ctl_reg); /* flush write */
390 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
394 ms = delay[delay_idx]; /* last element may repeat */
395 if (delay_idx < ARRAY_SIZE(delay) - 1)
401 v = t4_read_reg(adap, ctl_reg);
402 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
403 if (!(v & MBMSGVALID_F)) {
404 t4_write_reg(adap, ctl_reg, 0);
408 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
409 res = be64_to_cpu(cmd_rpl[0]);
411 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
412 fw_asrt(adap, data_reg);
413 res = FW_CMD_RETVAL_V(EIO);
415 memcpy(rpl, cmd_rpl, size);
418 t4_write_reg(adap, ctl_reg, 0);
421 t4_record_mbox(adap, cmd_rpl,
422 MBOX_LEN, access, execute);
423 spin_lock_bh(&adap->mbox_lock);
424 list_del(&entry.list);
425 spin_unlock_bh(&adap->mbox_lock);
426 return -FW_CMD_RETVAL_G((int)res);
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
431 t4_record_mbox(adap, cmd, size, access, ret);
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
433 *(const u8 *)cmd, mbox);
434 t4_report_fw_error(adap);
435 spin_lock_bh(&adap->mbox_lock);
436 list_del(&entry.list);
437 spin_unlock_bh(&adap->mbox_lock);
442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
443 void *rpl, bool sleep_ok)
445 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
449 static int t4_edc_err_read(struct adapter *adap, int idx)
451 u32 edc_ecc_err_addr_reg;
454 if (is_t4(adap->params.chip)) {
455 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
458 if (idx != 0 && idx != 1) {
459 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
463 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
464 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx, edc_ecc_err_addr_reg,
469 t4_read_reg(adap, edc_ecc_err_addr_reg));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap, rdata_reg),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
498 u32 *mem_base, u32 *mem_aperture)
500 u32 edc_size, mc_size, mem_reg;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
510 if (mtype == MEM_HMA) {
511 *mem_off = 2 * (edc_size * 1024 * 1024);
512 } else if (mtype != MEM_MC1) {
513 *mem_off = (mtype * (edc_size * 1024 * 1024));
515 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
516 MA_EXT_MEMORY0_BAR_A));
517 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg = t4_read_reg(adap,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg == 0xffffffff)
535 *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
536 *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
537 if (is_t4(adap->params.chip))
538 *mem_base -= adap->t4_bar0;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
583 if (dir == T4_MEMORY_READ) {
584 last.word = le32_to_cpu((__force __le32)
585 t4_read_reg(adap, addr));
586 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
587 bp[i] = last.byte[i];
590 for (i = off; i < 4; i++)
592 t4_write_reg(adap, addr,
593 (__force u32)cpu_to_le32(last.word));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boudaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
615 u32 len, void *hbuf, int dir)
617 u32 pos, offset, resid, memoffset;
618 u32 win_pf, mem_aperture, mem_base;
622 /* Argument sanity checks ...
624 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr = addr + memoffset;
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos = addr & ~(mem_aperture - 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap, win, pos | win_pf);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir == T4_MEMORY_READ)
693 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
696 t4_write_reg(adap, mem_base + offset,
697 (__force u32)cpu_to_le32(*buf++));
698 offset += sizeof(__be32);
699 len -= sizeof(__be32);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset == mem_aperture) {
710 t4_memory_update_win(adap, win, pos | win_pf);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap, resid, mem_base + offset,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
733 u32 val, ldst_addrspace;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd;
741 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
742 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
743 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
747 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
748 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd.u.pcie.ctrl_to_fn =
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
751 ldst_cmd.u.pcie.r = reg;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
759 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap, reg, &val);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
777 if (is_t4(adap->params.chip)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0 = t4_read_pcie_cfg4(adap, pci_base);
791 adap->t4_bar0 = bar0;
793 ret = bar0 + memwin_base;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32 t4_get_util_window(struct adapter *adap)
804 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
805 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
816 memwin_base | BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter *adapter)
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
832 switch (chip_version) {
834 return T4_REGMAP_SIZE;
838 return T5_REGMAP_SIZE;
841 dev_err(adapter->pdev_dev,
842 "Unsupported chip version %d\n", chip_version);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
858 static const unsigned int t4_reg_ranges[] = {
1317 static const unsigned int t5_reg_ranges[] = {
2084 static const unsigned int t6_reg_ranges[] = {
2645 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2646 const unsigned int *reg_ranges;
2647 int reg_ranges_size, range;
2648 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2650 /* Select the right set of register ranges to dump depending on the
2651 * adapter chip type.
2653 switch (chip_version) {
2655 reg_ranges = t4_reg_ranges;
2656 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2660 reg_ranges = t5_reg_ranges;
2661 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2665 reg_ranges = t6_reg_ranges;
2666 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2670 dev_err(adap->pdev_dev,
2671 "Unsupported chip version %d\n", chip_version);
2675 /* Clear the register buffer and insert the appropriate register
2676 * values selected by the above register ranges.
2678 memset(buf, 0, buf_size);
2679 for (range = 0; range < reg_ranges_size; range += 2) {
2680 unsigned int reg = reg_ranges[range];
2681 unsigned int last_reg = reg_ranges[range + 1];
2682 u32 *bufp = (u32 *)((char *)buf + reg);
2684 /* Iterate across the register range filling in the register
2685 * buffer but don't write past the end of the register buffer.
2687 while (reg <= last_reg && bufp < buf_end) {
2688 *bufp++ = t4_read_reg(adap, reg);
2694 #define EEPROM_STAT_ADDR 0x7bfc
2695 #define VPD_BASE 0x400
2696 #define VPD_BASE_OLD 0
2697 #define VPD_LEN 1024
2698 #define CHELSIO_VPD_UNIQUE_ID 0x82
2701 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2702 * @phys_addr: the physical EEPROM address
2703 * @fn: the PCI function number
2704 * @sz: size of function-specific area
2706 * Translate a physical EEPROM address to virtual. The first 1K is
2707 * accessed through virtual addresses starting at 31K, the rest is
2708 * accessed through virtual addresses starting at 0.
2710 * The mapping is as follows:
2711 * [0..1K) -> [31K..32K)
2712 * [1K..1K+A) -> [31K-A..31K)
2713 * [1K+A..ES) -> [0..ES-A-1K)
2715 * where A = @fn * @sz, and ES = EEPROM size.
2717 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2720 if (phys_addr < 1024)
2721 return phys_addr + (31 << 10);
2722 if (phys_addr < 1024 + fn)
2723 return 31744 - fn + phys_addr - 1024;
2724 if (phys_addr < EEPROMSIZE)
2725 return phys_addr - 1024 - fn;
2730 * t4_seeprom_wp - enable/disable EEPROM write protection
2731 * @adapter: the adapter
2732 * @enable: whether to enable or disable write protection
2734 * Enables or disables write protection on the serial EEPROM.
2736 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2738 unsigned int v = enable ? 0xc : 0;
2739 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2740 return ret < 0 ? ret : 0;
2744 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2745 * @adapter: adapter to read
2746 * @p: where to store the parameters
2748 * Reads card parameters stored in VPD EEPROM.
2750 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2752 int i, ret = 0, addr;
2755 unsigned int vpdr_len, kw_offset, id_len;
2757 vpd = vmalloc(VPD_LEN);
2761 /* Card information normally starts at VPD_BASE but early cards had
2764 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2768 /* The VPD shall have a unique identifier specified by the PCI SIG.
2769 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2770 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2771 * is expected to automatically put this entry at the
2772 * beginning of the VPD.
2774 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2776 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2780 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2781 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2786 id_len = pci_vpd_lrdt_size(vpd);
2787 if (id_len > ID_LEN)
2790 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2792 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2797 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2798 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2799 if (vpdr_len + kw_offset > VPD_LEN) {
2800 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2805 #define FIND_VPD_KW(var, name) do { \
2806 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2808 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2812 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2815 FIND_VPD_KW(i, "RV");
2816 for (csum = 0; i >= 0; i--)
2820 dev_err(adapter->pdev_dev,
2821 "corrupted VPD EEPROM, actual csum %u\n", csum);
2826 FIND_VPD_KW(ec, "EC");
2827 FIND_VPD_KW(sn, "SN");
2828 FIND_VPD_KW(pn, "PN");
2829 FIND_VPD_KW(na, "NA");
2832 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2834 memcpy(p->ec, vpd + ec, EC_LEN);
2836 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2837 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2839 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2840 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2842 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2843 strim((char *)p->na);
2847 return ret < 0 ? ret : 0;
2851 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2852 * @adapter: adapter to read
2853 * @p: where to store the parameters
2855 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2856 * Clock. This can only be called after a connection to the firmware
2859 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2861 u32 cclk_param, cclk_val;
2864 /* Grab the raw VPD parameters.
2866 ret = t4_get_raw_vpd_params(adapter, p);
2870 /* Ask firmware for the Core Clock since it knows how to translate the
2871 * Reference Clock ('V2') VPD field into a Core Clock value ...
2873 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2874 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2875 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2876 1, &cclk_param, &cclk_val);
2885 /* serial flash and firmware constants */
2887 SF_ATTEMPTS = 10, /* max retries for SF operations */
2889 /* flash command opcodes */
2890 SF_PROG_PAGE = 2, /* program page */
2891 SF_WR_DISABLE = 4, /* disable writes */
2892 SF_RD_STATUS = 5, /* read status register */
2893 SF_WR_ENABLE = 6, /* enable writes */
2894 SF_RD_DATA_FAST = 0xb, /* read flash */
2895 SF_RD_ID = 0x9f, /* read ID */
2896 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2900 * sf1_read - read data from the serial flash
2901 * @adapter: the adapter
2902 * @byte_cnt: number of bytes to read
2903 * @cont: whether another operation will be chained
2904 * @lock: whether to lock SF for PL access only
2905 * @valp: where to store the read data
2907 * Reads up to 4 bytes of data from the serial flash. The location of
2908 * the read needs to be specified prior to calling this by issuing the
2909 * appropriate commands to the serial flash.
2911 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2912 int lock, u32 *valp)
2916 if (!byte_cnt || byte_cnt > 4)
2918 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2920 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2921 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2922 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2924 *valp = t4_read_reg(adapter, SF_DATA_A);
2929 * sf1_write - write data to the serial flash
2930 * @adapter: the adapter
2931 * @byte_cnt: number of bytes to write
2932 * @cont: whether another operation will be chained
2933 * @lock: whether to lock SF for PL access only
2934 * @val: value to write
2936 * Writes up to 4 bytes of data to the serial flash. The location of
2937 * the write needs to be specified prior to calling this by issuing the
2938 * appropriate commands to the serial flash.
2940 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2943 if (!byte_cnt || byte_cnt > 4)
2945 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2947 t4_write_reg(adapter, SF_DATA_A, val);
2948 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2949 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2950 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2954 * flash_wait_op - wait for a flash operation to complete
2955 * @adapter: the adapter
2956 * @attempts: max number of polls of the status register
2957 * @delay: delay between polls in ms
2959 * Wait for a flash operation to complete by polling the status register.
2961 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2967 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2968 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2972 if (--attempts == 0)
2980 * t4_read_flash - read words from serial flash
2981 * @adapter: the adapter
2982 * @addr: the start address for the read
2983 * @nwords: how many 32-bit words to read
2984 * @data: where to store the read data
2985 * @byte_oriented: whether to store data as bytes or as words
2987 * Read the specified number of 32-bit words from the serial flash.
2988 * If @byte_oriented is set the read data is stored as a byte array
2989 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2990 * natural endianness.
2992 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2993 unsigned int nwords, u32 *data, int byte_oriented)
2997 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3000 addr = swab32(addr) | SF_RD_DATA_FAST;
3002 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3003 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3006 for ( ; nwords; nwords--, data++) {
3007 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3009 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3013 *data = (__force __u32)(cpu_to_be32(*data));
3019 * t4_write_flash - write up to a page of data to the serial flash
3020 * @adapter: the adapter
3021 * @addr: the start address to write
3022 * @n: length of data to write in bytes
3023 * @data: the data to write
3025 * Writes up to a page of data (256 bytes) to the serial flash starting
3026 * at the given address. All the data must be written to the same page.
3028 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3029 unsigned int n, const u8 *data)
3033 unsigned int i, c, left, val, offset = addr & 0xff;
3035 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3038 val = swab32(addr) | SF_PROG_PAGE;
3040 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3041 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3044 for (left = n; left; left -= c) {
3046 for (val = 0, i = 0; i < c; ++i)
3047 val = (val << 8) + *data++;
3049 ret = sf1_write(adapter, c, c != left, 1, val);
3053 ret = flash_wait_op(adapter, 8, 1);
3057 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3059 /* Read the page to verify the write succeeded */
3060 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3064 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3065 dev_err(adapter->pdev_dev,
3066 "failed to correctly write the flash page at %#x\n",
3073 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3078 * t4_get_fw_version - read the firmware version
3079 * @adapter: the adapter
3080 * @vers: where to place the version
3082 * Reads the FW version from flash.
3084 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3086 return t4_read_flash(adapter, FLASH_FW_START +
3087 offsetof(struct fw_hdr, fw_ver), 1,
3092 * t4_get_bs_version - read the firmware bootstrap version
3093 * @adapter: the adapter
3094 * @vers: where to place the version
3096 * Reads the FW Bootstrap version from flash.
3098 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3100 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3101 offsetof(struct fw_hdr, fw_ver), 1,
3106 * t4_get_tp_version - read the TP microcode version
3107 * @adapter: the adapter
3108 * @vers: where to place the version
3110 * Reads the TP microcode version from flash.
3112 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3114 return t4_read_flash(adapter, FLASH_FW_START +
3115 offsetof(struct fw_hdr, tp_microcode_ver),
3120 * t4_get_exprom_version - return the Expansion ROM version (if any)
3121 * @adapter: the adapter
3122 * @vers: where to place the version
3124 * Reads the Expansion ROM header from FLASH and returns the version
3125 * number (if present) through the @vers return value pointer. We return
3126 * this in the Firmware Version Format since it's convenient. Return
3127 * 0 on success, -ENOENT if no Expansion ROM is present.
3129 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3131 struct exprom_header {
3132 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3133 unsigned char hdr_ver[4]; /* Expansion ROM version */
3135 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3139 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3140 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3145 hdr = (struct exprom_header *)exprom_header_buf;
3146 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3149 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3150 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3151 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3152 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3157 * t4_get_vpd_version - return the VPD version
3158 * @adapter: the adapter
3159 * @vers: where to place the version
3161 * Reads the VPD via the Firmware interface (thus this can only be called
3162 * once we're ready to issue Firmware commands). The format of the
3163 * VPD version is adapter specific. Returns 0 on success, an error on
3166 * Note that early versions of the Firmware didn't include the ability
3167 * to retrieve the VPD version, so we zero-out the return-value parameter
3168 * in that case to avoid leaving it with garbage in it.
3170 * Also note that the Firmware will return its cached copy of the VPD
3171 * Revision ID, not the actual Revision ID as written in the Serial
3172 * EEPROM. This is only an issue if a new VPD has been written and the
3173 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3174 * to defer calling this routine till after a FW_RESET_CMD has been issued
3175 * if the Host Driver will be performing a full adapter initialization.
3177 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3182 vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3183 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3184 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3185 1, &vpdrev_param, vers);
3192 * t4_get_scfg_version - return the Serial Configuration version
3193 * @adapter: the adapter
3194 * @vers: where to place the version
3196 * Reads the Serial Configuration Version via the Firmware interface
3197 * (thus this can only be called once we're ready to issue Firmware
3198 * commands). The format of the Serial Configuration version is
3199 * adapter specific. Returns 0 on success, an error on failure.
3201 * Note that early versions of the Firmware didn't include the ability
3202 * to retrieve the Serial Configuration version, so we zero-out the
3203 * return-value parameter in that case to avoid leaving it with
3206 * Also note that the Firmware will return its cached copy of the Serial
3207 * Initialization Revision ID, not the actual Revision ID as written in
3208 * the Serial EEPROM. This is only an issue if a new VPD has been written
3209 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3210 * it's best to defer calling this routine till after a FW_RESET_CMD has
3211 * been issued if the Host Driver will be performing a full adapter
3214 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3219 scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3220 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3221 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3222 1, &scfgrev_param, vers);
3229 * t4_get_version_info - extract various chip/firmware version information
3230 * @adapter: the adapter
3232 * Reads various chip/firmware version numbers and stores them into the
3233 * adapter Adapter Parameters structure. If any of the efforts fails
3234 * the first failure will be returned, but all of the version numbers
3237 int t4_get_version_info(struct adapter *adapter)
3241 #define FIRST_RET(__getvinfo) \
3243 int __ret = __getvinfo; \
3244 if (__ret && !ret) \
3248 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3249 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3250 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3251 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3252 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3253 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3260 * t4_dump_version_info - dump all of the adapter configuration IDs
3261 * @adapter: the adapter
3263 * Dumps all of the various bits of adapter configuration version/revision
3264 * IDs information. This is typically called at some point after
3265 * t4_get_version_info() has been called.
3267 void t4_dump_version_info(struct adapter *adapter)
3269 /* Device information */
3270 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3271 adapter->params.vpd.id,
3272 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3273 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3274 adapter->params.vpd.sn, adapter->params.vpd.pn);
3276 /* Firmware Version */
3277 if (!adapter->params.fw_vers)
3278 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3280 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3281 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3282 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3283 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3284 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3286 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3287 * Firmware, so dev_info() is more appropriate here.)
3289 if (!adapter->params.bs_vers)
3290 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3292 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3293 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3294 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3295 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3296 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3298 /* TP Microcode Version */
3299 if (!adapter->params.tp_vers)
3300 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3302 dev_info(adapter->pdev_dev,
3303 "TP Microcode version: %u.%u.%u.%u\n",
3304 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3305 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3306 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3307 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3309 /* Expansion ROM version */
3310 if (!adapter->params.er_vers)
3311 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3313 dev_info(adapter->pdev_dev,
3314 "Expansion ROM version: %u.%u.%u.%u\n",
3315 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3316 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3317 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3318 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3320 /* Serial Configuration version */
3321 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3322 adapter->params.scfg_vers);
3325 dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3326 adapter->params.vpd_vers);
3330 * t4_check_fw_version - check if the FW is supported with this driver
3331 * @adap: the adapter
3333 * Checks if an adapter's FW is compatible with the driver. Returns 0
3334 * if there's exact match, a negative error if the version could not be
3335 * read or there's a major version mismatch
3337 int t4_check_fw_version(struct adapter *adap)
3339 int i, ret, major, minor, micro;
3340 int exp_major, exp_minor, exp_micro;
3341 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3343 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3344 /* Try multiple times before returning error */
3345 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3346 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3351 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3352 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3353 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3355 switch (chip_version) {
3357 exp_major = T4FW_MIN_VERSION_MAJOR;
3358 exp_minor = T4FW_MIN_VERSION_MINOR;
3359 exp_micro = T4FW_MIN_VERSION_MICRO;
3362 exp_major = T5FW_MIN_VERSION_MAJOR;
3363 exp_minor = T5FW_MIN_VERSION_MINOR;
3364 exp_micro = T5FW_MIN_VERSION_MICRO;
3367 exp_major = T6FW_MIN_VERSION_MAJOR;
3368 exp_minor = T6FW_MIN_VERSION_MINOR;
3369 exp_micro = T6FW_MIN_VERSION_MICRO;
3372 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3377 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3378 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3379 dev_err(adap->pdev_dev,
3380 "Card has firmware version %u.%u.%u, minimum "
3381 "supported firmware is %u.%u.%u.\n", major, minor,
3382 micro, exp_major, exp_minor, exp_micro);
3388 /* Is the given firmware API compatible with the one the driver was compiled
3391 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3394 /* short circuit if it's the exact same firmware version */
3395 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3398 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3399 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3400 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3407 /* The firmware in the filesystem is usable, but should it be installed?
3408 * This routine explains itself in detail if it indicates the filesystem
3409 * firmware should be installed.
3411 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3416 if (!card_fw_usable) {
3417 reason = "incompatible or unusable";
3422 reason = "older than the version supported with this driver";
3429 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3430 "installing firmware %u.%u.%u.%u on card.\n",
3431 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3432 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3433 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3434 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3439 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3440 const u8 *fw_data, unsigned int fw_size,
3441 struct fw_hdr *card_fw, enum dev_state state,
3444 int ret, card_fw_usable, fs_fw_usable;
3445 const struct fw_hdr *fs_fw;
3446 const struct fw_hdr *drv_fw;
3448 drv_fw = &fw_info->fw_hdr;
3450 /* Read the header of the firmware on the card */
3451 ret = -t4_read_flash(adap, FLASH_FW_START,
3452 sizeof(*card_fw) / sizeof(uint32_t),
3453 (uint32_t *)card_fw, 1);
3455 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3457 dev_err(adap->pdev_dev,
3458 "Unable to read card's firmware header: %d\n", ret);
3462 if (fw_data != NULL) {
3463 fs_fw = (const void *)fw_data;
3464 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3470 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3471 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3472 /* Common case: the firmware on the card is an exact match and
3473 * the filesystem one is an exact match too, or the filesystem
3474 * one is absent/incompatible.
3476 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3477 should_install_fs_fw(adap, card_fw_usable,
3478 be32_to_cpu(fs_fw->fw_ver),
3479 be32_to_cpu(card_fw->fw_ver))) {
3480 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3483 dev_err(adap->pdev_dev,
3484 "failed to install firmware: %d\n", ret);
3488 /* Installed successfully, update the cached header too. */
3491 *reset = 0; /* already reset as part of load_fw */
3494 if (!card_fw_usable) {
3497 d = be32_to_cpu(drv_fw->fw_ver);
3498 c = be32_to_cpu(card_fw->fw_ver);
3499 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3501 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3503 "driver compiled with %d.%d.%d.%d, "
3504 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3506 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3507 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3508 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3509 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3510 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3511 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3516 /* We're using whatever's on the card and it's known to be good. */
3517 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3518 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3525 * t4_flash_erase_sectors - erase a range of flash sectors
3526 * @adapter: the adapter
3527 * @start: the first sector to erase
3528 * @end: the last sector to erase
3530 * Erases the sectors in the given inclusive range.
3532 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3536 if (end >= adapter->params.sf_nsec)
3539 while (start <= end) {
3540 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3541 (ret = sf1_write(adapter, 4, 0, 1,
3542 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3543 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3544 dev_err(adapter->pdev_dev,
3545 "erase of flash sector %d failed, error %d\n",
3551 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3556 * t4_flash_cfg_addr - return the address of the flash configuration file
3557 * @adapter: the adapter
3559 * Return the address within the flash where the Firmware Configuration
3562 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3564 if (adapter->params.sf_size == 0x100000)
3565 return FLASH_FPGA_CFG_START;
3567 return FLASH_CFG_START;
3570 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3571 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3572 * and emit an error message for mismatched firmware to save our caller the
3575 static bool t4_fw_matches_chip(const struct adapter *adap,
3576 const struct fw_hdr *hdr)
3578 /* The expression below will return FALSE for any unsupported adapter
3579 * which will keep us "honest" in the future ...
3581 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3582 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3583 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3586 dev_err(adap->pdev_dev,
3587 "FW image (%d) is not suitable for this adapter (%d)\n",
3588 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3593 * t4_load_fw - download firmware
3594 * @adap: the adapter
3595 * @fw_data: the firmware image to write
3598 * Write the supplied firmware image to the card's serial flash.
3600 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3605 u8 first_page[SF_PAGE_SIZE];
3606 const __be32 *p = (const __be32 *)fw_data;
3607 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3608 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3609 unsigned int fw_start_sec = FLASH_FW_START_SEC;
3610 unsigned int fw_size = FLASH_FW_MAX_SIZE;
3611 unsigned int fw_start = FLASH_FW_START;
3614 dev_err(adap->pdev_dev, "FW image has no data\n");
3618 dev_err(adap->pdev_dev,
3619 "FW image size not multiple of 512 bytes\n");
3622 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3623 dev_err(adap->pdev_dev,
3624 "FW image size differs from size in FW header\n");
3627 if (size > fw_size) {
3628 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3632 if (!t4_fw_matches_chip(adap, hdr))
3635 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3636 csum += be32_to_cpu(p[i]);
3638 if (csum != 0xffffffff) {
3639 dev_err(adap->pdev_dev,
3640 "corrupted firmware image, checksum %#x\n", csum);
3644 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3645 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3650 * We write the correct version at the end so the driver can see a bad
3651 * version if the FW write fails. Start by writing a copy of the
3652 * first page with a bad version.
3654 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3655 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3656 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3661 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3662 addr += SF_PAGE_SIZE;
3663 fw_data += SF_PAGE_SIZE;
3664 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3669 ret = t4_write_flash(adap,
3670 fw_start + offsetof(struct fw_hdr, fw_ver),
3671 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3674 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3677 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3682 * t4_phy_fw_ver - return current PHY firmware version
3683 * @adap: the adapter
3684 * @phy_fw_ver: return value buffer for PHY firmware version
3686 * Returns the current version of external PHY firmware on the
3689 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3694 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3695 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3696 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3697 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3698 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3707 * t4_load_phy_fw - download port PHY firmware
3708 * @adap: the adapter
3709 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3710 * @win_lock: the lock to use to guard the memory copy
3711 * @phy_fw_version: function to check PHY firmware versions
3712 * @phy_fw_data: the PHY firmware image to write
3713 * @phy_fw_size: image size
3715 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3716 * @phy_fw_version is supplied, then it will be used to determine if
3717 * it's necessary to perform the transfer by comparing the version
3718 * of any existing adapter PHY firmware with that of the passed in
3719 * PHY firmware image. If @win_lock is non-NULL then it will be used
3720 * around the call to t4_memory_rw() which transfers the PHY firmware
3723 * A negative error number will be returned if an error occurs. If
3724 * version number support is available and there's no need to upgrade
3725 * the firmware, 0 will be returned. If firmware is successfully
3726 * transferred to the adapter, 1 will be retured.
3728 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3729 * a result, a RESET of the adapter would cause that RAM to lose its
3730 * contents. Thus, loading PHY firmware on such adapters must happen
3731 * after any FW_RESET_CMDs ...
3733 int t4_load_phy_fw(struct adapter *adap,
3734 int win, spinlock_t *win_lock,
3735 int (*phy_fw_version)(const u8 *, size_t),
3736 const u8 *phy_fw_data, size_t phy_fw_size)
3738 unsigned long mtype = 0, maddr = 0;
3740 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3743 /* If we have version number support, then check to see if the adapter
3744 * already has up-to-date PHY firmware loaded.
3746 if (phy_fw_version) {
3747 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3748 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3752 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3753 CH_WARN(adap, "PHY Firmware already up-to-date, "
3754 "version %#x\n", cur_phy_fw_ver);
3759 /* Ask the firmware where it wants us to copy the PHY firmware image.
3760 * The size of the file requires a special version of the READ coommand
3761 * which will pass the file size via the values field in PARAMS_CMD and
3762 * retrieve the return value from firmware and place it in the same
3765 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3766 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3767 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3768 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3770 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3771 ¶m, &val, 1, true);
3775 maddr = (val & 0xff) << 16;
3777 /* Copy the supplied PHY Firmware image to the adapter memory location
3778 * allocated by the adapter firmware.
3781 spin_lock_bh(win_lock);
3782 ret = t4_memory_rw(adap, win, mtype, maddr,
3783 phy_fw_size, (__be32 *)phy_fw_data,
3786 spin_unlock_bh(win_lock);
3790 /* Tell the firmware that the PHY firmware image has been written to
3791 * RAM and it can now start copying it over to the PHYs. The chip
3792 * firmware will RESET the affected PHYs as part of this operation
3793 * leaving them running the new PHY firmware image.
3795 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3796 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3797 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3798 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3799 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3800 ¶m, &val, 30000);
3802 /* If we have version number support, then check to see that the new
3803 * firmware got loaded properly.
3805 if (phy_fw_version) {
3806 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3810 if (cur_phy_fw_ver != new_phy_fw_vers) {
3811 CH_WARN(adap, "PHY Firmware did not update: "
3812 "version on adapter %#x, "
3813 "version flashed %#x\n",
3814 cur_phy_fw_ver, new_phy_fw_vers);
3823 * t4_fwcache - firmware cache operation
3824 * @adap: the adapter
3825 * @op : the operation (flush or flush and invalidate)
3827 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3829 struct fw_params_cmd c;
3831 memset(&c, 0, sizeof(c));
3833 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3834 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3835 FW_PARAMS_CMD_PFN_V(adap->pf) |
3836 FW_PARAMS_CMD_VFN_V(0));
3837 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3839 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3840 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3841 c.param[0].val = (__force __be32)op;
3843 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3846 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3847 unsigned int *pif_req_wrptr,
3848 unsigned int *pif_rsp_wrptr)
3851 u32 cfg, val, req, rsp;
3853 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3854 if (cfg & LADBGEN_F)
3855 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3857 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3858 req = POLADBGWRPTR_G(val);
3859 rsp = PILADBGWRPTR_G(val);
3861 *pif_req_wrptr = req;
3863 *pif_rsp_wrptr = rsp;
3865 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3866 for (j = 0; j < 6; j++) {
3867 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3868 PILADBGRDPTR_V(rsp));
3869 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3870 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3874 req = (req + 2) & POLADBGRDPTR_M;
3875 rsp = (rsp + 2) & PILADBGRDPTR_M;
3877 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3880 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3885 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3886 if (cfg & LADBGEN_F)
3887 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3889 for (i = 0; i < CIM_MALA_SIZE; i++) {
3890 for (j = 0; j < 5; j++) {
3892 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3893 PILADBGRDPTR_V(idx));
3894 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3895 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3898 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3901 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3905 for (i = 0; i < 8; i++) {
3906 u32 *p = la_buf + i;
3908 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3909 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3910 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3911 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3912 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3916 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3920 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3921 * @caps16: a 16-bit Port Capabilities value
3923 * Returns the equivalent 32-bit Port Capabilities value.
3925 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3927 fw_port_cap32_t caps32 = 0;
3929 #define CAP16_TO_CAP32(__cap) \
3931 if (caps16 & FW_PORT_CAP_##__cap) \
3932 caps32 |= FW_PORT_CAP32_##__cap; \
3935 CAP16_TO_CAP32(SPEED_100M);
3936 CAP16_TO_CAP32(SPEED_1G);
3937 CAP16_TO_CAP32(SPEED_25G);
3938 CAP16_TO_CAP32(SPEED_10G);
3939 CAP16_TO_CAP32(SPEED_40G);
3940 CAP16_TO_CAP32(SPEED_100G);
3941 CAP16_TO_CAP32(FC_RX);
3942 CAP16_TO_CAP32(FC_TX);
3943 CAP16_TO_CAP32(ANEG);
3944 CAP16_TO_CAP32(MDIX);
3945 CAP16_TO_CAP32(MDIAUTO);
3946 CAP16_TO_CAP32(FEC_RS);
3947 CAP16_TO_CAP32(FEC_BASER_RS);
3948 CAP16_TO_CAP32(802_3_PAUSE);
3949 CAP16_TO_CAP32(802_3_ASM_DIR);
3951 #undef CAP16_TO_CAP32
3957 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3958 * @caps32: a 32-bit Port Capabilities value
3960 * Returns the equivalent 16-bit Port Capabilities value. Note that
3961 * not all 32-bit Port Capabilities can be represented in the 16-bit
3962 * Port Capabilities and some fields/values may not make it.
3964 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3966 fw_port_cap16_t caps16 = 0;
3968 #define CAP32_TO_CAP16(__cap) \
3970 if (caps32 & FW_PORT_CAP32_##__cap) \
3971 caps16 |= FW_PORT_CAP_##__cap; \
3974 CAP32_TO_CAP16(SPEED_100M);
3975 CAP32_TO_CAP16(SPEED_1G);
3976 CAP32_TO_CAP16(SPEED_10G);
3977 CAP32_TO_CAP16(SPEED_25G);
3978 CAP32_TO_CAP16(SPEED_40G);
3979 CAP32_TO_CAP16(SPEED_100G);
3980 CAP32_TO_CAP16(FC_RX);
3981 CAP32_TO_CAP16(FC_TX);
3982 CAP32_TO_CAP16(802_3_PAUSE);
3983 CAP32_TO_CAP16(802_3_ASM_DIR);
3984 CAP32_TO_CAP16(ANEG);
3985 CAP32_TO_CAP16(MDIX);
3986 CAP32_TO_CAP16(MDIAUTO);
3987 CAP32_TO_CAP16(FEC_RS);
3988 CAP32_TO_CAP16(FEC_BASER_RS);
3990 #undef CAP32_TO_CAP16
3995 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3996 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
3998 enum cc_pause cc_pause = 0;
4000 if (fw_pause & FW_PORT_CAP32_FC_RX)
4001 cc_pause |= PAUSE_RX;
4002 if (fw_pause & FW_PORT_CAP32_FC_TX)
4003 cc_pause |= PAUSE_TX;
4008 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4009 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4011 fw_port_cap32_t fw_pause = 0;
4013 if (cc_pause & PAUSE_RX)
4014 fw_pause |= FW_PORT_CAP32_FC_RX;
4015 if (cc_pause & PAUSE_TX)
4016 fw_pause |= FW_PORT_CAP32_FC_TX;
4021 /* Translate Firmware Forward Error Correction specification to Common Code */
4022 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4024 enum cc_fec cc_fec = 0;
4026 if (fw_fec & FW_PORT_CAP32_FEC_RS)
4028 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4029 cc_fec |= FEC_BASER_RS;
4034 /* Translate Common Code Forward Error Correction specification to Firmware */
4035 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4037 fw_port_cap32_t fw_fec = 0;
4039 if (cc_fec & FEC_RS)
4040 fw_fec |= FW_PORT_CAP32_FEC_RS;
4041 if (cc_fec & FEC_BASER_RS)
4042 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4048 * t4_link_l1cfg - apply link configuration to MAC/PHY
4049 * @adapter: the adapter
4050 * @mbox: the Firmware Mailbox to use
4051 * @port: the Port ID
4052 * @lc: the Port's Link Configuration
4054 * Set up a port's MAC and PHY according to a desired link configuration.
4055 * - If the PHY can auto-negotiate first decide what to advertise, then
4056 * enable/disable auto-negotiation as desired, and reset.
4057 * - If the PHY does not auto-negotiate just reset it.
4058 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4059 * otherwise do it later based on the outcome of auto-negotiation.
4061 int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
4062 unsigned int port, struct link_config *lc)
4064 unsigned int fw_caps = adapter->params.fw_caps_support;
4065 struct fw_port_cmd cmd;
4066 unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
4067 fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
4069 /* Convert driver coding of Pause Frame Flow Control settings into the
4072 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4074 /* Convert Common Code Forward Error Control settings into the
4075 * Firmware's API. If the current Requested FEC has "Automatic"
4076 * (IEEE 802.3) specified, then we use whatever the Firmware
4077 * sent us as part of it's IEEE 802.3-based interpratation of
4078 * the Transceiver Module EPROM FEC parameters. Otherwise we
4079 * use whatever is in the current Requested FEC settings.
4081 if (lc->requested_fec & FEC_AUTO)
4082 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4084 cc_fec = lc->requested_fec;
4085 fw_fec = cc_to_fwcap_fec(cc_fec);
4087 /* Figure out what our Requested Port Capabilities are going to be.
4089 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4090 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
4091 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4093 } else if (lc->autoneg == AUTONEG_DISABLE) {
4094 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4095 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4098 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4101 /* And send that on to the Firmware ...
4103 memset(&cmd, 0, sizeof(cmd));
4104 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4105 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4106 FW_PORT_CMD_PORTID_V(port));
4107 cmd.action_to_len16 =
4108 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4109 ? FW_PORT_ACTION_L1_CFG
4110 : FW_PORT_ACTION_L1_CFG32) |
4112 if (fw_caps == FW_CAPS16)
4113 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4115 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4116 return t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4120 * t4_restart_aneg - restart autonegotiation
4121 * @adap: the adapter
4122 * @mbox: mbox to use for the FW command
4123 * @port: the port id
4125 * Restarts autonegotiation for the selected port.
4127 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4129 struct fw_port_cmd c;
4131 memset(&c, 0, sizeof(c));
4132 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4133 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4134 FW_PORT_CMD_PORTID_V(port));
4136 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4138 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4139 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4142 typedef void (*int_handler_t)(struct adapter *adap);
4145 unsigned int mask; /* bits to check in interrupt status */
4146 const char *msg; /* message to print or NULL */
4147 short stat_idx; /* stat counter to increment or -1 */
4148 unsigned short fatal; /* whether the condition reported is fatal */
4149 int_handler_t int_handler; /* platform-specific int handler */
4153 * t4_handle_intr_status - table driven interrupt handler
4154 * @adapter: the adapter that generated the interrupt
4155 * @reg: the interrupt status register to process
4156 * @acts: table of interrupt actions
4158 * A table driven interrupt handler that applies a set of masks to an
4159 * interrupt status word and performs the corresponding actions if the
4160 * interrupts described by the mask have occurred. The actions include
4161 * optionally emitting a warning or alert message. The table is terminated
4162 * by an entry specifying mask 0. Returns the number of fatal interrupt
4165 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4166 const struct intr_info *acts)
4169 unsigned int mask = 0;
4170 unsigned int status = t4_read_reg(adapter, reg);
4172 for ( ; acts->mask; ++acts) {
4173 if (!(status & acts->mask))
4177 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4178 status & acts->mask);
4179 } else if (acts->msg && printk_ratelimit())
4180 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4181 status & acts->mask);
4182 if (acts->int_handler)
4183 acts->int_handler(adapter);
4187 if (status) /* clear processed interrupts */
4188 t4_write_reg(adapter, reg, status);
4193 * Interrupt handler for the PCIE module.
4195 static void pcie_intr_handler(struct adapter *adapter)
4197 static const struct intr_info sysbus_intr_info[] = {
4198 { RNPP_F, "RXNP array parity error", -1, 1 },
4199 { RPCP_F, "RXPC array parity error", -1, 1 },
4200 { RCIP_F, "RXCIF array parity error", -1, 1 },
4201 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4202 { RFTP_F, "RXFT array parity error", -1, 1 },
4205 static const struct intr_info pcie_port_intr_info[] = {
4206 { TPCP_F, "TXPC array parity error", -1, 1 },
4207 { TNPP_F, "TXNP array parity error", -1, 1 },
4208 { TFTP_F, "TXFT array parity error", -1, 1 },
4209 { TCAP_F, "TXCA array parity error", -1, 1 },
4210 { TCIP_F, "TXCIF array parity error", -1, 1 },
4211 { RCAP_F, "RXCA array parity error", -1, 1 },
4212 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4213 { RDPE_F, "Rx data parity error", -1, 1 },
4214 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4217 static const struct intr_info pcie_intr_info[] = {
4218 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4219 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4220 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4221 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4222 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4223 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4224 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4225 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4226 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4227 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4228 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4229 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4230 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4231 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4232 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4233 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4234 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4235 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4236 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4237 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4238 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4239 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4240 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4241 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4242 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4243 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4244 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4245 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4246 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4247 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4252 static struct intr_info t5_pcie_intr_info[] = {
4253 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4255 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4256 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4257 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4258 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4259 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4260 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4261 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4263 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4265 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4266 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4267 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4268 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4269 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4271 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4272 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4273 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4274 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4275 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4276 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4277 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4278 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4279 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4280 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4281 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4283 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4285 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4286 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4287 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4288 { READRSPERR_F, "Outbound read error", -1, 0 },
4294 if (is_t4(adapter->params.chip))
4295 fat = t4_handle_intr_status(adapter,
4296 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4298 t4_handle_intr_status(adapter,
4299 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4300 pcie_port_intr_info) +
4301 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4304 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4308 t4_fatal_err(adapter);
4312 * TP interrupt handler.
4314 static void tp_intr_handler(struct adapter *adapter)
4316 static const struct intr_info tp_intr_info[] = {
4317 { 0x3fffffff, "TP parity error", -1, 1 },
4318 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4322 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4323 t4_fatal_err(adapter);
4327 * SGE interrupt handler.
4329 static void sge_intr_handler(struct adapter *adapter)
4334 static const struct intr_info sge_intr_info[] = {
4335 { ERR_CPL_EXCEED_IQE_SIZE_F,
4336 "SGE received CPL exceeding IQE size", -1, 1 },
4337 { ERR_INVALID_CIDX_INC_F,
4338 "SGE GTS CIDX increment too large", -1, 0 },
4339 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4340 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4341 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4342 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4343 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4345 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4347 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4349 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4351 { ERR_ING_CTXT_PRIO_F,
4352 "SGE too many priority ingress contexts", -1, 0 },
4353 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4354 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4358 static struct intr_info t4t5_sge_intr_info[] = {
4359 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4360 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4361 { ERR_EGR_CTXT_PRIO_F,
4362 "SGE too many priority egress contexts", -1, 0 },
4366 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4367 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4369 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4370 (unsigned long long)v);
4371 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4372 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4375 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4376 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4377 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4378 t4t5_sge_intr_info);
4380 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4381 if (err & ERROR_QID_VALID_F) {
4382 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4384 if (err & UNCAPTURED_ERROR_F)
4385 dev_err(adapter->pdev_dev,
4386 "SGE UNCAPTURED_ERROR set (clearing)\n");
4387 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4388 UNCAPTURED_ERROR_F);
4392 t4_fatal_err(adapter);
4395 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4396 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4397 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4398 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4401 * CIM interrupt handler.
4403 static void cim_intr_handler(struct adapter *adapter)
4405 static const struct intr_info cim_intr_info[] = {
4406 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4407 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4408 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4409 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4410 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4411 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4412 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4413 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4416 static const struct intr_info cim_upintr_info[] = {
4417 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4418 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4419 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4420 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4421 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4422 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4423 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4424 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4425 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4426 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4427 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4428 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4429 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4430 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4431 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4432 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4433 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4434 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4435 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4436 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4437 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4438 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4439 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4440 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4441 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4442 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4443 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4444 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4451 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4452 if (fw_err & PCIE_FW_ERR_F)
4453 t4_report_fw_error(adapter);
4455 /* When the Firmware detects an internal error which normally
4456 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4457 * in order to make sure the Host sees the Firmware Crash. So
4458 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4459 * ignore the Timer0 interrupt.
4462 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4463 if (val & TIMER0INT_F)
4464 if (!(fw_err & PCIE_FW_ERR_F) ||
4465 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4466 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4469 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4471 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4474 t4_fatal_err(adapter);
4478 * ULP RX interrupt handler.
4480 static void ulprx_intr_handler(struct adapter *adapter)
4482 static const struct intr_info ulprx_intr_info[] = {
4483 { 0x1800000, "ULPRX context error", -1, 1 },
4484 { 0x7fffff, "ULPRX parity error", -1, 1 },
4488 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4489 t4_fatal_err(adapter);
4493 * ULP TX interrupt handler.
4495 static void ulptx_intr_handler(struct adapter *adapter)
4497 static const struct intr_info ulptx_intr_info[] = {
4498 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4500 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4502 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4504 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4506 { 0xfffffff, "ULPTX parity error", -1, 1 },
4510 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4511 t4_fatal_err(adapter);
4515 * PM TX interrupt handler.
4517 static void pmtx_intr_handler(struct adapter *adapter)
4519 static const struct intr_info pmtx_intr_info[] = {
4520 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4521 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4522 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4523 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4524 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4525 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4526 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4528 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4529 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4533 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4534 t4_fatal_err(adapter);
4538 * PM RX interrupt handler.
4540 static void pmrx_intr_handler(struct adapter *adapter)
4542 static const struct intr_info pmrx_intr_info[] = {
4543 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4544 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4545 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4546 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4548 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4549 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4553 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4554 t4_fatal_err(adapter);
4558 * CPL switch interrupt handler.
4560 static void cplsw_intr_handler(struct adapter *adapter)
4562 static const struct intr_info cplsw_intr_info[] = {
4563 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4564 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4565 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4566 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4567 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4568 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4572 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4573 t4_fatal_err(adapter);
4577 * LE interrupt handler.
4579 static void le_intr_handler(struct adapter *adap)
4581 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4582 static const struct intr_info le_intr_info[] = {
4583 { LIPMISS_F, "LE LIP miss", -1, 0 },
4584 { LIP0_F, "LE 0 LIP error", -1, 0 },
4585 { PARITYERR_F, "LE parity error", -1, 1 },
4586 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4587 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4591 static struct intr_info t6_le_intr_info[] = {
4592 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4593 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4594 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4595 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4596 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4600 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4601 (chip <= CHELSIO_T5) ?
4602 le_intr_info : t6_le_intr_info))
4607 * MPS interrupt handler.
4609 static void mps_intr_handler(struct adapter *adapter)
4611 static const struct intr_info mps_rx_intr_info[] = {
4612 { 0xffffff, "MPS Rx parity error", -1, 1 },
4615 static const struct intr_info mps_tx_intr_info[] = {
4616 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4617 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4618 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4620 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4622 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4623 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4624 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4627 static const struct intr_info t6_mps_tx_intr_info[] = {
4628 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4629 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4630 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4632 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4634 /* MPS Tx Bubble is normal for T6 */
4635 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4636 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4639 static const struct intr_info mps_trc_intr_info[] = {
4640 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4641 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4643 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4646 static const struct intr_info mps_stat_sram_intr_info[] = {
4647 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4650 static const struct intr_info mps_stat_tx_intr_info[] = {
4651 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4654 static const struct intr_info mps_stat_rx_intr_info[] = {
4655 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4658 static const struct intr_info mps_cls_intr_info[] = {
4659 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4660 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4661 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4667 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4669 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4670 is_t6(adapter->params.chip)
4671 ? t6_mps_tx_intr_info
4672 : mps_tx_intr_info) +
4673 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4674 mps_trc_intr_info) +
4675 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4676 mps_stat_sram_intr_info) +
4677 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4678 mps_stat_tx_intr_info) +
4679 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4680 mps_stat_rx_intr_info) +
4681 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4684 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4685 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4687 t4_fatal_err(adapter);
4690 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4694 * EDC/MC interrupt handler.
4696 static void mem_intr_handler(struct adapter *adapter, int idx)
4698 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4700 unsigned int addr, cnt_addr, v;
4702 if (idx <= MEM_EDC1) {
4703 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4704 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4705 } else if (idx == MEM_MC) {
4706 if (is_t4(adapter->params.chip)) {
4707 addr = MC_INT_CAUSE_A;
4708 cnt_addr = MC_ECC_STATUS_A;
4710 addr = MC_P_INT_CAUSE_A;
4711 cnt_addr = MC_P_ECC_STATUS_A;
4714 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4715 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4718 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4719 if (v & PERR_INT_CAUSE_F)
4720 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4722 if (v & ECC_CE_INT_CAUSE_F) {
4723 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4725 t4_edc_err_read(adapter, idx);
4727 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4728 if (printk_ratelimit())
4729 dev_warn(adapter->pdev_dev,
4730 "%u %s correctable ECC data error%s\n",
4731 cnt, name[idx], cnt > 1 ? "s" : "");
4733 if (v & ECC_UE_INT_CAUSE_F)
4734 dev_alert(adapter->pdev_dev,
4735 "%s uncorrectable ECC data error\n", name[idx]);
4737 t4_write_reg(adapter, addr, v);
4738 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4739 t4_fatal_err(adapter);
4743 * MA interrupt handler.
4745 static void ma_intr_handler(struct adapter *adap)
4747 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4749 if (status & MEM_PERR_INT_CAUSE_F) {
4750 dev_alert(adap->pdev_dev,
4751 "MA parity error, parity status %#x\n",
4752 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4753 if (is_t5(adap->params.chip))
4754 dev_alert(adap->pdev_dev,
4755 "MA parity error, parity status %#x\n",
4757 MA_PARITY_ERROR_STATUS2_A));
4759 if (status & MEM_WRAP_INT_CAUSE_F) {
4760 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4761 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4762 "client %u to address %#x\n",
4763 MEM_WRAP_CLIENT_NUM_G(v),
4764 MEM_WRAP_ADDRESS_G(v) << 4);
4766 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4771 * SMB interrupt handler.
4773 static void smb_intr_handler(struct adapter *adap)
4775 static const struct intr_info smb_intr_info[] = {
4776 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4777 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4778 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4782 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4787 * NC-SI interrupt handler.
4789 static void ncsi_intr_handler(struct adapter *adap)
4791 static const struct intr_info ncsi_intr_info[] = {
4792 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4793 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4794 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4795 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4799 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4804 * XGMAC interrupt handler.
4806 static void xgmac_intr_handler(struct adapter *adap, int port)
4808 u32 v, int_cause_reg;
4810 if (is_t4(adap->params.chip))
4811 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4813 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4815 v = t4_read_reg(adap, int_cause_reg);
4817 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4821 if (v & TXFIFO_PRTY_ERR_F)
4822 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4824 if (v & RXFIFO_PRTY_ERR_F)
4825 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4827 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4832 * PL interrupt handler.
4834 static void pl_intr_handler(struct adapter *adap)
4836 static const struct intr_info pl_intr_info[] = {
4837 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4838 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4842 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4846 #define PF_INTR_MASK (PFSW_F)
4847 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4848 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4849 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4852 * t4_slow_intr_handler - control path interrupt handler
4853 * @adapter: the adapter
4855 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4856 * The designation 'slow' is because it involves register reads, while
4857 * data interrupts typically don't involve any MMIOs.
4859 int t4_slow_intr_handler(struct adapter *adapter)
4861 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4863 if (!(cause & GLBL_INTR_MASK))
4866 cim_intr_handler(adapter);
4868 mps_intr_handler(adapter);
4870 ncsi_intr_handler(adapter);
4872 pl_intr_handler(adapter);
4874 smb_intr_handler(adapter);
4875 if (cause & XGMAC0_F)
4876 xgmac_intr_handler(adapter, 0);
4877 if (cause & XGMAC1_F)
4878 xgmac_intr_handler(adapter, 1);
4879 if (cause & XGMAC_KR0_F)
4880 xgmac_intr_handler(adapter, 2);
4881 if (cause & XGMAC_KR1_F)
4882 xgmac_intr_handler(adapter, 3);
4884 pcie_intr_handler(adapter);
4886 mem_intr_handler(adapter, MEM_MC);
4887 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4888 mem_intr_handler(adapter, MEM_MC1);
4890 mem_intr_handler(adapter, MEM_EDC0);
4892 mem_intr_handler(adapter, MEM_EDC1);
4894 le_intr_handler(adapter);
4896 tp_intr_handler(adapter);
4898 ma_intr_handler(adapter);
4899 if (cause & PM_TX_F)
4900 pmtx_intr_handler(adapter);
4901 if (cause & PM_RX_F)
4902 pmrx_intr_handler(adapter);
4903 if (cause & ULP_RX_F)
4904 ulprx_intr_handler(adapter);
4905 if (cause & CPL_SWITCH_F)
4906 cplsw_intr_handler(adapter);
4908 sge_intr_handler(adapter);
4909 if (cause & ULP_TX_F)
4910 ulptx_intr_handler(adapter);
4912 /* Clear the interrupts just processed for which we are the master. */
4913 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4914 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4919 * t4_intr_enable - enable interrupts
4920 * @adapter: the adapter whose interrupts should be enabled
4922 * Enable PF-specific interrupts for the calling function and the top-level
4923 * interrupt concentrator for global interrupts. Interrupts are already
4924 * enabled at each module, here we just enable the roots of the interrupt
4927 * Note: this function should be called only when the driver manages
4928 * non PF-specific interrupts from the various HW modules. Only one PCI
4929 * function at a time should be doing this.
4931 void t4_intr_enable(struct adapter *adapter)
4934 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4935 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4936 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4938 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4939 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4940 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4941 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4942 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4943 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4944 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4945 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4946 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4947 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4948 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4952 * t4_intr_disable - disable interrupts
4953 * @adapter: the adapter whose interrupts should be disabled
4955 * Disable interrupts. We only disable the top-level interrupt
4956 * concentrators. The caller must be a PCI function managing global
4959 void t4_intr_disable(struct adapter *adapter)
4963 if (pci_channel_offline(adapter->pdev))
4966 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4967 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4968 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4970 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4971 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4974 unsigned int t4_chip_rss_size(struct adapter *adap)
4976 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
4977 return RSS_NENTRIES;
4979 return T6_RSS_NENTRIES;
4983 * t4_config_rss_range - configure a portion of the RSS mapping table
4984 * @adapter: the adapter
4985 * @mbox: mbox to use for the FW command
4986 * @viid: virtual interface whose RSS subtable is to be written
4987 * @start: start entry in the table to write
4988 * @n: how many table entries to write
4989 * @rspq: values for the response queue lookup table
4990 * @nrspq: number of values in @rspq
4992 * Programs the selected part of the VI's RSS mapping table with the
4993 * provided values. If @nrspq < @n the supplied values are used repeatedly
4994 * until the full table range is populated.
4996 * The caller must ensure the values in @rspq are in the range allowed for
4999 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5000 int start, int n, const u16 *rspq, unsigned int nrspq)
5003 const u16 *rsp = rspq;
5004 const u16 *rsp_end = rspq + nrspq;
5005 struct fw_rss_ind_tbl_cmd cmd;
5007 memset(&cmd, 0, sizeof(cmd));
5008 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5009 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5010 FW_RSS_IND_TBL_CMD_VIID_V(viid));
5011 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5013 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5015 int nq = min(n, 32);
5016 __be32 *qp = &cmd.iq0_to_iq2;
5018 cmd.niqid = cpu_to_be16(nq);
5019 cmd.startidx = cpu_to_be16(start);
5027 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5028 if (++rsp >= rsp_end)
5030 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5031 if (++rsp >= rsp_end)
5033 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5034 if (++rsp >= rsp_end)
5037 *qp++ = cpu_to_be32(v);
5041 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5049 * t4_config_glbl_rss - configure the global RSS mode
5050 * @adapter: the adapter
5051 * @mbox: mbox to use for the FW command
5052 * @mode: global RSS mode
5053 * @flags: mode-specific flags
5055 * Sets the global RSS mode.
5057 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5060 struct fw_rss_glb_config_cmd c;
5062 memset(&c, 0, sizeof(c));
5063 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5064 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5065 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5066 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5067 c.u.manual.mode_pkd =
5068 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5069 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5070 c.u.basicvirtual.mode_pkd =
5071 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5072 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5075 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5079 * t4_config_vi_rss - configure per VI RSS settings
5080 * @adapter: the adapter
5081 * @mbox: mbox to use for the FW command
5084 * @defq: id of the default RSS queue for the VI.
5086 * Configures VI-specific RSS properties.
5088 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5089 unsigned int flags, unsigned int defq)
5091 struct fw_rss_vi_config_cmd c;
5093 memset(&c, 0, sizeof(c));
5094 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5095 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5096 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5097 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5098 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5099 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5100 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5103 /* Read an RSS table row */
5104 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5106 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5107 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5112 * t4_read_rss - read the contents of the RSS mapping table
5113 * @adapter: the adapter
5114 * @map: holds the contents of the RSS mapping table
5116 * Reads the contents of the RSS hash->queue mapping table.
5118 int t4_read_rss(struct adapter *adapter, u16 *map)
5120 int i, ret, nentries;
5123 nentries = t4_chip_rss_size(adapter);
5124 for (i = 0; i < nentries / 2; ++i) {
5125 ret = rd_rss_row(adapter, i, &val);
5128 *map++ = LKPTBLQUEUE0_G(val);
5129 *map++ = LKPTBLQUEUE1_G(val);
5134 static unsigned int t4_use_ldst(struct adapter *adap)
5136 return (adap->flags & FW_OK) && !adap->use_bd;
5140 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5141 * @adap: the adapter
5142 * @cmd: TP fw ldst address space type
5143 * @vals: where the indirect register values are stored/written
5144 * @nregs: how many indirect registers to read/write
5145 * @start_idx: index of first indirect register to read/write
5146 * @rw: Read (1) or Write (0)
5147 * @sleep_ok: if true we may sleep while awaiting command completion
5149 * Access TP indirect registers through LDST
5151 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5152 unsigned int nregs, unsigned int start_index,
5153 unsigned int rw, bool sleep_ok)
5157 struct fw_ldst_cmd c;
5159 for (i = 0; i < nregs; i++) {
5160 memset(&c, 0, sizeof(c));
5161 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5163 (rw ? FW_CMD_READ_F :
5165 FW_LDST_CMD_ADDRSPACE_V(cmd));
5166 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5168 c.u.addrval.addr = cpu_to_be32(start_index + i);
5169 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5170 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5176 vals[i] = be32_to_cpu(c.u.addrval.val);
5182 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5183 * @adap: the adapter
5184 * @reg_addr: Address Register
5185 * @reg_data: Data register
5186 * @buff: where the indirect register values are stored/written
5187 * @nregs: how many indirect registers to read/write
5188 * @start_index: index of first indirect register to read/write
5189 * @rw: READ(1) or WRITE(0)
5190 * @sleep_ok: if true we may sleep while awaiting command completion
5192 * Read/Write TP indirect registers through LDST if possible.
5193 * Else, use backdoor access
5195 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5196 u32 *buff, u32 nregs, u32 start_index, int rw,
5204 cmd = FW_LDST_ADDRSPC_TP_PIO;
5206 case TP_TM_PIO_ADDR_A:
5207 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5209 case TP_MIB_INDEX_A:
5210 cmd = FW_LDST_ADDRSPC_TP_MIB;
5213 goto indirect_access;
5216 if (t4_use_ldst(adap))
5217 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5224 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5227 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5233 * t4_tp_pio_read - Read TP PIO registers
5234 * @adap: the adapter
5235 * @buff: where the indirect register values are written
5236 * @nregs: how many indirect registers to read
5237 * @start_index: index of first indirect register to read
5238 * @sleep_ok: if true we may sleep while awaiting command completion
5240 * Read TP PIO Registers
5242 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5243 u32 start_index, bool sleep_ok)
5245 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5246 start_index, 1, sleep_ok);
5250 * t4_tp_pio_write - Write TP PIO registers
5251 * @adap: the adapter
5252 * @buff: where the indirect register values are stored
5253 * @nregs: how many indirect registers to write
5254 * @start_index: index of first indirect register to write
5255 * @sleep_ok: if true we may sleep while awaiting command completion
5257 * Write TP PIO Registers
5259 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5260 u32 start_index, bool sleep_ok)
5262 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5263 start_index, 0, sleep_ok);
5267 * t4_tp_tm_pio_read - Read TP TM PIO registers
5268 * @adap: the adapter
5269 * @buff: where the indirect register values are written
5270 * @nregs: how many indirect registers to read
5271 * @start_index: index of first indirect register to read
5272 * @sleep_ok: if true we may sleep while awaiting command completion
5274 * Read TP TM PIO Registers
5276 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5277 u32 start_index, bool sleep_ok)
5279 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5280 nregs, start_index, 1, sleep_ok);
5284 * t4_tp_mib_read - Read TP MIB registers
5285 * @adap: the adapter
5286 * @buff: where the indirect register values are written
5287 * @nregs: how many indirect registers to read
5288 * @start_index: index of first indirect register to read
5289 * @sleep_ok: if true we may sleep while awaiting command completion
5291 * Read TP MIB Registers
5293 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5296 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5297 start_index, 1, sleep_ok);
5301 * t4_read_rss_key - read the global RSS key
5302 * @adap: the adapter
5303 * @key: 10-entry array holding the 320-bit RSS key
5304 * @sleep_ok: if true we may sleep while awaiting command completion
5306 * Reads the global 320-bit RSS key.
5308 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5310 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5314 * t4_write_rss_key - program one of the RSS keys
5315 * @adap: the adapter
5316 * @key: 10-entry array holding the 320-bit RSS key
5317 * @idx: which RSS key to write
5318 * @sleep_ok: if true we may sleep while awaiting command completion
5320 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5321 * 0..15 the corresponding entry in the RSS key table is written,
5322 * otherwise the global RSS key is written.
5324 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5327 u8 rss_key_addr_cnt = 16;
5328 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5330 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5331 * allows access to key addresses 16-63 by using KeyWrAddrX
5332 * as index[5:4](upper 2) into key table
5334 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5335 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5336 rss_key_addr_cnt = 32;
5338 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5340 if (idx >= 0 && idx < rss_key_addr_cnt) {
5341 if (rss_key_addr_cnt > 16)
5342 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5343 KEYWRADDRX_V(idx >> 4) |
5344 T6_VFWRADDR_V(idx) | KEYWREN_F);
5346 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5347 KEYWRADDR_V(idx) | KEYWREN_F);
5352 * t4_read_rss_pf_config - read PF RSS Configuration Table
5353 * @adapter: the adapter
5354 * @index: the entry in the PF RSS table to read
5355 * @valp: where to store the returned value
5356 * @sleep_ok: if true we may sleep while awaiting command completion
5358 * Reads the PF RSS Configuration Table at the specified index and returns
5359 * the value found there.
5361 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5362 u32 *valp, bool sleep_ok)
5364 t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5368 * t4_read_rss_vf_config - read VF RSS Configuration Table
5369 * @adapter: the adapter
5370 * @index: the entry in the VF RSS table to read
5371 * @vfl: where to store the returned VFL
5372 * @vfh: where to store the returned VFH
5373 * @sleep_ok: if true we may sleep while awaiting command completion
5375 * Reads the VF RSS Configuration Table at the specified index and returns
5376 * the (VFL, VFH) values found there.
5378 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5379 u32 *vfl, u32 *vfh, bool sleep_ok)
5381 u32 vrt, mask, data;
5383 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5384 mask = VFWRADDR_V(VFWRADDR_M);
5385 data = VFWRADDR_V(index);
5387 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
5388 data = T6_VFWRADDR_V(index);
5391 /* Request that the index'th VF Table values be read into VFL/VFH.
5393 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5394 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5395 vrt |= data | VFRDEN_F;
5396 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5398 /* Grab the VFL/VFH values ...
5400 t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5401 t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5405 * t4_read_rss_pf_map - read PF RSS Map
5406 * @adapter: the adapter
5407 * @sleep_ok: if true we may sleep while awaiting command completion
5409 * Reads the PF RSS Map register and returns its value.
5411 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5415 t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5420 * t4_read_rss_pf_mask - read PF RSS Mask
5421 * @adapter: the adapter
5422 * @sleep_ok: if true we may sleep while awaiting command completion
5424 * Reads the PF RSS Mask register and returns its value.
5426 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5430 t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5435 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5436 * @adap: the adapter
5437 * @v4: holds the TCP/IP counter values
5438 * @v6: holds the TCP/IPv6 counter values
5439 * @sleep_ok: if true we may sleep while awaiting command completion
5441 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5442 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5444 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5445 struct tp_tcp_stats *v6, bool sleep_ok)
5447 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5449 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5450 #define STAT(x) val[STAT_IDX(x)]
5451 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5454 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5455 TP_MIB_TCP_OUT_RST_A, sleep_ok);
5456 v4->tcp_out_rsts = STAT(OUT_RST);
5457 v4->tcp_in_segs = STAT64(IN_SEG);
5458 v4->tcp_out_segs = STAT64(OUT_SEG);
5459 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5462 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5463 TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5464 v6->tcp_out_rsts = STAT(OUT_RST);
5465 v6->tcp_in_segs = STAT64(IN_SEG);
5466 v6->tcp_out_segs = STAT64(OUT_SEG);
5467 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5475 * t4_tp_get_err_stats - read TP's error MIB counters
5476 * @adap: the adapter
5477 * @st: holds the counter values
5478 * @sleep_ok: if true we may sleep while awaiting command completion
5480 * Returns the values of TP's error counters.
5482 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5485 int nchan = adap->params.arch.nchan;
5487 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5489 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5491 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5493 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5494 TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5495 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5496 TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5497 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5499 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5500 TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5501 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5502 TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5503 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5508 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5509 * @adap: the adapter
5510 * @st: holds the counter values
5511 * @sleep_ok: if true we may sleep while awaiting command completion
5513 * Returns the values of TP's CPL counters.
5515 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5518 int nchan = adap->params.arch.nchan;
5520 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5522 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5526 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5527 * @adap: the adapter
5528 * @st: holds the counter values
5529 * @sleep_ok: if true we may sleep while awaiting command completion
5531 * Returns the values of TP's RDMA counters.
5533 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5536 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5541 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5542 * @adap: the adapter
5543 * @idx: the port index
5544 * @st: holds the counter values
5545 * @sleep_ok: if true we may sleep while awaiting command completion
5547 * Returns the values of TP's FCoE counters for the selected port.
5549 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5550 struct tp_fcoe_stats *st, bool sleep_ok)
5554 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5557 t4_tp_mib_read(adap, &st->frames_drop, 1,
5558 TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5560 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5563 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5567 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5568 * @adap: the adapter
5569 * @st: holds the counter values
5570 * @sleep_ok: if true we may sleep while awaiting command completion
5572 * Returns the values of TP's counters for non-TCP directly-placed packets.
5574 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5579 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5580 st->frames = val[0];
5582 st->octets = ((u64)val[2] << 32) | val[3];
5586 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5587 * @adap: the adapter
5588 * @mtus: where to store the MTU values
5589 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5591 * Reads the HW path MTU table.
5593 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5598 for (i = 0; i < NMTUS; ++i) {
5599 t4_write_reg(adap, TP_MTU_TABLE_A,
5600 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5601 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5602 mtus[i] = MTUVALUE_G(v);
5604 mtu_log[i] = MTUWIDTH_G(v);
5609 * t4_read_cong_tbl - reads the congestion control table
5610 * @adap: the adapter
5611 * @incr: where to store the alpha values
5613 * Reads the additive increments programmed into the HW congestion
5616 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5618 unsigned int mtu, w;
5620 for (mtu = 0; mtu < NMTUS; ++mtu)
5621 for (w = 0; w < NCCTRL_WIN; ++w) {
5622 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5623 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5624 incr[mtu][w] = (u16)t4_read_reg(adap,
5625 TP_CCTRL_TABLE_A) & 0x1fff;
5630 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5631 * @adap: the adapter
5632 * @addr: the indirect TP register address
5633 * @mask: specifies the field within the register to modify
5634 * @val: new value for the field
5636 * Sets a field of an indirect TP register to the given value.
5638 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5639 unsigned int mask, unsigned int val)
5641 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5642 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5643 t4_write_reg(adap, TP_PIO_DATA_A, val);
5647 * init_cong_ctrl - initialize congestion control parameters
5648 * @a: the alpha values for congestion control
5649 * @b: the beta values for congestion control
5651 * Initialize the congestion control parameters.
5653 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5655 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5680 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5683 b[13] = b[14] = b[15] = b[16] = 3;
5684 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5685 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5690 /* The minimum additive increment value for the congestion control table */
5691 #define CC_MIN_INCR 2U
5694 * t4_load_mtus - write the MTU and congestion control HW tables
5695 * @adap: the adapter
5696 * @mtus: the values for the MTU table
5697 * @alpha: the values for the congestion control alpha parameter
5698 * @beta: the values for the congestion control beta parameter
5700 * Write the HW MTU table with the supplied MTUs and the high-speed
5701 * congestion control table with the supplied alpha, beta, and MTUs.
5702 * We write the two tables together because the additive increments
5703 * depend on the MTUs.
5705 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5706 const unsigned short *alpha, const unsigned short *beta)
5708 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5709 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5710 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5711 28672, 40960, 57344, 81920, 114688, 163840, 229376
5716 for (i = 0; i < NMTUS; ++i) {
5717 unsigned int mtu = mtus[i];
5718 unsigned int log2 = fls(mtu);
5720 if (!(mtu & ((1 << log2) >> 2))) /* round */
5722 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5723 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5725 for (w = 0; w < NCCTRL_WIN; ++w) {
5728 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5731 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5732 (w << 16) | (beta[w] << 13) | inc);
5737 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5738 * clocks. The formula is
5740 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5742 * which is equivalent to
5744 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5746 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5748 u64 v = bytes256 * adap->params.vpd.cclk;
5750 return v * 62 + v / 2;
5754 * t4_get_chan_txrate - get the current per channel Tx rates
5755 * @adap: the adapter
5756 * @nic_rate: rates for NIC traffic
5757 * @ofld_rate: rates for offloaded traffic
5759 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5762 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5766 v = t4_read_reg(adap, TP_TX_TRATE_A);
5767 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5768 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5769 if (adap->params.arch.nchan == NCHAN) {
5770 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5771 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5774 v = t4_read_reg(adap, TP_TX_ORATE_A);
5775 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5776 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5777 if (adap->params.arch.nchan == NCHAN) {
5778 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5779 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5784 * t4_set_trace_filter - configure one of the tracing filters
5785 * @adap: the adapter
5786 * @tp: the desired trace filter parameters
5787 * @idx: which filter to configure
5788 * @enable: whether to enable or disable the filter
5790 * Configures one of the tracing filters available in HW. If @enable is
5791 * %0 @tp is not examined and may be %NULL. The user is responsible to
5792 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5794 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5795 int idx, int enable)
5797 int i, ofst = idx * 4;
5798 u32 data_reg, mask_reg, cfg;
5799 u32 multitrc = TRCMULTIFILTER_F;
5802 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5806 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5807 if (cfg & TRCMULTIFILTER_F) {
5808 /* If multiple tracers are enabled, then maximum
5809 * capture size is 2.5KB (FIFO size of a single channel)
5810 * minus 2 flits for CPL_TRACE_PKT header.
5812 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5815 /* If multiple tracers are disabled, to avoid deadlocks
5816 * maximum packet capture size of 9600 bytes is recommended.
5817 * Also in this mode, only trace0 can be enabled and running.
5820 if (tp->snap_len > 9600 || idx)
5824 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5825 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5826 tp->min_len > TFMINPKTSIZE_M)
5829 /* stop the tracer we'll be changing */
5830 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5832 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5833 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5834 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5836 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5837 t4_write_reg(adap, data_reg, tp->data[i]);
5838 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5840 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5841 TFCAPTUREMAX_V(tp->snap_len) |
5842 TFMINPKTSIZE_V(tp->min_len));
5843 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5844 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5845 (is_t4(adap->params.chip) ?
5846 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5847 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5848 T5_TFINVERTMATCH_V(tp->invert)));
5854 * t4_get_trace_filter - query one of the tracing filters
5855 * @adap: the adapter
5856 * @tp: the current trace filter parameters
5857 * @idx: which trace filter to query
5858 * @enabled: non-zero if the filter is enabled
5860 * Returns the current settings of one of the HW tracing filters.
5862 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5866 int i, ofst = idx * 4;
5867 u32 data_reg, mask_reg;
5869 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5870 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5872 if (is_t4(adap->params.chip)) {
5873 *enabled = !!(ctla & TFEN_F);
5874 tp->port = TFPORT_G(ctla);
5875 tp->invert = !!(ctla & TFINVERTMATCH_F);
5877 *enabled = !!(ctla & T5_TFEN_F);
5878 tp->port = T5_TFPORT_G(ctla);
5879 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5881 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5882 tp->min_len = TFMINPKTSIZE_G(ctlb);
5883 tp->skip_ofst = TFOFFSET_G(ctla);
5884 tp->skip_len = TFLENGTH_G(ctla);
5886 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5887 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5888 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5890 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5891 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5892 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5897 * t4_pmtx_get_stats - returns the HW stats from PMTX
5898 * @adap: the adapter
5899 * @cnt: where to store the count statistics
5900 * @cycles: where to store the cycle statistics
5902 * Returns performance statistics from PMTX.
5904 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5909 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5910 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5911 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5912 if (is_t4(adap->params.chip)) {
5913 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5915 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5916 PM_TX_DBG_DATA_A, data, 2,
5917 PM_TX_DBG_STAT_MSB_A);
5918 cycles[i] = (((u64)data[0] << 32) | data[1]);
5924 * t4_pmrx_get_stats - returns the HW stats from PMRX
5925 * @adap: the adapter
5926 * @cnt: where to store the count statistics
5927 * @cycles: where to store the cycle statistics
5929 * Returns performance statistics from PMRX.
5931 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5936 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5937 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5938 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5939 if (is_t4(adap->params.chip)) {
5940 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5942 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5943 PM_RX_DBG_DATA_A, data, 2,
5944 PM_RX_DBG_STAT_MSB_A);
5945 cycles[i] = (((u64)data[0] << 32) | data[1]);
5951 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5952 * @adap: the adapter
5953 * @pidx: the port index
5955 * Computes and returns a bitmap indicating which MPS buffer groups are
5956 * associated with the given Port. Bit i is set if buffer group i is
5959 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5962 unsigned int chip_version, nports;
5964 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5965 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5967 switch (chip_version) {
5972 case 2: return 3 << (2 * pidx);
5973 case 4: return 1 << pidx;
5979 case 2: return 1 << (2 * pidx);
5984 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5985 chip_version, nports);
5991 * t4_get_mps_bg_map - return the buffer groups associated with a port
5992 * @adapter: the adapter
5993 * @pidx: the port index
5995 * Returns a bitmap indicating which MPS buffer groups are associated
5996 * with the given Port. Bit i is set if buffer group i is used by the
5999 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6002 unsigned int nports;
6004 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6005 if (pidx >= nports) {
6006 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6011 /* If we've already retrieved/computed this, just return the result.
6013 mps_bg_map = adapter->params.mps_bg_map;
6014 if (mps_bg_map[pidx])
6015 return mps_bg_map[pidx];
6017 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6018 * If we're talking to such Firmware, let it tell us. If the new
6019 * API isn't supported, revert back to old hardcoded way. The value
6020 * obtained from Firmware is encoded in below format:
6022 * val = (( MPSBGMAP[Port 3] << 24 ) |
6023 * ( MPSBGMAP[Port 2] << 16 ) |
6024 * ( MPSBGMAP[Port 1] << 8 ) |
6025 * ( MPSBGMAP[Port 0] << 0 ))
6027 if (adapter->flags & FW_OK) {
6031 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6032 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6033 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6034 0, 1, ¶m, &val);
6038 /* Store the BG Map for all of the Ports in order to
6039 * avoid more calls to the Firmware in the future.
6041 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6042 mps_bg_map[p] = val & 0xff;
6044 return mps_bg_map[pidx];
6048 /* Either we're not talking to the Firmware or we're dealing with
6049 * older Firmware which doesn't support the new API to get the MPS
6050 * Buffer Group Map. Fall back to computing it ourselves.
6052 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6053 return mps_bg_map[pidx];
6057 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6058 * @adapter: the adapter
6059 * @pidx: the port index
6061 * Returns a bitmap indicating which TP Ingress Channels are associated
6062 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6065 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6067 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6068 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6070 if (pidx >= nports) {
6071 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6076 switch (chip_version) {
6079 /* Note that this happens to be the same values as the MPS
6080 * Buffer Group Map for these Chips. But we replicate the code
6081 * here because they're really separate concepts.
6085 case 2: return 3 << (2 * pidx);
6086 case 4: return 1 << pidx;
6093 case 2: return 1 << pidx;
6098 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6099 chip_version, nports);
6104 * t4_get_port_type_description - return Port Type string description
6105 * @port_type: firmware Port Type enumeration
6107 const char *t4_get_port_type_description(enum fw_port_type port_type)
6109 static const char *const port_type_description[] = {
6135 if (port_type < ARRAY_SIZE(port_type_description))
6136 return port_type_description[port_type];
6141 * t4_get_port_stats_offset - collect port stats relative to a previous
6143 * @adap: The adapter
6145 * @stats: Current stats to fill
6146 * @offset: Previous stats snapshot
6148 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6149 struct port_stats *stats,
6150 struct port_stats *offset)
6155 t4_get_port_stats(adap, idx, stats);
6156 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6157 i < (sizeof(struct port_stats) / sizeof(u64));
6163 * t4_get_port_stats - collect port statistics
6164 * @adap: the adapter
6165 * @idx: the port index
6166 * @p: the stats structure to fill
6168 * Collect statistics related to the given port from HW.
6170 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6172 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6173 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6175 #define GET_STAT(name) \
6176 t4_read_reg64(adap, \
6177 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6178 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6179 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6181 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6182 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6183 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6184 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6185 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6186 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6187 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6188 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6189 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6190 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6191 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6192 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6193 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6194 p->tx_drop = GET_STAT(TX_PORT_DROP);
6195 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6196 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6197 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6198 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6199 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6200 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6201 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6202 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6203 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6205 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6206 if (stat_ctl & COUNTPAUSESTATTX_F)
6207 p->tx_frames_64 -= p->tx_pause;
6208 if (stat_ctl & COUNTPAUSEMCTX_F)
6209 p->tx_mcast_frames -= p->tx_pause;
6211 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6212 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6213 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6214 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6215 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6216 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6217 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6218 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6219 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6220 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6221 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6222 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6223 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6224 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6225 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6226 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6227 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6228 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6229 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6230 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6231 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6232 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6233 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6234 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6235 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6236 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6237 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6239 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6240 if (stat_ctl & COUNTPAUSESTATRX_F)
6241 p->rx_frames_64 -= p->rx_pause;
6242 if (stat_ctl & COUNTPAUSEMCRX_F)
6243 p->rx_mcast_frames -= p->rx_pause;
6246 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6247 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6248 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6249 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6250 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6251 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6252 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6253 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6260 * t4_get_lb_stats - collect loopback port statistics
6261 * @adap: the adapter
6262 * @idx: the loopback port index
6263 * @p: the stats structure to fill
6265 * Return HW statistics for the given loopback port.
6267 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6269 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6271 #define GET_STAT(name) \
6272 t4_read_reg64(adap, \
6273 (is_t4(adap->params.chip) ? \
6274 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6275 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6276 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6278 p->octets = GET_STAT(BYTES);
6279 p->frames = GET_STAT(FRAMES);
6280 p->bcast_frames = GET_STAT(BCAST);
6281 p->mcast_frames = GET_STAT(MCAST);
6282 p->ucast_frames = GET_STAT(UCAST);
6283 p->error_frames = GET_STAT(ERROR);
6285 p->frames_64 = GET_STAT(64B);
6286 p->frames_65_127 = GET_STAT(65B_127B);
6287 p->frames_128_255 = GET_STAT(128B_255B);
6288 p->frames_256_511 = GET_STAT(256B_511B);
6289 p->frames_512_1023 = GET_STAT(512B_1023B);
6290 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6291 p->frames_1519_max = GET_STAT(1519B_MAX);
6292 p->drop = GET_STAT(DROP_FRAMES);
6294 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6295 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6296 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6297 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6298 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6299 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6300 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6301 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6307 /* t4_mk_filtdelwr - create a delete filter WR
6308 * @ftid: the filter ID
6309 * @wr: the filter work request to populate
6310 * @qid: ingress queue to receive the delete notification
6312 * Creates a filter work request to delete the supplied filter. If @qid is
6313 * negative the delete notification is suppressed.
6315 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6317 memset(wr, 0, sizeof(*wr));
6318 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6319 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6320 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6321 FW_FILTER_WR_NOREPLY_V(qid < 0));
6322 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6324 wr->rx_chan_rx_rpl_iq =
6325 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6328 #define INIT_CMD(var, cmd, rd_wr) do { \
6329 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6330 FW_CMD_REQUEST_F | \
6331 FW_CMD_##rd_wr##_F); \
6332 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6335 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6339 struct fw_ldst_cmd c;
6341 memset(&c, 0, sizeof(c));
6342 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6343 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6347 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6348 c.u.addrval.addr = cpu_to_be32(addr);
6349 c.u.addrval.val = cpu_to_be32(val);
6351 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6355 * t4_mdio_rd - read a PHY register through MDIO
6356 * @adap: the adapter
6357 * @mbox: mailbox to use for the FW command
6358 * @phy_addr: the PHY address
6359 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6360 * @reg: the register to read
6361 * @valp: where to store the value
6363 * Issues a FW command through the given mailbox to read a PHY register.
6365 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6366 unsigned int mmd, unsigned int reg, u16 *valp)
6370 struct fw_ldst_cmd c;
6372 memset(&c, 0, sizeof(c));
6373 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6374 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6375 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6377 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6378 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6379 FW_LDST_CMD_MMD_V(mmd));
6380 c.u.mdio.raddr = cpu_to_be16(reg);
6382 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6384 *valp = be16_to_cpu(c.u.mdio.rval);
6389 * t4_mdio_wr - write a PHY register through MDIO
6390 * @adap: the adapter
6391 * @mbox: mailbox to use for the FW command
6392 * @phy_addr: the PHY address
6393 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6394 * @reg: the register to write
6395 * @valp: value to write
6397 * Issues a FW command through the given mailbox to write a PHY register.
6399 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6400 unsigned int mmd, unsigned int reg, u16 val)
6403 struct fw_ldst_cmd c;
6405 memset(&c, 0, sizeof(c));
6406 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6407 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6408 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6410 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6411 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6412 FW_LDST_CMD_MMD_V(mmd));
6413 c.u.mdio.raddr = cpu_to_be16(reg);
6414 c.u.mdio.rval = cpu_to_be16(val);
6416 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6420 * t4_sge_decode_idma_state - decode the idma state
6421 * @adap: the adapter
6422 * @state: the state idma is stuck in
6424 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6426 static const char * const t4_decode[] = {
6428 "IDMA_PUSH_MORE_CPL_FIFO",
6429 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6431 "IDMA_PHYSADDR_SEND_PCIEHDR",
6432 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6433 "IDMA_PHYSADDR_SEND_PAYLOAD",
6434 "IDMA_SEND_FIFO_TO_IMSG",
6435 "IDMA_FL_REQ_DATA_FL_PREP",
6436 "IDMA_FL_REQ_DATA_FL",
6438 "IDMA_FL_H_REQ_HEADER_FL",
6439 "IDMA_FL_H_SEND_PCIEHDR",
6440 "IDMA_FL_H_PUSH_CPL_FIFO",
6441 "IDMA_FL_H_SEND_CPL",
6442 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6443 "IDMA_FL_H_SEND_IP_HDR",
6444 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6445 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6446 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6447 "IDMA_FL_D_SEND_PCIEHDR",
6448 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6449 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6450 "IDMA_FL_SEND_PCIEHDR",
6451 "IDMA_FL_PUSH_CPL_FIFO",
6453 "IDMA_FL_SEND_PAYLOAD_FIRST",
6454 "IDMA_FL_SEND_PAYLOAD",
6455 "IDMA_FL_REQ_NEXT_DATA_FL",
6456 "IDMA_FL_SEND_NEXT_PCIEHDR",
6457 "IDMA_FL_SEND_PADDING",
6458 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6459 "IDMA_FL_SEND_FIFO_TO_IMSG",
6460 "IDMA_FL_REQ_DATAFL_DONE",
6461 "IDMA_FL_REQ_HEADERFL_DONE",
6463 static const char * const t5_decode[] = {
6466 "IDMA_PUSH_MORE_CPL_FIFO",
6467 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6468 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6469 "IDMA_PHYSADDR_SEND_PCIEHDR",
6470 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6471 "IDMA_PHYSADDR_SEND_PAYLOAD",
6472 "IDMA_SEND_FIFO_TO_IMSG",
6473 "IDMA_FL_REQ_DATA_FL",
6475 "IDMA_FL_DROP_SEND_INC",
6476 "IDMA_FL_H_REQ_HEADER_FL",
6477 "IDMA_FL_H_SEND_PCIEHDR",
6478 "IDMA_FL_H_PUSH_CPL_FIFO",
6479 "IDMA_FL_H_SEND_CPL",
6480 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6481 "IDMA_FL_H_SEND_IP_HDR",
6482 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6483 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6484 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6485 "IDMA_FL_D_SEND_PCIEHDR",
6486 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6487 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6488 "IDMA_FL_SEND_PCIEHDR",
6489 "IDMA_FL_PUSH_CPL_FIFO",
6491 "IDMA_FL_SEND_PAYLOAD_FIRST",
6492 "IDMA_FL_SEND_PAYLOAD",
6493 "IDMA_FL_REQ_NEXT_DATA_FL",
6494 "IDMA_FL_SEND_NEXT_PCIEHDR",
6495 "IDMA_FL_SEND_PADDING",
6496 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6498 static const char * const t6_decode[] = {
6500 "IDMA_PUSH_MORE_CPL_FIFO",
6501 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6502 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6503 "IDMA_PHYSADDR_SEND_PCIEHDR",
6504 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6505 "IDMA_PHYSADDR_SEND_PAYLOAD",
6506 "IDMA_FL_REQ_DATA_FL",
6508 "IDMA_FL_DROP_SEND_INC",
6509 "IDMA_FL_H_REQ_HEADER_FL",
6510 "IDMA_FL_H_SEND_PCIEHDR",
6511 "IDMA_FL_H_PUSH_CPL_FIFO",
6512 "IDMA_FL_H_SEND_CPL",
6513 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6514 "IDMA_FL_H_SEND_IP_HDR",
6515 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6516 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6517 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6518 "IDMA_FL_D_SEND_PCIEHDR",
6519 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6520 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6521 "IDMA_FL_SEND_PCIEHDR",
6522 "IDMA_FL_PUSH_CPL_FIFO",
6524 "IDMA_FL_SEND_PAYLOAD_FIRST",
6525 "IDMA_FL_SEND_PAYLOAD",
6526 "IDMA_FL_REQ_NEXT_DATA_FL",
6527 "IDMA_FL_SEND_NEXT_PCIEHDR",
6528 "IDMA_FL_SEND_PADDING",
6529 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6531 static const u32 sge_regs[] = {
6532 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6533 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6534 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6536 const char **sge_idma_decode;
6537 int sge_idma_decode_nstates;
6539 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6541 /* Select the right set of decode strings to dump depending on the
6542 * adapter chip type.
6544 switch (chip_version) {
6546 sge_idma_decode = (const char **)t4_decode;
6547 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6551 sge_idma_decode = (const char **)t5_decode;
6552 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6556 sge_idma_decode = (const char **)t6_decode;
6557 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6561 dev_err(adapter->pdev_dev,
6562 "Unsupported chip version %d\n", chip_version);
6566 if (is_t4(adapter->params.chip)) {
6567 sge_idma_decode = (const char **)t4_decode;
6568 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6570 sge_idma_decode = (const char **)t5_decode;
6571 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6574 if (state < sge_idma_decode_nstates)
6575 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6577 CH_WARN(adapter, "idma state %d unknown\n", state);
6579 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6580 CH_WARN(adapter, "SGE register %#x value %#x\n",
6581 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6585 * t4_sge_ctxt_flush - flush the SGE context cache
6586 * @adap: the adapter
6587 * @mbox: mailbox to use for the FW command
6588 * @ctx_type: Egress or Ingress
6590 * Issues a FW command through the given mailbox to flush the
6591 * SGE context cache.
6593 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6597 struct fw_ldst_cmd c;
6599 memset(&c, 0, sizeof(c));
6600 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6601 FW_LDST_ADDRSPC_SGE_EGRC :
6602 FW_LDST_ADDRSPC_SGE_INGC);
6603 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6604 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6606 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6607 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6609 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6614 * t4_fw_hello - establish communication with FW
6615 * @adap: the adapter
6616 * @mbox: mailbox to use for the FW command
6617 * @evt_mbox: mailbox to receive async FW events
6618 * @master: specifies the caller's willingness to be the device master
6619 * @state: returns the current device state (if non-NULL)
6621 * Issues a command to establish communication with FW. Returns either
6622 * an error (negative integer) or the mailbox of the Master PF.
6624 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6625 enum dev_master master, enum dev_state *state)
6628 struct fw_hello_cmd c;
6630 unsigned int master_mbox;
6631 int retries = FW_CMD_HELLO_RETRIES;
6634 memset(&c, 0, sizeof(c));
6635 INIT_CMD(c, HELLO, WRITE);
6636 c.err_to_clearinit = cpu_to_be32(
6637 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6638 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6639 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6640 mbox : FW_HELLO_CMD_MBMASTER_M) |
6641 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6642 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6643 FW_HELLO_CMD_CLEARINIT_F);
6646 * Issue the HELLO command to the firmware. If it's not successful
6647 * but indicates that we got a "busy" or "timeout" condition, retry
6648 * the HELLO until we exhaust our retry limit. If we do exceed our
6649 * retry limit, check to see if the firmware left us any error
6650 * information and report that if so.
6652 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6654 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6656 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6657 t4_report_fw_error(adap);
6661 v = be32_to_cpu(c.err_to_clearinit);
6662 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6664 if (v & FW_HELLO_CMD_ERR_F)
6665 *state = DEV_STATE_ERR;
6666 else if (v & FW_HELLO_CMD_INIT_F)
6667 *state = DEV_STATE_INIT;
6669 *state = DEV_STATE_UNINIT;
6673 * If we're not the Master PF then we need to wait around for the
6674 * Master PF Driver to finish setting up the adapter.
6676 * Note that we also do this wait if we're a non-Master-capable PF and
6677 * there is no current Master PF; a Master PF may show up momentarily
6678 * and we wouldn't want to fail pointlessly. (This can happen when an
6679 * OS loads lots of different drivers rapidly at the same time). In
6680 * this case, the Master PF returned by the firmware will be
6681 * PCIE_FW_MASTER_M so the test below will work ...
6683 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6684 master_mbox != mbox) {
6685 int waiting = FW_CMD_HELLO_TIMEOUT;
6688 * Wait for the firmware to either indicate an error or
6689 * initialized state. If we see either of these we bail out
6690 * and report the issue to the caller. If we exhaust the
6691 * "hello timeout" and we haven't exhausted our retries, try
6692 * again. Otherwise bail with a timeout error.
6701 * If neither Error nor Initialialized are indicated
6702 * by the firmware keep waiting till we exaust our
6703 * timeout ... and then retry if we haven't exhausted
6706 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6707 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6718 * We either have an Error or Initialized condition
6719 * report errors preferentially.
6722 if (pcie_fw & PCIE_FW_ERR_F)
6723 *state = DEV_STATE_ERR;
6724 else if (pcie_fw & PCIE_FW_INIT_F)
6725 *state = DEV_STATE_INIT;
6729 * If we arrived before a Master PF was selected and
6730 * there's not a valid Master PF, grab its identity
6733 if (master_mbox == PCIE_FW_MASTER_M &&
6734 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6735 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6744 * t4_fw_bye - end communication with FW
6745 * @adap: the adapter
6746 * @mbox: mailbox to use for the FW command
6748 * Issues a command to terminate communication with FW.
6750 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6752 struct fw_bye_cmd c;
6754 memset(&c, 0, sizeof(c));
6755 INIT_CMD(c, BYE, WRITE);
6756 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6760 * t4_init_cmd - ask FW to initialize the device
6761 * @adap: the adapter
6762 * @mbox: mailbox to use for the FW command
6764 * Issues a command to FW to partially initialize the device. This
6765 * performs initialization that generally doesn't depend on user input.
6767 int t4_early_init(struct adapter *adap, unsigned int mbox)
6769 struct fw_initialize_cmd c;
6771 memset(&c, 0, sizeof(c));
6772 INIT_CMD(c, INITIALIZE, WRITE);
6773 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6777 * t4_fw_reset - issue a reset to FW
6778 * @adap: the adapter
6779 * @mbox: mailbox to use for the FW command
6780 * @reset: specifies the type of reset to perform
6782 * Issues a reset command of the specified type to FW.
6784 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6786 struct fw_reset_cmd c;
6788 memset(&c, 0, sizeof(c));
6789 INIT_CMD(c, RESET, WRITE);
6790 c.val = cpu_to_be32(reset);
6791 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6795 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6796 * @adap: the adapter
6797 * @mbox: mailbox to use for the FW RESET command (if desired)
6798 * @force: force uP into RESET even if FW RESET command fails
6800 * Issues a RESET command to firmware (if desired) with a HALT indication
6801 * and then puts the microprocessor into RESET state. The RESET command
6802 * will only be issued if a legitimate mailbox is provided (mbox <=
6803 * PCIE_FW_MASTER_M).
6805 * This is generally used in order for the host to safely manipulate the
6806 * adapter without fear of conflicting with whatever the firmware might
6807 * be doing. The only way out of this state is to RESTART the firmware
6810 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6815 * If a legitimate mailbox is provided, issue a RESET command
6816 * with a HALT indication.
6818 if (mbox <= PCIE_FW_MASTER_M) {
6819 struct fw_reset_cmd c;
6821 memset(&c, 0, sizeof(c));
6822 INIT_CMD(c, RESET, WRITE);
6823 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6824 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6825 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6829 * Normally we won't complete the operation if the firmware RESET
6830 * command fails but if our caller insists we'll go ahead and put the
6831 * uP into RESET. This can be useful if the firmware is hung or even
6832 * missing ... We'll have to take the risk of putting the uP into
6833 * RESET without the cooperation of firmware in that case.
6835 * We also force the firmware's HALT flag to be on in case we bypassed
6836 * the firmware RESET command above or we're dealing with old firmware
6837 * which doesn't have the HALT capability. This will serve as a flag
6838 * for the incoming firmware to know that it's coming out of a HALT
6839 * rather than a RESET ... if it's new enough to understand that ...
6841 if (ret == 0 || force) {
6842 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6843 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6848 * And we always return the result of the firmware RESET command
6849 * even when we force the uP into RESET ...
6855 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6856 * @adap: the adapter
6857 * @reset: if we want to do a RESET to restart things
6859 * Restart firmware previously halted by t4_fw_halt(). On successful
6860 * return the previous PF Master remains as the new PF Master and there
6861 * is no need to issue a new HELLO command, etc.
6863 * We do this in two ways:
6865 * 1. If we're dealing with newer firmware we'll simply want to take
6866 * the chip's microprocessor out of RESET. This will cause the
6867 * firmware to start up from its start vector. And then we'll loop
6868 * until the firmware indicates it's started again (PCIE_FW.HALT
6869 * reset to 0) or we timeout.
6871 * 2. If we're dealing with older firmware then we'll need to RESET
6872 * the chip since older firmware won't recognize the PCIE_FW.HALT
6873 * flag and automatically RESET itself on startup.
6875 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6879 * Since we're directing the RESET instead of the firmware
6880 * doing it automatically, we need to clear the PCIE_FW.HALT
6883 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6886 * If we've been given a valid mailbox, first try to get the
6887 * firmware to do the RESET. If that works, great and we can
6888 * return success. Otherwise, if we haven't been given a
6889 * valid mailbox or the RESET command failed, fall back to
6890 * hitting the chip with a hammer.
6892 if (mbox <= PCIE_FW_MASTER_M) {
6893 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6895 if (t4_fw_reset(adap, mbox,
6896 PIORST_F | PIORSTMODE_F) == 0)
6900 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6905 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6906 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6907 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6918 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6919 * @adap: the adapter
6920 * @mbox: mailbox to use for the FW RESET command (if desired)
6921 * @fw_data: the firmware image to write
6923 * @force: force upgrade even if firmware doesn't cooperate
6925 * Perform all of the steps necessary for upgrading an adapter's
6926 * firmware image. Normally this requires the cooperation of the
6927 * existing firmware in order to halt all existing activities
6928 * but if an invalid mailbox token is passed in we skip that step
6929 * (though we'll still put the adapter microprocessor into RESET in
6932 * On successful return the new firmware will have been loaded and
6933 * the adapter will have been fully RESET losing all previous setup
6934 * state. On unsuccessful return the adapter may be completely hosed ...
6935 * positive errno indicates that the adapter is ~probably~ intact, a
6936 * negative errno indicates that things are looking bad ...
6938 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6939 const u8 *fw_data, unsigned int size, int force)
6941 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6944 if (!t4_fw_matches_chip(adap, fw_hdr))
6947 /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6948 * wont be sent when we are flashing FW.
6950 adap->flags &= ~FW_OK;
6952 ret = t4_fw_halt(adap, mbox, force);
6953 if (ret < 0 && !force)
6956 ret = t4_load_fw(adap, fw_data, size);
6961 * If there was a Firmware Configuration File stored in FLASH,
6962 * there's a good chance that it won't be compatible with the new
6963 * Firmware. In order to prevent difficult to diagnose adapter
6964 * initialization issues, we clear out the Firmware Configuration File
6965 * portion of the FLASH . The user will need to re-FLASH a new
6966 * Firmware Configuration File which is compatible with the new
6967 * Firmware if that's desired.
6969 (void)t4_load_cfg(adap, NULL, 0);
6972 * Older versions of the firmware don't understand the new
6973 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6974 * restart. So for newly loaded older firmware we'll have to do the
6975 * RESET for it so it starts up on a clean slate. We can tell if
6976 * the newly loaded firmware will handle this right by checking
6977 * its header flags to see if it advertises the capability.
6979 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6980 ret = t4_fw_restart(adap, mbox, reset);
6982 /* Grab potentially new Firmware Device Log parameters so we can see
6983 * how healthy the new Firmware is. It's okay to contact the new
6984 * Firmware for these parameters even though, as far as it's
6985 * concerned, we've never said "HELLO" to it ...
6987 (void)t4_init_devlog_params(adap);
6989 adap->flags |= FW_OK;
6994 * t4_fl_pkt_align - return the fl packet alignment
6995 * @adap: the adapter
6997 * T4 has a single field to specify the packing and padding boundary.
6998 * T5 onwards has separate fields for this and hence the alignment for
6999 * next packet offset is maximum of these two.
7002 int t4_fl_pkt_align(struct adapter *adap)
7004 u32 sge_control, sge_control2;
7005 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7007 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7009 /* T4 uses a single control field to specify both the PCIe Padding and
7010 * Packing Boundary. T5 introduced the ability to specify these
7011 * separately. The actual Ingress Packet Data alignment boundary
7012 * within Packed Buffer Mode is the maximum of these two
7013 * specifications. (Note that it makes no real practical sense to
7014 * have the Pading Boudary be larger than the Packing Boundary but you
7015 * could set the chip up that way and, in fact, legacy T4 code would
7016 * end doing this because it would initialize the Padding Boundary and
7017 * leave the Packing Boundary initialized to 0 (16 bytes).)
7018 * Padding Boundary values in T6 starts from 8B,
7019 * where as it is 32B for T4 and T5.
7021 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7022 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7024 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7026 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7028 fl_align = ingpadboundary;
7029 if (!is_t4(adap->params.chip)) {
7030 /* T5 has a weird interpretation of one of the PCIe Packing
7031 * Boundary values. No idea why ...
7033 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7034 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7035 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7036 ingpackboundary = 16;
7038 ingpackboundary = 1 << (ingpackboundary +
7039 INGPACKBOUNDARY_SHIFT_X);
7041 fl_align = max(ingpadboundary, ingpackboundary);
7047 * t4_fixup_host_params - fix up host-dependent parameters
7048 * @adap: the adapter
7049 * @page_size: the host's Base Page Size
7050 * @cache_line_size: the host's Cache Line Size
7052 * Various registers in T4 contain values which are dependent on the
7053 * host's Base Page and Cache Line Sizes. This function will fix all of
7054 * those registers with the appropriate values as passed in ...
7056 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7057 unsigned int cache_line_size)
7059 unsigned int page_shift = fls(page_size) - 1;
7060 unsigned int sge_hps = page_shift - 10;
7061 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7062 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7063 unsigned int fl_align_log = fls(fl_align) - 1;
7065 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7066 HOSTPAGESIZEPF0_V(sge_hps) |
7067 HOSTPAGESIZEPF1_V(sge_hps) |
7068 HOSTPAGESIZEPF2_V(sge_hps) |
7069 HOSTPAGESIZEPF3_V(sge_hps) |
7070 HOSTPAGESIZEPF4_V(sge_hps) |
7071 HOSTPAGESIZEPF5_V(sge_hps) |
7072 HOSTPAGESIZEPF6_V(sge_hps) |
7073 HOSTPAGESIZEPF7_V(sge_hps));
7075 if (is_t4(adap->params.chip)) {
7076 t4_set_reg_field(adap, SGE_CONTROL_A,
7077 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7078 EGRSTATUSPAGESIZE_F,
7079 INGPADBOUNDARY_V(fl_align_log -
7080 INGPADBOUNDARY_SHIFT_X) |
7081 EGRSTATUSPAGESIZE_V(stat_len != 64));
7083 unsigned int pack_align;
7084 unsigned int ingpad, ingpack;
7085 unsigned int pcie_cap;
7087 /* T5 introduced the separation of the Free List Padding and
7088 * Packing Boundaries. Thus, we can select a smaller Padding
7089 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7090 * Bandwidth, and use a Packing Boundary which is large enough
7091 * to avoid false sharing between CPUs, etc.
7093 * For the PCI Link, the smaller the Padding Boundary the
7094 * better. For the Memory Controller, a smaller Padding
7095 * Boundary is better until we cross under the Memory Line
7096 * Size (the minimum unit of transfer to/from Memory). If we
7097 * have a Padding Boundary which is smaller than the Memory
7098 * Line Size, that'll involve a Read-Modify-Write cycle on the
7099 * Memory Controller which is never good.
7102 /* We want the Packing Boundary to be based on the Cache Line
7103 * Size in order to help avoid False Sharing performance
7104 * issues between CPUs, etc. We also want the Packing
7105 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7106 * get best performance when the Packing Boundary is a
7107 * multiple of the Maximum Payload Size.
7109 pack_align = fl_align;
7110 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
7112 unsigned int mps, mps_log;
7115 /* The PCIe Device Control Maximum Payload Size field
7116 * [bits 7:5] encodes sizes as powers of 2 starting at
7119 pci_read_config_word(adap->pdev,
7120 pcie_cap + PCI_EXP_DEVCTL,
7122 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7124 if (mps > pack_align)
7128 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7129 * value for the Packing Boundary. This corresponds to 16
7130 * bytes instead of the expected 32 bytes. So if we want 32
7131 * bytes, the best we can really do is 64 bytes ...
7133 if (pack_align <= 16) {
7134 ingpack = INGPACKBOUNDARY_16B_X;
7136 } else if (pack_align == 32) {
7137 ingpack = INGPACKBOUNDARY_64B_X;
7140 unsigned int pack_align_log = fls(pack_align) - 1;
7142 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7143 fl_align = pack_align;
7146 /* Use the smallest Ingress Padding which isn't smaller than
7147 * the Memory Controller Read/Write Size. We'll take that as
7148 * being 8 bytes since we don't know of any system with a
7149 * wider Memory Controller Bus Width.
7151 if (is_t5(adap->params.chip))
7152 ingpad = INGPADBOUNDARY_32B_X;
7154 ingpad = T6_INGPADBOUNDARY_8B_X;
7156 t4_set_reg_field(adap, SGE_CONTROL_A,
7157 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7158 EGRSTATUSPAGESIZE_F,
7159 INGPADBOUNDARY_V(ingpad) |
7160 EGRSTATUSPAGESIZE_V(stat_len != 64));
7161 t4_set_reg_field(adap, SGE_CONTROL2_A,
7162 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7163 INGPACKBOUNDARY_V(ingpack));
7166 * Adjust various SGE Free List Host Buffer Sizes.
7168 * This is something of a crock since we're using fixed indices into
7169 * the array which are also known by the sge.c code and the T4
7170 * Firmware Configuration File. We need to come up with a much better
7171 * approach to managing this array. For now, the first four entries
7176 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7177 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7179 * For the single-MTU buffers in unpacked mode we need to include
7180 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7181 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7182 * Padding boundary. All of these are accommodated in the Factory
7183 * Default Firmware Configuration File but we need to adjust it for
7184 * this host's cache line size.
7186 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7187 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7188 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7190 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7191 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7194 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7200 * t4_fw_initialize - ask FW to initialize the device
7201 * @adap: the adapter
7202 * @mbox: mailbox to use for the FW command
7204 * Issues a command to FW to partially initialize the device. This
7205 * performs initialization that generally doesn't depend on user input.
7207 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7209 struct fw_initialize_cmd c;
7211 memset(&c, 0, sizeof(c));
7212 INIT_CMD(c, INITIALIZE, WRITE);
7213 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7217 * t4_query_params_rw - query FW or device parameters
7218 * @adap: the adapter
7219 * @mbox: mailbox to use for the FW command
7222 * @nparams: the number of parameters
7223 * @params: the parameter names
7224 * @val: the parameter values
7225 * @rw: Write and read flag
7226 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7228 * Reads the value of FW or device parameters. Up to 7 parameters can be
7231 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7232 unsigned int vf, unsigned int nparams, const u32 *params,
7233 u32 *val, int rw, bool sleep_ok)
7236 struct fw_params_cmd c;
7237 __be32 *p = &c.param[0].mnem;
7242 memset(&c, 0, sizeof(c));
7243 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7244 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7245 FW_PARAMS_CMD_PFN_V(pf) |
7246 FW_PARAMS_CMD_VFN_V(vf));
7247 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7249 for (i = 0; i < nparams; i++) {
7250 *p++ = cpu_to_be32(*params++);
7252 *p = cpu_to_be32(*(val + i));
7256 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7258 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7259 *val++ = be32_to_cpu(*p);
7263 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7264 unsigned int vf, unsigned int nparams, const u32 *params,
7267 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7271 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7272 unsigned int vf, unsigned int nparams, const u32 *params,
7275 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7280 * t4_set_params_timeout - sets FW or device parameters
7281 * @adap: the adapter
7282 * @mbox: mailbox to use for the FW command
7285 * @nparams: the number of parameters
7286 * @params: the parameter names
7287 * @val: the parameter values
7288 * @timeout: the timeout time
7290 * Sets the value of FW or device parameters. Up to 7 parameters can be
7291 * specified at once.
7293 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7294 unsigned int pf, unsigned int vf,
7295 unsigned int nparams, const u32 *params,
7296 const u32 *val, int timeout)
7298 struct fw_params_cmd c;
7299 __be32 *p = &c.param[0].mnem;
7304 memset(&c, 0, sizeof(c));
7305 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7306 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7307 FW_PARAMS_CMD_PFN_V(pf) |
7308 FW_PARAMS_CMD_VFN_V(vf));
7309 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7312 *p++ = cpu_to_be32(*params++);
7313 *p++ = cpu_to_be32(*val++);
7316 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7320 * t4_set_params - sets FW or device parameters
7321 * @adap: the adapter
7322 * @mbox: mailbox to use for the FW command
7325 * @nparams: the number of parameters
7326 * @params: the parameter names
7327 * @val: the parameter values
7329 * Sets the value of FW or device parameters. Up to 7 parameters can be
7330 * specified at once.
7332 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7333 unsigned int vf, unsigned int nparams, const u32 *params,
7336 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7337 FW_CMD_MAX_TIMEOUT);
7341 * t4_cfg_pfvf - configure PF/VF resource limits
7342 * @adap: the adapter
7343 * @mbox: mailbox to use for the FW command
7344 * @pf: the PF being configured
7345 * @vf: the VF being configured
7346 * @txq: the max number of egress queues
7347 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7348 * @rxqi: the max number of interrupt-capable ingress queues
7349 * @rxq: the max number of interruptless ingress queues
7350 * @tc: the PCI traffic class
7351 * @vi: the max number of virtual interfaces
7352 * @cmask: the channel access rights mask for the PF/VF
7353 * @pmask: the port access rights mask for the PF/VF
7354 * @nexact: the maximum number of exact MPS filters
7355 * @rcaps: read capabilities
7356 * @wxcaps: write/execute capabilities
7358 * Configures resource limits and capabilities for a physical or virtual
7361 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7362 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7363 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7364 unsigned int vi, unsigned int cmask, unsigned int pmask,
7365 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7367 struct fw_pfvf_cmd c;
7369 memset(&c, 0, sizeof(c));
7370 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7371 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7372 FW_PFVF_CMD_VFN_V(vf));
7373 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7374 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7375 FW_PFVF_CMD_NIQ_V(rxq));
7376 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7377 FW_PFVF_CMD_PMASK_V(pmask) |
7378 FW_PFVF_CMD_NEQ_V(txq));
7379 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7380 FW_PFVF_CMD_NVI_V(vi) |
7381 FW_PFVF_CMD_NEXACTF_V(nexact));
7382 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7383 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7384 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7385 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7389 * t4_alloc_vi - allocate a virtual interface
7390 * @adap: the adapter
7391 * @mbox: mailbox to use for the FW command
7392 * @port: physical port associated with the VI
7393 * @pf: the PF owning the VI
7394 * @vf: the VF owning the VI
7395 * @nmac: number of MAC addresses needed (1 to 5)
7396 * @mac: the MAC addresses of the VI
7397 * @rss_size: size of RSS table slice associated with this VI
7399 * Allocates a virtual interface for the given physical port. If @mac is
7400 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7401 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7402 * stored consecutively so the space needed is @nmac * 6 bytes.
7403 * Returns a negative error number or the non-negative VI id.
7405 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7406 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7407 unsigned int *rss_size)
7412 memset(&c, 0, sizeof(c));
7413 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7414 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7415 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7416 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7417 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7420 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7425 memcpy(mac, c.mac, sizeof(c.mac));
7428 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7430 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7432 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7434 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7438 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7439 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7443 * t4_free_vi - free a virtual interface
7444 * @adap: the adapter
7445 * @mbox: mailbox to use for the FW command
7446 * @pf: the PF owning the VI
7447 * @vf: the VF owning the VI
7448 * @viid: virtual interface identifiler
7450 * Free a previously allocated virtual interface.
7452 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7453 unsigned int vf, unsigned int viid)
7457 memset(&c, 0, sizeof(c));
7458 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7461 FW_VI_CMD_PFN_V(pf) |
7462 FW_VI_CMD_VFN_V(vf));
7463 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7464 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7466 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7470 * t4_set_rxmode - set Rx properties of a virtual interface
7471 * @adap: the adapter
7472 * @mbox: mailbox to use for the FW command
7474 * @mtu: the new MTU or -1
7475 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7476 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7477 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7478 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7479 * @sleep_ok: if true we may sleep while awaiting command completion
7481 * Sets Rx properties of a virtual interface.
7483 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7484 int mtu, int promisc, int all_multi, int bcast, int vlanex,
7487 struct fw_vi_rxmode_cmd c;
7489 /* convert to FW values */
7491 mtu = FW_RXMODE_MTU_NO_CHG;
7493 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7495 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7497 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7499 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7501 memset(&c, 0, sizeof(c));
7502 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7503 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7504 FW_VI_RXMODE_CMD_VIID_V(viid));
7505 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7507 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7508 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7509 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7510 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7511 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7512 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7516 * t4_free_encap_mac_filt - frees MPS entry at given index
7517 * @adap: the adapter
7519 * @idx: index of MPS entry to be freed
7520 * @sleep_ok: call is allowed to sleep
7522 * Frees the MPS entry at supplied index
7524 * Returns a negative error number or zero on success
7526 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7527 int idx, bool sleep_ok)
7529 struct fw_vi_mac_exact *p;
7530 u8 addr[] = {0, 0, 0, 0, 0, 0};
7531 struct fw_vi_mac_cmd c;
7535 memset(&c, 0, sizeof(c));
7536 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7537 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7539 FW_VI_MAC_CMD_VIID_V(viid));
7540 exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7541 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7545 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7546 FW_VI_MAC_CMD_IDX_V(idx));
7547 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7548 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7553 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7554 * @adap: the adapter
7556 * @addr: the MAC address
7558 * @idx: index of the entry in mps tcam
7559 * @lookup_type: MAC address for inner (1) or outer (0) header
7560 * @port_id: the port index
7561 * @sleep_ok: call is allowed to sleep
7563 * Removes the mac entry at the specified index using raw mac interface.
7565 * Returns a negative error number on failure.
7567 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7568 const u8 *addr, const u8 *mask, unsigned int idx,
7569 u8 lookup_type, u8 port_id, bool sleep_ok)
7571 struct fw_vi_mac_cmd c;
7572 struct fw_vi_mac_raw *p = &c.u.raw;
7575 memset(&c, 0, sizeof(c));
7576 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7577 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7579 FW_VI_MAC_CMD_VIID_V(viid));
7580 val = FW_CMD_LEN16_V(1) |
7581 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7582 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7583 FW_CMD_LEN16_V(val));
7585 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7586 FW_VI_MAC_ID_BASED_FREE);
7588 /* Lookup Type. Outer header: 0, Inner header: 1 */
7589 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7590 DATAPORTNUM_V(port_id));
7591 /* Lookup mask and port mask */
7592 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7593 DATAPORTNUM_V(DATAPORTNUM_M));
7595 /* Copy the address and the mask */
7596 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7597 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7599 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7603 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7604 * @adap: the adapter
7606 * @mac: the MAC address
7608 * @vni: the VNI id for the tunnel protocol
7609 * @vni_mask: mask for the VNI id
7610 * @dip_hit: to enable DIP match for the MPS entry
7611 * @lookup_type: MAC address for inner (1) or outer (0) header
7612 * @sleep_ok: call is allowed to sleep
7614 * Allocates an MPS entry with specified MAC address and VNI value.
7616 * Returns a negative error number or the allocated index for this mac.
7618 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7619 const u8 *addr, const u8 *mask, unsigned int vni,
7620 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7623 struct fw_vi_mac_cmd c;
7624 struct fw_vi_mac_vni *p = c.u.exact_vni;
7628 memset(&c, 0, sizeof(c));
7629 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7630 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7631 FW_VI_MAC_CMD_VIID_V(viid));
7632 val = FW_CMD_LEN16_V(1) |
7633 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7634 c.freemacs_to_len16 = cpu_to_be32(val);
7635 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7636 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7637 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7638 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7640 p->lookup_type_to_vni =
7641 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7642 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7643 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7644 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7645 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7647 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7652 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7653 * @adap: the adapter
7655 * @mac: the MAC address
7657 * @idx: index at which to add this entry
7658 * @port_id: the port index
7659 * @lookup_type: MAC address for inner (1) or outer (0) header
7660 * @sleep_ok: call is allowed to sleep
7662 * Adds the mac entry at the specified index using raw mac interface.
7664 * Returns a negative error number or the allocated index for this mac.
7666 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7667 const u8 *addr, const u8 *mask, unsigned int idx,
7668 u8 lookup_type, u8 port_id, bool sleep_ok)
7671 struct fw_vi_mac_cmd c;
7672 struct fw_vi_mac_raw *p = &c.u.raw;
7675 memset(&c, 0, sizeof(c));
7676 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7677 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7678 FW_VI_MAC_CMD_VIID_V(viid));
7679 val = FW_CMD_LEN16_V(1) |
7680 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7681 c.freemacs_to_len16 = cpu_to_be32(val);
7683 /* Specify that this is an inner mac address */
7684 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7686 /* Lookup Type. Outer header: 0, Inner header: 1 */
7687 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7688 DATAPORTNUM_V(port_id));
7689 /* Lookup mask and port mask */
7690 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7691 DATAPORTNUM_V(DATAPORTNUM_M));
7693 /* Copy the address and the mask */
7694 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7695 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7697 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7699 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7708 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7709 * @adap: the adapter
7710 * @mbox: mailbox to use for the FW command
7712 * @free: if true any existing filters for this VI id are first removed
7713 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7714 * @addr: the MAC address(es)
7715 * @idx: where to store the index of each allocated filter
7716 * @hash: pointer to hash address filter bitmap
7717 * @sleep_ok: call is allowed to sleep
7719 * Allocates an exact-match filter for each of the supplied addresses and
7720 * sets it to the corresponding address. If @idx is not %NULL it should
7721 * have at least @naddr entries, each of which will be set to the index of
7722 * the filter allocated for the corresponding MAC address. If a filter
7723 * could not be allocated for an address its index is set to 0xffff.
7724 * If @hash is not %NULL addresses that fail to allocate an exact filter
7725 * are hashed and update the hash filter bitmap pointed at by @hash.
7727 * Returns a negative error number or the number of filters allocated.
7729 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7730 unsigned int viid, bool free, unsigned int naddr,
7731 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7733 int offset, ret = 0;
7734 struct fw_vi_mac_cmd c;
7735 unsigned int nfilters = 0;
7736 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7737 unsigned int rem = naddr;
7739 if (naddr > max_naddr)
7742 for (offset = 0; offset < naddr ; /**/) {
7743 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7744 rem : ARRAY_SIZE(c.u.exact));
7745 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7746 u.exact[fw_naddr]), 16);
7747 struct fw_vi_mac_exact *p;
7750 memset(&c, 0, sizeof(c));
7751 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7754 FW_CMD_EXEC_V(free) |
7755 FW_VI_MAC_CMD_VIID_V(viid));
7756 c.freemacs_to_len16 =
7757 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7758 FW_CMD_LEN16_V(len16));
7760 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7762 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7763 FW_VI_MAC_CMD_IDX_V(
7764 FW_VI_MAC_ADD_MAC));
7765 memcpy(p->macaddr, addr[offset + i],
7766 sizeof(p->macaddr));
7769 /* It's okay if we run out of space in our MAC address arena.
7770 * Some of the addresses we submit may get stored so we need
7771 * to run through the reply to see what the results were ...
7773 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7774 if (ret && ret != -FW_ENOMEM)
7777 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7778 u16 index = FW_VI_MAC_CMD_IDX_G(
7779 be16_to_cpu(p->valid_to_idx));
7782 idx[offset + i] = (index >= max_naddr ?
7784 if (index < max_naddr)
7788 hash_mac_addr(addr[offset + i]));
7796 if (ret == 0 || ret == -FW_ENOMEM)
7802 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
7803 * @adap: the adapter
7804 * @mbox: mailbox to use for the FW command
7806 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7807 * @addr: the MAC address(es)
7808 * @sleep_ok: call is allowed to sleep
7810 * Frees the exact-match filter for each of the supplied addresses
7812 * Returns a negative error number or the number of filters freed.
7814 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7815 unsigned int viid, unsigned int naddr,
7816 const u8 **addr, bool sleep_ok)
7818 int offset, ret = 0;
7819 struct fw_vi_mac_cmd c;
7820 unsigned int nfilters = 0;
7821 unsigned int max_naddr = is_t4(adap->params.chip) ?
7822 NUM_MPS_CLS_SRAM_L_INSTANCES :
7823 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7824 unsigned int rem = naddr;
7826 if (naddr > max_naddr)
7829 for (offset = 0; offset < (int)naddr ; /**/) {
7830 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7832 : ARRAY_SIZE(c.u.exact));
7833 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7834 u.exact[fw_naddr]), 16);
7835 struct fw_vi_mac_exact *p;
7838 memset(&c, 0, sizeof(c));
7839 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7843 FW_VI_MAC_CMD_VIID_V(viid));
7844 c.freemacs_to_len16 =
7845 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7846 FW_CMD_LEN16_V(len16));
7848 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7849 p->valid_to_idx = cpu_to_be16(
7850 FW_VI_MAC_CMD_VALID_F |
7851 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7852 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7855 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7859 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7860 u16 index = FW_VI_MAC_CMD_IDX_G(
7861 be16_to_cpu(p->valid_to_idx));
7863 if (index < max_naddr)
7877 * t4_change_mac - modifies the exact-match filter for a MAC address
7878 * @adap: the adapter
7879 * @mbox: mailbox to use for the FW command
7881 * @idx: index of existing filter for old value of MAC address, or -1
7882 * @addr: the new MAC address value
7883 * @persist: whether a new MAC allocation should be persistent
7884 * @add_smt: if true also add the address to the HW SMT
7886 * Modifies an exact-match filter and sets it to the new MAC address.
7887 * Note that in general it is not possible to modify the value of a given
7888 * filter so the generic way to modify an address filter is to free the one
7889 * being used by the old address value and allocate a new filter for the
7890 * new address value. @idx can be -1 if the address is a new addition.
7892 * Returns a negative error number or the index of the filter with the new
7895 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7896 int idx, const u8 *addr, bool persist, bool add_smt)
7899 struct fw_vi_mac_cmd c;
7900 struct fw_vi_mac_exact *p = c.u.exact;
7901 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7903 if (idx < 0) /* new allocation */
7904 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7905 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7907 memset(&c, 0, sizeof(c));
7908 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7909 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7910 FW_VI_MAC_CMD_VIID_V(viid));
7911 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7912 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7913 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7914 FW_VI_MAC_CMD_IDX_V(idx));
7915 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7917 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7919 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7920 if (ret >= max_mac_addr)
7927 * t4_set_addr_hash - program the MAC inexact-match hash filter
7928 * @adap: the adapter
7929 * @mbox: mailbox to use for the FW command
7931 * @ucast: whether the hash filter should also match unicast addresses
7932 * @vec: the value to be written to the hash filter
7933 * @sleep_ok: call is allowed to sleep
7935 * Sets the 64-bit inexact-match hash filter for a virtual interface.
7937 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7938 bool ucast, u64 vec, bool sleep_ok)
7940 struct fw_vi_mac_cmd c;
7942 memset(&c, 0, sizeof(c));
7943 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7944 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7945 FW_VI_ENABLE_CMD_VIID_V(viid));
7946 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7947 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7949 c.u.hash.hashvec = cpu_to_be64(vec);
7950 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7954 * t4_enable_vi_params - enable/disable a virtual interface
7955 * @adap: the adapter
7956 * @mbox: mailbox to use for the FW command
7958 * @rx_en: 1=enable Rx, 0=disable Rx
7959 * @tx_en: 1=enable Tx, 0=disable Tx
7960 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
7962 * Enables/disables a virtual interface. Note that setting DCB Enable
7963 * only makes sense when enabling a Virtual Interface ...
7965 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7966 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7968 struct fw_vi_enable_cmd c;
7970 memset(&c, 0, sizeof(c));
7971 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7972 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7973 FW_VI_ENABLE_CMD_VIID_V(viid));
7974 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7975 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7976 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7978 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7982 * t4_enable_vi - enable/disable a virtual interface
7983 * @adap: the adapter
7984 * @mbox: mailbox to use for the FW command
7986 * @rx_en: 1=enable Rx, 0=disable Rx
7987 * @tx_en: 1=enable Tx, 0=disable Tx
7989 * Enables/disables a virtual interface.
7991 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7992 bool rx_en, bool tx_en)
7994 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7998 * t4_identify_port - identify a VI's port by blinking its LED
7999 * @adap: the adapter
8000 * @mbox: mailbox to use for the FW command
8002 * @nblinks: how many times to blink LED at 2.5 Hz
8004 * Identifies a VI's port by blinking its LED.
8006 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8007 unsigned int nblinks)
8009 struct fw_vi_enable_cmd c;
8011 memset(&c, 0, sizeof(c));
8012 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8013 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8014 FW_VI_ENABLE_CMD_VIID_V(viid));
8015 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8016 c.blinkdur = cpu_to_be16(nblinks);
8017 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8021 * t4_iq_stop - stop an ingress queue and its FLs
8022 * @adap: the adapter
8023 * @mbox: mailbox to use for the FW command
8024 * @pf: the PF owning the queues
8025 * @vf: the VF owning the queues
8026 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8027 * @iqid: ingress queue id
8028 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8029 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8031 * Stops an ingress queue and its associated FLs, if any. This causes
8032 * any current or future data/messages destined for these queues to be
8035 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8036 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8037 unsigned int fl0id, unsigned int fl1id)
8041 memset(&c, 0, sizeof(c));
8042 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8043 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8044 FW_IQ_CMD_VFN_V(vf));
8045 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8046 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8047 c.iqid = cpu_to_be16(iqid);
8048 c.fl0id = cpu_to_be16(fl0id);
8049 c.fl1id = cpu_to_be16(fl1id);
8050 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8054 * t4_iq_free - free an ingress queue and its FLs
8055 * @adap: the adapter
8056 * @mbox: mailbox to use for the FW command
8057 * @pf: the PF owning the queues
8058 * @vf: the VF owning the queues
8059 * @iqtype: the ingress queue type
8060 * @iqid: ingress queue id
8061 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8062 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8064 * Frees an ingress queue and its associated FLs, if any.
8066 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8067 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8068 unsigned int fl0id, unsigned int fl1id)
8072 memset(&c, 0, sizeof(c));
8073 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8074 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8075 FW_IQ_CMD_VFN_V(vf));
8076 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8077 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8078 c.iqid = cpu_to_be16(iqid);
8079 c.fl0id = cpu_to_be16(fl0id);
8080 c.fl1id = cpu_to_be16(fl1id);
8081 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8085 * t4_eth_eq_free - free an Ethernet egress queue
8086 * @adap: the adapter
8087 * @mbox: mailbox to use for the FW command
8088 * @pf: the PF owning the queue
8089 * @vf: the VF owning the queue
8090 * @eqid: egress queue id
8092 * Frees an Ethernet egress queue.
8094 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8095 unsigned int vf, unsigned int eqid)
8097 struct fw_eq_eth_cmd c;
8099 memset(&c, 0, sizeof(c));
8100 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8101 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8102 FW_EQ_ETH_CMD_PFN_V(pf) |
8103 FW_EQ_ETH_CMD_VFN_V(vf));
8104 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8105 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8106 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8110 * t4_ctrl_eq_free - free a control egress queue
8111 * @adap: the adapter
8112 * @mbox: mailbox to use for the FW command
8113 * @pf: the PF owning the queue
8114 * @vf: the VF owning the queue
8115 * @eqid: egress queue id
8117 * Frees a control egress queue.
8119 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8120 unsigned int vf, unsigned int eqid)
8122 struct fw_eq_ctrl_cmd c;
8124 memset(&c, 0, sizeof(c));
8125 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8126 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8127 FW_EQ_CTRL_CMD_PFN_V(pf) |
8128 FW_EQ_CTRL_CMD_VFN_V(vf));
8129 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8130 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8131 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8135 * t4_ofld_eq_free - free an offload egress queue
8136 * @adap: the adapter
8137 * @mbox: mailbox to use for the FW command
8138 * @pf: the PF owning the queue
8139 * @vf: the VF owning the queue
8140 * @eqid: egress queue id
8142 * Frees a control egress queue.
8144 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8145 unsigned int vf, unsigned int eqid)
8147 struct fw_eq_ofld_cmd c;
8149 memset(&c, 0, sizeof(c));
8150 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8151 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8152 FW_EQ_OFLD_CMD_PFN_V(pf) |
8153 FW_EQ_OFLD_CMD_VFN_V(vf));
8154 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8155 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8156 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8160 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8161 * @adap: the adapter
8162 * @link_down_rc: Link Down Reason Code
8164 * Returns a string representation of the Link Down Reason Code.
8166 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8168 static const char * const reason[] = {
8171 "Auto-negotiation Failure",
8173 "Insufficient Airflow",
8174 "Unable To Determine Reason",
8175 "No RX Signal Detected",
8179 if (link_down_rc >= ARRAY_SIZE(reason))
8180 return "Bad Reason Code";
8182 return reason[link_down_rc];
8186 * Return the highest speed set in the port capabilities, in Mb/s.
8188 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8190 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8192 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8196 TEST_SPEED_RETURN(400G, 400000);
8197 TEST_SPEED_RETURN(200G, 200000);
8198 TEST_SPEED_RETURN(100G, 100000);
8199 TEST_SPEED_RETURN(50G, 50000);
8200 TEST_SPEED_RETURN(40G, 40000);
8201 TEST_SPEED_RETURN(25G, 25000);
8202 TEST_SPEED_RETURN(10G, 10000);
8203 TEST_SPEED_RETURN(1G, 1000);
8204 TEST_SPEED_RETURN(100M, 100);
8206 #undef TEST_SPEED_RETURN
8212 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8213 * @acaps: advertised Port Capabilities
8215 * Get the highest speed for the port from the advertised Port
8216 * Capabilities. It will be either the highest speed from the list of
8217 * speeds or whatever user has set using ethtool.
8219 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8221 #define TEST_SPEED_RETURN(__caps_speed) \
8223 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8224 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8227 TEST_SPEED_RETURN(400G);
8228 TEST_SPEED_RETURN(200G);
8229 TEST_SPEED_RETURN(100G);
8230 TEST_SPEED_RETURN(50G);
8231 TEST_SPEED_RETURN(40G);
8232 TEST_SPEED_RETURN(25G);
8233 TEST_SPEED_RETURN(10G);
8234 TEST_SPEED_RETURN(1G);
8235 TEST_SPEED_RETURN(100M);
8237 #undef TEST_SPEED_RETURN
8243 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8244 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8246 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8247 * 32-bit Port Capabilities value.
8249 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8251 fw_port_cap32_t linkattr = 0;
8253 /* Unfortunately the format of the Link Status in the old
8254 * 16-bit Port Information message isn't the same as the
8255 * 16-bit Port Capabilities bitfield used everywhere else ...
8257 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8258 linkattr |= FW_PORT_CAP32_FC_RX;
8259 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8260 linkattr |= FW_PORT_CAP32_FC_TX;
8261 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8262 linkattr |= FW_PORT_CAP32_SPEED_100M;
8263 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8264 linkattr |= FW_PORT_CAP32_SPEED_1G;
8265 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8266 linkattr |= FW_PORT_CAP32_SPEED_10G;
8267 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8268 linkattr |= FW_PORT_CAP32_SPEED_25G;
8269 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8270 linkattr |= FW_PORT_CAP32_SPEED_40G;
8271 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8272 linkattr |= FW_PORT_CAP32_SPEED_100G;
8278 * t4_handle_get_port_info - process a FW reply message
8279 * @pi: the port info
8280 * @rpl: start of the FW message
8282 * Processes a GET_PORT_INFO FW reply message.
8284 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8286 const struct fw_port_cmd *cmd = (const void *)rpl;
8287 int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8288 struct adapter *adapter = pi->adapter;
8289 struct link_config *lc = &pi->link_cfg;
8290 int link_ok, linkdnrc;
8291 enum fw_port_type port_type;
8292 enum fw_port_module_type mod_type;
8293 unsigned int speed, fc, fec;
8294 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8296 /* Extract the various fields from the Port Information message.
8299 case FW_PORT_ACTION_GET_PORT_INFO: {
8300 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8302 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8303 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8304 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8305 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8306 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8307 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8308 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8309 linkattr = lstatus_to_fwcap(lstatus);
8313 case FW_PORT_ACTION_GET_PORT_INFO32: {
8316 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8317 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8318 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8319 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8320 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8321 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8322 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8323 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8324 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8329 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8330 be32_to_cpu(cmd->action_to_len16));
8334 fec = fwcap_to_cc_fec(acaps);
8335 fc = fwcap_to_cc_pause(linkattr);
8336 speed = fwcap_to_speed(linkattr);
8338 if (mod_type != pi->mod_type) {
8339 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8340 * various fundamental Port Capabilities which used to be
8341 * immutable can now change radically. We can now have
8342 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8343 * all change based on what Transceiver Module is inserted.
8344 * So we need to record the Physical "Port" Capabilities on
8345 * every Transceiver Module change.
8349 /* When a new Transceiver Module is inserted, the Firmware
8350 * will examine its i2c EPROM to determine its type and
8351 * general operating parameters including things like Forward
8352 * Error Control, etc. Various IEEE 802.3 standards dictate
8353 * how to interpret these i2c values to determine default
8354 * "sutomatic" settings. We record these for future use when
8355 * the user explicitly requests these standards-based values.
8357 lc->def_acaps = acaps;
8359 /* Some versions of the early T6 Firmware "cheated" when
8360 * handling different Transceiver Modules by changing the
8361 * underlaying Port Type reported to the Host Drivers. As
8362 * such we need to capture whatever Port Type the Firmware
8363 * sends us and record it in case it's different from what we
8364 * were told earlier. Unfortunately, since Firmware is
8365 * forever, we'll need to keep this code here forever, but in
8366 * later T6 Firmware it should just be an assignment of the
8367 * same value already recorded.
8369 pi->port_type = port_type;
8371 pi->mod_type = mod_type;
8372 t4_os_portmod_changed(adapter, pi->port_id);
8375 if (link_ok != lc->link_ok || speed != lc->speed ||
8376 fc != lc->fc || fec != lc->fec) { /* something changed */
8377 if (!link_ok && lc->link_ok) {
8378 lc->link_down_rc = linkdnrc;
8379 dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
8380 pi->tx_chan, t4_link_down_rc_str(linkdnrc));
8382 lc->link_ok = link_ok;
8387 lc->lpacaps = lpacaps;
8388 lc->acaps = acaps & ADVERT_MASK;
8390 if (lc->acaps & FW_PORT_CAP32_ANEG) {
8391 lc->autoneg = AUTONEG_ENABLE;
8393 /* When Autoneg is disabled, user needs to set
8395 * Similar to cxgb4_ethtool.c: set_link_ksettings
8398 lc->speed_caps = fwcap_to_fwspeed(acaps);
8399 lc->autoneg = AUTONEG_DISABLE;
8402 t4_os_link_changed(adapter, pi->port_id, link_ok);
8407 * t4_update_port_info - retrieve and update port information if changed
8408 * @pi: the port_info
8410 * We issue a Get Port Information Command to the Firmware and, if
8411 * successful, we check to see if anything is different from what we
8412 * last recorded and update things accordingly.
8414 int t4_update_port_info(struct port_info *pi)
8416 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8417 struct fw_port_cmd port_cmd;
8420 memset(&port_cmd, 0, sizeof(port_cmd));
8421 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8422 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8423 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8424 port_cmd.action_to_len16 = cpu_to_be32(
8425 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8426 ? FW_PORT_ACTION_GET_PORT_INFO
8427 : FW_PORT_ACTION_GET_PORT_INFO32) |
8428 FW_LEN16(port_cmd));
8429 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8430 &port_cmd, sizeof(port_cmd), &port_cmd);
8434 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8439 * t4_get_link_params - retrieve basic link parameters for given port
8441 * @link_okp: value return pointer for link up/down
8442 * @speedp: value return pointer for speed (Mb/s)
8443 * @mtup: value return pointer for mtu
8445 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8446 * and MTU for a specified port. A negative error is returned on
8447 * failure; 0 on success.
8449 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8450 unsigned int *speedp, unsigned int *mtup)
8452 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8453 struct fw_port_cmd port_cmd;
8454 unsigned int action, link_ok, speed, mtu;
8455 fw_port_cap32_t linkattr;
8458 memset(&port_cmd, 0, sizeof(port_cmd));
8459 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8460 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8461 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8462 action = (fw_caps == FW_CAPS16
8463 ? FW_PORT_ACTION_GET_PORT_INFO
8464 : FW_PORT_ACTION_GET_PORT_INFO32);
8465 port_cmd.action_to_len16 = cpu_to_be32(
8466 FW_PORT_CMD_ACTION_V(action) |
8467 FW_LEN16(port_cmd));
8468 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8469 &port_cmd, sizeof(port_cmd), &port_cmd);
8473 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8474 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8476 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8477 linkattr = lstatus_to_fwcap(lstatus);
8478 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8481 be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8483 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8484 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8485 mtu = FW_PORT_CMD_MTU32_G(
8486 be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8488 speed = fwcap_to_speed(linkattr);
8490 *link_okp = link_ok;
8491 *speedp = fwcap_to_speed(linkattr);
8498 * t4_handle_fw_rpl - process a FW reply message
8499 * @adap: the adapter
8500 * @rpl: start of the FW message
8502 * Processes a FW message, such as link state change messages.
8504 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8506 u8 opcode = *(const u8 *)rpl;
8508 /* This might be a port command ... this simplifies the following
8509 * conditionals ... We can get away with pre-dereferencing
8510 * action_to_len16 because it's in the first 16 bytes and all messages
8511 * will be at least that long.
8513 const struct fw_port_cmd *p = (const void *)rpl;
8514 unsigned int action =
8515 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8517 if (opcode == FW_PORT_CMD &&
8518 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8519 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8521 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8522 struct port_info *pi = NULL;
8524 for_each_port(adap, i) {
8525 pi = adap2pinfo(adap, i);
8526 if (pi->tx_chan == chan)
8530 t4_handle_get_port_info(pi, rpl);
8532 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8539 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8543 if (pci_is_pcie(adapter->pdev)) {
8544 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8545 p->speed = val & PCI_EXP_LNKSTA_CLS;
8546 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8551 * init_link_config - initialize a link's SW state
8552 * @lc: pointer to structure holding the link state
8553 * @pcaps: link Port Capabilities
8554 * @acaps: link current Advertised Port Capabilities
8556 * Initializes the SW state maintained for each link, including the link's
8557 * capabilities and default speed/flow-control/autonegotiation settings.
8559 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8560 fw_port_cap32_t acaps)
8563 lc->def_acaps = acaps;
8567 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8569 /* For Forward Error Control, we default to whatever the Firmware
8570 * tells us the Link is currently advertising.
8572 lc->requested_fec = FEC_AUTO;
8573 lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8575 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8576 lc->acaps = lc->pcaps & ADVERT_MASK;
8577 lc->autoneg = AUTONEG_ENABLE;
8578 lc->requested_fc |= PAUSE_AUTONEG;
8581 lc->autoneg = AUTONEG_DISABLE;
8585 #define CIM_PF_NOACCESS 0xeeeeeeee
8587 int t4_wait_dev_ready(void __iomem *regs)
8591 whoami = readl(regs + PL_WHOAMI_A);
8592 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8596 whoami = readl(regs + PL_WHOAMI_A);
8597 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8601 u32 vendor_and_model_id;
8605 static int t4_get_flash_params(struct adapter *adap)
8607 /* Table for non-Numonix supported flash parts. Numonix parts are left
8608 * to the preexisting code. All flash parts have 64KB sectors.
8610 static struct flash_desc supported_flash[] = {
8611 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8614 unsigned int part, manufacturer;
8615 unsigned int density, size;
8619 /* Issue a Read ID Command to the Flash part. We decode supported
8620 * Flash parts and their sizes from this. There's a newer Query
8621 * Command which can retrieve detailed geometry information but many
8622 * Flash parts don't support it.
8625 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8627 ret = sf1_read(adap, 3, 0, 1, &flashid);
8628 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
8632 /* Check to see if it's one of our non-standard supported Flash parts.
8634 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8635 if (supported_flash[part].vendor_and_model_id == flashid) {
8636 adap->params.sf_size = supported_flash[part].size_mb;
8637 adap->params.sf_nsec =
8638 adap->params.sf_size / SF_SEC_SIZE;
8642 /* Decode Flash part size. The code below looks repetative with
8643 * common encodings, but that's not guaranteed in the JEDEC
8644 * specification for the Read JADEC ID command. The only thing that
8645 * we're guaranteed by the JADEC specification is where the
8646 * Manufacturer ID is in the returned result. After that each
8647 * Manufacturer ~could~ encode things completely differently.
8648 * Note, all Flash parts must have 64KB sectors.
8650 manufacturer = flashid & 0xff;
8651 switch (manufacturer) {
8652 case 0x20: { /* Micron/Numonix */
8653 /* This Density -> Size decoding table is taken from Micron
8656 density = (flashid >> 16) & 0xff;
8658 case 0x14: /* 1MB */
8661 case 0x15: /* 2MB */
8664 case 0x16: /* 4MB */
8667 case 0x17: /* 8MB */
8670 case 0x18: /* 16MB */
8673 case 0x19: /* 32MB */
8676 case 0x20: /* 64MB */
8679 case 0x21: /* 128MB */
8682 case 0x22: /* 256MB */
8687 dev_err(adap->pdev_dev, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
8693 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
8694 /* This Density -> Size decoding table is taken from ISSI
8697 density = (flashid >> 16) & 0xff;
8699 case 0x16: /* 32 MB */
8702 case 0x17: /* 64MB */
8706 dev_err(adap->pdev_dev, "ISSI Flash Part has bad size, ID = %#x, Density code = %#x\n",
8712 case 0xc2: { /* Macronix */
8713 /* This Density -> Size decoding table is taken from Macronix
8716 density = (flashid >> 16) & 0xff;
8718 case 0x17: /* 8MB */
8721 case 0x18: /* 16MB */
8725 dev_err(adap->pdev_dev, "Macronix Flash Part has bad size, ID = %#x, Density code = %#x\n",
8731 case 0xef: { /* Winbond */
8732 /* This Density -> Size decoding table is taken from Winbond
8735 density = (flashid >> 16) & 0xff;
8737 case 0x17: /* 8MB */
8740 case 0x18: /* 16MB */
8744 dev_err(adap->pdev_dev, "Winbond Flash Part has bad size, ID = %#x, Density code = %#x\n",
8751 dev_err(adap->pdev_dev, "Unsupported Flash Part, ID = %#x\n",
8756 /* Store decoded Flash size and fall through into vetting code. */
8757 adap->params.sf_size = size;
8758 adap->params.sf_nsec = size / SF_SEC_SIZE;
8761 if (adap->params.sf_size < FLASH_MIN_SIZE)
8762 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8763 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
8768 * t4_prep_adapter - prepare SW and HW for operation
8769 * @adapter: the adapter
8770 * @reset: if true perform a HW reset
8772 * Initialize adapter SW state for the various HW modules, set initial
8773 * values for some adapter tunables, take PHYs out of reset, and
8774 * initialize the MDIO interface.
8776 int t4_prep_adapter(struct adapter *adapter)
8782 get_pci_mode(adapter, &adapter->params.pci);
8783 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8785 ret = t4_get_flash_params(adapter);
8787 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8791 /* Retrieve adapter's device ID
8793 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8794 ver = device_id >> 12;
8795 adapter->params.chip = 0;
8798 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8799 adapter->params.arch.sge_fl_db = DBPRIO_F;
8800 adapter->params.arch.mps_tcam_size =
8801 NUM_MPS_CLS_SRAM_L_INSTANCES;
8802 adapter->params.arch.mps_rplc_size = 128;
8803 adapter->params.arch.nchan = NCHAN;
8804 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8805 adapter->params.arch.vfcount = 128;
8806 /* Congestion map is for 4 channels so that
8807 * MPS can have 4 priority per port.
8809 adapter->params.arch.cng_ch_bits_log = 2;
8812 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8813 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8814 adapter->params.arch.mps_tcam_size =
8815 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8816 adapter->params.arch.mps_rplc_size = 128;
8817 adapter->params.arch.nchan = NCHAN;
8818 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8819 adapter->params.arch.vfcount = 128;
8820 adapter->params.arch.cng_ch_bits_log = 2;
8823 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8824 adapter->params.arch.sge_fl_db = 0;
8825 adapter->params.arch.mps_tcam_size =
8826 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8827 adapter->params.arch.mps_rplc_size = 256;
8828 adapter->params.arch.nchan = 2;
8829 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8830 adapter->params.arch.vfcount = 256;
8831 /* Congestion map will be for 2 channels so that
8832 * MPS can have 8 priority per port.
8834 adapter->params.arch.cng_ch_bits_log = 3;
8837 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8842 adapter->params.cim_la_size = CIMLA_SIZE;
8843 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8846 * Default port for debugging in case we can't reach FW.
8848 adapter->params.nports = 1;
8849 adapter->params.portvec = 1;
8850 adapter->params.vpd.cclk = 50000;
8852 /* Set PCIe completion timeout to 4 seconds. */
8853 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
8854 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
8859 * t4_shutdown_adapter - shut down adapter, host & wire
8860 * @adapter: the adapter
8862 * Perform an emergency shutdown of the adapter and stop it from
8863 * continuing any further communication on the ports or DMA to the
8864 * host. This is typically used when the adapter and/or firmware
8865 * have crashed and we want to prevent any further accidental
8866 * communication with the rest of the world. This will also force
8867 * the port Link Status to go down -- if register writes work --
8868 * which should help our peers figure out that we're down.
8870 int t4_shutdown_adapter(struct adapter *adapter)
8874 t4_intr_disable(adapter);
8875 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8876 for_each_port(adapter, port) {
8877 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8878 PORT_REG(port, XGMAC_PORT_CFG_A) :
8879 T5_PORT_REG(port, MAC_PORT_CFG_A);
8881 t4_write_reg(adapter, a_port_cfg,
8882 t4_read_reg(adapter, a_port_cfg)
8883 & ~SIGNAL_DET_V(1));
8885 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8891 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8892 * @adapter: the adapter
8893 * @qid: the Queue ID
8894 * @qtype: the Ingress or Egress type for @qid
8895 * @user: true if this request is for a user mode queue
8896 * @pbar2_qoffset: BAR2 Queue Offset
8897 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8899 * Returns the BAR2 SGE Queue Registers information associated with the
8900 * indicated Absolute Queue ID. These are passed back in return value
8901 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8902 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8904 * This may return an error which indicates that BAR2 SGE Queue
8905 * registers aren't available. If an error is not returned, then the
8906 * following values are returned:
8908 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8909 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8911 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8912 * require the "Inferred Queue ID" ability may be used. E.g. the
8913 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8914 * then these "Inferred Queue ID" register may not be used.
8916 int t4_bar2_sge_qregs(struct adapter *adapter,
8918 enum t4_bar2_qtype qtype,
8921 unsigned int *pbar2_qid)
8923 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
8924 u64 bar2_page_offset, bar2_qoffset;
8925 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
8927 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8928 if (!user && is_t4(adapter->params.chip))
8931 /* Get our SGE Page Size parameters.
8933 page_shift = adapter->params.sge.hps + 10;
8934 page_size = 1 << page_shift;
8936 /* Get the right Queues per Page parameters for our Queue.
8938 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
8939 ? adapter->params.sge.eq_qpp
8940 : adapter->params.sge.iq_qpp);
8941 qpp_mask = (1 << qpp_shift) - 1;
8943 /* Calculate the basics of the BAR2 SGE Queue register area:
8944 * o The BAR2 page the Queue registers will be in.
8945 * o The BAR2 Queue ID.
8946 * o The BAR2 Queue ID Offset into the BAR2 page.
8948 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
8949 bar2_qid = qid & qpp_mask;
8950 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
8952 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8953 * hardware will infer the Absolute Queue ID simply from the writes to
8954 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8955 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
8956 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8957 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8958 * from the BAR2 Page and BAR2 Queue ID.
8960 * One important censequence of this is that some BAR2 SGE registers
8961 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8962 * there. But other registers synthesize the SGE Queue ID purely
8963 * from the writes to the registers -- the Write Combined Doorbell
8964 * Buffer is a good example. These BAR2 SGE Registers are only
8965 * available for those BAR2 SGE Register areas where the SGE Absolute
8966 * Queue ID can be inferred from simple writes.
8968 bar2_qoffset = bar2_page_offset;
8969 bar2_qinferred = (bar2_qid_offset < page_size);
8970 if (bar2_qinferred) {
8971 bar2_qoffset += bar2_qid_offset;
8975 *pbar2_qoffset = bar2_qoffset;
8976 *pbar2_qid = bar2_qid;
8981 * t4_init_devlog_params - initialize adapter->params.devlog
8982 * @adap: the adapter
8984 * Initialize various fields of the adapter's Firmware Device Log
8985 * Parameters structure.
8987 int t4_init_devlog_params(struct adapter *adap)
8989 struct devlog_params *dparams = &adap->params.devlog;
8991 unsigned int devlog_meminfo;
8992 struct fw_devlog_cmd devlog_cmd;
8995 /* If we're dealing with newer firmware, the Device Log Paramerters
8996 * are stored in a designated register which allows us to access the
8997 * Device Log even if we can't talk to the firmware.
9000 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9002 unsigned int nentries, nentries128;
9004 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9005 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9007 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9008 nentries = (nentries128 + 1) * 128;
9009 dparams->size = nentries * sizeof(struct fw_devlog_e);
9014 /* Otherwise, ask the firmware for it's Device Log Parameters.
9016 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9017 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9018 FW_CMD_REQUEST_F | FW_CMD_READ_F);
9019 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9020 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9026 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9027 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9028 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9029 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9035 * t4_init_sge_params - initialize adap->params.sge
9036 * @adapter: the adapter
9038 * Initialize various fields of the adapter's SGE Parameters structure.
9040 int t4_init_sge_params(struct adapter *adapter)
9042 struct sge_params *sge_params = &adapter->params.sge;
9044 unsigned int s_hps, s_qpp;
9046 /* Extract the SGE Page Size for our PF.
9048 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9049 s_hps = (HOSTPAGESIZEPF0_S +
9050 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9051 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9053 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9055 s_qpp = (QUEUESPERPAGEPF0_S +
9056 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9057 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9058 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9059 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9060 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9066 * t4_init_tp_params - initialize adap->params.tp
9067 * @adap: the adapter
9068 * @sleep_ok: if true we may sleep while awaiting command completion
9070 * Initialize various fields of the adapter's TP Parameters structure.
9072 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9077 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9078 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9079 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9081 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9082 for (chan = 0; chan < NCHAN; chan++)
9083 adap->params.tp.tx_modq[chan] = chan;
9085 /* Cache the adapter's Compressed Filter Mode and global Incress
9088 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9089 TP_VLAN_PRI_MAP_A, sleep_ok);
9090 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9091 TP_INGRESS_CONFIG_A, sleep_ok);
9093 /* For T6, cache the adapter's compressed error vector
9094 * and passing outer header info for encapsulated packets.
9096 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9097 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9098 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9101 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9102 * shift positions of several elements of the Compressed Filter Tuple
9103 * for this adapter which we need frequently ...
9105 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9106 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9107 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9108 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9109 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9110 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9112 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9114 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9116 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9118 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9121 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9122 * represents the presence of an Outer VLAN instead of a VNIC ID.
9124 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9125 adap->params.tp.vnic_shift = -1;
9127 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9128 adap->params.tp.hash_filter_mask = v;
9129 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9130 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9135 * t4_filter_field_shift - calculate filter field shift
9136 * @adap: the adapter
9137 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9139 * Return the shift position of a filter field within the Compressed
9140 * Filter Tuple. The filter field is specified via its selection bit
9141 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9143 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9145 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9149 if ((filter_mode & filter_sel) == 0)
9152 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9153 switch (filter_mode & sel) {
9155 field_shift += FT_FCOE_W;
9158 field_shift += FT_PORT_W;
9161 field_shift += FT_VNIC_ID_W;
9164 field_shift += FT_VLAN_W;
9167 field_shift += FT_TOS_W;
9170 field_shift += FT_PROTOCOL_W;
9173 field_shift += FT_ETHERTYPE_W;
9176 field_shift += FT_MACMATCH_W;
9179 field_shift += FT_MPSHITTYPE_W;
9181 case FRAGMENTATION_F:
9182 field_shift += FT_FRAGMENTATION_W;
9189 int t4_init_rss_mode(struct adapter *adap, int mbox)
9192 struct fw_rss_vi_config_cmd rvc;
9194 memset(&rvc, 0, sizeof(rvc));
9196 for_each_port(adap, i) {
9197 struct port_info *p = adap2pinfo(adap, i);
9200 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9201 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9202 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9203 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9204 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9207 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9213 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9214 * @pi: the port_info
9215 * @mbox: mailbox to use for the FW command
9216 * @port: physical port associated with the VI
9217 * @pf: the PF owning the VI
9218 * @vf: the VF owning the VI
9219 * @mac: the MAC address of the VI
9221 * Allocates a virtual interface for the given physical port. If @mac is
9222 * not %NULL it contains the MAC address of the VI as assigned by FW.
9223 * @mac should be large enough to hold an Ethernet address.
9224 * Returns < 0 on error.
9226 int t4_init_portinfo(struct port_info *pi, int mbox,
9227 int port, int pf, int vf, u8 mac[])
9229 struct adapter *adapter = pi->adapter;
9230 unsigned int fw_caps = adapter->params.fw_caps_support;
9231 struct fw_port_cmd cmd;
9232 unsigned int rss_size;
9233 enum fw_port_type port_type;
9235 fw_port_cap32_t pcaps, acaps;
9238 /* If we haven't yet determined whether we're talking to Firmware
9239 * which knows the new 32-bit Port Capabilities, it's time to find
9240 * out now. This will also tell new Firmware to send us Port Status
9241 * Updates using the new 32-bit Port Capabilities version of the
9242 * Port Information message.
9244 if (fw_caps == FW_CAPS_UNKNOWN) {
9247 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9248 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9250 ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val);
9251 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9252 adapter->params.fw_caps_support = fw_caps;
9255 memset(&cmd, 0, sizeof(cmd));
9256 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9257 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9258 FW_PORT_CMD_PORTID_V(port));
9259 cmd.action_to_len16 = cpu_to_be32(
9260 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9261 ? FW_PORT_ACTION_GET_PORT_INFO
9262 : FW_PORT_ACTION_GET_PORT_INFO32) |
9264 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9268 /* Extract the various fields from the Port Information message.
9270 if (fw_caps == FW_CAPS16) {
9271 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9273 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9274 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9275 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9277 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9278 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9280 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9282 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9283 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9284 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9286 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9287 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9290 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
9297 pi->rss_size = rss_size;
9299 pi->port_type = port_type;
9300 pi->mdio_addr = mdio_addr;
9301 pi->mod_type = FW_PORT_MOD_TYPE_NA;
9303 init_link_config(&pi->link_cfg, pcaps, acaps);
9307 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9312 for_each_port(adap, i) {
9313 struct port_info *pi = adap2pinfo(adap, i);
9315 while ((adap->params.portvec & (1 << j)) == 0)
9318 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9322 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9329 * t4_read_cimq_cfg - read CIM queue configuration
9330 * @adap: the adapter
9331 * @base: holds the queue base addresses in bytes
9332 * @size: holds the queue sizes in bytes
9333 * @thres: holds the queue full thresholds in bytes
9335 * Returns the current configuration of the CIM queues, starting with
9336 * the IBQs, then the OBQs.
9338 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9341 int cim_num_obq = is_t4(adap->params.chip) ?
9342 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9344 for (i = 0; i < CIM_NUM_IBQ; i++) {
9345 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9347 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9348 /* value is in 256-byte units */
9349 *base++ = CIMQBASE_G(v) * 256;
9350 *size++ = CIMQSIZE_G(v) * 256;
9351 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9353 for (i = 0; i < cim_num_obq; i++) {
9354 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9356 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9357 /* value is in 256-byte units */
9358 *base++ = CIMQBASE_G(v) * 256;
9359 *size++ = CIMQSIZE_G(v) * 256;
9364 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9365 * @adap: the adapter
9366 * @qid: the queue index
9367 * @data: where to store the queue contents
9368 * @n: capacity of @data in 32-bit words
9370 * Reads the contents of the selected CIM queue starting at address 0 up
9371 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9372 * error and the number of 32-bit words actually read on success.
9374 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9376 int i, err, attempts;
9378 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9380 if (qid > 5 || (n & 3))
9383 addr = qid * nwords;
9387 /* It might take 3-10ms before the IBQ debug read access is allowed.
9388 * Wait for 1 Sec with a delay of 1 usec.
9392 for (i = 0; i < n; i++, addr++) {
9393 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9395 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9399 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9401 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9406 * t4_read_cim_obq - read the contents of a CIM outbound queue
9407 * @adap: the adapter
9408 * @qid: the queue index
9409 * @data: where to store the queue contents
9410 * @n: capacity of @data in 32-bit words
9412 * Reads the contents of the selected CIM queue starting at address 0 up
9413 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9414 * error and the number of 32-bit words actually read on success.
9416 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9419 unsigned int addr, v, nwords;
9420 int cim_num_obq = is_t4(adap->params.chip) ?
9421 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9423 if ((qid > (cim_num_obq - 1)) || (n & 3))
9426 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9427 QUENUMSELECT_V(qid));
9428 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9430 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
9431 nwords = CIMQSIZE_G(v) * 64; /* same */
9435 for (i = 0; i < n; i++, addr++) {
9436 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9438 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9442 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9444 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9449 * t4_cim_read - read a block from CIM internal address space
9450 * @adap: the adapter
9451 * @addr: the start address within the CIM address space
9452 * @n: number of words to read
9453 * @valp: where to store the result
9455 * Reads a block of 4-byte words from the CIM intenal address space.
9457 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9462 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9465 for ( ; !ret && n--; addr += 4) {
9466 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9467 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9470 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9476 * t4_cim_write - write a block into CIM internal address space
9477 * @adap: the adapter
9478 * @addr: the start address within the CIM address space
9479 * @n: number of words to write
9480 * @valp: set of values to write
9482 * Writes a block of 4-byte words into the CIM intenal address space.
9484 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9485 const unsigned int *valp)
9489 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9492 for ( ; !ret && n--; addr += 4) {
9493 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9494 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9495 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9501 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9504 return t4_cim_write(adap, addr, 1, &val);
9508 * t4_cim_read_la - read CIM LA capture buffer
9509 * @adap: the adapter
9510 * @la_buf: where to store the LA data
9511 * @wrptr: the HW write pointer within the capture buffer
9513 * Reads the contents of the CIM LA buffer with the most recent entry at
9514 * the end of the returned data and with the entry at @wrptr first.
9515 * We try to leave the LA in the running state we find it in.
9517 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9520 unsigned int cfg, val, idx;
9522 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9526 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
9527 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9532 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9536 idx = UPDBGLAWRPTR_G(val);
9540 for (i = 0; i < adap->params.cim_la_size; i++) {
9541 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9542 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9545 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9548 if (val & UPDBGLARDEN_F) {
9552 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9556 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9557 * identify the 32-bit portion of the full 312-bit data
9559 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9560 idx = (idx & 0xff0) + 0x10;
9563 /* address can't exceed 0xfff */
9564 idx &= UPDBGLARDPTR_M;
9567 if (cfg & UPDBGLAEN_F) {
9568 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9569 cfg & ~UPDBGLARDEN_F);
9577 * t4_tp_read_la - read TP LA capture buffer
9578 * @adap: the adapter
9579 * @la_buf: where to store the LA data
9580 * @wrptr: the HW write pointer within the capture buffer
9582 * Reads the contents of the TP LA buffer with the most recent entry at
9583 * the end of the returned data and with the entry at @wrptr first.
9584 * We leave the LA in the running state we find it in.
9586 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9588 bool last_incomplete;
9589 unsigned int i, cfg, val, idx;
9591 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9592 if (cfg & DBGLAENABLE_F) /* freeze LA */
9593 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9594 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9596 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9597 idx = DBGLAWPTR_G(val);
9598 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9599 if (last_incomplete)
9600 idx = (idx + 1) & DBGLARPTR_M;
9605 val &= ~DBGLARPTR_V(DBGLARPTR_M);
9606 val |= adap->params.tp.la_mask;
9608 for (i = 0; i < TPLA_SIZE; i++) {
9609 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9610 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9611 idx = (idx + 1) & DBGLARPTR_M;
9614 /* Wipe out last entry if it isn't valid */
9615 if (last_incomplete)
9616 la_buf[TPLA_SIZE - 1] = ~0ULL;
9618 if (cfg & DBGLAENABLE_F) /* restore running state */
9619 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9620 cfg | adap->params.tp.la_mask);
9623 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9624 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
9625 * state for more than the Warning Threshold then we'll issue a warning about
9626 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
9627 * appears to be hung every Warning Repeat second till the situation clears.
9628 * If the situation clears, we'll note that as well.
9630 #define SGE_IDMA_WARN_THRESH 1
9631 #define SGE_IDMA_WARN_REPEAT 300
9634 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9635 * @adapter: the adapter
9636 * @idma: the adapter IDMA Monitor state
9638 * Initialize the state of an SGE Ingress DMA Monitor.
9640 void t4_idma_monitor_init(struct adapter *adapter,
9641 struct sge_idma_monitor_state *idma)
9643 /* Initialize the state variables for detecting an SGE Ingress DMA
9644 * hang. The SGE has internal counters which count up on each clock
9645 * tick whenever the SGE finds its Ingress DMA State Engines in the
9646 * same state they were on the previous clock tick. The clock used is
9647 * the Core Clock so we have a limit on the maximum "time" they can
9648 * record; typically a very small number of seconds. For instance,
9649 * with a 600MHz Core Clock, we can only count up to a bit more than
9650 * 7s. So we'll synthesize a larger counter in order to not run the
9651 * risk of having the "timers" overflow and give us the flexibility to
9652 * maintain a Hung SGE State Machine of our own which operates across
9653 * a longer time frame.
9655 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9656 idma->idma_stalled[0] = 0;
9657 idma->idma_stalled[1] = 0;
9661 * t4_idma_monitor - monitor SGE Ingress DMA state
9662 * @adapter: the adapter
9663 * @idma: the adapter IDMA Monitor state
9664 * @hz: number of ticks/second
9665 * @ticks: number of ticks since the last IDMA Monitor call
9667 void t4_idma_monitor(struct adapter *adapter,
9668 struct sge_idma_monitor_state *idma,
9671 int i, idma_same_state_cnt[2];
9673 /* Read the SGE Debug Ingress DMA Same State Count registers. These
9674 * are counters inside the SGE which count up on each clock when the
9675 * SGE finds its Ingress DMA State Engines in the same states they
9676 * were in the previous clock. The counters will peg out at
9677 * 0xffffffff without wrapping around so once they pass the 1s
9678 * threshold they'll stay above that till the IDMA state changes.
9680 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9681 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9682 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9684 for (i = 0; i < 2; i++) {
9685 u32 debug0, debug11;
9687 /* If the Ingress DMA Same State Counter ("timer") is less
9688 * than 1s, then we can reset our synthesized Stall Timer and
9689 * continue. If we have previously emitted warnings about a
9690 * potential stalled Ingress Queue, issue a note indicating
9691 * that the Ingress Queue has resumed forward progress.
9693 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9694 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9695 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9696 "resumed after %d seconds\n",
9697 i, idma->idma_qid[i],
9698 idma->idma_stalled[i] / hz);
9699 idma->idma_stalled[i] = 0;
9703 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9704 * domain. The first time we get here it'll be because we
9705 * passed the 1s Threshold; each additional time it'll be
9706 * because the RX Timer Callback is being fired on its regular
9709 * If the stall is below our Potential Hung Ingress Queue
9710 * Warning Threshold, continue.
9712 if (idma->idma_stalled[i] == 0) {
9713 idma->idma_stalled[i] = hz;
9714 idma->idma_warn[i] = 0;
9716 idma->idma_stalled[i] += ticks;
9717 idma->idma_warn[i] -= ticks;
9720 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9723 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9725 if (idma->idma_warn[i] > 0)
9727 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9729 /* Read and save the SGE IDMA State and Queue ID information.
9730 * We do this every time in case it changes across time ...
9731 * can't be too careful ...
9733 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9734 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9735 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9737 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9738 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9739 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9741 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9742 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9743 i, idma->idma_qid[i], idma->idma_state[i],
9744 idma->idma_stalled[i] / hz,
9746 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9751 * t4_load_cfg - download config file
9752 * @adap: the adapter
9753 * @cfg_data: the cfg text file to write
9754 * @size: text file size
9756 * Write the supplied config text file to the card's serial flash.
9758 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9760 int ret, i, n, cfg_addr;
9762 unsigned int flash_cfg_start_sec;
9763 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9765 cfg_addr = t4_flash_cfg_addr(adap);
9770 flash_cfg_start_sec = addr / SF_SEC_SIZE;
9772 if (size > FLASH_CFG_MAX_SIZE) {
9773 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9774 FLASH_CFG_MAX_SIZE);
9778 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
9780 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9781 flash_cfg_start_sec + i - 1);
9782 /* If size == 0 then we're simply erasing the FLASH sectors associated
9783 * with the on-adapter Firmware Configuration File.
9785 if (ret || size == 0)
9788 /* this will write to the flash up to SF_PAGE_SIZE at a time */
9789 for (i = 0; i < size; i += SF_PAGE_SIZE) {
9790 if ((size - i) < SF_PAGE_SIZE)
9794 ret = t4_write_flash(adap, addr, n, cfg_data);
9798 addr += SF_PAGE_SIZE;
9799 cfg_data += SF_PAGE_SIZE;
9804 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9805 (size == 0 ? "clear" : "download"), ret);
9810 * t4_set_vf_mac - Set MAC address for the specified VF
9811 * @adapter: The adapter
9812 * @vf: one of the VFs instantiated by the specified PF
9813 * @naddr: the number of MAC addresses
9814 * @addr: the MAC address(es) to be set to the specified VF
9816 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9817 unsigned int naddr, u8 *addr)
9819 struct fw_acl_mac_cmd cmd;
9821 memset(&cmd, 0, sizeof(cmd));
9822 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9825 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9826 FW_ACL_MAC_CMD_VFN_V(vf));
9828 /* Note: Do not enable the ACL */
9829 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9832 switch (adapter->pf) {
9834 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9837 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9840 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9843 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9847 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9851 * t4_read_pace_tbl - read the pace table
9852 * @adap: the adapter
9853 * @pace_vals: holds the returned values
9855 * Returns the values of TP's pace table in microseconds.
9857 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9861 for (i = 0; i < NTX_SCHED; i++) {
9862 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
9863 v = t4_read_reg(adap, TP_PACE_TABLE_A);
9864 pace_vals[i] = dack_ticks_to_usec(adap, v);
9869 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9870 * @adap: the adapter
9871 * @sched: the scheduler index
9872 * @kbps: the byte rate in Kbps
9873 * @ipg: the interpacket delay in tenths of nanoseconds
9874 * @sleep_ok: if true we may sleep while awaiting command completion
9876 * Return the current configuration of a HW Tx scheduler.
9878 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
9879 unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
9881 unsigned int v, addr, bpt, cpt;
9884 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
9885 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9888 bpt = (v >> 8) & 0xff;
9891 *kbps = 0; /* scheduler disabled */
9893 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9894 *kbps = (v * bpt) / 125;
9898 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
9899 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9903 *ipg = (10000 * v) / core_ticks_per_usec(adap);
9907 /* t4_sge_ctxt_rd - read an SGE context through FW
9908 * @adap: the adapter
9909 * @mbox: mailbox to use for the FW command
9910 * @cid: the context id
9911 * @ctype: the context type
9912 * @data: where to store the context data
9914 * Issues a FW command through the given mailbox to read an SGE context.
9916 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9917 enum ctxt_type ctype, u32 *data)
9919 struct fw_ldst_cmd c;
9922 if (ctype == CTXT_FLM)
9923 ret = FW_LDST_ADDRSPC_SGE_FLMC;
9925 ret = FW_LDST_ADDRSPC_SGE_CONMC;
9927 memset(&c, 0, sizeof(c));
9928 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
9929 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9930 FW_LDST_CMD_ADDRSPACE_V(ret));
9931 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9932 c.u.idctxt.physid = cpu_to_be32(cid);
9934 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9936 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9937 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9938 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9939 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9940 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9941 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9947 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9948 * @adap: the adapter
9949 * @cid: the context id
9950 * @ctype: the context type
9951 * @data: where to store the context data
9953 * Reads an SGE context directly, bypassing FW. This is only for
9954 * debugging when FW is unavailable.
9956 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
9957 enum ctxt_type ctype, u32 *data)
9961 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
9962 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
9964 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
9965 *data++ = t4_read_reg(adap, i);
9969 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9970 int rateunit, int ratemode, int channel, int class,
9971 int minrate, int maxrate, int weight, int pktsize)
9973 struct fw_sched_cmd cmd;
9975 memset(&cmd, 0, sizeof(cmd));
9976 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
9979 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9981 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9982 cmd.u.params.type = type;
9983 cmd.u.params.level = level;
9984 cmd.u.params.mode = mode;
9985 cmd.u.params.ch = channel;
9986 cmd.u.params.cl = class;
9987 cmd.u.params.unit = rateunit;
9988 cmd.u.params.rate = ratemode;
9989 cmd.u.params.min = cpu_to_be32(minrate);
9990 cmd.u.params.max = cpu_to_be32(maxrate);
9991 cmd.u.params.weight = cpu_to_be16(weight);
9992 cmd.u.params.pktsize = cpu_to_be16(pktsize);
9994 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
9999 * t4_i2c_rd - read I2C data from adapter
10000 * @adap: the adapter
10001 * @port: Port number if per-port device; <0 if not
10002 * @devid: per-port device ID or absolute device ID
10003 * @offset: byte offset into device I2C space
10004 * @len: byte length of I2C space data
10005 * @buf: buffer in which to return I2C data
10007 * Reads the I2C data from the indicated device and location.
10009 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10010 unsigned int devid, unsigned int offset,
10011 unsigned int len, u8 *buf)
10013 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10014 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10017 if (len > I2C_PAGE_SIZE)
10020 /* Dont allow reads that spans multiple pages */
10021 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10024 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10025 ldst_cmd.op_to_addrspace =
10026 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10029 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10030 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10031 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10032 ldst_cmd.u.i2c.did = devid;
10035 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10037 ldst_cmd.u.i2c.boffset = offset;
10038 ldst_cmd.u.i2c.blen = i2c_len;
10040 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10045 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10055 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10056 * @adapter: the adapter
10057 * @mbox: mailbox to use for the FW command
10058 * @vf: one of the VFs instantiated by the specified PF
10059 * @vlan: The vlanid to be set
10061 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10064 struct fw_acl_vlan_cmd vlan_cmd;
10065 unsigned int enable;
10067 enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10068 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10069 vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10073 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10074 FW_ACL_VLAN_CMD_VFN_V(vf));
10075 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10076 /* Drop all packets that donot match vlan id */
10077 vlan_cmd.dropnovlan_fm = FW_ACL_VLAN_CMD_FM_F;
10079 vlan_cmd.nvlan = 1;
10080 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10083 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);