drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Broadcom GENET MDIO routines
   4  *
   5  * Copyright (c) 2014-2017 Broadcom
   6  */
   7
   8
   9 #include <linux/types.h>
  10 #include <linux/delay.h>
  11 #include <linux/wait.h>
  12 #include <linux/mii.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/bitops.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/phy.h>
  18 #include <linux/phy_fixed.h>
  19 #include <linux/brcmphy.h>
  20 #include <linux/of.h>
  21 #include <linux/of_net.h>
  22 #include <linux/of_mdio.h>
  23 #include <linux/platform_data/bcmgenet.h>
  24 #include <linux/platform_data/mdio-bcm-unimac.h>
  25
  26 #include "bcmgenet.h"
  27
  28 /* setup netdev link state when PHY link status change and
  29  * update UMAC and RGMII block when link up
  30  */
  31 void bcmgenet_mii_setup(struct net_device *dev)
  32 {
  33         struct bcmgenet_priv *priv = netdev_priv(dev);
  34         struct phy_device *phydev = dev->phydev;
  35         u32 reg, cmd_bits = 0;
  36         bool status_changed = false;
  37
  38         if (priv->old_link != phydev->link) {
  39                 status_changed = true;
  40                 priv->old_link = phydev->link;
  41         }
  42
  43         if (phydev->link) {
  44                 /* check speed/duplex/pause changes */
  45                 if (priv->old_speed != phydev->speed) {
  46                         status_changed = true;
  47                         priv->old_speed = phydev->speed;
  48                 }
  49
  50                 if (priv->old_duplex != phydev->duplex) {
  51                         status_changed = true;
  52                         priv->old_duplex = phydev->duplex;
  53                 }
  54
  55                 if (priv->old_pause != phydev->pause) {
  56                         status_changed = true;
  57                         priv->old_pause = phydev->pause;
  58                 }
  59
  60                 /* done if nothing has changed */
  61                 if (!status_changed)
  62                         return;
  63
  64                 /* speed */
  65                 if (phydev->speed == SPEED_1000)
  66                         cmd_bits = UMAC_SPEED_1000;
  67                 else if (phydev->speed == SPEED_100)
  68                         cmd_bits = UMAC_SPEED_100;
  69                 else
  70                         cmd_bits = UMAC_SPEED_10;
  71                 cmd_bits <<= CMD_SPEED_SHIFT;
  72
  73                 /* duplex */
  74                 if (phydev->duplex != DUPLEX_FULL)
  75                         cmd_bits |= CMD_HD_EN;
  76
  77                 /* pause capability */
  78                 if (!phydev->pause)
  79                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
  80
  81                 /*
  82                  * Program UMAC and RGMII block based on established
  83                  * link speed, duplex, and pause. The speed set in
  84                  * umac->cmd tell RGMII block which clock to use for
  85                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
  86                  * Receive clock is provided by the PHY.
  87                  */
  88                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
  89                 reg &= ~OOB_DISABLE;
  90                 reg |= RGMII_LINK;
  91                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
  92
  93                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
  94                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
  95                                CMD_HD_EN |
  96                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
  97                 reg |= cmd_bits;
  98                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
  99         } else {
 100                 /* done if nothing has changed */
 101                 if (!status_changed)
 102                         return;
 103
 104                 /* needed for MoCA fixed PHY to reflect correct link status */
 105                 netif_carrier_off(dev);
 106         }
 107
 108         phy_print_status(phydev);
 109 }
 110
 111
 112 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 113                                           struct fixed_phy_status *status)
 114 {
 115         struct bcmgenet_priv *priv;
 116         u32 reg;
 117
 118         if (dev && dev->phydev && status) {
 119                 priv = netdev_priv(dev);
 120                 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
 121                 status->link = !!(reg & MODE_LINK_STATUS);
 122         }
 123
 124         return 0;
 125 }
 126
 127 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 128 {
 129         struct bcmgenet_priv *priv = netdev_priv(dev);
 130         u32 reg = 0;
 131
 132         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 133         if (GENET_IS_V4(priv)) {
 134                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 135                 if (enable) {
 136                         reg &= ~EXT_CK25_DIS;
 137                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 138                         mdelay(1);
 139
 140                         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 141                         reg |= EXT_GPHY_RESET;
 142                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 143                         mdelay(1);
 144
 145                         reg &= ~EXT_GPHY_RESET;
 146                 } else {
 147                         reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
 148                                EXT_GPHY_RESET;
 149                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 150                         mdelay(1);
 151                         reg |= EXT_CK25_DIS;
 152                 }
 153                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 154                 udelay(60);
 155         } else {
 156                 mdelay(1);
 157         }
 158 }
 159
 160 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 161 {
 162         u32 reg;
 163
 164         if (!GENET_IS_V5(priv)) {
 165                 /* Speed settings are set in bcmgenet_mii_setup() */
 166                 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 167                 reg |= LED_ACT_SOURCE_MAC;
 168                 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 169         }
 170
 171         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 172                 fixed_phy_set_link_update(priv->dev->phydev,
 173                                           bcmgenet_fixed_phy_link_update);
 174 }
 175
 176 int bcmgenet_mii_config(struct net_device *dev, bool init)
 177 {
 178         struct bcmgenet_priv *priv = netdev_priv(dev);
 179         struct phy_device *phydev = dev->phydev;
 180         struct device *kdev = &priv->pdev->dev;
 181         const char *phy_name = NULL;
 182         u32 id_mode_dis = 0;
 183         u32 port_ctrl;
 184         u32 reg;
 185
 186         priv->ext_phy = !priv->internal_phy &&
 187                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 188
 189         switch (priv->phy_interface) {
 190         case PHY_INTERFACE_MODE_INTERNAL:
 191         case PHY_INTERFACE_MODE_MOCA:
 192                 /* Irrespective of the actually configured PHY speed (100 or
 193                  * 1000) GENETv4 only has an internal GPHY so we will just end
 194                  * up masking the Gigabit features from what we support, not
 195                  * switching to the EPHY
 196                  */
 197                 if (GENET_IS_V4(priv))
 198                         port_ctrl = PORT_MODE_INT_GPHY;
 199                 else
 200                         port_ctrl = PORT_MODE_INT_EPHY;
 201
 202                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 203
 204                 if (priv->internal_phy) {
 205                         phy_name = "internal PHY";
 206                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 207                         phy_name = "MoCA";
 208                         bcmgenet_moca_phy_setup(priv);
 209                 }
 210                 break;
 211
 212         case PHY_INTERFACE_MODE_MII:
 213                 phy_name = "external MII";
 214                 phy_set_max_speed(phydev, SPEED_100);
 215                 bcmgenet_sys_writel(priv,
 216                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 217                 break;
 218
 219         case PHY_INTERFACE_MODE_REVMII:
 220                 phy_name = "external RvMII";
 221                 /* of_mdiobus_register took care of reading the 'max-speed'
 222                  * PHY property for us, effectively limiting the PHY supported
 223                  * capabilities, use that knowledge to also configure the
 224                  * Reverse MII interface correctly.
 225                  */
 226                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 227                                       dev->phydev->supported))
 228                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 229                 else
 230                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 231                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 232                 break;
 233
 234         case PHY_INTERFACE_MODE_RGMII:
 235                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 236                  *              (requires PCB or receiver-side delay)
 237                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 238                  *
 239                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 240                  */
 241                 id_mode_dis = BIT(16);
 242                 /* fall through */
 243         case PHY_INTERFACE_MODE_RGMII_TXID:
 244                 if (id_mode_dis)
 245                         phy_name = "external RGMII (no delay)";
 246                 else
 247                         phy_name = "external RGMII (TX delay)";
 248                 bcmgenet_sys_writel(priv,
 249                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 250                 break;
 251         default:
 252                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 253                 return -EINVAL;
 254         }
 255
 256         /* This is an external PHY (xMII), so we need to enable the RGMII
 257          * block for the interface to work
 258          */
 259         if (priv->ext_phy) {
 260                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 261                 reg |= RGMII_MODE_EN | id_mode_dis;
 262                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 263         }
 264
 265         if (init)
 266                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 267
 268         return 0;
 269 }
 270
 271 int bcmgenet_mii_probe(struct net_device *dev)
 272 {
 273         struct bcmgenet_priv *priv = netdev_priv(dev);
 274         struct device_node *dn = priv->pdev->dev.of_node;
 275         struct phy_device *phydev;
 276         u32 phy_flags;
 277         int ret;
 278
 279         /* Communicate the integrated PHY revision */
 280         phy_flags = priv->gphy_rev;
 281
 282         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 283         priv->old_link = -1;
 284         priv->old_speed = -1;
 285         priv->old_duplex = -1;
 286         priv->old_pause = -1;
 287
 288         if (dn) {
 289                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 290                                         phy_flags, priv->phy_interface);
 291                 if (!phydev) {
 292                         pr_err("could not attach to PHY\n");
 293                         return -ENODEV;
 294                 }
 295         } else {
 296                 phydev = dev->phydev;
 297                 phydev->dev_flags = phy_flags;
 298
 299                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 300                                          priv->phy_interface);
 301                 if (ret) {
 302                         pr_err("could not attach to PHY\n");
 303                         return -ENODEV;
 304                 }
 305         }
 306
 307         /* Configure port multiplexer based on what the probed PHY device since
 308          * reading the 'max-speed' property determines the maximum supported
 309          * PHY speed which is needed for bcmgenet_mii_config() to configure
 310          * things appropriately.
 311          */
 312         ret = bcmgenet_mii_config(dev, true);
 313         if (ret) {
 314                 phy_disconnect(dev->phydev);
 315                 return ret;
 316         }
 317
 318         linkmode_copy(phydev->advertising, phydev->supported);
 319
 320         /* The internal PHY has its link interrupts routed to the
 321          * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
 322          * that prevents the signaling of link UP interrupts when
 323          * the link operates at 10Mbps, so fallback to polling for
 324          * those versions of GENET.
 325          */
 326         if (priv->internal_phy && !GENET_IS_V5(priv))
 327                 dev->phydev->irq = PHY_IGNORE_INTERRUPT;
 328
 329         return 0;
 330 }
 331
 332 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
 333 {
 334         struct device_node *dn = priv->pdev->dev.of_node;
 335         struct device *kdev = &priv->pdev->dev;
 336         char *compat;
 337
 338         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 339         if (!compat)
 340                 return NULL;
 341
 342         priv->mdio_dn = of_get_compatible_child(dn, compat);
 343         kfree(compat);
 344         if (!priv->mdio_dn) {
 345                 dev_err(kdev, "unable to find MDIO bus node\n");
 346                 return NULL;
 347         }
 348
 349         return priv->mdio_dn;
 350 }
 351
 352 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
 353                                     struct unimac_mdio_pdata *ppd)
 354 {
 355         struct device *kdev = &priv->pdev->dev;
 356         struct bcmgenet_platform_data *pd = kdev->platform_data;
 357
 358         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 359                 /*
 360                  * Internal or external PHY with MDIO access
 361                  */
 362                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 363                         ppd->phy_mask = 1 << pd->phy_address;
 364                 else
 365                         ppd->phy_mask = 0;
 366         }
 367 }
 368
 369 static int bcmgenet_mii_wait(void *wait_func_data)
 370 {
 371         struct bcmgenet_priv *priv = wait_func_data;
 372
 373         wait_event_timeout(priv->wq,
 374                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
 375                            & MDIO_START_BUSY),
 376                            HZ / 100);
 377         return 0;
 378 }
 379
 380 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
 381 {
 382         struct platform_device *pdev = priv->pdev;
 383         struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
 384         struct device_node *dn = pdev->dev.of_node;
 385         struct unimac_mdio_pdata ppd;
 386         struct platform_device *ppdev;
 387         struct resource *pres, res;
 388         int id, ret;
 389
 390         pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 391         memset(&res, 0, sizeof(res));
 392         memset(&ppd, 0, sizeof(ppd));
 393
 394         ppd.wait_func = bcmgenet_mii_wait;
 395         ppd.wait_func_data = priv;
 396         ppd.bus_name = "bcmgenet MII bus";
 397
 398         /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
 399          * and is 2 * 32-bits word long, 8 bytes total.
 400          */
 401         res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
 402         res.end = res.start + 8;
 403         res.flags = IORESOURCE_MEM;
 404
 405         if (dn)
 406                 id = of_alias_get_id(dn, "eth");
 407         else
 408                 id = pdev->id;
 409
 410         ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
 411         if (!ppdev)
 412                 return -ENOMEM;
 413
 414         /* Retain this platform_device pointer for later cleanup */
 415         priv->mii_pdev = ppdev;
 416         ppdev->dev.parent = &pdev->dev;
 417         ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
 418         if (pdata)
 419                 bcmgenet_mii_pdata_init(priv, &ppd);
 420
 421         ret = platform_device_add_resources(ppdev, &res, 1);
 422         if (ret)
 423                 goto out;
 424
 425         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
 426         if (ret)
 427                 goto out;
 428
 429         ret = platform_device_add(ppdev);
 430         if (ret)
 431                 goto out;
 432
 433         return 0;
 434 out:
 435         platform_device_put(ppdev);
 436         return ret;
 437 }
 438
 439 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 440 {
 441         struct device_node *dn = priv->pdev->dev.of_node;
 442         struct device *kdev = &priv->pdev->dev;
 443         struct phy_device *phydev;
 444         int phy_mode;
 445         int ret;
 446
 447         /* Fetch the PHY phandle */
 448         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 449
 450         /* In the case of a fixed PHY, the DT node associated
 451          * to the PHY is the Ethernet MAC DT node.
 452          */
 453         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 454                 ret = of_phy_register_fixed_link(dn);
 455                 if (ret)
 456                         return ret;
 457
 458                 priv->phy_dn = of_node_get(dn);
 459         }
 460
 461         /* Get the link mode */
 462         phy_mode = of_get_phy_mode(dn);
 463         if (phy_mode < 0) {
 464                 dev_err(kdev, "invalid PHY mode property\n");
 465                 return phy_mode;
 466         }
 467
 468         priv->phy_interface = phy_mode;
 469
 470         /* We need to specifically look up whether this PHY interface is internal
 471          * or not *before* we even try to probe the PHY driver over MDIO as we
 472          * may have shut down the internal PHY for power saving purposes.
 473          */
 474         if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
 475                 priv->internal_phy = true;
 476
 477         /* Make sure we initialize MoCA PHYs with a link down */
 478         if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
 479                 phydev = of_phy_find_device(dn);
 480                 if (phydev) {
 481                         phydev->link = 0;
 482                         put_device(&phydev->mdio.dev);
 483                 }
 484         }
 485
 486         return 0;
 487 }
 488
 489 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 490 {
 491         struct device *kdev = &priv->pdev->dev;
 492         struct bcmgenet_platform_data *pd = kdev->platform_data;
 493         char phy_name[MII_BUS_ID_SIZE + 3];
 494         char mdio_bus_id[MII_BUS_ID_SIZE];
 495         struct phy_device *phydev;
 496
 497         snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
 498                  UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
 499
 500         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 501                 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
 502                          mdio_bus_id, pd->phy_address);
 503
 504                 /*
 505                  * Internal or external PHY with MDIO access
 506                  */
 507                 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
 508                 if (!phydev) {
 509                         dev_err(kdev, "failed to register PHY device\n");
 510                         return -ENODEV;
 511                 }
 512         } else {
 513                 /*
 514                  * MoCA port or no MDIO access.
 515                  * Use fixed PHY to represent the link layer.
 516                  */
 517                 struct fixed_phy_status fphy_status = {
 518                         .link = 1,
 519                         .speed = pd->phy_speed,
 520                         .duplex = pd->phy_duplex,
 521                         .pause = 0,
 522                         .asym_pause = 0,
 523                 };
 524
 525                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
 526                 if (!phydev || IS_ERR(phydev)) {
 527                         dev_err(kdev, "failed to register fixed PHY device\n");
 528                         return -ENODEV;
 529                 }
 530
 531                 /* Make sure we initialize MoCA PHYs with a link down */
 532                 phydev->link = 0;
 533
 534         }
 535
 536         priv->phy_interface = pd->phy_interface;
 537
 538         return 0;
 539 }
 540
 541 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 542 {
 543         struct device_node *dn = priv->pdev->dev.of_node;
 544
 545         if (dn)
 546                 return bcmgenet_mii_of_init(priv);
 547         else
 548                 return bcmgenet_mii_pd_init(priv);
 549 }
 550
 551 int bcmgenet_mii_init(struct net_device *dev)
 552 {
 553         struct bcmgenet_priv *priv = netdev_priv(dev);
 554         int ret;
 555
 556         ret = bcmgenet_mii_register(priv);
 557         if (ret)
 558                 return ret;
 559
 560         ret = bcmgenet_mii_bus_init(priv);
 561         if (ret)
 562                 goto out;
 563
 564         return 0;
 565
 566 out:
 567         bcmgenet_mii_exit(dev);
 568         return ret;
 569 }
 570
 571 void bcmgenet_mii_exit(struct net_device *dev)
 572 {
 573         struct bcmgenet_priv *priv = netdev_priv(dev);
 574         struct device_node *dn = priv->pdev->dev.of_node;
 575
 576         if (of_phy_is_fixed_link(dn))
 577                 of_phy_deregister_fixed_link(dn);
 578         of_node_put(priv->phy_dn);
 579         platform_device_unregister(priv->mii_pdev);
 580 }