1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET (Gigabit Ethernet) controller driver
5 * Copyright (c) 2014-2019 Broadcom
8 #define pr_fmt(fmt) "bcmgenet: " fmt
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/types.h>
14 #include <linux/fcntl.h>
15 #include <linux/interrupt.h>
16 #include <linux/string.h>
17 #include <linux/if_ether.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
24 #include <linux/clk.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_net.h>
29 #include <linux/of_platform.h>
32 #include <linux/mii.h>
33 #include <linux/ethtool.h>
34 #include <linux/netdevice.h>
35 #include <linux/inetdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
40 #include <linux/ipv6.h>
41 #include <linux/phy.h>
42 #include <linux/platform_data/bcmgenet.h>
44 #include <asm/unaligned.h>
48 /* Maximum number of hardware queues, downsized if needed */
49 #define GENET_MAX_MQ_CNT 4
51 /* Default highest priority queue for multi queue support */
52 #define GENET_Q0_PRIORITY 0
54 #define GENET_Q16_RX_BD_CNT \
55 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
56 #define GENET_Q16_TX_BD_CNT \
57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
59 #define RX_BUF_LENGTH 2048
60 #define SKB_ALIGNMENT 32
62 /* Tx/Rx DMA register offset, skip 256 descriptors */
63 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
64 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
66 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
67 TOTAL_DESC * DMA_DESC_SIZE)
69 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
72 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
74 /* MIPS chips strapped for BE will automagically configure the
75 * peripheral registers for CPU-native byte order.
77 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
78 __raw_writel(value, offset);
80 writel_relaxed(value, offset);
83 static inline u32 bcmgenet_readl(void __iomem *offset)
85 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
86 return __raw_readl(offset);
88 return readl_relaxed(offset);
91 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
92 void __iomem *d, u32 value)
94 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
97 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
100 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
103 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
107 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
109 /* Register writes to GISB bus can take couple hundred nanoseconds
110 * and are done for each packet, save these expensive writes unless
111 * the platform is explicitly configured for 64-bits/LPAE.
113 #ifdef CONFIG_PHYS_ADDR_T_64BIT
114 if (priv->hw_params->flags & GENET_HAS_40BITS)
115 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
119 /* Combined address + length/status setter */
120 static inline void dmadesc_set(struct bcmgenet_priv *priv,
121 void __iomem *d, dma_addr_t addr, u32 val)
123 dmadesc_set_addr(priv, d, addr);
124 dmadesc_set_length_status(priv, d, val);
127 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
132 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
134 /* Register writes to GISB bus can take couple hundred nanoseconds
135 * and are done for each packet, save these expensive writes unless
136 * the platform is explicitly configured for 64-bits/LPAE.
138 #ifdef CONFIG_PHYS_ADDR_T_64BIT
139 if (priv->hw_params->flags & GENET_HAS_40BITS)
140 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
145 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
147 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
150 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
152 if (GENET_IS_V1(priv))
153 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
155 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
158 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
160 if (GENET_IS_V1(priv))
161 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
163 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
166 /* These macros are defined to deal with register map change
167 * between GENET1.1 and GENET2. Only those currently being used
168 * by driver are defined.
170 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
172 if (GENET_IS_V1(priv))
173 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
175 return bcmgenet_readl(priv->base +
176 priv->hw_params->tbuf_offset + TBUF_CTRL);
179 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
181 if (GENET_IS_V1(priv))
182 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
184 bcmgenet_writel(val, priv->base +
185 priv->hw_params->tbuf_offset + TBUF_CTRL);
188 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
190 if (GENET_IS_V1(priv))
191 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
193 return bcmgenet_readl(priv->base +
194 priv->hw_params->tbuf_offset + TBUF_BP_MC);
197 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
199 if (GENET_IS_V1(priv))
200 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
202 bcmgenet_writel(val, priv->base +
203 priv->hw_params->tbuf_offset + TBUF_BP_MC);
206 /* RX/TX DMA register accessors */
243 static const u8 bcmgenet_dma_regs_v3plus[] = {
244 [DMA_RING_CFG] = 0x00,
247 [DMA_SCB_BURST_SIZE] = 0x0C,
248 [DMA_ARB_CTRL] = 0x2C,
249 [DMA_PRIORITY_0] = 0x30,
250 [DMA_PRIORITY_1] = 0x34,
251 [DMA_PRIORITY_2] = 0x38,
252 [DMA_RING0_TIMEOUT] = 0x2C,
253 [DMA_RING1_TIMEOUT] = 0x30,
254 [DMA_RING2_TIMEOUT] = 0x34,
255 [DMA_RING3_TIMEOUT] = 0x38,
256 [DMA_RING4_TIMEOUT] = 0x3c,
257 [DMA_RING5_TIMEOUT] = 0x40,
258 [DMA_RING6_TIMEOUT] = 0x44,
259 [DMA_RING7_TIMEOUT] = 0x48,
260 [DMA_RING8_TIMEOUT] = 0x4c,
261 [DMA_RING9_TIMEOUT] = 0x50,
262 [DMA_RING10_TIMEOUT] = 0x54,
263 [DMA_RING11_TIMEOUT] = 0x58,
264 [DMA_RING12_TIMEOUT] = 0x5c,
265 [DMA_RING13_TIMEOUT] = 0x60,
266 [DMA_RING14_TIMEOUT] = 0x64,
267 [DMA_RING15_TIMEOUT] = 0x68,
268 [DMA_RING16_TIMEOUT] = 0x6C,
269 [DMA_INDEX2RING_0] = 0x70,
270 [DMA_INDEX2RING_1] = 0x74,
271 [DMA_INDEX2RING_2] = 0x78,
272 [DMA_INDEX2RING_3] = 0x7C,
273 [DMA_INDEX2RING_4] = 0x80,
274 [DMA_INDEX2RING_5] = 0x84,
275 [DMA_INDEX2RING_6] = 0x88,
276 [DMA_INDEX2RING_7] = 0x8C,
279 static const u8 bcmgenet_dma_regs_v2[] = {
280 [DMA_RING_CFG] = 0x00,
283 [DMA_SCB_BURST_SIZE] = 0x0C,
284 [DMA_ARB_CTRL] = 0x30,
285 [DMA_PRIORITY_0] = 0x34,
286 [DMA_PRIORITY_1] = 0x38,
287 [DMA_PRIORITY_2] = 0x3C,
288 [DMA_RING0_TIMEOUT] = 0x2C,
289 [DMA_RING1_TIMEOUT] = 0x30,
290 [DMA_RING2_TIMEOUT] = 0x34,
291 [DMA_RING3_TIMEOUT] = 0x38,
292 [DMA_RING4_TIMEOUT] = 0x3c,
293 [DMA_RING5_TIMEOUT] = 0x40,
294 [DMA_RING6_TIMEOUT] = 0x44,
295 [DMA_RING7_TIMEOUT] = 0x48,
296 [DMA_RING8_TIMEOUT] = 0x4c,
297 [DMA_RING9_TIMEOUT] = 0x50,
298 [DMA_RING10_TIMEOUT] = 0x54,
299 [DMA_RING11_TIMEOUT] = 0x58,
300 [DMA_RING12_TIMEOUT] = 0x5c,
301 [DMA_RING13_TIMEOUT] = 0x60,
302 [DMA_RING14_TIMEOUT] = 0x64,
303 [DMA_RING15_TIMEOUT] = 0x68,
304 [DMA_RING16_TIMEOUT] = 0x6C,
307 static const u8 bcmgenet_dma_regs_v1[] = {
310 [DMA_SCB_BURST_SIZE] = 0x0C,
311 [DMA_ARB_CTRL] = 0x30,
312 [DMA_PRIORITY_0] = 0x34,
313 [DMA_PRIORITY_1] = 0x38,
314 [DMA_PRIORITY_2] = 0x3C,
315 [DMA_RING0_TIMEOUT] = 0x2C,
316 [DMA_RING1_TIMEOUT] = 0x30,
317 [DMA_RING2_TIMEOUT] = 0x34,
318 [DMA_RING3_TIMEOUT] = 0x38,
319 [DMA_RING4_TIMEOUT] = 0x3c,
320 [DMA_RING5_TIMEOUT] = 0x40,
321 [DMA_RING6_TIMEOUT] = 0x44,
322 [DMA_RING7_TIMEOUT] = 0x48,
323 [DMA_RING8_TIMEOUT] = 0x4c,
324 [DMA_RING9_TIMEOUT] = 0x50,
325 [DMA_RING10_TIMEOUT] = 0x54,
326 [DMA_RING11_TIMEOUT] = 0x58,
327 [DMA_RING12_TIMEOUT] = 0x5c,
328 [DMA_RING13_TIMEOUT] = 0x60,
329 [DMA_RING14_TIMEOUT] = 0x64,
330 [DMA_RING15_TIMEOUT] = 0x68,
331 [DMA_RING16_TIMEOUT] = 0x6C,
334 /* Set at runtime once bcmgenet version is known */
335 static const u8 *bcmgenet_dma_regs;
337 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
339 return netdev_priv(dev_get_drvdata(dev));
342 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
345 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
349 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
350 u32 val, enum dma_reg r)
352 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
356 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
359 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
363 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
364 u32 val, enum dma_reg r)
366 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
367 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
370 /* RDMA/TDMA ring registers and accessors
371 * we merge the common fields and just prefix with T/D the registers
372 * having different meaning depending on the direction
376 RDMA_WRITE_PTR = TDMA_READ_PTR,
378 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
380 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
382 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
388 DMA_MBUF_DONE_THRESH,
390 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
392 RDMA_READ_PTR = TDMA_WRITE_PTR,
394 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
397 /* GENET v4 supports 40-bits pointer addressing
398 * for obvious reasons the LO and HI word parts
399 * are contiguous, but this offsets the other
402 static const u8 genet_dma_ring_regs_v4[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_READ_PTR_HI] = 0x04,
405 [TDMA_CONS_INDEX] = 0x08,
406 [TDMA_PROD_INDEX] = 0x0C,
407 [DMA_RING_BUF_SIZE] = 0x10,
408 [DMA_START_ADDR] = 0x14,
409 [DMA_START_ADDR_HI] = 0x18,
410 [DMA_END_ADDR] = 0x1C,
411 [DMA_END_ADDR_HI] = 0x20,
412 [DMA_MBUF_DONE_THRESH] = 0x24,
413 [TDMA_FLOW_PERIOD] = 0x28,
414 [TDMA_WRITE_PTR] = 0x2C,
415 [TDMA_WRITE_PTR_HI] = 0x30,
418 static const u8 genet_dma_ring_regs_v123[] = {
419 [TDMA_READ_PTR] = 0x00,
420 [TDMA_CONS_INDEX] = 0x04,
421 [TDMA_PROD_INDEX] = 0x08,
422 [DMA_RING_BUF_SIZE] = 0x0C,
423 [DMA_START_ADDR] = 0x10,
424 [DMA_END_ADDR] = 0x14,
425 [DMA_MBUF_DONE_THRESH] = 0x18,
426 [TDMA_FLOW_PERIOD] = 0x1C,
427 [TDMA_WRITE_PTR] = 0x20,
430 /* Set at runtime once GENET version is known */
431 static const u8 *genet_dma_ring_regs;
433 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
437 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
438 (DMA_RING_SIZE * ring) +
439 genet_dma_ring_regs[r]);
442 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
443 unsigned int ring, u32 val,
446 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
447 (DMA_RING_SIZE * ring) +
448 genet_dma_ring_regs[r]);
451 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
455 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
456 (DMA_RING_SIZE * ring) +
457 genet_dma_ring_regs[r]);
460 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
461 unsigned int ring, u32 val,
464 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
465 (DMA_RING_SIZE * ring) +
466 genet_dma_ring_regs[r]);
469 static int bcmgenet_begin(struct net_device *dev)
471 struct bcmgenet_priv *priv = netdev_priv(dev);
473 /* Turn on the clock */
474 return clk_prepare_enable(priv->clk);
477 static void bcmgenet_complete(struct net_device *dev)
479 struct bcmgenet_priv *priv = netdev_priv(dev);
481 /* Turn off the clock */
482 clk_disable_unprepare(priv->clk);
485 static int bcmgenet_get_link_ksettings(struct net_device *dev,
486 struct ethtool_link_ksettings *cmd)
488 if (!netif_running(dev))
494 phy_ethtool_ksettings_get(dev->phydev, cmd);
499 static int bcmgenet_set_link_ksettings(struct net_device *dev,
500 const struct ethtool_link_ksettings *cmd)
502 if (!netif_running(dev))
508 return phy_ethtool_ksettings_set(dev->phydev, cmd);
511 static int bcmgenet_set_rx_csum(struct net_device *dev,
512 netdev_features_t wanted)
514 struct bcmgenet_priv *priv = netdev_priv(dev);
518 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
520 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
522 /* enable rx checksumming */
524 rbuf_chk_ctrl |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
526 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
527 priv->desc_rxchk_en = rx_csum_en;
529 /* If UniMAC forwards CRC, we need to skip over it to get
530 * a valid CHK bit to be set in the per-packet status word
532 if (rx_csum_en && priv->crc_fwd_en)
533 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
535 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
537 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
542 static int bcmgenet_set_tx_csum(struct net_device *dev,
543 netdev_features_t wanted)
545 struct bcmgenet_priv *priv = netdev_priv(dev);
547 u32 tbuf_ctrl, rbuf_ctrl;
549 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
550 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
552 desc_64b_en = !!(wanted & NETIF_F_HW_CSUM);
554 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
556 tbuf_ctrl |= RBUF_64B_EN;
557 rbuf_ctrl |= RBUF_64B_EN;
559 tbuf_ctrl &= ~RBUF_64B_EN;
560 rbuf_ctrl &= ~RBUF_64B_EN;
562 priv->desc_64b_en = desc_64b_en;
564 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
565 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
570 static int bcmgenet_set_features(struct net_device *dev,
571 netdev_features_t features)
573 netdev_features_t changed = features ^ dev->features;
574 netdev_features_t wanted = dev->wanted_features;
577 if (changed & NETIF_F_HW_CSUM)
578 ret = bcmgenet_set_tx_csum(dev, wanted);
579 if (changed & (NETIF_F_RXCSUM))
580 ret = bcmgenet_set_rx_csum(dev, wanted);
585 static u32 bcmgenet_get_msglevel(struct net_device *dev)
587 struct bcmgenet_priv *priv = netdev_priv(dev);
589 return priv->msg_enable;
592 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
594 struct bcmgenet_priv *priv = netdev_priv(dev);
596 priv->msg_enable = level;
599 static int bcmgenet_get_coalesce(struct net_device *dev,
600 struct ethtool_coalesce *ec)
602 struct bcmgenet_priv *priv = netdev_priv(dev);
603 struct bcmgenet_rx_ring *ring;
606 ec->tx_max_coalesced_frames =
607 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
608 DMA_MBUF_DONE_THRESH);
609 ec->rx_max_coalesced_frames =
610 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
611 DMA_MBUF_DONE_THRESH);
612 ec->rx_coalesce_usecs =
613 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
615 for (i = 0; i < priv->hw_params->rx_queues; i++) {
616 ring = &priv->rx_rings[i];
617 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
619 ring = &priv->rx_rings[DESC_INDEX];
620 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
625 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
628 struct bcmgenet_priv *priv = ring->priv;
629 unsigned int i = ring->index;
632 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
634 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
635 reg &= ~DMA_TIMEOUT_MASK;
636 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
637 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
640 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
641 struct ethtool_coalesce *ec)
643 struct dim_cq_moder moder;
646 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
647 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
648 usecs = ring->rx_coalesce_usecs;
649 pkts = ring->rx_max_coalesced_frames;
651 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
652 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
657 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
658 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
661 static int bcmgenet_set_coalesce(struct net_device *dev,
662 struct ethtool_coalesce *ec)
664 struct bcmgenet_priv *priv = netdev_priv(dev);
667 /* Base system clock is 125Mhz, DMA timeout is this reference clock
668 * divided by 1024, which yields roughly 8.192us, our maximum value
669 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
671 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
672 ec->tx_max_coalesced_frames == 0 ||
673 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
674 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
677 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
680 /* GENET TDMA hardware does not support a configurable timeout, but will
681 * always generate an interrupt either after MBDONE packets have been
682 * transmitted, or when the ring is empty.
684 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
685 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low ||
686 ec->use_adaptive_tx_coalesce)
689 /* Program all TX queues with the same values, as there is no
690 * ethtool knob to do coalescing on a per-queue basis
692 for (i = 0; i < priv->hw_params->tx_queues; i++)
693 bcmgenet_tdma_ring_writel(priv, i,
694 ec->tx_max_coalesced_frames,
695 DMA_MBUF_DONE_THRESH);
696 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
697 ec->tx_max_coalesced_frames,
698 DMA_MBUF_DONE_THRESH);
700 for (i = 0; i < priv->hw_params->rx_queues; i++)
701 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
702 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
707 /* standard ethtool support functions. */
708 enum bcmgenet_stat_type {
709 BCMGENET_STAT_NETDEV = -1,
710 BCMGENET_STAT_MIB_RX,
711 BCMGENET_STAT_MIB_TX,
717 struct bcmgenet_stats {
718 char stat_string[ETH_GSTRING_LEN];
721 enum bcmgenet_stat_type type;
722 /* reg offset from UMAC base for misc counters */
726 #define STAT_NETDEV(m) { \
727 .stat_string = __stringify(m), \
728 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
729 .stat_offset = offsetof(struct net_device_stats, m), \
730 .type = BCMGENET_STAT_NETDEV, \
733 #define STAT_GENET_MIB(str, m, _type) { \
734 .stat_string = str, \
735 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
736 .stat_offset = offsetof(struct bcmgenet_priv, m), \
740 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
741 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
742 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
743 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
745 #define STAT_GENET_MISC(str, m, offset) { \
746 .stat_string = str, \
747 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
748 .stat_offset = offsetof(struct bcmgenet_priv, m), \
749 .type = BCMGENET_STAT_MISC, \
750 .reg_offset = offset, \
753 #define STAT_GENET_Q(num) \
754 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
755 tx_rings[num].packets), \
756 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
757 tx_rings[num].bytes), \
758 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
759 rx_rings[num].bytes), \
760 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
761 rx_rings[num].packets), \
762 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
763 rx_rings[num].errors), \
764 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
765 rx_rings[num].dropped)
767 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
768 * between the end of TX stats and the beginning of the RX RUNT
770 #define BCMGENET_STAT_OFFSET 0xc
772 /* Hardware counters must be kept in sync because the order/offset
773 * is important here (order in structure declaration = order in hardware)
775 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
777 STAT_NETDEV(rx_packets),
778 STAT_NETDEV(tx_packets),
779 STAT_NETDEV(rx_bytes),
780 STAT_NETDEV(tx_bytes),
781 STAT_NETDEV(rx_errors),
782 STAT_NETDEV(tx_errors),
783 STAT_NETDEV(rx_dropped),
784 STAT_NETDEV(tx_dropped),
785 STAT_NETDEV(multicast),
786 /* UniMAC RSV counters */
787 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
788 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
789 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
790 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
791 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
792 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
793 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
794 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
795 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
796 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
797 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
798 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
799 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
800 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
801 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
802 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
803 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
804 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
805 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
806 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
807 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
808 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
809 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
810 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
811 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
812 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
813 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
814 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
815 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
816 /* UniMAC TSV counters */
817 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
818 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
819 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
820 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
821 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
822 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
823 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
824 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
825 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
826 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
827 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
828 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
829 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
830 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
831 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
832 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
833 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
834 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
835 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
836 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
837 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
838 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
839 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
840 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
841 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
842 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
843 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
844 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
845 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
846 /* UniMAC RUNT counters */
847 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
848 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
849 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
850 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
851 /* Misc UniMAC counters */
852 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
853 UMAC_RBUF_OVFL_CNT_V1),
854 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
855 UMAC_RBUF_ERR_CNT_V1),
856 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
857 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
858 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
859 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
868 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
870 static void bcmgenet_get_drvinfo(struct net_device *dev,
871 struct ethtool_drvinfo *info)
873 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
874 strlcpy(info->version, "v2.0", sizeof(info->version));
877 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
879 switch (string_set) {
881 return BCMGENET_STATS_LEN;
887 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
894 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
895 memcpy(data + i * ETH_GSTRING_LEN,
896 bcmgenet_gstrings_stats[i].stat_string,
903 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
909 case UMAC_RBUF_OVFL_CNT_V1:
910 if (GENET_IS_V2(priv))
911 new_offset = RBUF_OVFL_CNT_V2;
913 new_offset = RBUF_OVFL_CNT_V3PLUS;
915 val = bcmgenet_rbuf_readl(priv, new_offset);
916 /* clear if overflowed */
918 bcmgenet_rbuf_writel(priv, 0, new_offset);
920 case UMAC_RBUF_ERR_CNT_V1:
921 if (GENET_IS_V2(priv))
922 new_offset = RBUF_ERR_CNT_V2;
924 new_offset = RBUF_ERR_CNT_V3PLUS;
926 val = bcmgenet_rbuf_readl(priv, new_offset);
927 /* clear if overflowed */
929 bcmgenet_rbuf_writel(priv, 0, new_offset);
932 val = bcmgenet_umac_readl(priv, offset);
933 /* clear if overflowed */
935 bcmgenet_umac_writel(priv, 0, offset);
942 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
946 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
947 const struct bcmgenet_stats *s;
952 s = &bcmgenet_gstrings_stats[i];
954 case BCMGENET_STAT_NETDEV:
955 case BCMGENET_STAT_SOFT:
957 case BCMGENET_STAT_RUNT:
958 offset += BCMGENET_STAT_OFFSET;
960 case BCMGENET_STAT_MIB_TX:
961 offset += BCMGENET_STAT_OFFSET;
963 case BCMGENET_STAT_MIB_RX:
964 val = bcmgenet_umac_readl(priv,
965 UMAC_MIB_START + j + offset);
966 offset = 0; /* Reset Offset */
968 case BCMGENET_STAT_MISC:
969 if (GENET_IS_V1(priv)) {
970 val = bcmgenet_umac_readl(priv, s->reg_offset);
971 /* clear if overflowed */
973 bcmgenet_umac_writel(priv, 0,
976 val = bcmgenet_update_stat_misc(priv,
983 p = (char *)priv + s->stat_offset;
988 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
989 struct ethtool_stats *stats,
992 struct bcmgenet_priv *priv = netdev_priv(dev);
995 if (netif_running(dev))
996 bcmgenet_update_mib_counters(priv);
998 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
999 const struct bcmgenet_stats *s;
1002 s = &bcmgenet_gstrings_stats[i];
1003 if (s->type == BCMGENET_STAT_NETDEV)
1004 p = (char *)&dev->stats;
1007 p += s->stat_offset;
1008 if (sizeof(unsigned long) != sizeof(u32) &&
1009 s->stat_sizeof == sizeof(unsigned long))
1010 data[i] = *(unsigned long *)p;
1012 data[i] = *(u32 *)p;
1016 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1018 struct bcmgenet_priv *priv = netdev_priv(dev);
1019 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1022 if (enable && !priv->clk_eee_enabled) {
1023 clk_prepare_enable(priv->clk_eee);
1024 priv->clk_eee_enabled = true;
1027 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1032 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1034 /* Enable EEE and switch to a 27Mhz clock automatically */
1035 reg = bcmgenet_readl(priv->base + off);
1037 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1039 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1040 bcmgenet_writel(reg, priv->base + off);
1042 /* Do the same for thing for RBUF */
1043 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1045 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1047 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1048 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1050 if (!enable && priv->clk_eee_enabled) {
1051 clk_disable_unprepare(priv->clk_eee);
1052 priv->clk_eee_enabled = false;
1055 priv->eee.eee_enabled = enable;
1056 priv->eee.eee_active = enable;
1059 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1061 struct bcmgenet_priv *priv = netdev_priv(dev);
1062 struct ethtool_eee *p = &priv->eee;
1064 if (GENET_IS_V1(priv))
1070 e->eee_enabled = p->eee_enabled;
1071 e->eee_active = p->eee_active;
1072 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1074 return phy_ethtool_get_eee(dev->phydev, e);
1077 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1079 struct bcmgenet_priv *priv = netdev_priv(dev);
1080 struct ethtool_eee *p = &priv->eee;
1083 if (GENET_IS_V1(priv))
1089 p->eee_enabled = e->eee_enabled;
1091 if (!p->eee_enabled) {
1092 bcmgenet_eee_enable_set(dev, false);
1094 ret = phy_init_eee(dev->phydev, 0);
1096 netif_err(priv, hw, dev, "EEE initialization failed\n");
1100 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1101 bcmgenet_eee_enable_set(dev, true);
1104 return phy_ethtool_set_eee(dev->phydev, e);
1107 /* standard ethtool support functions. */
1108 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1109 .begin = bcmgenet_begin,
1110 .complete = bcmgenet_complete,
1111 .get_strings = bcmgenet_get_strings,
1112 .get_sset_count = bcmgenet_get_sset_count,
1113 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1114 .get_drvinfo = bcmgenet_get_drvinfo,
1115 .get_link = ethtool_op_get_link,
1116 .get_msglevel = bcmgenet_get_msglevel,
1117 .set_msglevel = bcmgenet_set_msglevel,
1118 .get_wol = bcmgenet_get_wol,
1119 .set_wol = bcmgenet_set_wol,
1120 .get_eee = bcmgenet_get_eee,
1121 .set_eee = bcmgenet_set_eee,
1122 .nway_reset = phy_ethtool_nway_reset,
1123 .get_coalesce = bcmgenet_get_coalesce,
1124 .set_coalesce = bcmgenet_set_coalesce,
1125 .get_link_ksettings = bcmgenet_get_link_ksettings,
1126 .set_link_ksettings = bcmgenet_set_link_ksettings,
1127 .get_ts_info = ethtool_op_get_ts_info,
1130 /* Power down the unimac, based on mode. */
1131 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1132 enum bcmgenet_power_mode mode)
1138 case GENET_POWER_CABLE_SENSE:
1139 phy_detach(priv->dev->phydev);
1142 case GENET_POWER_WOL_MAGIC:
1143 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1146 case GENET_POWER_PASSIVE:
1147 /* Power down LED */
1148 if (priv->hw_params->flags & GENET_HAS_EXT) {
1149 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1150 if (GENET_IS_V5(priv))
1151 reg |= EXT_PWR_DOWN_PHY_EN |
1152 EXT_PWR_DOWN_PHY_RD |
1153 EXT_PWR_DOWN_PHY_SD |
1154 EXT_PWR_DOWN_PHY_RX |
1155 EXT_PWR_DOWN_PHY_TX |
1158 reg |= EXT_PWR_DOWN_PHY;
1160 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1161 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1163 bcmgenet_phy_power_set(priv->dev, false);
1173 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1174 enum bcmgenet_power_mode mode)
1178 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1181 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1184 case GENET_POWER_PASSIVE:
1185 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1186 if (GENET_IS_V5(priv)) {
1187 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1188 EXT_PWR_DOWN_PHY_RD |
1189 EXT_PWR_DOWN_PHY_SD |
1190 EXT_PWR_DOWN_PHY_RX |
1191 EXT_PWR_DOWN_PHY_TX |
1193 reg |= EXT_PHY_RESET;
1194 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1197 reg &= ~EXT_PHY_RESET;
1199 reg &= ~EXT_PWR_DOWN_PHY;
1200 reg |= EXT_PWR_DN_EN_LD;
1202 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1203 bcmgenet_phy_power_set(priv->dev, true);
1206 case GENET_POWER_CABLE_SENSE:
1208 if (!GENET_IS_V5(priv)) {
1209 reg |= EXT_PWR_DN_EN_LD;
1210 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1213 case GENET_POWER_WOL_MAGIC:
1214 bcmgenet_wol_power_up_cfg(priv, mode);
1221 /* ioctl handle special commands that are not present in ethtool. */
1222 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1224 if (!netif_running(dev))
1230 return phy_mii_ioctl(dev->phydev, rq, cmd);
1233 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1234 struct bcmgenet_tx_ring *ring)
1236 struct enet_cb *tx_cb_ptr;
1238 tx_cb_ptr = ring->cbs;
1239 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1241 /* Advancing local write pointer */
1242 if (ring->write_ptr == ring->end_ptr)
1243 ring->write_ptr = ring->cb_ptr;
1250 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1251 struct bcmgenet_tx_ring *ring)
1253 struct enet_cb *tx_cb_ptr;
1255 tx_cb_ptr = ring->cbs;
1256 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1258 /* Rewinding local write pointer */
1259 if (ring->write_ptr == ring->cb_ptr)
1260 ring->write_ptr = ring->end_ptr;
1267 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1269 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1270 INTRL2_CPU_MASK_SET);
1273 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1275 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1276 INTRL2_CPU_MASK_CLEAR);
1279 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1281 bcmgenet_intrl2_1_writel(ring->priv,
1282 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1283 INTRL2_CPU_MASK_SET);
1286 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1288 bcmgenet_intrl2_1_writel(ring->priv,
1289 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1290 INTRL2_CPU_MASK_CLEAR);
1293 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1295 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1296 INTRL2_CPU_MASK_SET);
1299 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1301 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1302 INTRL2_CPU_MASK_CLEAR);
1305 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1307 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1308 INTRL2_CPU_MASK_CLEAR);
1311 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1313 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1314 INTRL2_CPU_MASK_SET);
1317 /* Simple helper to free a transmit control block's resources
1318 * Returns an skb when the last transmit control block associated with the
1319 * skb is freed. The skb should be freed by the caller if necessary.
1321 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1324 struct sk_buff *skb;
1330 if (cb == GENET_CB(skb)->first_cb)
1331 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1332 dma_unmap_len(cb, dma_len),
1335 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1336 dma_unmap_len(cb, dma_len),
1338 dma_unmap_addr_set(cb, dma_addr, 0);
1340 if (cb == GENET_CB(skb)->last_cb)
1343 } else if (dma_unmap_addr(cb, dma_addr)) {
1345 dma_unmap_addr(cb, dma_addr),
1346 dma_unmap_len(cb, dma_len),
1348 dma_unmap_addr_set(cb, dma_addr, 0);
1354 /* Simple helper to free a receive control block's resources */
1355 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1358 struct sk_buff *skb;
1363 if (dma_unmap_addr(cb, dma_addr)) {
1364 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1365 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1366 dma_unmap_addr_set(cb, dma_addr, 0);
1372 /* Unlocked version of the reclaim routine */
1373 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1374 struct bcmgenet_tx_ring *ring)
1376 struct bcmgenet_priv *priv = netdev_priv(dev);
1377 unsigned int txbds_processed = 0;
1378 unsigned int bytes_compl = 0;
1379 unsigned int pkts_compl = 0;
1380 unsigned int txbds_ready;
1381 unsigned int c_index;
1382 struct sk_buff *skb;
1384 /* Clear status before servicing to reduce spurious interrupts */
1385 if (ring->index == DESC_INDEX)
1386 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1389 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1392 /* Compute how many buffers are transmitted since last xmit call */
1393 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1395 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1397 netif_dbg(priv, tx_done, dev,
1398 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1399 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1401 /* Reclaim transmitted buffers */
1402 while (txbds_processed < txbds_ready) {
1403 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1404 &priv->tx_cbs[ring->clean_ptr]);
1407 bytes_compl += GENET_CB(skb)->bytes_sent;
1408 dev_consume_skb_any(skb);
1412 if (likely(ring->clean_ptr < ring->end_ptr))
1415 ring->clean_ptr = ring->cb_ptr;
1418 ring->free_bds += txbds_processed;
1419 ring->c_index = c_index;
1421 ring->packets += pkts_compl;
1422 ring->bytes += bytes_compl;
1424 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1425 pkts_compl, bytes_compl);
1427 return txbds_processed;
1430 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1431 struct bcmgenet_tx_ring *ring)
1433 unsigned int released;
1435 spin_lock_bh(&ring->lock);
1436 released = __bcmgenet_tx_reclaim(dev, ring);
1437 spin_unlock_bh(&ring->lock);
1442 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1444 struct bcmgenet_tx_ring *ring =
1445 container_of(napi, struct bcmgenet_tx_ring, napi);
1446 unsigned int work_done = 0;
1447 struct netdev_queue *txq;
1449 spin_lock(&ring->lock);
1450 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1451 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1452 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1453 netif_tx_wake_queue(txq);
1455 spin_unlock(&ring->lock);
1457 if (work_done == 0) {
1458 napi_complete(napi);
1459 ring->int_enable(ring);
1467 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1469 struct bcmgenet_priv *priv = netdev_priv(dev);
1472 if (netif_is_multiqueue(dev)) {
1473 for (i = 0; i < priv->hw_params->tx_queues; i++)
1474 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1477 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1480 /* Reallocate the SKB to put enough headroom in front of it and insert
1481 * the transmit checksum offsets in the descriptors
1483 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1484 struct sk_buff *skb)
1486 struct status_64 *status = NULL;
1487 struct sk_buff *new_skb;
1493 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1494 /* If 64 byte status block enabled, must make sure skb has
1495 * enough headroom for us to insert 64B status block.
1497 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1500 dev->stats.tx_dropped++;
1506 skb_push(skb, sizeof(*status));
1507 status = (struct status_64 *)skb->data;
1509 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1510 ip_ver = skb->protocol;
1512 case htons(ETH_P_IP):
1513 ip_proto = ip_hdr(skb)->protocol;
1515 case htons(ETH_P_IPV6):
1516 ip_proto = ipv6_hdr(skb)->nexthdr;
1519 /* don't use UDP flag */
1524 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1525 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1526 (offset + skb->csum_offset) |
1529 /* Set the special UDP flag for UDP */
1530 if (ip_proto == IPPROTO_UDP)
1531 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1533 status->tx_csum_info = tx_csum_info;
1539 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1541 struct bcmgenet_priv *priv = netdev_priv(dev);
1542 struct device *kdev = &priv->pdev->dev;
1543 struct bcmgenet_tx_ring *ring = NULL;
1544 struct enet_cb *tx_cb_ptr;
1545 struct netdev_queue *txq;
1546 int nr_frags, index;
1554 index = skb_get_queue_mapping(skb);
1555 /* Mapping strategy:
1556 * queue_mapping = 0, unclassified, packet xmited through ring16
1557 * queue_mapping = 1, goes to ring 0. (highest priority queue
1558 * queue_mapping = 2, goes to ring 1.
1559 * queue_mapping = 3, goes to ring 2.
1560 * queue_mapping = 4, goes to ring 3.
1567 ring = &priv->tx_rings[index];
1568 txq = netdev_get_tx_queue(dev, ring->queue);
1570 nr_frags = skb_shinfo(skb)->nr_frags;
1572 spin_lock(&ring->lock);
1573 if (ring->free_bds <= (nr_frags + 1)) {
1574 if (!netif_tx_queue_stopped(txq)) {
1575 netif_tx_stop_queue(txq);
1577 "%s: tx ring %d full when queue %d awake\n",
1578 __func__, index, ring->queue);
1580 ret = NETDEV_TX_BUSY;
1584 if (skb_padto(skb, ETH_ZLEN)) {
1589 /* Retain how many bytes will be sent on the wire, without TSB inserted
1590 * by transmit checksum offload
1592 GENET_CB(skb)->bytes_sent = skb->len;
1594 /* set the SKB transmit checksum */
1595 if (priv->desc_64b_en) {
1596 skb = bcmgenet_put_tx_csum(dev, skb);
1603 for (i = 0; i <= nr_frags; i++) {
1604 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1609 /* Transmit single SKB or head of fragment list */
1610 GENET_CB(skb)->first_cb = tx_cb_ptr;
1611 size = skb_headlen(skb);
1612 mapping = dma_map_single(kdev, skb->data, size,
1616 frag = &skb_shinfo(skb)->frags[i - 1];
1617 size = skb_frag_size(frag);
1618 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1622 ret = dma_mapping_error(kdev, mapping);
1624 priv->mib.tx_dma_failed++;
1625 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1627 goto out_unmap_frags;
1629 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1630 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1632 tx_cb_ptr->skb = skb;
1634 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1635 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1638 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1639 if (skb->ip_summed == CHECKSUM_PARTIAL)
1640 len_stat |= DMA_TX_DO_CSUM;
1643 len_stat |= DMA_EOP;
1645 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1648 GENET_CB(skb)->last_cb = tx_cb_ptr;
1649 skb_tx_timestamp(skb);
1651 /* Decrement total BD count and advance our write pointer */
1652 ring->free_bds -= nr_frags + 1;
1653 ring->prod_index += nr_frags + 1;
1654 ring->prod_index &= DMA_P_INDEX_MASK;
1656 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1658 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1659 netif_tx_stop_queue(txq);
1661 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
1662 /* Packets are ready, update producer index */
1663 bcmgenet_tdma_ring_writel(priv, ring->index,
1664 ring->prod_index, TDMA_PROD_INDEX);
1666 spin_unlock(&ring->lock);
1671 /* Back up for failed control block mapping */
1672 bcmgenet_put_txcb(priv, ring);
1674 /* Unmap successfully mapped control blocks */
1676 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1677 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1684 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1687 struct device *kdev = &priv->pdev->dev;
1688 struct sk_buff *skb;
1689 struct sk_buff *rx_skb;
1692 /* Allocate a new Rx skb */
1693 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1695 priv->mib.alloc_rx_buff_failed++;
1696 netif_err(priv, rx_err, priv->dev,
1697 "%s: Rx skb allocation failed\n", __func__);
1701 /* DMA-map the new Rx skb */
1702 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1704 if (dma_mapping_error(kdev, mapping)) {
1705 priv->mib.rx_dma_failed++;
1706 dev_kfree_skb_any(skb);
1707 netif_err(priv, rx_err, priv->dev,
1708 "%s: Rx skb DMA mapping failed\n", __func__);
1712 /* Grab the current Rx skb from the ring and DMA-unmap it */
1713 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1715 /* Put the new Rx skb on the ring */
1717 dma_unmap_addr_set(cb, dma_addr, mapping);
1718 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1719 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1721 /* Return the current Rx skb to caller */
1725 /* bcmgenet_desc_rx - descriptor based rx process.
1726 * this could be called from bottom half, or from NAPI polling method.
1728 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1729 unsigned int budget)
1731 struct bcmgenet_priv *priv = ring->priv;
1732 struct net_device *dev = priv->dev;
1734 struct sk_buff *skb;
1735 u32 dma_length_status;
1736 unsigned long dma_flag;
1738 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1739 unsigned int bytes_processed = 0;
1740 unsigned int p_index, mask;
1741 unsigned int discards;
1743 /* Clear status before servicing to reduce spurious interrupts */
1744 if (ring->index == DESC_INDEX) {
1745 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1748 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1749 bcmgenet_intrl2_1_writel(priv,
1754 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1756 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1757 DMA_P_INDEX_DISCARD_CNT_MASK;
1758 if (discards > ring->old_discards) {
1759 discards = discards - ring->old_discards;
1760 ring->errors += discards;
1761 ring->old_discards += discards;
1763 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1764 if (ring->old_discards >= 0xC000) {
1765 ring->old_discards = 0;
1766 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1771 p_index &= DMA_P_INDEX_MASK;
1772 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1774 netif_dbg(priv, rx_status, dev,
1775 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1777 while ((rxpktprocessed < rxpkttoprocess) &&
1778 (rxpktprocessed < budget)) {
1779 cb = &priv->rx_cbs[ring->read_ptr];
1780 skb = bcmgenet_rx_refill(priv, cb);
1782 if (unlikely(!skb)) {
1787 if (!priv->desc_64b_en) {
1789 dmadesc_get_length_status(priv, cb->bd_addr);
1791 struct status_64 *status;
1794 status = (struct status_64 *)skb->data;
1795 dma_length_status = status->length_status;
1796 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
1797 if (priv->desc_rxchk_en) {
1798 skb->csum = (__force __wsum)ntohs(rx_csum);
1799 skb->ip_summed = CHECKSUM_COMPLETE;
1803 /* DMA flags and length are still valid no matter how
1804 * we got the Receive Status Vector (64B RSB or register)
1806 dma_flag = dma_length_status & 0xffff;
1807 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1809 netif_dbg(priv, rx_status, dev,
1810 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1811 __func__, p_index, ring->c_index,
1812 ring->read_ptr, dma_length_status);
1814 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1815 netif_err(priv, rx_status, dev,
1816 "dropping fragmented packet!\n");
1818 dev_kfree_skb_any(skb);
1823 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1828 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1829 (unsigned int)dma_flag);
1830 if (dma_flag & DMA_RX_CRC_ERROR)
1831 dev->stats.rx_crc_errors++;
1832 if (dma_flag & DMA_RX_OV)
1833 dev->stats.rx_over_errors++;
1834 if (dma_flag & DMA_RX_NO)
1835 dev->stats.rx_frame_errors++;
1836 if (dma_flag & DMA_RX_LG)
1837 dev->stats.rx_length_errors++;
1838 dev->stats.rx_errors++;
1839 dev_kfree_skb_any(skb);
1841 } /* error packet */
1844 if (priv->desc_64b_en) {
1849 /* remove hardware 2bytes added for IP alignment */
1853 if (priv->crc_fwd_en) {
1854 skb_trim(skb, len - ETH_FCS_LEN);
1858 bytes_processed += len;
1860 /*Finish setting up the received SKB and send it to the kernel*/
1861 skb->protocol = eth_type_trans(skb, priv->dev);
1864 if (dma_flag & DMA_RX_MULT)
1865 dev->stats.multicast++;
1868 napi_gro_receive(&ring->napi, skb);
1869 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1873 if (likely(ring->read_ptr < ring->end_ptr))
1876 ring->read_ptr = ring->cb_ptr;
1878 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1879 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1882 ring->dim.bytes = bytes_processed;
1883 ring->dim.packets = rxpktprocessed;
1885 return rxpktprocessed;
1888 /* Rx NAPI polling method */
1889 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1891 struct bcmgenet_rx_ring *ring = container_of(napi,
1892 struct bcmgenet_rx_ring, napi);
1893 struct dim_sample dim_sample = {};
1894 unsigned int work_done;
1896 work_done = bcmgenet_desc_rx(ring, budget);
1898 if (work_done < budget) {
1899 napi_complete_done(napi, work_done);
1900 ring->int_enable(ring);
1903 if (ring->dim.use_dim) {
1904 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
1905 ring->dim.bytes, &dim_sample);
1906 net_dim(&ring->dim.dim, dim_sample);
1912 static void bcmgenet_dim_work(struct work_struct *work)
1914 struct dim *dim = container_of(work, struct dim, work);
1915 struct bcmgenet_net_dim *ndim =
1916 container_of(dim, struct bcmgenet_net_dim, dim);
1917 struct bcmgenet_rx_ring *ring =
1918 container_of(ndim, struct bcmgenet_rx_ring, dim);
1919 struct dim_cq_moder cur_profile =
1920 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1922 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
1923 dim->state = DIM_START_MEASURE;
1926 /* Assign skb to RX DMA descriptor. */
1927 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1928 struct bcmgenet_rx_ring *ring)
1931 struct sk_buff *skb;
1934 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1936 /* loop here for each buffer needing assign */
1937 for (i = 0; i < ring->size; i++) {
1939 skb = bcmgenet_rx_refill(priv, cb);
1941 dev_consume_skb_any(skb);
1949 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1951 struct sk_buff *skb;
1955 for (i = 0; i < priv->num_rx_bds; i++) {
1956 cb = &priv->rx_cbs[i];
1958 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1960 dev_consume_skb_any(skb);
1964 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1968 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1973 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1975 /* UniMAC stops on a packet boundary, wait for a full-size packet
1979 usleep_range(1000, 2000);
1982 static void reset_umac(struct bcmgenet_priv *priv)
1984 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1985 bcmgenet_rbuf_ctrl_set(priv, 0);
1988 /* disable MAC while updating its registers */
1989 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1991 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
1992 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
1995 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1997 /* Mask all interrupts.*/
1998 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1999 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2000 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2001 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2004 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2006 u32 int0_enable = 0;
2008 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2011 if (priv->internal_phy) {
2012 int0_enable |= UMAC_IRQ_LINK_EVENT;
2013 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2014 int0_enable |= UMAC_IRQ_PHY_DET_R;
2015 } else if (priv->ext_phy) {
2016 int0_enable |= UMAC_IRQ_LINK_EVENT;
2017 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2018 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2019 int0_enable |= UMAC_IRQ_LINK_EVENT;
2021 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2024 static void init_umac(struct bcmgenet_priv *priv)
2026 struct device *kdev = &priv->pdev->dev;
2028 u32 int0_enable = 0;
2030 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2034 /* clear tx/rx counter */
2035 bcmgenet_umac_writel(priv,
2036 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2038 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2040 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2042 /* init rx registers, enable ip header optimization */
2043 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2044 reg |= RBUF_ALIGN_2B;
2045 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2047 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2048 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2050 bcmgenet_intr_disable(priv);
2052 /* Configure backpressure vectors for MoCA */
2053 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2054 reg = bcmgenet_bp_mc_get(priv);
2055 reg |= BIT(priv->hw_params->bp_in_en_shift);
2057 /* bp_mask: back pressure mask */
2058 if (netif_is_multiqueue(priv->dev))
2059 reg |= priv->hw_params->bp_in_mask;
2061 reg &= ~priv->hw_params->bp_in_mask;
2062 bcmgenet_bp_mc_set(priv, reg);
2065 /* Enable MDIO interrupts on GENET v3+ */
2066 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2067 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2069 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2071 dev_dbg(kdev, "done init umac\n");
2074 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2075 void (*cb)(struct work_struct *work))
2077 struct bcmgenet_net_dim *dim = &ring->dim;
2079 INIT_WORK(&dim->dim.work, cb);
2080 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2086 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2088 struct bcmgenet_net_dim *dim = &ring->dim;
2089 struct dim_cq_moder moder;
2092 usecs = ring->rx_coalesce_usecs;
2093 pkts = ring->rx_max_coalesced_frames;
2095 /* If DIM was enabled, re-apply default parameters */
2097 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2102 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2105 /* Initialize a Tx ring along with corresponding hardware registers */
2106 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2107 unsigned int index, unsigned int size,
2108 unsigned int start_ptr, unsigned int end_ptr)
2110 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2111 u32 words_per_bd = WORDS_PER_BD(priv);
2112 u32 flow_period_val = 0;
2114 spin_lock_init(&ring->lock);
2116 ring->index = index;
2117 if (index == DESC_INDEX) {
2119 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2120 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2122 ring->queue = index + 1;
2123 ring->int_enable = bcmgenet_tx_ring_int_enable;
2124 ring->int_disable = bcmgenet_tx_ring_int_disable;
2126 ring->cbs = priv->tx_cbs + start_ptr;
2128 ring->clean_ptr = start_ptr;
2130 ring->free_bds = size;
2131 ring->write_ptr = start_ptr;
2132 ring->cb_ptr = start_ptr;
2133 ring->end_ptr = end_ptr - 1;
2134 ring->prod_index = 0;
2136 /* Set flow period for ring != 16 */
2137 if (index != DESC_INDEX)
2138 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2140 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2141 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2142 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2143 /* Disable rate control for now */
2144 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2146 bcmgenet_tdma_ring_writel(priv, index,
2147 ((size << DMA_RING_SIZE_SHIFT) |
2148 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2150 /* Set start and end address, read and write pointers */
2151 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2153 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2155 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2157 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2160 /* Initialize Tx NAPI */
2161 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2165 /* Initialize a RDMA ring */
2166 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2167 unsigned int index, unsigned int size,
2168 unsigned int start_ptr, unsigned int end_ptr)
2170 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2171 u32 words_per_bd = WORDS_PER_BD(priv);
2175 ring->index = index;
2176 if (index == DESC_INDEX) {
2177 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2178 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2180 ring->int_enable = bcmgenet_rx_ring_int_enable;
2181 ring->int_disable = bcmgenet_rx_ring_int_disable;
2183 ring->cbs = priv->rx_cbs + start_ptr;
2186 ring->read_ptr = start_ptr;
2187 ring->cb_ptr = start_ptr;
2188 ring->end_ptr = end_ptr - 1;
2190 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2194 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2195 bcmgenet_init_rx_coalesce(ring);
2197 /* Initialize Rx NAPI */
2198 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2201 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2202 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2203 bcmgenet_rdma_ring_writel(priv, index,
2204 ((size << DMA_RING_SIZE_SHIFT) |
2205 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2206 bcmgenet_rdma_ring_writel(priv, index,
2207 (DMA_FC_THRESH_LO <<
2208 DMA_XOFF_THRESHOLD_SHIFT) |
2209 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2211 /* Set start and end address, read and write pointers */
2212 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2214 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2216 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2218 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2224 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2227 struct bcmgenet_tx_ring *ring;
2229 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2230 ring = &priv->tx_rings[i];
2231 napi_enable(&ring->napi);
2232 ring->int_enable(ring);
2235 ring = &priv->tx_rings[DESC_INDEX];
2236 napi_enable(&ring->napi);
2237 ring->int_enable(ring);
2240 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2243 struct bcmgenet_tx_ring *ring;
2245 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2246 ring = &priv->tx_rings[i];
2247 napi_disable(&ring->napi);
2250 ring = &priv->tx_rings[DESC_INDEX];
2251 napi_disable(&ring->napi);
2254 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2257 struct bcmgenet_tx_ring *ring;
2259 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2260 ring = &priv->tx_rings[i];
2261 netif_napi_del(&ring->napi);
2264 ring = &priv->tx_rings[DESC_INDEX];
2265 netif_napi_del(&ring->napi);
2268 /* Initialize Tx queues
2270 * Queues 0-3 are priority-based, each one has 32 descriptors,
2271 * with queue 0 being the highest priority queue.
2273 * Queue 16 is the default Tx queue with
2274 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2276 * The transmit control block pool is then partitioned as follows:
2277 * - Tx queue 0 uses tx_cbs[0..31]
2278 * - Tx queue 1 uses tx_cbs[32..63]
2279 * - Tx queue 2 uses tx_cbs[64..95]
2280 * - Tx queue 3 uses tx_cbs[96..127]
2281 * - Tx queue 16 uses tx_cbs[128..255]
2283 static void bcmgenet_init_tx_queues(struct net_device *dev)
2285 struct bcmgenet_priv *priv = netdev_priv(dev);
2287 u32 dma_ctrl, ring_cfg;
2288 u32 dma_priority[3] = {0, 0, 0};
2290 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2291 dma_enable = dma_ctrl & DMA_EN;
2292 dma_ctrl &= ~DMA_EN;
2293 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2298 /* Enable strict priority arbiter mode */
2299 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2301 /* Initialize Tx priority queues */
2302 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2303 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2304 i * priv->hw_params->tx_bds_per_q,
2305 (i + 1) * priv->hw_params->tx_bds_per_q);
2306 ring_cfg |= (1 << i);
2307 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2308 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2309 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2312 /* Initialize Tx default queue 16 */
2313 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2314 priv->hw_params->tx_queues *
2315 priv->hw_params->tx_bds_per_q,
2317 ring_cfg |= (1 << DESC_INDEX);
2318 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2319 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2320 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2321 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2323 /* Set Tx queue priorities */
2324 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2325 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2326 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2328 /* Enable Tx queues */
2329 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2334 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2337 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2340 struct bcmgenet_rx_ring *ring;
2342 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2343 ring = &priv->rx_rings[i];
2344 napi_enable(&ring->napi);
2345 ring->int_enable(ring);
2348 ring = &priv->rx_rings[DESC_INDEX];
2349 napi_enable(&ring->napi);
2350 ring->int_enable(ring);
2353 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2356 struct bcmgenet_rx_ring *ring;
2358 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2359 ring = &priv->rx_rings[i];
2360 napi_disable(&ring->napi);
2361 cancel_work_sync(&ring->dim.dim.work);
2364 ring = &priv->rx_rings[DESC_INDEX];
2365 napi_disable(&ring->napi);
2366 cancel_work_sync(&ring->dim.dim.work);
2369 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2372 struct bcmgenet_rx_ring *ring;
2374 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2375 ring = &priv->rx_rings[i];
2376 netif_napi_del(&ring->napi);
2379 ring = &priv->rx_rings[DESC_INDEX];
2380 netif_napi_del(&ring->napi);
2383 /* Initialize Rx queues
2385 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2386 * used to direct traffic to these queues.
2388 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2390 static int bcmgenet_init_rx_queues(struct net_device *dev)
2392 struct bcmgenet_priv *priv = netdev_priv(dev);
2399 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2400 dma_enable = dma_ctrl & DMA_EN;
2401 dma_ctrl &= ~DMA_EN;
2402 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2407 /* Initialize Rx priority queues */
2408 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2409 ret = bcmgenet_init_rx_ring(priv, i,
2410 priv->hw_params->rx_bds_per_q,
2411 i * priv->hw_params->rx_bds_per_q,
2413 priv->hw_params->rx_bds_per_q);
2417 ring_cfg |= (1 << i);
2418 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2421 /* Initialize Rx default queue 16 */
2422 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2423 priv->hw_params->rx_queues *
2424 priv->hw_params->rx_bds_per_q,
2429 ring_cfg |= (1 << DESC_INDEX);
2430 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2433 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2435 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2438 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2443 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2451 /* Disable TDMA to stop add more frames in TX DMA */
2452 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2454 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2456 /* Check TDMA status register to confirm TDMA is disabled */
2457 while (timeout++ < DMA_TIMEOUT_VAL) {
2458 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2459 if (reg & DMA_DISABLED)
2465 if (timeout == DMA_TIMEOUT_VAL) {
2466 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2470 /* Wait 10ms for packet drain in both tx and rx dma */
2471 usleep_range(10000, 20000);
2474 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2476 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2479 /* Check RDMA status register to confirm RDMA is disabled */
2480 while (timeout++ < DMA_TIMEOUT_VAL) {
2481 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2482 if (reg & DMA_DISABLED)
2488 if (timeout == DMA_TIMEOUT_VAL) {
2489 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2494 for (i = 0; i < priv->hw_params->rx_queues; i++)
2495 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2496 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2498 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2501 for (i = 0; i < priv->hw_params->tx_queues; i++)
2502 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2503 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2505 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2510 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2512 struct netdev_queue *txq;
2515 bcmgenet_fini_rx_napi(priv);
2516 bcmgenet_fini_tx_napi(priv);
2518 for (i = 0; i < priv->num_tx_bds; i++)
2519 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
2522 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2523 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2524 netdev_tx_reset_queue(txq);
2527 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2528 netdev_tx_reset_queue(txq);
2530 bcmgenet_free_rx_buffers(priv);
2531 kfree(priv->rx_cbs);
2532 kfree(priv->tx_cbs);
2535 /* init_edma: Initialize DMA control register */
2536 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2542 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2544 /* Initialize common Rx ring structures */
2545 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2546 priv->num_rx_bds = TOTAL_DESC;
2547 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2552 for (i = 0; i < priv->num_rx_bds; i++) {
2553 cb = priv->rx_cbs + i;
2554 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2557 /* Initialize common TX ring structures */
2558 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2559 priv->num_tx_bds = TOTAL_DESC;
2560 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2562 if (!priv->tx_cbs) {
2563 kfree(priv->rx_cbs);
2567 for (i = 0; i < priv->num_tx_bds; i++) {
2568 cb = priv->tx_cbs + i;
2569 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2573 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
2574 DMA_SCB_BURST_SIZE);
2576 /* Initialize Rx queues */
2577 ret = bcmgenet_init_rx_queues(priv->dev);
2579 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2580 bcmgenet_free_rx_buffers(priv);
2581 kfree(priv->rx_cbs);
2582 kfree(priv->tx_cbs);
2587 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
2588 DMA_SCB_BURST_SIZE);
2590 /* Initialize Tx queues */
2591 bcmgenet_init_tx_queues(priv->dev);
2596 /* Interrupt bottom half */
2597 static void bcmgenet_irq_task(struct work_struct *work)
2599 unsigned int status;
2600 struct bcmgenet_priv *priv = container_of(
2601 work, struct bcmgenet_priv, bcmgenet_irq_work);
2603 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2605 spin_lock_irq(&priv->lock);
2606 status = priv->irq0_stat;
2607 priv->irq0_stat = 0;
2608 spin_unlock_irq(&priv->lock);
2610 if (status & UMAC_IRQ_PHY_DET_R &&
2611 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2612 phy_init_hw(priv->dev->phydev);
2613 genphy_config_aneg(priv->dev->phydev);
2616 /* Link UP/DOWN event */
2617 if (status & UMAC_IRQ_LINK_EVENT)
2618 phy_mac_interrupt(priv->dev->phydev);
2622 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2623 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2625 struct bcmgenet_priv *priv = dev_id;
2626 struct bcmgenet_rx_ring *rx_ring;
2627 struct bcmgenet_tx_ring *tx_ring;
2628 unsigned int index, status;
2630 /* Read irq status */
2631 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2632 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2634 /* clear interrupts */
2635 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2637 netif_dbg(priv, intr, priv->dev,
2638 "%s: IRQ=0x%x\n", __func__, status);
2640 /* Check Rx priority queue interrupts */
2641 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2642 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2645 rx_ring = &priv->rx_rings[index];
2646 rx_ring->dim.event_ctr++;
2648 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2649 rx_ring->int_disable(rx_ring);
2650 __napi_schedule_irqoff(&rx_ring->napi);
2654 /* Check Tx priority queue interrupts */
2655 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2656 if (!(status & BIT(index)))
2659 tx_ring = &priv->tx_rings[index];
2661 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2662 tx_ring->int_disable(tx_ring);
2663 __napi_schedule_irqoff(&tx_ring->napi);
2670 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2671 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2673 struct bcmgenet_priv *priv = dev_id;
2674 struct bcmgenet_rx_ring *rx_ring;
2675 struct bcmgenet_tx_ring *tx_ring;
2676 unsigned int status;
2677 unsigned long flags;
2679 /* Read irq status */
2680 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2681 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2683 /* clear interrupts */
2684 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2686 netif_dbg(priv, intr, priv->dev,
2687 "IRQ=0x%x\n", status);
2689 if (status & UMAC_IRQ_RXDMA_DONE) {
2690 rx_ring = &priv->rx_rings[DESC_INDEX];
2691 rx_ring->dim.event_ctr++;
2693 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2694 rx_ring->int_disable(rx_ring);
2695 __napi_schedule_irqoff(&rx_ring->napi);
2699 if (status & UMAC_IRQ_TXDMA_DONE) {
2700 tx_ring = &priv->tx_rings[DESC_INDEX];
2702 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2703 tx_ring->int_disable(tx_ring);
2704 __napi_schedule_irqoff(&tx_ring->napi);
2708 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2709 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2713 /* all other interested interrupts handled in bottom half */
2714 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
2716 /* Save irq status for bottom-half processing. */
2717 spin_lock_irqsave(&priv->lock, flags);
2718 priv->irq0_stat |= status;
2719 spin_unlock_irqrestore(&priv->lock, flags);
2721 schedule_work(&priv->bcmgenet_irq_work);
2727 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2729 struct bcmgenet_priv *priv = dev_id;
2731 pm_wakeup_event(&priv->pdev->dev, 0);
2736 #ifdef CONFIG_NET_POLL_CONTROLLER
2737 static void bcmgenet_poll_controller(struct net_device *dev)
2739 struct bcmgenet_priv *priv = netdev_priv(dev);
2741 /* Invoke the main RX/TX interrupt handler */
2742 disable_irq(priv->irq0);
2743 bcmgenet_isr0(priv->irq0, priv);
2744 enable_irq(priv->irq0);
2746 /* And the interrupt handler for RX/TX priority queues */
2747 disable_irq(priv->irq1);
2748 bcmgenet_isr1(priv->irq1, priv);
2749 enable_irq(priv->irq1);
2753 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2757 reg = bcmgenet_rbuf_ctrl_get(priv);
2759 bcmgenet_rbuf_ctrl_set(priv, reg);
2763 bcmgenet_rbuf_ctrl_set(priv, reg);
2767 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2768 unsigned char *addr)
2770 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2771 (addr[2] << 8) | addr[3], UMAC_MAC0);
2772 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2775 /* Returns a reusable dma control register value */
2776 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2782 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2783 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2785 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2787 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2789 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2791 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2793 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2798 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2802 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2804 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2806 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2808 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2811 /* bcmgenet_hfb_clear
2813 * Clear Hardware Filter Block and disable all filtering.
2815 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2819 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2820 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2821 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2823 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2824 bcmgenet_rdma_writel(priv, 0x0, i);
2826 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2827 bcmgenet_hfb_reg_writel(priv, 0x0,
2828 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2830 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2831 priv->hw_params->hfb_filter_size; i++)
2832 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2835 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2837 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2840 bcmgenet_hfb_clear(priv);
2843 static void bcmgenet_netif_start(struct net_device *dev)
2845 struct bcmgenet_priv *priv = netdev_priv(dev);
2847 /* Start the network engine */
2848 bcmgenet_enable_rx_napi(priv);
2850 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2852 bcmgenet_enable_tx_napi(priv);
2854 /* Monitor link interrupts now */
2855 bcmgenet_link_intr_enable(priv);
2857 phy_start(dev->phydev);
2860 static int bcmgenet_open(struct net_device *dev)
2862 struct bcmgenet_priv *priv = netdev_priv(dev);
2863 unsigned long dma_ctrl;
2867 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2869 /* Turn on the clock */
2870 clk_prepare_enable(priv->clk);
2872 /* If this is an internal GPHY, power it back on now, before UniMAC is
2873 * brought out of reset as absolutely no UniMAC activity is allowed
2875 if (priv->internal_phy)
2876 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2878 /* take MAC out of reset */
2879 bcmgenet_umac_reset(priv);
2883 /* Make sure we reflect the value of CRC_CMD_FWD */
2884 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2885 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2887 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2889 if (priv->internal_phy) {
2890 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2891 reg |= EXT_ENERGY_DET_MASK;
2892 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2895 /* Disable RX/TX DMA and flush TX queues */
2896 dma_ctrl = bcmgenet_dma_disable(priv);
2898 /* Reinitialize TDMA and RDMA and SW housekeeping */
2899 ret = bcmgenet_init_dma(priv);
2901 netdev_err(dev, "failed to initialize DMA\n");
2902 goto err_clk_disable;
2905 /* Always enable ring 16 - descriptor ring */
2906 bcmgenet_enable_dma(priv, dma_ctrl);
2909 bcmgenet_hfb_init(priv);
2911 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2914 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2918 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2921 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2925 ret = bcmgenet_mii_probe(dev);
2927 netdev_err(dev, "failed to connect to PHY\n");
2931 bcmgenet_netif_start(dev);
2933 netif_tx_start_all_queues(dev);
2938 free_irq(priv->irq1, priv);
2940 free_irq(priv->irq0, priv);
2942 bcmgenet_dma_teardown(priv);
2943 bcmgenet_fini_dma(priv);
2945 if (priv->internal_phy)
2946 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2947 clk_disable_unprepare(priv->clk);
2951 static void bcmgenet_netif_stop(struct net_device *dev)
2953 struct bcmgenet_priv *priv = netdev_priv(dev);
2955 bcmgenet_disable_tx_napi(priv);
2956 netif_tx_disable(dev);
2958 /* Disable MAC receive */
2959 umac_enable_set(priv, CMD_RX_EN, false);
2961 bcmgenet_dma_teardown(priv);
2963 /* Disable MAC transmit. TX DMA disabled must be done before this */
2964 umac_enable_set(priv, CMD_TX_EN, false);
2966 phy_stop(dev->phydev);
2967 bcmgenet_disable_rx_napi(priv);
2968 bcmgenet_intr_disable(priv);
2970 /* Wait for pending work items to complete. Since interrupts are
2971 * disabled no new work will be scheduled.
2973 cancel_work_sync(&priv->bcmgenet_irq_work);
2975 priv->old_link = -1;
2976 priv->old_speed = -1;
2977 priv->old_duplex = -1;
2978 priv->old_pause = -1;
2981 bcmgenet_tx_reclaim_all(dev);
2982 bcmgenet_fini_dma(priv);
2985 static int bcmgenet_close(struct net_device *dev)
2987 struct bcmgenet_priv *priv = netdev_priv(dev);
2990 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2992 bcmgenet_netif_stop(dev);
2994 /* Really kill the PHY state machine and disconnect from it */
2995 phy_disconnect(dev->phydev);
2997 free_irq(priv->irq0, priv);
2998 free_irq(priv->irq1, priv);
3000 if (priv->internal_phy)
3001 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3003 clk_disable_unprepare(priv->clk);
3008 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3010 struct bcmgenet_priv *priv = ring->priv;
3011 u32 p_index, c_index, intsts, intmsk;
3012 struct netdev_queue *txq;
3013 unsigned int free_bds;
3016 if (!netif_msg_tx_err(priv))
3019 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3021 spin_lock(&ring->lock);
3022 if (ring->index == DESC_INDEX) {
3023 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3024 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3026 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3027 intmsk = 1 << ring->index;
3029 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3030 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3031 txq_stopped = netif_tx_queue_stopped(txq);
3032 free_bds = ring->free_bds;
3033 spin_unlock(&ring->lock);
3035 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3036 "TX queue status: %s, interrupts: %s\n"
3037 "(sw)free_bds: %d (sw)size: %d\n"
3038 "(sw)p_index: %d (hw)p_index: %d\n"
3039 "(sw)c_index: %d (hw)c_index: %d\n"
3040 "(sw)clean_p: %d (sw)write_p: %d\n"
3041 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3042 ring->index, ring->queue,
3043 txq_stopped ? "stopped" : "active",
3044 intsts & intmsk ? "enabled" : "disabled",
3045 free_bds, ring->size,
3046 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3047 ring->c_index, c_index & DMA_C_INDEX_MASK,
3048 ring->clean_ptr, ring->write_ptr,
3049 ring->cb_ptr, ring->end_ptr);
3052 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3054 struct bcmgenet_priv *priv = netdev_priv(dev);
3055 u32 int0_enable = 0;
3056 u32 int1_enable = 0;
3059 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3061 for (q = 0; q < priv->hw_params->tx_queues; q++)
3062 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3063 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3065 bcmgenet_tx_reclaim_all(dev);
3067 for (q = 0; q < priv->hw_params->tx_queues; q++)
3068 int1_enable |= (1 << q);
3070 int0_enable = UMAC_IRQ_TXDMA_DONE;
3072 /* Re-enable TX interrupts if disabled */
3073 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3074 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3076 netif_trans_update(dev);
3078 dev->stats.tx_errors++;
3080 netif_tx_wake_all_queues(dev);
3083 #define MAX_MDF_FILTER 17
3085 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3086 unsigned char *addr,
3089 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3090 UMAC_MDF_ADDR + (*i * 4));
3091 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3092 addr[4] << 8 | addr[5],
3093 UMAC_MDF_ADDR + ((*i + 1) * 4));
3097 static void bcmgenet_set_rx_mode(struct net_device *dev)
3099 struct bcmgenet_priv *priv = netdev_priv(dev);
3100 struct netdev_hw_addr *ha;
3104 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3106 /* Number of filters needed */
3107 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3110 * Turn on promicuous mode for three scenarios
3111 * 1. IFF_PROMISC flag is set
3112 * 2. IFF_ALLMULTI flag is set
3113 * 3. The number of filters needed exceeds the number filters
3114 * supported by the hardware.
3116 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3117 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3118 (nfilter > MAX_MDF_FILTER)) {
3120 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3121 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3124 reg &= ~CMD_PROMISC;
3125 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3128 /* update MDF filter */
3131 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3132 /* my own address.*/
3133 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3136 netdev_for_each_uc_addr(ha, dev)
3137 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3140 netdev_for_each_mc_addr(ha, dev)
3141 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3143 /* Enable filters */
3144 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3145 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3148 /* Set the hardware MAC address. */
3149 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3151 struct sockaddr *addr = p;
3153 /* Setting the MAC address at the hardware level is not possible
3154 * without disabling the UniMAC RX/TX enable bits.
3156 if (netif_running(dev))
3159 ether_addr_copy(dev->dev_addr, addr->sa_data);
3164 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3166 struct bcmgenet_priv *priv = netdev_priv(dev);
3167 unsigned long tx_bytes = 0, tx_packets = 0;
3168 unsigned long rx_bytes = 0, rx_packets = 0;
3169 unsigned long rx_errors = 0, rx_dropped = 0;
3170 struct bcmgenet_tx_ring *tx_ring;
3171 struct bcmgenet_rx_ring *rx_ring;
3174 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3175 tx_ring = &priv->tx_rings[q];
3176 tx_bytes += tx_ring->bytes;
3177 tx_packets += tx_ring->packets;
3179 tx_ring = &priv->tx_rings[DESC_INDEX];
3180 tx_bytes += tx_ring->bytes;
3181 tx_packets += tx_ring->packets;
3183 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3184 rx_ring = &priv->rx_rings[q];
3186 rx_bytes += rx_ring->bytes;
3187 rx_packets += rx_ring->packets;
3188 rx_errors += rx_ring->errors;
3189 rx_dropped += rx_ring->dropped;
3191 rx_ring = &priv->rx_rings[DESC_INDEX];
3192 rx_bytes += rx_ring->bytes;
3193 rx_packets += rx_ring->packets;
3194 rx_errors += rx_ring->errors;
3195 rx_dropped += rx_ring->dropped;
3197 dev->stats.tx_bytes = tx_bytes;
3198 dev->stats.tx_packets = tx_packets;
3199 dev->stats.rx_bytes = rx_bytes;
3200 dev->stats.rx_packets = rx_packets;
3201 dev->stats.rx_errors = rx_errors;
3202 dev->stats.rx_missed_errors = rx_errors;
3206 static const struct net_device_ops bcmgenet_netdev_ops = {
3207 .ndo_open = bcmgenet_open,
3208 .ndo_stop = bcmgenet_close,
3209 .ndo_start_xmit = bcmgenet_xmit,
3210 .ndo_tx_timeout = bcmgenet_timeout,
3211 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3212 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3213 .ndo_do_ioctl = bcmgenet_ioctl,
3214 .ndo_set_features = bcmgenet_set_features,
3215 #ifdef CONFIG_NET_POLL_CONTROLLER
3216 .ndo_poll_controller = bcmgenet_poll_controller,
3218 .ndo_get_stats = bcmgenet_get_stats,
3221 /* Array of GENET hardware parameters/characteristics */
3222 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3228 .bp_in_en_shift = 16,
3229 .bp_in_mask = 0xffff,
3230 .hfb_filter_cnt = 16,
3232 .hfb_offset = 0x1000,
3233 .rdma_offset = 0x2000,
3234 .tdma_offset = 0x3000,
3242 .bp_in_en_shift = 16,
3243 .bp_in_mask = 0xffff,
3244 .hfb_filter_cnt = 16,
3246 .tbuf_offset = 0x0600,
3247 .hfb_offset = 0x1000,
3248 .hfb_reg_offset = 0x2000,
3249 .rdma_offset = 0x3000,
3250 .tdma_offset = 0x4000,
3252 .flags = GENET_HAS_EXT,
3259 .bp_in_en_shift = 17,
3260 .bp_in_mask = 0x1ffff,
3261 .hfb_filter_cnt = 48,
3262 .hfb_filter_size = 128,
3264 .tbuf_offset = 0x0600,
3265 .hfb_offset = 0x8000,
3266 .hfb_reg_offset = 0xfc00,
3267 .rdma_offset = 0x10000,
3268 .tdma_offset = 0x11000,
3270 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3271 GENET_HAS_MOCA_LINK_DET,
3278 .bp_in_en_shift = 17,
3279 .bp_in_mask = 0x1ffff,
3280 .hfb_filter_cnt = 48,
3281 .hfb_filter_size = 128,
3283 .tbuf_offset = 0x0600,
3284 .hfb_offset = 0x8000,
3285 .hfb_reg_offset = 0xfc00,
3286 .rdma_offset = 0x2000,
3287 .tdma_offset = 0x4000,
3289 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3290 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3297 .bp_in_en_shift = 17,
3298 .bp_in_mask = 0x1ffff,
3299 .hfb_filter_cnt = 48,
3300 .hfb_filter_size = 128,
3302 .tbuf_offset = 0x0600,
3303 .hfb_offset = 0x8000,
3304 .hfb_reg_offset = 0xfc00,
3305 .rdma_offset = 0x2000,
3306 .tdma_offset = 0x4000,
3308 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3309 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3313 /* Infer hardware parameters from the detected GENET version */
3314 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3316 struct bcmgenet_hw_params *params;
3321 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3322 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3323 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3324 } else if (GENET_IS_V3(priv)) {
3325 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3326 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3327 } else if (GENET_IS_V2(priv)) {
3328 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3329 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3330 } else if (GENET_IS_V1(priv)) {
3331 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3332 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3335 /* enum genet_version starts at 1 */
3336 priv->hw_params = &bcmgenet_hw_params[priv->version];
3337 params = priv->hw_params;
3339 /* Read GENET HW version */
3340 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3341 major = (reg >> 24 & 0x0f);
3344 else if (major == 5)
3346 else if (major == 0)
3348 if (major != priv->version) {
3349 dev_err(&priv->pdev->dev,
3350 "GENET version mismatch, got: %d, configured for: %d\n",
3351 major, priv->version);
3354 /* Print the GENET core version */
3355 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3356 major, (reg >> 16) & 0x0f, reg & 0xffff);
3358 /* Store the integrated PHY revision for the MDIO probing function
3359 * to pass this information to the PHY driver. The PHY driver expects
3360 * to find the PHY major revision in bits 15:8 while the GENET register
3361 * stores that information in bits 7:0, account for that.
3363 * On newer chips, starting with PHY revision G0, a new scheme is
3364 * deployed similar to the Starfighter 2 switch with GPHY major
3365 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3366 * is reserved as well as special value 0x01ff, we have a small
3367 * heuristic to check for the new GPHY revision and re-arrange things
3368 * so the GPHY driver is happy.
3370 gphy_rev = reg & 0xffff;
3372 if (GENET_IS_V5(priv)) {
3373 /* The EPHY revision should come from the MDIO registers of
3374 * the PHY not from GENET.
3376 if (gphy_rev != 0) {
3377 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3380 /* This is reserved so should require special treatment */
3381 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3382 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3384 /* This is the good old scheme, just GPHY major, no minor nor patch */
3385 } else if ((gphy_rev & 0xf0) != 0) {
3386 priv->gphy_rev = gphy_rev << 8;
3387 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3388 } else if ((gphy_rev & 0xff00) != 0) {
3389 priv->gphy_rev = gphy_rev;
3392 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3393 if (!(params->flags & GENET_HAS_40BITS))
3394 pr_warn("GENET does not support 40-bits PA\n");
3397 pr_debug("Configuration for version: %d\n"
3398 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3399 "BP << en: %2d, BP msk: 0x%05x\n"
3400 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3401 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3402 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3405 params->tx_queues, params->tx_bds_per_q,
3406 params->rx_queues, params->rx_bds_per_q,
3407 params->bp_in_en_shift, params->bp_in_mask,
3408 params->hfb_filter_cnt, params->qtag_mask,
3409 params->tbuf_offset, params->hfb_offset,
3410 params->hfb_reg_offset,
3411 params->rdma_offset, params->tdma_offset,
3412 params->words_per_bd);
3415 struct bcmgenet_plat_data {
3416 enum bcmgenet_version version;
3417 u32 dma_max_burst_length;
3420 static const struct bcmgenet_plat_data v1_plat_data = {
3421 .version = GENET_V1,
3422 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3425 static const struct bcmgenet_plat_data v2_plat_data = {
3426 .version = GENET_V2,
3427 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3430 static const struct bcmgenet_plat_data v3_plat_data = {
3431 .version = GENET_V3,
3432 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3435 static const struct bcmgenet_plat_data v4_plat_data = {
3436 .version = GENET_V4,
3437 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3440 static const struct bcmgenet_plat_data v5_plat_data = {
3441 .version = GENET_V5,
3442 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3445 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3446 .version = GENET_V5,
3447 .dma_max_burst_length = 0x08,
3450 static const struct of_device_id bcmgenet_match[] = {
3451 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3452 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3453 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3454 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3455 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3456 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3459 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3461 static int bcmgenet_probe(struct platform_device *pdev)
3463 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3464 struct device_node *dn = pdev->dev.of_node;
3465 const struct of_device_id *of_id = NULL;
3466 const struct bcmgenet_plat_data *pdata;
3467 struct bcmgenet_priv *priv;
3468 struct net_device *dev;
3469 const void *macaddr;
3472 const char *phy_mode_str;
3474 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3475 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3476 GENET_MAX_MQ_CNT + 1);
3478 dev_err(&pdev->dev, "can't allocate net device\n");
3483 of_id = of_match_node(bcmgenet_match, dn);
3488 priv = netdev_priv(dev);
3489 priv->irq0 = platform_get_irq(pdev, 0);
3490 if (priv->irq0 < 0) {
3494 priv->irq1 = platform_get_irq(pdev, 1);
3495 if (priv->irq1 < 0) {
3499 priv->wol_irq = platform_get_irq_optional(pdev, 2);
3502 macaddr = of_get_mac_address(dn);
3504 macaddr = pd->mac_address;
3506 priv->base = devm_platform_ioremap_resource(pdev, 0);
3507 if (IS_ERR(priv->base)) {
3508 err = PTR_ERR(priv->base);
3512 spin_lock_init(&priv->lock);
3514 SET_NETDEV_DEV(dev, &pdev->dev);
3515 dev_set_drvdata(&pdev->dev, dev);
3516 if (IS_ERR_OR_NULL(macaddr) || !is_valid_ether_addr(macaddr)) {
3517 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
3518 eth_hw_addr_random(dev);
3520 ether_addr_copy(dev->dev_addr, macaddr);
3522 dev->watchdog_timeo = 2 * HZ;
3523 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3524 dev->netdev_ops = &bcmgenet_netdev_ops;
3526 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3528 /* Set hardware features */
3529 dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
3532 /* Request the WOL interrupt and advertise suspend if available */
3533 priv->wol_irq_disabled = true;
3534 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3537 device_set_wakeup_capable(&pdev->dev, 1);
3539 /* Set the needed headroom to account for any possible
3540 * features enabling/disabling at runtime
3542 dev->needed_headroom += 64;
3544 netdev_boot_setup_check(dev);
3549 pdata = of_id->data;
3550 priv->version = pdata->version;
3551 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3553 priv->version = pd->genet_version;
3554 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
3557 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3558 if (IS_ERR(priv->clk)) {
3559 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3563 clk_prepare_enable(priv->clk);
3565 bcmgenet_set_hw_params(priv);
3568 if (priv->hw_params->flags & GENET_HAS_40BITS)
3569 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
3571 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3575 /* Mii wait queue */
3576 init_waitqueue_head(&priv->wq);
3577 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3578 priv->rx_buf_len = RX_BUF_LENGTH;
3579 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3581 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3582 if (IS_ERR(priv->clk_wol)) {
3583 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3584 priv->clk_wol = NULL;
3587 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3588 if (IS_ERR(priv->clk_eee)) {
3589 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3590 priv->clk_eee = NULL;
3593 /* If this is an internal GPHY, power it on now, before UniMAC is
3594 * brought out of reset as absolutely no UniMAC activity is allowed
3596 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3597 !strcasecmp(phy_mode_str, "internal"))
3598 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3602 err = bcmgenet_mii_init(dev);
3604 goto err_clk_disable;
3606 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3607 * just the ring 16 descriptor based TX
3609 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3610 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3612 /* Set default coalescing parameters */
3613 for (i = 0; i < priv->hw_params->rx_queues; i++)
3614 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3615 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3617 /* libphy will determine the link state */
3618 netif_carrier_off(dev);
3620 /* Turn off the main clock, WOL clock is handled separately */
3621 clk_disable_unprepare(priv->clk);
3623 err = register_netdev(dev);
3630 clk_disable_unprepare(priv->clk);
3636 static int bcmgenet_remove(struct platform_device *pdev)
3638 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3640 dev_set_drvdata(&pdev->dev, NULL);
3641 unregister_netdev(priv->dev);
3642 bcmgenet_mii_exit(priv->dev);
3643 free_netdev(priv->dev);
3648 static void bcmgenet_shutdown(struct platform_device *pdev)
3650 bcmgenet_remove(pdev);
3653 #ifdef CONFIG_PM_SLEEP
3654 static int bcmgenet_resume(struct device *d)
3656 struct net_device *dev = dev_get_drvdata(d);
3657 struct bcmgenet_priv *priv = netdev_priv(dev);
3658 unsigned long dma_ctrl;
3662 if (!netif_running(dev))
3665 /* Turn on the clock */
3666 ret = clk_prepare_enable(priv->clk);
3670 /* If this is an internal GPHY, power it back on now, before UniMAC is
3671 * brought out of reset as absolutely no UniMAC activity is allowed
3673 if (priv->internal_phy)
3674 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3676 bcmgenet_umac_reset(priv);
3680 /* From WOL-enabled suspend, switch to regular clock */
3682 clk_disable_unprepare(priv->clk_wol);
3684 phy_init_hw(dev->phydev);
3686 /* Speed settings must be restored */
3687 genphy_config_aneg(dev->phydev);
3688 bcmgenet_mii_config(priv->dev, false);
3690 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3692 if (priv->internal_phy) {
3693 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3694 reg |= EXT_ENERGY_DET_MASK;
3695 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3699 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3701 /* Disable RX/TX DMA and flush TX queues */
3702 dma_ctrl = bcmgenet_dma_disable(priv);
3704 /* Reinitialize TDMA and RDMA and SW housekeeping */
3705 ret = bcmgenet_init_dma(priv);
3707 netdev_err(dev, "failed to initialize DMA\n");
3708 goto out_clk_disable;
3711 /* Always enable ring 16 - descriptor ring */
3712 bcmgenet_enable_dma(priv, dma_ctrl);
3714 if (!device_may_wakeup(d))
3715 phy_resume(dev->phydev);
3717 if (priv->eee.eee_enabled)
3718 bcmgenet_eee_enable_set(dev, true);
3720 bcmgenet_netif_start(dev);
3722 netif_device_attach(dev);
3727 if (priv->internal_phy)
3728 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3729 clk_disable_unprepare(priv->clk);
3733 static int bcmgenet_suspend(struct device *d)
3735 struct net_device *dev = dev_get_drvdata(d);
3736 struct bcmgenet_priv *priv = netdev_priv(dev);
3739 if (!netif_running(dev))
3742 netif_device_detach(dev);
3744 bcmgenet_netif_stop(dev);
3746 if (!device_may_wakeup(d))
3747 phy_suspend(dev->phydev);
3749 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3750 if (device_may_wakeup(d) && priv->wolopts) {
3751 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3752 clk_prepare_enable(priv->clk_wol);
3753 } else if (priv->internal_phy) {
3754 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3757 /* Turn off the clocks */
3758 clk_disable_unprepare(priv->clk);
3765 #endif /* CONFIG_PM_SLEEP */
3767 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3769 static struct platform_driver bcmgenet_driver = {
3770 .probe = bcmgenet_probe,
3771 .remove = bcmgenet_remove,
3772 .shutdown = bcmgenet_shutdown,
3775 .of_match_table = bcmgenet_match,
3776 .pm = &bcmgenet_pm_ops,
3779 module_platform_driver(bcmgenet_driver);
3781 MODULE_AUTHOR("Broadcom Corporation");
3782 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3783 MODULE_ALIAS("platform:bcmgenet");
3784 MODULE_LICENSE("GPL");