drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/ip.h>
  41 #include <net/tcp.h>
  42 #include <net/udp.h>
  43 #include <net/checksum.h>
  44 #include <net/ip6_checksum.h>
  45 #include <net/udp_tunnel.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57
  58 #include "bnxt_hsi.h"
  59 #include "bnxt.h"
  60 #include "bnxt_ulp.h"
  61 #include "bnxt_sriov.h"
  62 #include "bnxt_ethtool.h"
  63 #include "bnxt_dcb.h"
  64 #include "bnxt_xdp.h"
  65 #include "bnxt_vfr.h"
  66 #include "bnxt_tc.h"
  67 #include "bnxt_devlink.h"
  68 #include "bnxt_debugfs.h"
  69
  70 #define BNXT_TX_TIMEOUT         (5 * HZ)
  71
  72 static const char version[] =
  73         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  74
  75 MODULE_LICENSE("GPL");
  76 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  77 MODULE_VERSION(DRV_MODULE_VERSION);
  78
  79 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  80 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  81 #define BNXT_RX_COPY_THRESH 256
  82
  83 #define BNXT_TX_PUSH_THRESH 164
  84
  85 enum board_idx {
  86         BCM57301,
  87         BCM57302,
  88         BCM57304,
  89         BCM57417_NPAR,
  90         BCM58700,
  91         BCM57311,
  92         BCM57312,
  93         BCM57402,
  94         BCM57404,
  95         BCM57406,
  96         BCM57402_NPAR,
  97         BCM57407,
  98         BCM57412,
  99         BCM57414,
 100         BCM57416,
 101         BCM57417,
 102         BCM57412_NPAR,
 103         BCM57314,
 104         BCM57417_SFP,
 105         BCM57416_SFP,
 106         BCM57404_NPAR,
 107         BCM57406_NPAR,
 108         BCM57407_SFP,
 109         BCM57407_NPAR,
 110         BCM57414_NPAR,
 111         BCM57416_NPAR,
 112         BCM57452,
 113         BCM57454,
 114         BCM5745x_NPAR,
 115         BCM57508,
 116         BCM57504,
 117         BCM57502,
 118         BCM58802,
 119         BCM58804,
 120         BCM58808,
 121         NETXTREME_E_VF,
 122         NETXTREME_C_VF,
 123         NETXTREME_S_VF,
 124         NETXTREME_E_P5_VF,
 125 };
 126
 127 /* indexed by enum above */
 128 static const struct {
 129         char *name;
 130 } board_info[] = {
 131         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 132         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 133         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 134         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 135         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 136         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 137         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 138         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 139         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 140         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 141         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 142         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 143         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 144         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 145         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 146         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 147         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 148         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 149         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 150         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 151         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 152         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 153         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 154         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 155         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 156         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 157         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 158         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 159         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 160         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 161         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 162         [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
 163         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 164         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 165         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 166         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 167         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 168         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 169         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 170 };
 171
 172 static const struct pci_device_id bnxt_pci_tbl[] = {
 173         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 174         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 176         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 177         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 178         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 179         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 180         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 181         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 182         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 183         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 184         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 185         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 186         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 187         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 188         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 189         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 190         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 191         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 192         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 193         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 194         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 195         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 196         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 197         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 198         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 199         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 200         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 201         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 202         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 203         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 204         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 205         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 206         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 207         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 208         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 209         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 210         { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
 211         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 212         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 213 #ifdef CONFIG_BNXT_SRIOV
 214         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 215         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 216         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 217         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 218         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 219         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 220         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 221         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 222         { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
 223         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 224         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 225 #endif
 226         { 0 }
 227 };
 228
 229 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 230
 231 static const u16 bnxt_vf_req_snif[] = {
 232         HWRM_FUNC_CFG,
 233         HWRM_FUNC_VF_CFG,
 234         HWRM_PORT_PHY_QCFG,
 235         HWRM_CFA_L2_FILTER_ALLOC,
 236 };
 237
 238 static const u16 bnxt_async_events_arr[] = {
 239         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 240         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 241         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 242         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 243         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 244 };
 245
 246 static struct workqueue_struct *bnxt_pf_wq;
 247
 248 static bool bnxt_vf_pciid(enum board_idx idx)
 249 {
 250         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 251                 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
 252 }
 253
 254 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 255 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 256 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 257
 258 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 259                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 260
 261 #define BNXT_DB_CQ(db, idx)                                             \
 262         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 263
 264 #define BNXT_DB_NQ_P5(db, idx)                                          \
 265         writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
 266
 267 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 268         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 269
 270 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 271         writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
 272
 273 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 274 {
 275         if (bp->flags & BNXT_FLAG_CHIP_P5)
 276                 BNXT_DB_NQ_P5(db, idx);
 277         else
 278                 BNXT_DB_CQ(db, idx);
 279 }
 280
 281 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 282 {
 283         if (bp->flags & BNXT_FLAG_CHIP_P5)
 284                 BNXT_DB_NQ_ARM_P5(db, idx);
 285         else
 286                 BNXT_DB_CQ_ARM(db, idx);
 287 }
 288
 289 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 290 {
 291         if (bp->flags & BNXT_FLAG_CHIP_P5)
 292                 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
 293                        db->doorbell);
 294         else
 295                 BNXT_DB_CQ(db, idx);
 296 }
 297
 298 const u16 bnxt_lhint_arr[] = {
 299         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 300         TX_BD_FLAGS_LHINT_512_TO_1023,
 301         TX_BD_FLAGS_LHINT_1024_TO_2047,
 302         TX_BD_FLAGS_LHINT_1024_TO_2047,
 303         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 315         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 316         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 317         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 318 };
 319
 320 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 321 {
 322         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 323
 324         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 325                 return 0;
 326
 327         return md_dst->u.port_info.port_id;
 328 }
 329
 330 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 331 {
 332         struct bnxt *bp = netdev_priv(dev);
 333         struct tx_bd *txbd;
 334         struct tx_bd_ext *txbd1;
 335         struct netdev_queue *txq;
 336         int i;
 337         dma_addr_t mapping;
 338         unsigned int length, pad = 0;
 339         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 340         u16 prod, last_frag;
 341         struct pci_dev *pdev = bp->pdev;
 342         struct bnxt_tx_ring_info *txr;
 343         struct bnxt_sw_tx_bd *tx_buf;
 344
 345         i = skb_get_queue_mapping(skb);
 346         if (unlikely(i >= bp->tx_nr_rings)) {
 347                 dev_kfree_skb_any(skb);
 348                 return NETDEV_TX_OK;
 349         }
 350
 351         txq = netdev_get_tx_queue(dev, i);
 352         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 353         prod = txr->tx_prod;
 354
 355         free_size = bnxt_tx_avail(bp, txr);
 356         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 357                 netif_tx_stop_queue(txq);
 358                 return NETDEV_TX_BUSY;
 359         }
 360
 361         length = skb->len;
 362         len = skb_headlen(skb);
 363         last_frag = skb_shinfo(skb)->nr_frags;
 364
 365         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 366
 367         txbd->tx_bd_opaque = prod;
 368
 369         tx_buf = &txr->tx_buf_ring[prod];
 370         tx_buf->skb = skb;
 371         tx_buf->nr_frags = last_frag;
 372
 373         vlan_tag_flags = 0;
 374         cfa_action = bnxt_xmit_get_cfa_action(skb);
 375         if (skb_vlan_tag_present(skb)) {
 376                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 377                                  skb_vlan_tag_get(skb);
 378                 /* Currently supports 8021Q, 8021AD vlan offloads
 379                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 380                  */
 381                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 382                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 383         }
 384
 385         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 386                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 387                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 388                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 389                 void __iomem *db = txr->tx_db.doorbell;
 390                 void *pdata = tx_push_buf->data;
 391                 u64 *end;
 392                 int j, push_len;
 393
 394                 /* Set COAL_NOW to be ready quickly for the next push */
 395                 tx_push->tx_bd_len_flags_type =
 396                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 397                                         TX_BD_TYPE_LONG_TX_BD |
 398                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 399                                         TX_BD_FLAGS_COAL_NOW |
 400                                         TX_BD_FLAGS_PACKET_END |
 401                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 402
 403                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 404                         tx_push1->tx_bd_hsize_lflags =
 405                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 406                 else
 407                         tx_push1->tx_bd_hsize_lflags = 0;
 408
 409                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 410                 tx_push1->tx_bd_cfa_action =
 411                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 412
 413                 end = pdata + length;
 414                 end = PTR_ALIGN(end, 8) - 1;
 415                 *end = 0;
 416
 417                 skb_copy_from_linear_data(skb, pdata, len);
 418                 pdata += len;
 419                 for (j = 0; j < last_frag; j++) {
 420                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 421                         void *fptr;
 422
 423                         fptr = skb_frag_address_safe(frag);
 424                         if (!fptr)
 425                                 goto normal_tx;
 426
 427                         memcpy(pdata, fptr, skb_frag_size(frag));
 428                         pdata += skb_frag_size(frag);
 429                 }
 430
 431                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 432                 txbd->tx_bd_haddr = txr->data_mapping;
 433                 prod = NEXT_TX(prod);
 434                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 435                 memcpy(txbd, tx_push1, sizeof(*txbd));
 436                 prod = NEXT_TX(prod);
 437                 tx_push->doorbell =
 438                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 439                 txr->tx_prod = prod;
 440
 441                 tx_buf->is_push = 1;
 442                 netdev_tx_sent_queue(txq, skb->len);
 443                 wmb();  /* Sync is_push and byte queue before pushing data */
 444
 445                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 446                 if (push_len > 16) {
 447                         __iowrite64_copy(db, tx_push_buf, 16);
 448                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 449                                          (push_len - 16) << 1);
 450                 } else {
 451                         __iowrite64_copy(db, tx_push_buf, push_len);
 452                 }
 453
 454                 goto tx_done;
 455         }
 456
 457 normal_tx:
 458         if (length < BNXT_MIN_PKT_SIZE) {
 459                 pad = BNXT_MIN_PKT_SIZE - length;
 460                 if (skb_pad(skb, pad)) {
 461                         /* SKB already freed. */
 462                         tx_buf->skb = NULL;
 463                         return NETDEV_TX_OK;
 464                 }
 465                 length = BNXT_MIN_PKT_SIZE;
 466         }
 467
 468         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 469
 470         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 471                 dev_kfree_skb_any(skb);
 472                 tx_buf->skb = NULL;
 473                 return NETDEV_TX_OK;
 474         }
 475
 476         dma_unmap_addr_set(tx_buf, mapping, mapping);
 477         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 478                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 479
 480         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 481
 482         prod = NEXT_TX(prod);
 483         txbd1 = (struct tx_bd_ext *)
 484                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 485
 486         txbd1->tx_bd_hsize_lflags = 0;
 487         if (skb_is_gso(skb)) {
 488                 u32 hdr_len;
 489
 490                 if (skb->encapsulation)
 491                         hdr_len = skb_inner_network_offset(skb) +
 492                                 skb_inner_network_header_len(skb) +
 493                                 inner_tcp_hdrlen(skb);
 494                 else
 495                         hdr_len = skb_transport_offset(skb) +
 496                                 tcp_hdrlen(skb);
 497
 498                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 499                                         TX_BD_FLAGS_T_IPID |
 500                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 501                 length = skb_shinfo(skb)->gso_size;
 502                 txbd1->tx_bd_mss = cpu_to_le32(length);
 503                 length += hdr_len;
 504         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 505                 txbd1->tx_bd_hsize_lflags =
 506                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 507                 txbd1->tx_bd_mss = 0;
 508         }
 509
 510         length >>= 9;
 511         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 512                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 513                                      skb->len);
 514                 i = 0;
 515                 goto tx_dma_error;
 516         }
 517         flags |= bnxt_lhint_arr[length];
 518         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 519
 520         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 521         txbd1->tx_bd_cfa_action =
 522                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 523         for (i = 0; i < last_frag; i++) {
 524                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 525
 526                 prod = NEXT_TX(prod);
 527                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 528
 529                 len = skb_frag_size(frag);
 530                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 531                                            DMA_TO_DEVICE);
 532
 533                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 534                         goto tx_dma_error;
 535
 536                 tx_buf = &txr->tx_buf_ring[prod];
 537                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 538
 539                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 540
 541                 flags = len << TX_BD_LEN_SHIFT;
 542                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 543         }
 544
 545         flags &= ~TX_BD_LEN;
 546         txbd->tx_bd_len_flags_type =
 547                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 548                             TX_BD_FLAGS_PACKET_END);
 549
 550         netdev_tx_sent_queue(txq, skb->len);
 551
 552         /* Sync BD data before updating doorbell */
 553         wmb();
 554
 555         prod = NEXT_TX(prod);
 556         txr->tx_prod = prod;
 557
 558         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
 559                 bnxt_db_write(bp, &txr->tx_db, prod);
 560
 561 tx_done:
 562
 563         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 564                 if (netdev_xmit_more() && !tx_buf->is_push)
 565                         bnxt_db_write(bp, &txr->tx_db, prod);
 566
 567                 netif_tx_stop_queue(txq);
 568
 569                 /* netif_tx_stop_queue() must be done before checking
 570                  * tx index in bnxt_tx_avail() below, because in
 571                  * bnxt_tx_int(), we update tx index before checking for
 572                  * netif_tx_queue_stopped().
 573                  */
 574                 smp_mb();
 575                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 576                         netif_tx_wake_queue(txq);
 577         }
 578         return NETDEV_TX_OK;
 579
 580 tx_dma_error:
 581         last_frag = i;
 582
 583         /* start back at beginning and unmap skb */
 584         prod = txr->tx_prod;
 585         tx_buf = &txr->tx_buf_ring[prod];
 586         tx_buf->skb = NULL;
 587         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 588                          skb_headlen(skb), PCI_DMA_TODEVICE);
 589         prod = NEXT_TX(prod);
 590
 591         /* unmap remaining mapped pages */
 592         for (i = 0; i < last_frag; i++) {
 593                 prod = NEXT_TX(prod);
 594                 tx_buf = &txr->tx_buf_ring[prod];
 595                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 596                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 597                                PCI_DMA_TODEVICE);
 598         }
 599
 600         dev_kfree_skb_any(skb);
 601         return NETDEV_TX_OK;
 602 }
 603
 604 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 605 {
 606         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 607         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 608         u16 cons = txr->tx_cons;
 609         struct pci_dev *pdev = bp->pdev;
 610         int i;
 611         unsigned int tx_bytes = 0;
 612
 613         for (i = 0; i < nr_pkts; i++) {
 614                 struct bnxt_sw_tx_bd *tx_buf;
 615                 struct sk_buff *skb;
 616                 int j, last;
 617
 618                 tx_buf = &txr->tx_buf_ring[cons];
 619                 cons = NEXT_TX(cons);
 620                 skb = tx_buf->skb;
 621                 tx_buf->skb = NULL;
 622
 623                 if (tx_buf->is_push) {
 624                         tx_buf->is_push = 0;
 625                         goto next_tx_int;
 626                 }
 627
 628                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 629                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 630                 last = tx_buf->nr_frags;
 631
 632                 for (j = 0; j < last; j++) {
 633                         cons = NEXT_TX(cons);
 634                         tx_buf = &txr->tx_buf_ring[cons];
 635                         dma_unmap_page(
 636                                 &pdev->dev,
 637                                 dma_unmap_addr(tx_buf, mapping),
 638                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 639                                 PCI_DMA_TODEVICE);
 640                 }
 641
 642 next_tx_int:
 643                 cons = NEXT_TX(cons);
 644
 645                 tx_bytes += skb->len;
 646                 dev_kfree_skb_any(skb);
 647         }
 648
 649         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 650         txr->tx_cons = cons;
 651
 652         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 653          * before checking for netif_tx_queue_stopped().  Without the
 654          * memory barrier, there is a small possibility that bnxt_start_xmit()
 655          * will miss it and cause the queue to be stopped forever.
 656          */
 657         smp_mb();
 658
 659         if (unlikely(netif_tx_queue_stopped(txq)) &&
 660             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 661                 __netif_tx_lock(txq, smp_processor_id());
 662                 if (netif_tx_queue_stopped(txq) &&
 663                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 664                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 665                         netif_tx_wake_queue(txq);
 666                 __netif_tx_unlock(txq);
 667         }
 668 }
 669
 670 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 671                                          gfp_t gfp)
 672 {
 673         struct device *dev = &bp->pdev->dev;
 674         struct page *page;
 675
 676         page = alloc_page(gfp);
 677         if (!page)
 678                 return NULL;
 679
 680         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 681                                       DMA_ATTR_WEAK_ORDERING);
 682         if (dma_mapping_error(dev, *mapping)) {
 683                 __free_page(page);
 684                 return NULL;
 685         }
 686         *mapping += bp->rx_dma_offset;
 687         return page;
 688 }
 689
 690 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 691                                        gfp_t gfp)
 692 {
 693         u8 *data;
 694         struct pci_dev *pdev = bp->pdev;
 695
 696         data = kmalloc(bp->rx_buf_size, gfp);
 697         if (!data)
 698                 return NULL;
 699
 700         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 701                                         bp->rx_buf_use_size, bp->rx_dir,
 702                                         DMA_ATTR_WEAK_ORDERING);
 703
 704         if (dma_mapping_error(&pdev->dev, *mapping)) {
 705                 kfree(data);
 706                 data = NULL;
 707         }
 708         return data;
 709 }
 710
 711 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 712                        u16 prod, gfp_t gfp)
 713 {
 714         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 715         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 716         dma_addr_t mapping;
 717
 718         if (BNXT_RX_PAGE_MODE(bp)) {
 719                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 720
 721                 if (!page)
 722                         return -ENOMEM;
 723
 724                 rx_buf->data = page;
 725                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 726         } else {
 727                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 728
 729                 if (!data)
 730                         return -ENOMEM;
 731
 732                 rx_buf->data = data;
 733                 rx_buf->data_ptr = data + bp->rx_offset;
 734         }
 735         rx_buf->mapping = mapping;
 736
 737         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 738         return 0;
 739 }
 740
 741 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 742 {
 743         u16 prod = rxr->rx_prod;
 744         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 745         struct rx_bd *cons_bd, *prod_bd;
 746
 747         prod_rx_buf = &rxr->rx_buf_ring[prod];
 748         cons_rx_buf = &rxr->rx_buf_ring[cons];
 749
 750         prod_rx_buf->data = data;
 751         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 752
 753         prod_rx_buf->mapping = cons_rx_buf->mapping;
 754
 755         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 756         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 757
 758         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 759 }
 760
 761 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 762 {
 763         u16 next, max = rxr->rx_agg_bmap_size;
 764
 765         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 766         if (next >= max)
 767                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 768         return next;
 769 }
 770
 771 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 772                                      struct bnxt_rx_ring_info *rxr,
 773                                      u16 prod, gfp_t gfp)
 774 {
 775         struct rx_bd *rxbd =
 776                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 777         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 778         struct pci_dev *pdev = bp->pdev;
 779         struct page *page;
 780         dma_addr_t mapping;
 781         u16 sw_prod = rxr->rx_sw_agg_prod;
 782         unsigned int offset = 0;
 783
 784         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 785                 page = rxr->rx_page;
 786                 if (!page) {
 787                         page = alloc_page(gfp);
 788                         if (!page)
 789                                 return -ENOMEM;
 790                         rxr->rx_page = page;
 791                         rxr->rx_page_offset = 0;
 792                 }
 793                 offset = rxr->rx_page_offset;
 794                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 795                 if (rxr->rx_page_offset == PAGE_SIZE)
 796                         rxr->rx_page = NULL;
 797                 else
 798                         get_page(page);
 799         } else {
 800                 page = alloc_page(gfp);
 801                 if (!page)
 802                         return -ENOMEM;
 803         }
 804
 805         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 806                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 807                                      DMA_ATTR_WEAK_ORDERING);
 808         if (dma_mapping_error(&pdev->dev, mapping)) {
 809                 __free_page(page);
 810                 return -EIO;
 811         }
 812
 813         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 814                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 815
 816         __set_bit(sw_prod, rxr->rx_agg_bmap);
 817         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 818         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 819
 820         rx_agg_buf->page = page;
 821         rx_agg_buf->offset = offset;
 822         rx_agg_buf->mapping = mapping;
 823         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 824         rxbd->rx_bd_opaque = sw_prod;
 825         return 0;
 826 }
 827
 828 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
 829                                    u32 agg_bufs)
 830 {
 831         struct bnxt_napi *bnapi = cpr->bnapi;
 832         struct bnxt *bp = bnapi->bp;
 833         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 834         u16 prod = rxr->rx_agg_prod;
 835         u16 sw_prod = rxr->rx_sw_agg_prod;
 836         u32 i;
 837
 838         for (i = 0; i < agg_bufs; i++) {
 839                 u16 cons;
 840                 struct rx_agg_cmp *agg;
 841                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 842                 struct rx_bd *prod_bd;
 843                 struct page *page;
 844
 845                 agg = (struct rx_agg_cmp *)
 846                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 847                 cons = agg->rx_agg_cmp_opaque;
 848                 __clear_bit(cons, rxr->rx_agg_bmap);
 849
 850                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 851                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 852
 853                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 854                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 855                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 856
 857                 /* It is possible for sw_prod to be equal to cons, so
 858                  * set cons_rx_buf->page to NULL first.
 859                  */
 860                 page = cons_rx_buf->page;
 861                 cons_rx_buf->page = NULL;
 862                 prod_rx_buf->page = page;
 863                 prod_rx_buf->offset = cons_rx_buf->offset;
 864
 865                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 866
 867                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 868
 869                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 870                 prod_bd->rx_bd_opaque = sw_prod;
 871
 872                 prod = NEXT_RX_AGG(prod);
 873                 sw_prod = NEXT_RX_AGG(sw_prod);
 874                 cp_cons = NEXT_CMP(cp_cons);
 875         }
 876         rxr->rx_agg_prod = prod;
 877         rxr->rx_sw_agg_prod = sw_prod;
 878 }
 879
 880 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 881                                         struct bnxt_rx_ring_info *rxr,
 882                                         u16 cons, void *data, u8 *data_ptr,
 883                                         dma_addr_t dma_addr,
 884                                         unsigned int offset_and_len)
 885 {
 886         unsigned int payload = offset_and_len >> 16;
 887         unsigned int len = offset_and_len & 0xffff;
 888         struct skb_frag_struct *frag;
 889         struct page *page = data;
 890         u16 prod = rxr->rx_prod;
 891         struct sk_buff *skb;
 892         int off, err;
 893
 894         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 895         if (unlikely(err)) {
 896                 bnxt_reuse_rx_data(rxr, cons, data);
 897                 return NULL;
 898         }
 899         dma_addr -= bp->rx_dma_offset;
 900         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 901                              DMA_ATTR_WEAK_ORDERING);
 902
 903         if (unlikely(!payload))
 904                 payload = eth_get_headlen(bp->dev, data_ptr, len);
 905
 906         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 907         if (!skb) {
 908                 __free_page(page);
 909                 return NULL;
 910         }
 911
 912         off = (void *)data_ptr - page_address(page);
 913         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 914         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 915                payload + NET_IP_ALIGN);
 916
 917         frag = &skb_shinfo(skb)->frags[0];
 918         skb_frag_size_sub(frag, payload);
 919         frag->page_offset += payload;
 920         skb->data_len -= payload;
 921         skb->tail += payload;
 922
 923         return skb;
 924 }
 925
 926 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 927                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 928                                    void *data, u8 *data_ptr,
 929                                    dma_addr_t dma_addr,
 930                                    unsigned int offset_and_len)
 931 {
 932         u16 prod = rxr->rx_prod;
 933         struct sk_buff *skb;
 934         int err;
 935
 936         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 937         if (unlikely(err)) {
 938                 bnxt_reuse_rx_data(rxr, cons, data);
 939                 return NULL;
 940         }
 941
 942         skb = build_skb(data, 0);
 943         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 944                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 945         if (!skb) {
 946                 kfree(data);
 947                 return NULL;
 948         }
 949
 950         skb_reserve(skb, bp->rx_offset);
 951         skb_put(skb, offset_and_len & 0xffff);
 952         return skb;
 953 }
 954
 955 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
 956                                      struct bnxt_cp_ring_info *cpr,
 957                                      struct sk_buff *skb, u16 cp_cons,
 958                                      u32 agg_bufs)
 959 {
 960         struct bnxt_napi *bnapi = cpr->bnapi;
 961         struct pci_dev *pdev = bp->pdev;
 962         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 963         u16 prod = rxr->rx_agg_prod;
 964         u32 i;
 965
 966         for (i = 0; i < agg_bufs; i++) {
 967                 u16 cons, frag_len;
 968                 struct rx_agg_cmp *agg;
 969                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 970                 struct page *page;
 971                 dma_addr_t mapping;
 972
 973                 agg = (struct rx_agg_cmp *)
 974                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 975                 cons = agg->rx_agg_cmp_opaque;
 976                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 977                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 978
 979                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 980                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 981                                    cons_rx_buf->offset, frag_len);
 982                 __clear_bit(cons, rxr->rx_agg_bmap);
 983
 984                 /* It is possible for bnxt_alloc_rx_page() to allocate
 985                  * a sw_prod index that equals the cons index, so we
 986                  * need to clear the cons entry now.
 987                  */
 988                 mapping = cons_rx_buf->mapping;
 989                 page = cons_rx_buf->page;
 990                 cons_rx_buf->page = NULL;
 991
 992                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 993                         struct skb_shared_info *shinfo;
 994                         unsigned int nr_frags;
 995
 996                         shinfo = skb_shinfo(skb);
 997                         nr_frags = --shinfo->nr_frags;
 998                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 999
1000                         dev_kfree_skb(skb);
1001
1002                         cons_rx_buf->page = page;
1003
1004                         /* Update prod since possibly some pages have been
1005                          * allocated already.
1006                          */
1007                         rxr->rx_agg_prod = prod;
1008                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1009                         return NULL;
1010                 }
1011
1012                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1013                                      PCI_DMA_FROMDEVICE,
1014                                      DMA_ATTR_WEAK_ORDERING);
1015
1016                 skb->data_len += frag_len;
1017                 skb->len += frag_len;
1018                 skb->truesize += PAGE_SIZE;
1019
1020                 prod = NEXT_RX_AGG(prod);
1021                 cp_cons = NEXT_CMP(cp_cons);
1022         }
1023         rxr->rx_agg_prod = prod;
1024         return skb;
1025 }
1026
1027 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1028                                u8 agg_bufs, u32 *raw_cons)
1029 {
1030         u16 last;
1031         struct rx_agg_cmp *agg;
1032
1033         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1034         last = RING_CMP(*raw_cons);
1035         agg = (struct rx_agg_cmp *)
1036                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1037         return RX_AGG_CMP_VALID(agg, *raw_cons);
1038 }
1039
1040 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1041                                             unsigned int len,
1042                                             dma_addr_t mapping)
1043 {
1044         struct bnxt *bp = bnapi->bp;
1045         struct pci_dev *pdev = bp->pdev;
1046         struct sk_buff *skb;
1047
1048         skb = napi_alloc_skb(&bnapi->napi, len);
1049         if (!skb)
1050                 return NULL;
1051
1052         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1053                                 bp->rx_dir);
1054
1055         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1056                len + NET_IP_ALIGN);
1057
1058         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1059                                    bp->rx_dir);
1060
1061         skb_put(skb, len);
1062         return skb;
1063 }
1064
1065 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1066                            u32 *raw_cons, void *cmp)
1067 {
1068         struct rx_cmp *rxcmp = cmp;
1069         u32 tmp_raw_cons = *raw_cons;
1070         u8 cmp_type, agg_bufs = 0;
1071
1072         cmp_type = RX_CMP_TYPE(rxcmp);
1073
1074         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1075                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1076                             RX_CMP_AGG_BUFS) >>
1077                            RX_CMP_AGG_BUFS_SHIFT;
1078         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1079                 struct rx_tpa_end_cmp *tpa_end = cmp;
1080
1081                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1082                             RX_TPA_END_CMP_AGG_BUFS) >>
1083                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1084         }
1085
1086         if (agg_bufs) {
1087                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1088                         return -EBUSY;
1089         }
1090         *raw_cons = tmp_raw_cons;
1091         return 0;
1092 }
1093
1094 static void bnxt_queue_sp_work(struct bnxt *bp)
1095 {
1096         if (BNXT_PF(bp))
1097                 queue_work(bnxt_pf_wq, &bp->sp_task);
1098         else
1099                 schedule_work(&bp->sp_task);
1100 }
1101
1102 static void bnxt_cancel_sp_work(struct bnxt *bp)
1103 {
1104         if (BNXT_PF(bp))
1105                 flush_workqueue(bnxt_pf_wq);
1106         else
1107                 cancel_work_sync(&bp->sp_task);
1108 }
1109
1110 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1111 {
1112         if (!rxr->bnapi->in_reset) {
1113                 rxr->bnapi->in_reset = true;
1114                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1115                 bnxt_queue_sp_work(bp);
1116         }
1117         rxr->rx_next_cons = 0xffff;
1118 }
1119
1120 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1121                            struct rx_tpa_start_cmp *tpa_start,
1122                            struct rx_tpa_start_cmp_ext *tpa_start1)
1123 {
1124         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1125         u16 cons, prod;
1126         struct bnxt_tpa_info *tpa_info;
1127         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1128         struct rx_bd *prod_bd;
1129         dma_addr_t mapping;
1130
1131         cons = tpa_start->rx_tpa_start_cmp_opaque;
1132         prod = rxr->rx_prod;
1133         cons_rx_buf = &rxr->rx_buf_ring[cons];
1134         prod_rx_buf = &rxr->rx_buf_ring[prod];
1135         tpa_info = &rxr->rx_tpa[agg_id];
1136
1137         if (unlikely(cons != rxr->rx_next_cons)) {
1138                 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1139                             cons, rxr->rx_next_cons);
1140                 bnxt_sched_reset(bp, rxr);
1141                 return;
1142         }
1143         /* Store cfa_code in tpa_info to use in tpa_end
1144          * completion processing.
1145          */
1146         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1147         prod_rx_buf->data = tpa_info->data;
1148         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1149
1150         mapping = tpa_info->mapping;
1151         prod_rx_buf->mapping = mapping;
1152
1153         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1154
1155         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1156
1157         tpa_info->data = cons_rx_buf->data;
1158         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1159         cons_rx_buf->data = NULL;
1160         tpa_info->mapping = cons_rx_buf->mapping;
1161
1162         tpa_info->len =
1163                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1164                                 RX_TPA_START_CMP_LEN_SHIFT;
1165         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1166                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1167
1168                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1169                 tpa_info->gso_type = SKB_GSO_TCPV4;
1170                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1171                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1172                         tpa_info->gso_type = SKB_GSO_TCPV6;
1173                 tpa_info->rss_hash =
1174                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1175         } else {
1176                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1177                 tpa_info->gso_type = 0;
1178                 if (netif_msg_rx_err(bp))
1179                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1180         }
1181         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1182         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1183         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1184
1185         rxr->rx_prod = NEXT_RX(prod);
1186         cons = NEXT_RX(cons);
1187         rxr->rx_next_cons = NEXT_RX(cons);
1188         cons_rx_buf = &rxr->rx_buf_ring[cons];
1189
1190         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1191         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1192         cons_rx_buf->data = NULL;
1193 }
1194
1195 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1196                            u32 agg_bufs)
1197 {
1198         if (agg_bufs)
1199                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1200 }
1201
1202 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1203                                            int payload_off, int tcp_ts,
1204                                            struct sk_buff *skb)
1205 {
1206 #ifdef CONFIG_INET
1207         struct tcphdr *th;
1208         int len, nw_off;
1209         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1210         u32 hdr_info = tpa_info->hdr_info;
1211         bool loopback = false;
1212
1213         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1214         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1215         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1216
1217         /* If the packet is an internal loopback packet, the offsets will
1218          * have an extra 4 bytes.
1219          */
1220         if (inner_mac_off == 4) {
1221                 loopback = true;
1222         } else if (inner_mac_off > 4) {
1223                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1224                                             ETH_HLEN - 2));
1225
1226                 /* We only support inner iPv4/ipv6.  If we don't see the
1227                  * correct protocol ID, it must be a loopback packet where
1228                  * the offsets are off by 4.
1229                  */
1230                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1231                         loopback = true;
1232         }
1233         if (loopback) {
1234                 /* internal loopback packet, subtract all offsets by 4 */
1235                 inner_ip_off -= 4;
1236                 inner_mac_off -= 4;
1237                 outer_ip_off -= 4;
1238         }
1239
1240         nw_off = inner_ip_off - ETH_HLEN;
1241         skb_set_network_header(skb, nw_off);
1242         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1243                 struct ipv6hdr *iph = ipv6_hdr(skb);
1244
1245                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1246                 len = skb->len - skb_transport_offset(skb);
1247                 th = tcp_hdr(skb);
1248                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1249         } else {
1250                 struct iphdr *iph = ip_hdr(skb);
1251
1252                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1253                 len = skb->len - skb_transport_offset(skb);
1254                 th = tcp_hdr(skb);
1255                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1256         }
1257
1258         if (inner_mac_off) { /* tunnel */
1259                 struct udphdr *uh = NULL;
1260                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1261                                             ETH_HLEN - 2));
1262
1263                 if (proto == htons(ETH_P_IP)) {
1264                         struct iphdr *iph = (struct iphdr *)skb->data;
1265
1266                         if (iph->protocol == IPPROTO_UDP)
1267                                 uh = (struct udphdr *)(iph + 1);
1268                 } else {
1269                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1270
1271                         if (iph->nexthdr == IPPROTO_UDP)
1272                                 uh = (struct udphdr *)(iph + 1);
1273                 }
1274                 if (uh) {
1275                         if (uh->check)
1276                                 skb_shinfo(skb)->gso_type |=
1277                                         SKB_GSO_UDP_TUNNEL_CSUM;
1278                         else
1279                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1280                 }
1281         }
1282 #endif
1283         return skb;
1284 }
1285
1286 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1287 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1288
1289 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1290                                            int payload_off, int tcp_ts,
1291                                            struct sk_buff *skb)
1292 {
1293 #ifdef CONFIG_INET
1294         struct tcphdr *th;
1295         int len, nw_off, tcp_opt_len = 0;
1296
1297         if (tcp_ts)
1298                 tcp_opt_len = 12;
1299
1300         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1301                 struct iphdr *iph;
1302
1303                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1304                          ETH_HLEN;
1305                 skb_set_network_header(skb, nw_off);
1306                 iph = ip_hdr(skb);
1307                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1308                 len = skb->len - skb_transport_offset(skb);
1309                 th = tcp_hdr(skb);
1310                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1311         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1312                 struct ipv6hdr *iph;
1313
1314                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1315                          ETH_HLEN;
1316                 skb_set_network_header(skb, nw_off);
1317                 iph = ipv6_hdr(skb);
1318                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1319                 len = skb->len - skb_transport_offset(skb);
1320                 th = tcp_hdr(skb);
1321                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1322         } else {
1323                 dev_kfree_skb_any(skb);
1324                 return NULL;
1325         }
1326
1327         if (nw_off) { /* tunnel */
1328                 struct udphdr *uh = NULL;
1329
1330                 if (skb->protocol == htons(ETH_P_IP)) {
1331                         struct iphdr *iph = (struct iphdr *)skb->data;
1332
1333                         if (iph->protocol == IPPROTO_UDP)
1334                                 uh = (struct udphdr *)(iph + 1);
1335                 } else {
1336                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1337
1338                         if (iph->nexthdr == IPPROTO_UDP)
1339                                 uh = (struct udphdr *)(iph + 1);
1340                 }
1341                 if (uh) {
1342                         if (uh->check)
1343                                 skb_shinfo(skb)->gso_type |=
1344                                         SKB_GSO_UDP_TUNNEL_CSUM;
1345                         else
1346                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1347                 }
1348         }
1349 #endif
1350         return skb;
1351 }
1352
1353 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1354                                            struct bnxt_tpa_info *tpa_info,
1355                                            struct rx_tpa_end_cmp *tpa_end,
1356                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1357                                            struct sk_buff *skb)
1358 {
1359 #ifdef CONFIG_INET
1360         int payload_off;
1361         u16 segs;
1362
1363         segs = TPA_END_TPA_SEGS(tpa_end);
1364         if (segs == 1)
1365                 return skb;
1366
1367         NAPI_GRO_CB(skb)->count = segs;
1368         skb_shinfo(skb)->gso_size =
1369                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1370         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1371         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1372                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1373                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1374         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1375         if (likely(skb))
1376                 tcp_gro_complete(skb);
1377 #endif
1378         return skb;
1379 }
1380
1381 /* Given the cfa_code of a received packet determine which
1382  * netdev (vf-rep or PF) the packet is destined to.
1383  */
1384 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1385 {
1386         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1387
1388         /* if vf-rep dev is NULL, the must belongs to the PF */
1389         return dev ? dev : bp->dev;
1390 }
1391
1392 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1393                                            struct bnxt_cp_ring_info *cpr,
1394                                            u32 *raw_cons,
1395                                            struct rx_tpa_end_cmp *tpa_end,
1396                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1397                                            u8 *event)
1398 {
1399         struct bnxt_napi *bnapi = cpr->bnapi;
1400         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1401         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1402         u8 *data_ptr, agg_bufs;
1403         u16 cp_cons = RING_CMP(*raw_cons);
1404         unsigned int len;
1405         struct bnxt_tpa_info *tpa_info;
1406         dma_addr_t mapping;
1407         struct sk_buff *skb;
1408         void *data;
1409
1410         if (unlikely(bnapi->in_reset)) {
1411                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1412
1413                 if (rc < 0)
1414                         return ERR_PTR(-EBUSY);
1415                 return NULL;
1416         }
1417
1418         tpa_info = &rxr->rx_tpa[agg_id];
1419         data = tpa_info->data;
1420         data_ptr = tpa_info->data_ptr;
1421         prefetch(data_ptr);
1422         len = tpa_info->len;
1423         mapping = tpa_info->mapping;
1424
1425         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1426                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1427
1428         if (agg_bufs) {
1429                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1430                         return ERR_PTR(-EBUSY);
1431
1432                 *event |= BNXT_AGG_EVENT;
1433                 cp_cons = NEXT_CMP(cp_cons);
1434         }
1435
1436         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1437                 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1438                 if (agg_bufs > MAX_SKB_FRAGS)
1439                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1440                                     agg_bufs, (int)MAX_SKB_FRAGS);
1441                 return NULL;
1442         }
1443
1444         if (len <= bp->rx_copy_thresh) {
1445                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1446                 if (!skb) {
1447                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1448                         return NULL;
1449                 }
1450         } else {
1451                 u8 *new_data;
1452                 dma_addr_t new_mapping;
1453
1454                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1455                 if (!new_data) {
1456                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1457                         return NULL;
1458                 }
1459
1460                 tpa_info->data = new_data;
1461                 tpa_info->data_ptr = new_data + bp->rx_offset;
1462                 tpa_info->mapping = new_mapping;
1463
1464                 skb = build_skb(data, 0);
1465                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1466                                        bp->rx_buf_use_size, bp->rx_dir,
1467                                        DMA_ATTR_WEAK_ORDERING);
1468
1469                 if (!skb) {
1470                         kfree(data);
1471                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1472                         return NULL;
1473                 }
1474                 skb_reserve(skb, bp->rx_offset);
1475                 skb_put(skb, len);
1476         }
1477
1478         if (agg_bufs) {
1479                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1480                 if (!skb) {
1481                         /* Page reuse already handled by bnxt_rx_pages(). */
1482                         return NULL;
1483                 }
1484         }
1485
1486         skb->protocol =
1487                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1488
1489         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1490                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1491
1492         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1493             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1494                 u16 vlan_proto = tpa_info->metadata >>
1495                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1496                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1497
1498                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1499         }
1500
1501         skb_checksum_none_assert(skb);
1502         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1503                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1504                 skb->csum_level =
1505                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1506         }
1507
1508         if (TPA_END_GRO(tpa_end))
1509                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1510
1511         return skb;
1512 }
1513
1514 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1515                              struct sk_buff *skb)
1516 {
1517         if (skb->dev != bp->dev) {
1518                 /* this packet belongs to a vf-rep */
1519                 bnxt_vf_rep_rx(bp, skb);
1520                 return;
1521         }
1522         skb_record_rx_queue(skb, bnapi->index);
1523         napi_gro_receive(&bnapi->napi, skb);
1524 }
1525
1526 /* returns the following:
1527  * 1       - 1 packet successfully received
1528  * 0       - successful TPA_START, packet not completed yet
1529  * -EBUSY  - completion ring does not have all the agg buffers yet
1530  * -ENOMEM - packet aborted due to out of memory
1531  * -EIO    - packet aborted due to hw error indicated in BD
1532  */
1533 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1534                        u32 *raw_cons, u8 *event)
1535 {
1536         struct bnxt_napi *bnapi = cpr->bnapi;
1537         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1538         struct net_device *dev = bp->dev;
1539         struct rx_cmp *rxcmp;
1540         struct rx_cmp_ext *rxcmp1;
1541         u32 tmp_raw_cons = *raw_cons;
1542         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1543         struct bnxt_sw_rx_bd *rx_buf;
1544         unsigned int len;
1545         u8 *data_ptr, agg_bufs, cmp_type;
1546         dma_addr_t dma_addr;
1547         struct sk_buff *skb;
1548         void *data;
1549         int rc = 0;
1550         u32 misc;
1551
1552         rxcmp = (struct rx_cmp *)
1553                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1554
1555         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1556         cp_cons = RING_CMP(tmp_raw_cons);
1557         rxcmp1 = (struct rx_cmp_ext *)
1558                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1559
1560         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1561                 return -EBUSY;
1562
1563         cmp_type = RX_CMP_TYPE(rxcmp);
1564
1565         prod = rxr->rx_prod;
1566
1567         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1568                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1569                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1570
1571                 *event |= BNXT_RX_EVENT;
1572                 goto next_rx_no_prod_no_len;
1573
1574         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1575                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1576                                    (struct rx_tpa_end_cmp *)rxcmp,
1577                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1578
1579                 if (IS_ERR(skb))
1580                         return -EBUSY;
1581
1582                 rc = -ENOMEM;
1583                 if (likely(skb)) {
1584                         bnxt_deliver_skb(bp, bnapi, skb);
1585                         rc = 1;
1586                 }
1587                 *event |= BNXT_RX_EVENT;
1588                 goto next_rx_no_prod_no_len;
1589         }
1590
1591         cons = rxcmp->rx_cmp_opaque;
1592         if (unlikely(cons != rxr->rx_next_cons)) {
1593                 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1594
1595                 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1596                             cons, rxr->rx_next_cons);
1597                 bnxt_sched_reset(bp, rxr);
1598                 return rc1;
1599         }
1600         rx_buf = &rxr->rx_buf_ring[cons];
1601         data = rx_buf->data;
1602         data_ptr = rx_buf->data_ptr;
1603         prefetch(data_ptr);
1604
1605         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1606         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1607
1608         if (agg_bufs) {
1609                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1610                         return -EBUSY;
1611
1612                 cp_cons = NEXT_CMP(cp_cons);
1613                 *event |= BNXT_AGG_EVENT;
1614         }
1615         *event |= BNXT_RX_EVENT;
1616
1617         rx_buf->data = NULL;
1618         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1619                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1620
1621                 bnxt_reuse_rx_data(rxr, cons, data);
1622                 if (agg_bufs)
1623                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1624
1625                 rc = -EIO;
1626                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1627                         netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1628                         bnxt_sched_reset(bp, rxr);
1629                 }
1630                 goto next_rx_no_len;
1631         }
1632
1633         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1634         dma_addr = rx_buf->mapping;
1635
1636         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1637                 rc = 1;
1638                 goto next_rx;
1639         }
1640
1641         if (len <= bp->rx_copy_thresh) {
1642                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1643                 bnxt_reuse_rx_data(rxr, cons, data);
1644                 if (!skb) {
1645                         if (agg_bufs)
1646                                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1647                         rc = -ENOMEM;
1648                         goto next_rx;
1649                 }
1650         } else {
1651                 u32 payload;
1652
1653                 if (rx_buf->data_ptr == data_ptr)
1654                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1655                 else
1656                         payload = 0;
1657                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1658                                       payload | len);
1659                 if (!skb) {
1660                         rc = -ENOMEM;
1661                         goto next_rx;
1662                 }
1663         }
1664
1665         if (agg_bufs) {
1666                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1667                 if (!skb) {
1668                         rc = -ENOMEM;
1669                         goto next_rx;
1670                 }
1671         }
1672
1673         if (RX_CMP_HASH_VALID(rxcmp)) {
1674                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1675                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1676
1677                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1678                 if (hash_type != 1 && hash_type != 3)
1679                         type = PKT_HASH_TYPE_L3;
1680                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1681         }
1682
1683         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1684         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1685
1686         if ((rxcmp1->rx_cmp_flags2 &
1687              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1688             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1689                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1690                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1691                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1692
1693                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1694         }
1695
1696         skb_checksum_none_assert(skb);
1697         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1698                 if (dev->features & NETIF_F_RXCSUM) {
1699                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1700                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1701                 }
1702         } else {
1703                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1704                         if (dev->features & NETIF_F_RXCSUM)
1705                                 bnapi->cp_ring.rx_l4_csum_errors++;
1706                 }
1707         }
1708
1709         bnxt_deliver_skb(bp, bnapi, skb);
1710         rc = 1;
1711
1712 next_rx:
1713         cpr->rx_packets += 1;
1714         cpr->rx_bytes += len;
1715
1716 next_rx_no_len:
1717         rxr->rx_prod = NEXT_RX(prod);
1718         rxr->rx_next_cons = NEXT_RX(cons);
1719
1720 next_rx_no_prod_no_len:
1721         *raw_cons = tmp_raw_cons;
1722
1723         return rc;
1724 }
1725
1726 /* In netpoll mode, if we are using a combined completion ring, we need to
1727  * discard the rx packets and recycle the buffers.
1728  */
1729 static int bnxt_force_rx_discard(struct bnxt *bp,
1730                                  struct bnxt_cp_ring_info *cpr,
1731                                  u32 *raw_cons, u8 *event)
1732 {
1733         u32 tmp_raw_cons = *raw_cons;
1734         struct rx_cmp_ext *rxcmp1;
1735         struct rx_cmp *rxcmp;
1736         u16 cp_cons;
1737         u8 cmp_type;
1738
1739         cp_cons = RING_CMP(tmp_raw_cons);
1740         rxcmp = (struct rx_cmp *)
1741                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1742
1743         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1744         cp_cons = RING_CMP(tmp_raw_cons);
1745         rxcmp1 = (struct rx_cmp_ext *)
1746                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1747
1748         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1749                 return -EBUSY;
1750
1751         cmp_type = RX_CMP_TYPE(rxcmp);
1752         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1753                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1754                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1755         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1756                 struct rx_tpa_end_cmp_ext *tpa_end1;
1757
1758                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1759                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1760                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1761         }
1762         return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1763 }
1764
1765 #define BNXT_GET_EVENT_PORT(data)       \
1766         ((data) &                       \
1767          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1768
1769 static int bnxt_async_event_process(struct bnxt *bp,
1770                                     struct hwrm_async_event_cmpl *cmpl)
1771 {
1772         u16 event_id = le16_to_cpu(cmpl->event_id);
1773
1774         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1775         switch (event_id) {
1776         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1777                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1778                 struct bnxt_link_info *link_info = &bp->link_info;
1779
1780                 if (BNXT_VF(bp))
1781                         goto async_event_process_exit;
1782
1783                 /* print unsupported speed warning in forced speed mode only */
1784                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1785                     (data1 & 0x20000)) {
1786                         u16 fw_speed = link_info->force_link_speed;
1787                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1788
1789                         if (speed != SPEED_UNKNOWN)
1790                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1791                                             speed);
1792                 }
1793                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1794         }
1795         /* fall through */
1796         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1797                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1798                 break;
1799         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1800                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1801                 break;
1802         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1803                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1804                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1805
1806                 if (BNXT_VF(bp))
1807                         break;
1808
1809                 if (bp->pf.port_id != port_id)
1810                         break;
1811
1812                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1813                 break;
1814         }
1815         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1816                 if (BNXT_PF(bp))
1817                         goto async_event_process_exit;
1818                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1819                 break;
1820         default:
1821                 goto async_event_process_exit;
1822         }
1823         bnxt_queue_sp_work(bp);
1824 async_event_process_exit:
1825         bnxt_ulp_async_events(bp, cmpl);
1826         return 0;
1827 }
1828
1829 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1830 {
1831         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1832         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1833         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1834                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1835
1836         switch (cmpl_type) {
1837         case CMPL_BASE_TYPE_HWRM_DONE:
1838                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1839                 if (seq_id == bp->hwrm_intr_seq_id)
1840                         bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1841                 else
1842                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1843                 break;
1844
1845         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1846                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1847
1848                 if ((vf_id < bp->pf.first_vf_id) ||
1849                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1850                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1851                                    vf_id);
1852                         return -EINVAL;
1853                 }
1854
1855                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1856                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1857                 bnxt_queue_sp_work(bp);
1858                 break;
1859
1860         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1861                 bnxt_async_event_process(bp,
1862                                          (struct hwrm_async_event_cmpl *)txcmp);
1863
1864         default:
1865                 break;
1866         }
1867
1868         return 0;
1869 }
1870
1871 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1872 {
1873         struct bnxt_napi *bnapi = dev_instance;
1874         struct bnxt *bp = bnapi->bp;
1875         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1876         u32 cons = RING_CMP(cpr->cp_raw_cons);
1877
1878         cpr->event_ctr++;
1879         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1880         napi_schedule(&bnapi->napi);
1881         return IRQ_HANDLED;
1882 }
1883
1884 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1885 {
1886         u32 raw_cons = cpr->cp_raw_cons;
1887         u16 cons = RING_CMP(raw_cons);
1888         struct tx_cmp *txcmp;
1889
1890         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1891
1892         return TX_CMP_VALID(txcmp, raw_cons);
1893 }
1894
1895 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1896 {
1897         struct bnxt_napi *bnapi = dev_instance;
1898         struct bnxt *bp = bnapi->bp;
1899         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1900         u32 cons = RING_CMP(cpr->cp_raw_cons);
1901         u32 int_status;
1902
1903         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1904
1905         if (!bnxt_has_work(bp, cpr)) {
1906                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1907                 /* return if erroneous interrupt */
1908                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1909                         return IRQ_NONE;
1910         }
1911
1912         /* disable ring IRQ */
1913         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1914
1915         /* Return here if interrupt is shared and is disabled. */
1916         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1917                 return IRQ_HANDLED;
1918
1919         napi_schedule(&bnapi->napi);
1920         return IRQ_HANDLED;
1921 }
1922
1923 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1924                             int budget)
1925 {
1926         struct bnxt_napi *bnapi = cpr->bnapi;
1927         u32 raw_cons = cpr->cp_raw_cons;
1928         u32 cons;
1929         int tx_pkts = 0;
1930         int rx_pkts = 0;
1931         u8 event = 0;
1932         struct tx_cmp *txcmp;
1933
1934         cpr->has_more_work = 0;
1935         while (1) {
1936                 int rc;
1937
1938                 cons = RING_CMP(raw_cons);
1939                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1940
1941                 if (!TX_CMP_VALID(txcmp, raw_cons))
1942                         break;
1943
1944                 /* The valid test of the entry must be done first before
1945                  * reading any further.
1946                  */
1947                 dma_rmb();
1948                 cpr->had_work_done = 1;
1949                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1950                         tx_pkts++;
1951                         /* return full budget so NAPI will complete. */
1952                         if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1953                                 rx_pkts = budget;
1954                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1955                                 if (budget)
1956                                         cpr->has_more_work = 1;
1957                                 break;
1958                         }
1959                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1960                         if (likely(budget))
1961                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1962                         else
1963                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1964                                                            &event);
1965                         if (likely(rc >= 0))
1966                                 rx_pkts += rc;
1967                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1968                          * the NAPI budget.  Otherwise, we may potentially loop
1969                          * here forever if we consistently cannot allocate
1970                          * buffers.
1971                          */
1972                         else if (rc == -ENOMEM && budget)
1973                                 rx_pkts++;
1974                         else if (rc == -EBUSY)  /* partial completion */
1975                                 break;
1976                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1977                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1978                                     (TX_CMP_TYPE(txcmp) ==
1979                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1980                                     (TX_CMP_TYPE(txcmp) ==
1981                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1982                         bnxt_hwrm_handler(bp, txcmp);
1983                 }
1984                 raw_cons = NEXT_RAW_CMP(raw_cons);
1985
1986                 if (rx_pkts && rx_pkts == budget) {
1987                         cpr->has_more_work = 1;
1988                         break;
1989                 }
1990         }
1991
1992         if (event & BNXT_TX_EVENT) {
1993                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1994                 u16 prod = txr->tx_prod;
1995
1996                 /* Sync BD data before updating doorbell */
1997                 wmb();
1998
1999                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2000         }
2001
2002         cpr->cp_raw_cons = raw_cons;
2003         bnapi->tx_pkts += tx_pkts;
2004         bnapi->events |= event;
2005         return rx_pkts;
2006 }
2007
2008 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2009 {
2010         if (bnapi->tx_pkts) {
2011                 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2012                 bnapi->tx_pkts = 0;
2013         }
2014
2015         if (bnapi->events & BNXT_RX_EVENT) {
2016                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2017
2018                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2019                 if (bnapi->events & BNXT_AGG_EVENT)
2020                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2021         }
2022         bnapi->events = 0;
2023 }
2024
2025 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2026                           int budget)
2027 {
2028         struct bnxt_napi *bnapi = cpr->bnapi;
2029         int rx_pkts;
2030
2031         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2032
2033         /* ACK completion ring before freeing tx ring and producing new
2034          * buffers in rx/agg rings to prevent overflowing the completion
2035          * ring.
2036          */
2037         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2038
2039         __bnxt_poll_work_done(bp, bnapi);
2040         return rx_pkts;
2041 }
2042
2043 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2044 {
2045         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2046         struct bnxt *bp = bnapi->bp;
2047         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2048         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2049         struct tx_cmp *txcmp;
2050         struct rx_cmp_ext *rxcmp1;
2051         u32 cp_cons, tmp_raw_cons;
2052         u32 raw_cons = cpr->cp_raw_cons;
2053         u32 rx_pkts = 0;
2054         u8 event = 0;
2055
2056         while (1) {
2057                 int rc;
2058
2059                 cp_cons = RING_CMP(raw_cons);
2060                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2061
2062                 if (!TX_CMP_VALID(txcmp, raw_cons))
2063                         break;
2064
2065                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2066                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2067                         cp_cons = RING_CMP(tmp_raw_cons);
2068                         rxcmp1 = (struct rx_cmp_ext *)
2069                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2070
2071                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2072                                 break;
2073
2074                         /* force an error to recycle the buffer */
2075                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2076                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2077
2078                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2079                         if (likely(rc == -EIO) && budget)
2080                                 rx_pkts++;
2081                         else if (rc == -EBUSY)  /* partial completion */
2082                                 break;
2083                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2084                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2085                         bnxt_hwrm_handler(bp, txcmp);
2086                 } else {
2087                         netdev_err(bp->dev,
2088                                    "Invalid completion received on special ring\n");
2089                 }
2090                 raw_cons = NEXT_RAW_CMP(raw_cons);
2091
2092                 if (rx_pkts == budget)
2093                         break;
2094         }
2095
2096         cpr->cp_raw_cons = raw_cons;
2097         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2098         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2099
2100         if (event & BNXT_AGG_EVENT)
2101                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2102
2103         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2104                 napi_complete_done(napi, rx_pkts);
2105                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2106         }
2107         return rx_pkts;
2108 }
2109
2110 static int bnxt_poll(struct napi_struct *napi, int budget)
2111 {
2112         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2113         struct bnxt *bp = bnapi->bp;
2114         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2115         int work_done = 0;
2116
2117         while (1) {
2118                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2119
2120                 if (work_done >= budget) {
2121                         if (!budget)
2122                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2123                         break;
2124                 }
2125
2126                 if (!bnxt_has_work(bp, cpr)) {
2127                         if (napi_complete_done(napi, work_done))
2128                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2129                         break;
2130                 }
2131         }
2132         if (bp->flags & BNXT_FLAG_DIM) {
2133                 struct net_dim_sample dim_sample;
2134
2135                 net_dim_sample(cpr->event_ctr,
2136                                cpr->rx_packets,
2137                                cpr->rx_bytes,
2138                                &dim_sample);
2139                 net_dim(&cpr->dim, dim_sample);
2140         }
2141         return work_done;
2142 }
2143
2144 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2145 {
2146         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2147         int i, work_done = 0;
2148
2149         for (i = 0; i < 2; i++) {
2150                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2151
2152                 if (cpr2) {
2153                         work_done += __bnxt_poll_work(bp, cpr2,
2154                                                       budget - work_done);
2155                         cpr->has_more_work |= cpr2->has_more_work;
2156                 }
2157         }
2158         return work_done;
2159 }
2160
2161 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2162                                  u64 dbr_type, bool all)
2163 {
2164         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2165         int i;
2166
2167         for (i = 0; i < 2; i++) {
2168                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2169                 struct bnxt_db_info *db;
2170
2171                 if (cpr2 && (all || cpr2->had_work_done)) {
2172                         db = &cpr2->cp_db;
2173                         writeq(db->db_key64 | dbr_type |
2174                                RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2175                         cpr2->had_work_done = 0;
2176                 }
2177         }
2178         __bnxt_poll_work_done(bp, bnapi);
2179 }
2180
2181 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2182 {
2183         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2184         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2185         u32 raw_cons = cpr->cp_raw_cons;
2186         struct bnxt *bp = bnapi->bp;
2187         struct nqe_cn *nqcmp;
2188         int work_done = 0;
2189         u32 cons;
2190
2191         if (cpr->has_more_work) {
2192                 cpr->has_more_work = 0;
2193                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2194                 if (cpr->has_more_work) {
2195                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2196                         return work_done;
2197                 }
2198                 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2199                 if (napi_complete_done(napi, work_done))
2200                         BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2201                 return work_done;
2202         }
2203         while (1) {
2204                 cons = RING_CMP(raw_cons);
2205                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2206
2207                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2208                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2209                                              false);
2210                         cpr->cp_raw_cons = raw_cons;
2211                         if (napi_complete_done(napi, work_done))
2212                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2213                                                   cpr->cp_raw_cons);
2214                         return work_done;
2215                 }
2216
2217                 /* The valid test of the entry must be done first before
2218                  * reading any further.
2219                  */
2220                 dma_rmb();
2221
2222                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2223                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2224                         struct bnxt_cp_ring_info *cpr2;
2225
2226                         cpr2 = cpr->cp_ring_arr[idx];
2227                         work_done += __bnxt_poll_work(bp, cpr2,
2228                                                       budget - work_done);
2229                         cpr->has_more_work = cpr2->has_more_work;
2230                 } else {
2231                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2232                 }
2233                 raw_cons = NEXT_RAW_CMP(raw_cons);
2234                 if (cpr->has_more_work)
2235                         break;
2236         }
2237         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2238         cpr->cp_raw_cons = raw_cons;
2239         return work_done;
2240 }
2241
2242 static void bnxt_free_tx_skbs(struct bnxt *bp)
2243 {
2244         int i, max_idx;
2245         struct pci_dev *pdev = bp->pdev;
2246
2247         if (!bp->tx_ring)
2248                 return;
2249
2250         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2251         for (i = 0; i < bp->tx_nr_rings; i++) {
2252                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2253                 int j;
2254
2255                 for (j = 0; j < max_idx;) {
2256                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2257                         struct sk_buff *skb = tx_buf->skb;
2258                         int k, last;
2259
2260                         if (!skb) {
2261                                 j++;
2262                                 continue;
2263                         }
2264
2265                         tx_buf->skb = NULL;
2266
2267                         if (tx_buf->is_push) {
2268                                 dev_kfree_skb(skb);
2269                                 j += 2;
2270                                 continue;
2271                         }
2272
2273                         dma_unmap_single(&pdev->dev,
2274                                          dma_unmap_addr(tx_buf, mapping),
2275                                          skb_headlen(skb),
2276                                          PCI_DMA_TODEVICE);
2277
2278                         last = tx_buf->nr_frags;
2279                         j += 2;
2280                         for (k = 0; k < last; k++, j++) {
2281                                 int ring_idx = j & bp->tx_ring_mask;
2282                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2283
2284                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2285                                 dma_unmap_page(
2286                                         &pdev->dev,
2287                                         dma_unmap_addr(tx_buf, mapping),
2288                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2289                         }
2290                         dev_kfree_skb(skb);
2291                 }
2292                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2293         }
2294 }
2295
2296 static void bnxt_free_rx_skbs(struct bnxt *bp)
2297 {
2298         int i, max_idx, max_agg_idx;
2299         struct pci_dev *pdev = bp->pdev;
2300
2301         if (!bp->rx_ring)
2302                 return;
2303
2304         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2305         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2306         for (i = 0; i < bp->rx_nr_rings; i++) {
2307                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2308                 int j;
2309
2310                 if (rxr->rx_tpa) {
2311                         for (j = 0; j < MAX_TPA; j++) {
2312                                 struct bnxt_tpa_info *tpa_info =
2313                                                         &rxr->rx_tpa[j];
2314                                 u8 *data = tpa_info->data;
2315
2316                                 if (!data)
2317                                         continue;
2318
2319                                 dma_unmap_single_attrs(&pdev->dev,
2320                                                        tpa_info->mapping,
2321                                                        bp->rx_buf_use_size,
2322                                                        bp->rx_dir,
2323                                                        DMA_ATTR_WEAK_ORDERING);
2324
2325                                 tpa_info->data = NULL;
2326
2327                                 kfree(data);
2328                         }
2329                 }
2330
2331                 for (j = 0; j < max_idx; j++) {
2332                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2333                         dma_addr_t mapping = rx_buf->mapping;
2334                         void *data = rx_buf->data;
2335
2336                         if (!data)
2337                                 continue;
2338
2339                         rx_buf->data = NULL;
2340
2341                         if (BNXT_RX_PAGE_MODE(bp)) {
2342                                 mapping -= bp->rx_dma_offset;
2343                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2344                                                      PAGE_SIZE, bp->rx_dir,
2345                                                      DMA_ATTR_WEAK_ORDERING);
2346                                 __free_page(data);
2347                         } else {
2348                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2349                                                        bp->rx_buf_use_size,
2350                                                        bp->rx_dir,
2351                                                        DMA_ATTR_WEAK_ORDERING);
2352                                 kfree(data);
2353                         }
2354                 }
2355
2356                 for (j = 0; j < max_agg_idx; j++) {
2357                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2358                                 &rxr->rx_agg_ring[j];
2359                         struct page *page = rx_agg_buf->page;
2360
2361                         if (!page)
2362                                 continue;
2363
2364                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2365                                              BNXT_RX_PAGE_SIZE,
2366                                              PCI_DMA_FROMDEVICE,
2367                                              DMA_ATTR_WEAK_ORDERING);
2368
2369                         rx_agg_buf->page = NULL;
2370                         __clear_bit(j, rxr->rx_agg_bmap);
2371
2372                         __free_page(page);
2373                 }
2374                 if (rxr->rx_page) {
2375                         __free_page(rxr->rx_page);
2376                         rxr->rx_page = NULL;
2377                 }
2378         }
2379 }
2380
2381 static void bnxt_free_skbs(struct bnxt *bp)
2382 {
2383         bnxt_free_tx_skbs(bp);
2384         bnxt_free_rx_skbs(bp);
2385 }
2386
2387 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2388 {
2389         struct pci_dev *pdev = bp->pdev;
2390         int i;
2391
2392         for (i = 0; i < rmem->nr_pages; i++) {
2393                 if (!rmem->pg_arr[i])
2394                         continue;
2395
2396                 dma_free_coherent(&pdev->dev, rmem->page_size,
2397                                   rmem->pg_arr[i], rmem->dma_arr[i]);
2398
2399                 rmem->pg_arr[i] = NULL;
2400         }
2401         if (rmem->pg_tbl) {
2402                 size_t pg_tbl_size = rmem->nr_pages * 8;
2403
2404                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2405                         pg_tbl_size = rmem->page_size;
2406                 dma_free_coherent(&pdev->dev, pg_tbl_size,
2407                                   rmem->pg_tbl, rmem->pg_tbl_map);
2408                 rmem->pg_tbl = NULL;
2409         }
2410         if (rmem->vmem_size && *rmem->vmem) {
2411                 vfree(*rmem->vmem);
2412                 *rmem->vmem = NULL;
2413         }
2414 }
2415
2416 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2417 {
2418         struct pci_dev *pdev = bp->pdev;
2419         u64 valid_bit = 0;
2420         int i;
2421
2422         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2423                 valid_bit = PTU_PTE_VALID;
2424         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2425                 size_t pg_tbl_size = rmem->nr_pages * 8;
2426
2427                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2428                         pg_tbl_size = rmem->page_size;
2429                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2430                                                   &rmem->pg_tbl_map,
2431                                                   GFP_KERNEL);
2432                 if (!rmem->pg_tbl)
2433                         return -ENOMEM;
2434         }
2435
2436         for (i = 0; i < rmem->nr_pages; i++) {
2437                 u64 extra_bits = valid_bit;
2438
2439                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2440                                                      rmem->page_size,
2441                                                      &rmem->dma_arr[i],
2442                                                      GFP_KERNEL);
2443                 if (!rmem->pg_arr[i])
2444                         return -ENOMEM;
2445
2446                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2447                         if (i == rmem->nr_pages - 2 &&
2448                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2449                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2450                         else if (i == rmem->nr_pages - 1 &&
2451                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2452                                 extra_bits |= PTU_PTE_LAST;
2453                         rmem->pg_tbl[i] =
2454                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2455                 }
2456         }
2457
2458         if (rmem->vmem_size) {
2459                 *rmem->vmem = vzalloc(rmem->vmem_size);
2460                 if (!(*rmem->vmem))
2461                         return -ENOMEM;
2462         }
2463         return 0;
2464 }
2465
2466 static void bnxt_free_rx_rings(struct bnxt *bp)
2467 {
2468         int i;
2469
2470         if (!bp->rx_ring)
2471                 return;
2472
2473         for (i = 0; i < bp->rx_nr_rings; i++) {
2474                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2475                 struct bnxt_ring_struct *ring;
2476
2477                 if (rxr->xdp_prog)
2478                         bpf_prog_put(rxr->xdp_prog);
2479
2480                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2481                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2482
2483                 kfree(rxr->rx_tpa);
2484                 rxr->rx_tpa = NULL;
2485
2486                 kfree(rxr->rx_agg_bmap);
2487                 rxr->rx_agg_bmap = NULL;
2488
2489                 ring = &rxr->rx_ring_struct;
2490                 bnxt_free_ring(bp, &ring->ring_mem);
2491
2492                 ring = &rxr->rx_agg_ring_struct;
2493                 bnxt_free_ring(bp, &ring->ring_mem);
2494         }
2495 }
2496
2497 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2498 {
2499         int i, rc, agg_rings = 0, tpa_rings = 0;
2500
2501         if (!bp->rx_ring)
2502                 return -ENOMEM;
2503
2504         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2505                 agg_rings = 1;
2506
2507         if (bp->flags & BNXT_FLAG_TPA)
2508                 tpa_rings = 1;
2509
2510         for (i = 0; i < bp->rx_nr_rings; i++) {
2511                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2512                 struct bnxt_ring_struct *ring;
2513
2514                 ring = &rxr->rx_ring_struct;
2515
2516                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2517                 if (rc < 0)
2518                         return rc;
2519
2520                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2521                 if (rc)
2522                         return rc;
2523
2524                 ring->grp_idx = i;
2525                 if (agg_rings) {
2526                         u16 mem_size;
2527
2528                         ring = &rxr->rx_agg_ring_struct;
2529                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2530                         if (rc)
2531                                 return rc;
2532
2533                         ring->grp_idx = i;
2534                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2535                         mem_size = rxr->rx_agg_bmap_size / 8;
2536                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2537                         if (!rxr->rx_agg_bmap)
2538                                 return -ENOMEM;
2539
2540                         if (tpa_rings) {
2541                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2542                                                 sizeof(struct bnxt_tpa_info),
2543                                                 GFP_KERNEL);
2544                                 if (!rxr->rx_tpa)
2545                                         return -ENOMEM;
2546                         }
2547                 }
2548         }
2549         return 0;
2550 }
2551
2552 static void bnxt_free_tx_rings(struct bnxt *bp)
2553 {
2554         int i;
2555         struct pci_dev *pdev = bp->pdev;
2556
2557         if (!bp->tx_ring)
2558                 return;
2559
2560         for (i = 0; i < bp->tx_nr_rings; i++) {
2561                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2562                 struct bnxt_ring_struct *ring;
2563
2564                 if (txr->tx_push) {
2565                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2566                                           txr->tx_push, txr->tx_push_mapping);
2567                         txr->tx_push = NULL;
2568                 }
2569
2570                 ring = &txr->tx_ring_struct;
2571
2572                 bnxt_free_ring(bp, &ring->ring_mem);
2573         }
2574 }
2575
2576 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2577 {
2578         int i, j, rc;
2579         struct pci_dev *pdev = bp->pdev;
2580
2581         bp->tx_push_size = 0;
2582         if (bp->tx_push_thresh) {
2583                 int push_size;
2584
2585                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2586                                         bp->tx_push_thresh);
2587
2588                 if (push_size > 256) {
2589                         push_size = 0;
2590                         bp->tx_push_thresh = 0;
2591                 }
2592
2593                 bp->tx_push_size = push_size;
2594         }
2595
2596         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2597                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2598                 struct bnxt_ring_struct *ring;
2599                 u8 qidx;
2600
2601                 ring = &txr->tx_ring_struct;
2602
2603                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2604                 if (rc)
2605                         return rc;
2606
2607                 ring->grp_idx = txr->bnapi->index;
2608                 if (bp->tx_push_size) {
2609                         dma_addr_t mapping;
2610
2611                         /* One pre-allocated DMA buffer to backup
2612                          * TX push operation
2613                          */
2614                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2615                                                 bp->tx_push_size,
2616                                                 &txr->tx_push_mapping,
2617                                                 GFP_KERNEL);
2618
2619                         if (!txr->tx_push)
2620                                 return -ENOMEM;
2621
2622                         mapping = txr->tx_push_mapping +
2623                                 sizeof(struct tx_push_bd);
2624                         txr->data_mapping = cpu_to_le64(mapping);
2625
2626                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2627                 }
2628                 qidx = bp->tc_to_qidx[j];
2629                 ring->queue_id = bp->q_info[qidx].queue_id;
2630                 if (i < bp->tx_nr_rings_xdp)
2631                         continue;
2632                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2633                         j++;
2634         }
2635         return 0;
2636 }
2637
2638 static void bnxt_free_cp_rings(struct bnxt *bp)
2639 {
2640         int i;
2641
2642         if (!bp->bnapi)
2643                 return;
2644
2645         for (i = 0; i < bp->cp_nr_rings; i++) {
2646                 struct bnxt_napi *bnapi = bp->bnapi[i];
2647                 struct bnxt_cp_ring_info *cpr;
2648                 struct bnxt_ring_struct *ring;
2649                 int j;
2650
2651                 if (!bnapi)
2652                         continue;
2653
2654                 cpr = &bnapi->cp_ring;
2655                 ring = &cpr->cp_ring_struct;
2656
2657                 bnxt_free_ring(bp, &ring->ring_mem);
2658
2659                 for (j = 0; j < 2; j++) {
2660                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2661
2662                         if (cpr2) {
2663                                 ring = &cpr2->cp_ring_struct;
2664                                 bnxt_free_ring(bp, &ring->ring_mem);
2665                                 kfree(cpr2);
2666                                 cpr->cp_ring_arr[j] = NULL;
2667                         }
2668                 }
2669         }
2670 }
2671
2672 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2673 {
2674         struct bnxt_ring_mem_info *rmem;
2675         struct bnxt_ring_struct *ring;
2676         struct bnxt_cp_ring_info *cpr;
2677         int rc;
2678
2679         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2680         if (!cpr)
2681                 return NULL;
2682
2683         ring = &cpr->cp_ring_struct;
2684         rmem = &ring->ring_mem;
2685         rmem->nr_pages = bp->cp_nr_pages;
2686         rmem->page_size = HW_CMPD_RING_SIZE;
2687         rmem->pg_arr = (void **)cpr->cp_desc_ring;
2688         rmem->dma_arr = cpr->cp_desc_mapping;
2689         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2690         rc = bnxt_alloc_ring(bp, rmem);
2691         if (rc) {
2692                 bnxt_free_ring(bp, rmem);
2693                 kfree(cpr);
2694                 cpr = NULL;
2695         }
2696         return cpr;
2697 }
2698
2699 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2700 {
2701         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2702         int i, rc, ulp_base_vec, ulp_msix;
2703
2704         ulp_msix = bnxt_get_ulp_msix_num(bp);
2705         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2706         for (i = 0; i < bp->cp_nr_rings; i++) {
2707                 struct bnxt_napi *bnapi = bp->bnapi[i];
2708                 struct bnxt_cp_ring_info *cpr;
2709                 struct bnxt_ring_struct *ring;
2710
2711                 if (!bnapi)
2712                         continue;
2713
2714                 cpr = &bnapi->cp_ring;
2715                 cpr->bnapi = bnapi;
2716                 ring = &cpr->cp_ring_struct;
2717
2718                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2719                 if (rc)
2720                         return rc;
2721
2722                 if (ulp_msix && i >= ulp_base_vec)
2723                         ring->map_idx = i + ulp_msix;
2724                 else
2725                         ring->map_idx = i;
2726
2727                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2728                         continue;
2729
2730                 if (i < bp->rx_nr_rings) {
2731                         struct bnxt_cp_ring_info *cpr2 =
2732                                 bnxt_alloc_cp_sub_ring(bp);
2733
2734                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2735                         if (!cpr2)
2736                                 return -ENOMEM;
2737                         cpr2->bnapi = bnapi;
2738                 }
2739                 if ((sh && i < bp->tx_nr_rings) ||
2740                     (!sh && i >= bp->rx_nr_rings)) {
2741                         struct bnxt_cp_ring_info *cpr2 =
2742                                 bnxt_alloc_cp_sub_ring(bp);
2743
2744                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2745                         if (!cpr2)
2746                                 return -ENOMEM;
2747                         cpr2->bnapi = bnapi;
2748                 }
2749         }
2750         return 0;
2751 }
2752
2753 static void bnxt_init_ring_struct(struct bnxt *bp)
2754 {
2755         int i;
2756
2757         for (i = 0; i < bp->cp_nr_rings; i++) {
2758                 struct bnxt_napi *bnapi = bp->bnapi[i];
2759                 struct bnxt_ring_mem_info *rmem;
2760                 struct bnxt_cp_ring_info *cpr;
2761                 struct bnxt_rx_ring_info *rxr;
2762                 struct bnxt_tx_ring_info *txr;
2763                 struct bnxt_ring_struct *ring;
2764
2765                 if (!bnapi)
2766                         continue;
2767
2768                 cpr = &bnapi->cp_ring;
2769                 ring = &cpr->cp_ring_struct;
2770                 rmem = &ring->ring_mem;
2771                 rmem->nr_pages = bp->cp_nr_pages;
2772                 rmem->page_size = HW_CMPD_RING_SIZE;
2773                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2774                 rmem->dma_arr = cpr->cp_desc_mapping;
2775                 rmem->vmem_size = 0;
2776
2777                 rxr = bnapi->rx_ring;
2778                 if (!rxr)
2779                         goto skip_rx;
2780
2781                 ring = &rxr->rx_ring_struct;
2782                 rmem = &ring->ring_mem;
2783                 rmem->nr_pages = bp->rx_nr_pages;
2784                 rmem->page_size = HW_RXBD_RING_SIZE;
2785                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2786                 rmem->dma_arr = rxr->rx_desc_mapping;
2787                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2788                 rmem->vmem = (void **)&rxr->rx_buf_ring;
2789
2790                 ring = &rxr->rx_agg_ring_struct;
2791                 rmem = &ring->ring_mem;
2792                 rmem->nr_pages = bp->rx_agg_nr_pages;
2793                 rmem->page_size = HW_RXBD_RING_SIZE;
2794                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2795                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2796                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2797                 rmem->vmem = (void **)&rxr->rx_agg_ring;
2798
2799 skip_rx:
2800                 txr = bnapi->tx_ring;
2801                 if (!txr)
2802                         continue;
2803
2804                 ring = &txr->tx_ring_struct;
2805                 rmem = &ring->ring_mem;
2806                 rmem->nr_pages = bp->tx_nr_pages;
2807                 rmem->page_size = HW_RXBD_RING_SIZE;
2808                 rmem->pg_arr = (void **)txr->tx_desc_ring;
2809                 rmem->dma_arr = txr->tx_desc_mapping;
2810                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2811                 rmem->vmem = (void **)&txr->tx_buf_ring;
2812         }
2813 }
2814
2815 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2816 {
2817         int i;
2818         u32 prod;
2819         struct rx_bd **rx_buf_ring;
2820
2821         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2822         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2823                 int j;
2824                 struct rx_bd *rxbd;
2825
2826                 rxbd = rx_buf_ring[i];
2827                 if (!rxbd)
2828                         continue;
2829
2830                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2831                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2832                         rxbd->rx_bd_opaque = prod;
2833                 }
2834         }
2835 }
2836
2837 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2838 {
2839         struct net_device *dev = bp->dev;
2840         struct bnxt_rx_ring_info *rxr;
2841         struct bnxt_ring_struct *ring;
2842         u32 prod, type;
2843         int i;
2844
2845         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2846                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2847
2848         if (NET_IP_ALIGN == 2)
2849                 type |= RX_BD_FLAGS_SOP;
2850
2851         rxr = &bp->rx_ring[ring_nr];
2852         ring = &rxr->rx_ring_struct;
2853         bnxt_init_rxbd_pages(ring, type);
2854
2855         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2856                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2857                 if (IS_ERR(rxr->xdp_prog)) {
2858                         int rc = PTR_ERR(rxr->xdp_prog);
2859
2860                         rxr->xdp_prog = NULL;
2861                         return rc;
2862                 }
2863         }
2864         prod = rxr->rx_prod;
2865         for (i = 0; i < bp->rx_ring_size; i++) {
2866                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2867                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2868                                     ring_nr, i, bp->rx_ring_size);
2869                         break;
2870                 }
2871                 prod = NEXT_RX(prod);
2872         }
2873         rxr->rx_prod = prod;
2874         ring->fw_ring_id = INVALID_HW_RING_ID;
2875
2876         ring = &rxr->rx_agg_ring_struct;
2877         ring->fw_ring_id = INVALID_HW_RING_ID;
2878
2879         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2880                 return 0;
2881
2882         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2883                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2884
2885         bnxt_init_rxbd_pages(ring, type);
2886
2887         prod = rxr->rx_agg_prod;
2888         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2889                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2890                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2891                                     ring_nr, i, bp->rx_ring_size);
2892                         break;
2893                 }
2894                 prod = NEXT_RX_AGG(prod);
2895         }
2896         rxr->rx_agg_prod = prod;
2897
2898         if (bp->flags & BNXT_FLAG_TPA) {
2899                 if (rxr->rx_tpa) {
2900                         u8 *data;
2901                         dma_addr_t mapping;
2902
2903                         for (i = 0; i < MAX_TPA; i++) {
2904                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2905                                                             GFP_KERNEL);
2906                                 if (!data)
2907                                         return -ENOMEM;
2908
2909                                 rxr->rx_tpa[i].data = data;
2910                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2911                                 rxr->rx_tpa[i].mapping = mapping;
2912                         }
2913                 } else {
2914                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2915                         return -ENOMEM;
2916                 }
2917         }
2918
2919         return 0;
2920 }
2921
2922 static void bnxt_init_cp_rings(struct bnxt *bp)
2923 {
2924         int i, j;
2925
2926         for (i = 0; i < bp->cp_nr_rings; i++) {
2927                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2928                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2929
2930                 ring->fw_ring_id = INVALID_HW_RING_ID;
2931                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2932                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2933                 for (j = 0; j < 2; j++) {
2934                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2935
2936                         if (!cpr2)
2937                                 continue;
2938
2939                         ring = &cpr2->cp_ring_struct;
2940                         ring->fw_ring_id = INVALID_HW_RING_ID;
2941                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2942                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2943                 }
2944         }
2945 }
2946
2947 static int bnxt_init_rx_rings(struct bnxt *bp)
2948 {
2949         int i, rc = 0;
2950
2951         if (BNXT_RX_PAGE_MODE(bp)) {
2952                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2953                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2954         } else {
2955                 bp->rx_offset = BNXT_RX_OFFSET;
2956                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2957         }
2958
2959         for (i = 0; i < bp->rx_nr_rings; i++) {
2960                 rc = bnxt_init_one_rx_ring(bp, i);
2961                 if (rc)
2962                         break;
2963         }
2964
2965         return rc;
2966 }
2967
2968 static int bnxt_init_tx_rings(struct bnxt *bp)
2969 {
2970         u16 i;
2971
2972         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2973                                    MAX_SKB_FRAGS + 1);
2974
2975         for (i = 0; i < bp->tx_nr_rings; i++) {
2976                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2977                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2978
2979                 ring->fw_ring_id = INVALID_HW_RING_ID;
2980         }
2981
2982         return 0;
2983 }
2984
2985 static void bnxt_free_ring_grps(struct bnxt *bp)
2986 {
2987         kfree(bp->grp_info);
2988         bp->grp_info = NULL;
2989 }
2990
2991 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2992 {
2993         int i;
2994
2995         if (irq_re_init) {
2996                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2997                                        sizeof(struct bnxt_ring_grp_info),
2998                                        GFP_KERNEL);
2999                 if (!bp->grp_info)
3000                         return -ENOMEM;
3001         }
3002         for (i = 0; i < bp->cp_nr_rings; i++) {
3003                 if (irq_re_init)
3004                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3005                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3006                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3007                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3008                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3009         }
3010         return 0;
3011 }
3012
3013 static void bnxt_free_vnics(struct bnxt *bp)
3014 {
3015         kfree(bp->vnic_info);
3016         bp->vnic_info = NULL;
3017         bp->nr_vnics = 0;
3018 }
3019
3020 static int bnxt_alloc_vnics(struct bnxt *bp)
3021 {
3022         int num_vnics = 1;
3023
3024 #ifdef CONFIG_RFS_ACCEL
3025         if (bp->flags & BNXT_FLAG_RFS)
3026                 num_vnics += bp->rx_nr_rings;
3027 #endif
3028
3029         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3030                 num_vnics++;
3031
3032         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3033                                 GFP_KERNEL);
3034         if (!bp->vnic_info)
3035                 return -ENOMEM;
3036
3037         bp->nr_vnics = num_vnics;
3038         return 0;
3039 }
3040
3041 static void bnxt_init_vnics(struct bnxt *bp)
3042 {
3043         int i;
3044
3045         for (i = 0; i < bp->nr_vnics; i++) {
3046                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3047                 int j;
3048
3049                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3050                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3051                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3052
3053                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3054
3055                 if (bp->vnic_info[i].rss_hash_key) {
3056                         if (i == 0)
3057                                 prandom_bytes(vnic->rss_hash_key,
3058                                               HW_HASH_KEY_SIZE);
3059                         else
3060                                 memcpy(vnic->rss_hash_key,
3061                                        bp->vnic_info[0].rss_hash_key,
3062                                        HW_HASH_KEY_SIZE);
3063                 }
3064         }
3065 }
3066
3067 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3068 {
3069         int pages;
3070
3071         pages = ring_size / desc_per_pg;
3072
3073         if (!pages)
3074                 return 1;
3075
3076         pages++;
3077
3078         while (pages & (pages - 1))
3079                 pages++;
3080
3081         return pages;
3082 }
3083
3084 void bnxt_set_tpa_flags(struct bnxt *bp)
3085 {
3086         bp->flags &= ~BNXT_FLAG_TPA;
3087         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3088                 return;
3089         if (bp->dev->features & NETIF_F_LRO)
3090                 bp->flags |= BNXT_FLAG_LRO;
3091         else if (bp->dev->features & NETIF_F_GRO_HW)
3092                 bp->flags |= BNXT_FLAG_GRO;
3093 }
3094
3095 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3096  * be set on entry.
3097  */
3098 void bnxt_set_ring_params(struct bnxt *bp)
3099 {
3100         u32 ring_size, rx_size, rx_space;
3101         u32 agg_factor = 0, agg_ring_size = 0;
3102
3103         /* 8 for CRC and VLAN */
3104         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3105
3106         rx_space = rx_size + NET_SKB_PAD +
3107                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3108
3109         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3110         ring_size = bp->rx_ring_size;
3111         bp->rx_agg_ring_size = 0;
3112         bp->rx_agg_nr_pages = 0;
3113
3114         if (bp->flags & BNXT_FLAG_TPA)
3115                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3116
3117         bp->flags &= ~BNXT_FLAG_JUMBO;
3118         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3119                 u32 jumbo_factor;
3120
3121                 bp->flags |= BNXT_FLAG_JUMBO;
3122                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3123                 if (jumbo_factor > agg_factor)
3124                         agg_factor = jumbo_factor;
3125         }
3126         agg_ring_size = ring_size * agg_factor;
3127
3128         if (agg_ring_size) {
3129                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3130                                                         RX_DESC_CNT);
3131                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3132                         u32 tmp = agg_ring_size;
3133
3134                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3135                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3136                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3137                                     tmp, agg_ring_size);
3138                 }
3139                 bp->rx_agg_ring_size = agg_ring_size;
3140                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3141                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3142                 rx_space = rx_size + NET_SKB_PAD +
3143                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3144         }
3145
3146         bp->rx_buf_use_size = rx_size;
3147         bp->rx_buf_size = rx_space;
3148
3149         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3150         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3151
3152         ring_size = bp->tx_ring_size;
3153         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3154         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3155
3156         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3157         bp->cp_ring_size = ring_size;
3158
3159         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3160         if (bp->cp_nr_pages > MAX_CP_PAGES) {
3161                 bp->cp_nr_pages = MAX_CP_PAGES;
3162                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3163                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3164                             ring_size, bp->cp_ring_size);
3165         }
3166         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3167         bp->cp_ring_mask = bp->cp_bit - 1;
3168 }
3169
3170 /* Changing allocation mode of RX rings.
3171  * TODO: Update when extending xdp_rxq_info to support allocation modes.
3172  */
3173 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3174 {
3175         if (page_mode) {
3176                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3177                         return -EOPNOTSUPP;
3178                 bp->dev->max_mtu =
3179                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3180                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3181                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3182                 bp->rx_dir = DMA_BIDIRECTIONAL;
3183                 bp->rx_skb_func = bnxt_rx_page_skb;
3184                 /* Disable LRO or GRO_HW */
3185                 netdev_update_features(bp->dev);
3186         } else {
3187                 bp->dev->max_mtu = bp->max_mtu;
3188                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3189                 bp->rx_dir = DMA_FROM_DEVICE;
3190                 bp->rx_skb_func = bnxt_rx_skb;
3191         }
3192         return 0;
3193 }
3194
3195 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3196 {
3197         int i;
3198         struct bnxt_vnic_info *vnic;
3199         struct pci_dev *pdev = bp->pdev;
3200
3201         if (!bp->vnic_info)
3202                 return;
3203
3204         for (i = 0; i < bp->nr_vnics; i++) {
3205                 vnic = &bp->vnic_info[i];
3206
3207                 kfree(vnic->fw_grp_ids);
3208                 vnic->fw_grp_ids = NULL;
3209
3210                 kfree(vnic->uc_list);
3211                 vnic->uc_list = NULL;
3212
3213                 if (vnic->mc_list) {
3214                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3215                                           vnic->mc_list, vnic->mc_list_mapping);
3216                         vnic->mc_list = NULL;
3217                 }
3218
3219                 if (vnic->rss_table) {
3220                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
3221                                           vnic->rss_table,
3222                                           vnic->rss_table_dma_addr);
3223                         vnic->rss_table = NULL;
3224                 }
3225
3226                 vnic->rss_hash_key = NULL;
3227                 vnic->flags = 0;
3228         }
3229 }
3230
3231 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3232 {
3233         int i, rc = 0, size;
3234         struct bnxt_vnic_info *vnic;
3235         struct pci_dev *pdev = bp->pdev;
3236         int max_rings;
3237
3238         for (i = 0; i < bp->nr_vnics; i++) {
3239                 vnic = &bp->vnic_info[i];
3240
3241                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3242                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3243
3244                         if (mem_size > 0) {
3245                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3246                                 if (!vnic->uc_list) {
3247                                         rc = -ENOMEM;
3248                                         goto out;
3249                                 }
3250                         }
3251                 }
3252
3253                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3254                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3255                         vnic->mc_list =
3256                                 dma_alloc_coherent(&pdev->dev,
3257                                                    vnic->mc_list_size,
3258                                                    &vnic->mc_list_mapping,
3259                                                    GFP_KERNEL);
3260                         if (!vnic->mc_list) {
3261                                 rc = -ENOMEM;
3262                                 goto out;
3263                         }
3264                 }
3265
3266                 if (bp->flags & BNXT_FLAG_CHIP_P5)
3267                         goto vnic_skip_grps;
3268
3269                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3270                         max_rings = bp->rx_nr_rings;
3271                 else
3272                         max_rings = 1;
3273
3274                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3275                 if (!vnic->fw_grp_ids) {
3276                         rc = -ENOMEM;
3277                         goto out;
3278                 }
3279 vnic_skip_grps:
3280                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3281                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3282                         continue;
3283
3284                 /* Allocate rss table and hash key */
3285                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3286                                                      &vnic->rss_table_dma_addr,
3287                                                      GFP_KERNEL);
3288                 if (!vnic->rss_table) {
3289                         rc = -ENOMEM;
3290                         goto out;
3291                 }
3292
3293                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3294
3295                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3296                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3297         }
3298         return 0;
3299
3300 out:
3301         return rc;
3302 }
3303
3304 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3305 {
3306         struct pci_dev *pdev = bp->pdev;
3307
3308         if (bp->hwrm_cmd_resp_addr) {
3309                 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3310                                   bp->hwrm_cmd_resp_dma_addr);
3311                 bp->hwrm_cmd_resp_addr = NULL;
3312         }
3313
3314         if (bp->hwrm_cmd_kong_resp_addr) {
3315                 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3316                                   bp->hwrm_cmd_kong_resp_addr,
3317                                   bp->hwrm_cmd_kong_resp_dma_addr);
3318                 bp->hwrm_cmd_kong_resp_addr = NULL;
3319         }
3320 }
3321
3322 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3323 {
3324         struct pci_dev *pdev = bp->pdev;
3325
3326         bp->hwrm_cmd_kong_resp_addr =
3327                 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3328                                    &bp->hwrm_cmd_kong_resp_dma_addr,
3329                                    GFP_KERNEL);
3330         if (!bp->hwrm_cmd_kong_resp_addr)
3331                 return -ENOMEM;
3332
3333         return 0;
3334 }
3335
3336 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3337 {
3338         struct pci_dev *pdev = bp->pdev;
3339
3340         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3341                                                    &bp->hwrm_cmd_resp_dma_addr,
3342                                                    GFP_KERNEL);
3343         if (!bp->hwrm_cmd_resp_addr)
3344                 return -ENOMEM;
3345
3346         return 0;
3347 }
3348
3349 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3350 {
3351         if (bp->hwrm_short_cmd_req_addr) {
3352                 struct pci_dev *pdev = bp->pdev;
3353
3354                 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3355                                   bp->hwrm_short_cmd_req_addr,
3356                                   bp->hwrm_short_cmd_req_dma_addr);
3357                 bp->hwrm_short_cmd_req_addr = NULL;
3358         }
3359 }
3360
3361 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3362 {
3363         struct pci_dev *pdev = bp->pdev;
3364
3365         bp->hwrm_short_cmd_req_addr =
3366                 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3367                                    &bp->hwrm_short_cmd_req_dma_addr,
3368                                    GFP_KERNEL);
3369         if (!bp->hwrm_short_cmd_req_addr)
3370                 return -ENOMEM;
3371
3372         return 0;
3373 }
3374
3375 static void bnxt_free_port_stats(struct bnxt *bp)
3376 {
3377         struct pci_dev *pdev = bp->pdev;
3378
3379         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3380         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3381
3382         if (bp->hw_rx_port_stats) {
3383                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3384                                   bp->hw_rx_port_stats,
3385                                   bp->hw_rx_port_stats_map);
3386                 bp->hw_rx_port_stats = NULL;
3387         }
3388
3389         if (bp->hw_tx_port_stats_ext) {
3390                 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3391                                   bp->hw_tx_port_stats_ext,
3392                                   bp->hw_tx_port_stats_ext_map);
3393                 bp->hw_tx_port_stats_ext = NULL;
3394         }
3395
3396         if (bp->hw_rx_port_stats_ext) {
3397                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3398                                   bp->hw_rx_port_stats_ext,
3399                                   bp->hw_rx_port_stats_ext_map);
3400                 bp->hw_rx_port_stats_ext = NULL;
3401         }
3402
3403         if (bp->hw_pcie_stats) {
3404                 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3405                                   bp->hw_pcie_stats, bp->hw_pcie_stats_map);
3406                 bp->hw_pcie_stats = NULL;
3407         }
3408 }
3409
3410 static void bnxt_free_ring_stats(struct bnxt *bp)
3411 {
3412         struct pci_dev *pdev = bp->pdev;
3413         int size, i;
3414
3415         if (!bp->bnapi)
3416                 return;
3417
3418         size = sizeof(struct ctx_hw_stats);
3419
3420         for (i = 0; i < bp->cp_nr_rings; i++) {
3421                 struct bnxt_napi *bnapi = bp->bnapi[i];
3422                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3423
3424                 if (cpr->hw_stats) {
3425                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3426                                           cpr->hw_stats_map);
3427                         cpr->hw_stats = NULL;
3428                 }
3429         }
3430 }
3431
3432 static int bnxt_alloc_stats(struct bnxt *bp)
3433 {
3434         u32 size, i;
3435         struct pci_dev *pdev = bp->pdev;
3436
3437         size = sizeof(struct ctx_hw_stats);
3438
3439         for (i = 0; i < bp->cp_nr_rings; i++) {
3440                 struct bnxt_napi *bnapi = bp->bnapi[i];
3441                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3442
3443                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3444                                                    &cpr->hw_stats_map,
3445                                                    GFP_KERNEL);
3446                 if (!cpr->hw_stats)
3447                         return -ENOMEM;
3448
3449                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3450         }
3451
3452         if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3453                 return 0;
3454
3455         if (bp->hw_rx_port_stats)
3456                 goto alloc_ext_stats;
3457
3458         bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3459                                  sizeof(struct tx_port_stats) + 1024;
3460
3461         bp->hw_rx_port_stats =
3462                 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3463                                    &bp->hw_rx_port_stats_map,
3464                                    GFP_KERNEL);
3465         if (!bp->hw_rx_port_stats)
3466                 return -ENOMEM;
3467
3468         bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512;
3469         bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3470                                    sizeof(struct rx_port_stats) + 512;
3471         bp->flags |= BNXT_FLAG_PORT_STATS;
3472
3473 alloc_ext_stats:
3474         /* Display extended statistics only if FW supports it */
3475         if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3476                 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3477                         return 0;
3478
3479         if (bp->hw_rx_port_stats_ext)
3480                 goto alloc_tx_ext_stats;
3481
3482         bp->hw_rx_port_stats_ext =
3483                 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3484                                    &bp->hw_rx_port_stats_ext_map, GFP_KERNEL);
3485         if (!bp->hw_rx_port_stats_ext)
3486                 return 0;
3487
3488 alloc_tx_ext_stats:
3489         if (bp->hw_tx_port_stats_ext)
3490                 goto alloc_pcie_stats;
3491
3492         if (bp->hwrm_spec_code >= 0x10902 ||
3493             (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3494                 bp->hw_tx_port_stats_ext =
3495                         dma_alloc_coherent(&pdev->dev,
3496                                            sizeof(struct tx_port_stats_ext),
3497                                            &bp->hw_tx_port_stats_ext_map,
3498                                            GFP_KERNEL);
3499         }
3500         bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3501
3502 alloc_pcie_stats:
3503         if (bp->hw_pcie_stats ||
3504             !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
3505                 return 0;
3506
3507         bp->hw_pcie_stats =
3508                 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3509                                    &bp->hw_pcie_stats_map, GFP_KERNEL);
3510         if (!bp->hw_pcie_stats)
3511                 return 0;
3512
3513         bp->flags |= BNXT_FLAG_PCIE_STATS;
3514         return 0;
3515 }
3516
3517 static void bnxt_clear_ring_indices(struct bnxt *bp)
3518 {
3519         int i;
3520
3521         if (!bp->bnapi)
3522                 return;
3523
3524         for (i = 0; i < bp->cp_nr_rings; i++) {
3525                 struct bnxt_napi *bnapi = bp->bnapi[i];
3526                 struct bnxt_cp_ring_info *cpr;
3527                 struct bnxt_rx_ring_info *rxr;
3528                 struct bnxt_tx_ring_info *txr;
3529
3530                 if (!bnapi)
3531                         continue;
3532
3533                 cpr = &bnapi->cp_ring;
3534                 cpr->cp_raw_cons = 0;
3535
3536                 txr = bnapi->tx_ring;
3537                 if (txr) {
3538                         txr->tx_prod = 0;
3539                         txr->tx_cons = 0;
3540                 }
3541
3542                 rxr = bnapi->rx_ring;
3543                 if (rxr) {
3544                         rxr->rx_prod = 0;
3545                         rxr->rx_agg_prod = 0;
3546                         rxr->rx_sw_agg_prod = 0;
3547                         rxr->rx_next_cons = 0;
3548                 }
3549         }
3550 }
3551
3552 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3553 {
3554 #ifdef CONFIG_RFS_ACCEL
3555         int i;
3556
3557         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3558          * safe to delete the hash table.
3559          */
3560         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3561                 struct hlist_head *head;
3562                 struct hlist_node *tmp;
3563                 struct bnxt_ntuple_filter *fltr;
3564
3565                 head = &bp->ntp_fltr_hash_tbl[i];
3566                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3567                         hlist_del(&fltr->hash);
3568                         kfree(fltr);
3569                 }
3570         }
3571         if (irq_reinit) {
3572                 kfree(bp->ntp_fltr_bmap);
3573                 bp->ntp_fltr_bmap = NULL;
3574         }
3575         bp->ntp_fltr_count = 0;
3576 #endif
3577 }
3578
3579 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3580 {
3581 #ifdef CONFIG_RFS_ACCEL
3582         int i, rc = 0;
3583
3584         if (!(bp->flags & BNXT_FLAG_RFS))
3585                 return 0;
3586
3587         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3588                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3589
3590         bp->ntp_fltr_count = 0;
3591         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3592                                     sizeof(long),
3593                                     GFP_KERNEL);
3594
3595         if (!bp->ntp_fltr_bmap)
3596                 rc = -ENOMEM;
3597
3598         return rc;
3599 #else
3600         return 0;
3601 #endif
3602 }
3603
3604 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3605 {
3606         bnxt_free_vnic_attributes(bp);
3607         bnxt_free_tx_rings(bp);
3608         bnxt_free_rx_rings(bp);
3609         bnxt_free_cp_rings(bp);
3610         bnxt_free_ntp_fltrs(bp, irq_re_init);
3611         if (irq_re_init) {
3612                 bnxt_free_ring_stats(bp);
3613                 bnxt_free_ring_grps(bp);
3614                 bnxt_free_vnics(bp);
3615                 kfree(bp->tx_ring_map);
3616                 bp->tx_ring_map = NULL;
3617                 kfree(bp->tx_ring);
3618                 bp->tx_ring = NULL;
3619                 kfree(bp->rx_ring);
3620                 bp->rx_ring = NULL;
3621                 kfree(bp->bnapi);
3622                 bp->bnapi = NULL;
3623         } else {
3624                 bnxt_clear_ring_indices(bp);
3625         }
3626 }
3627
3628 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3629 {
3630         int i, j, rc, size, arr_size;
3631         void *bnapi;
3632
3633         if (irq_re_init) {
3634                 /* Allocate bnapi mem pointer array and mem block for
3635                  * all queues
3636                  */
3637                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3638                                 bp->cp_nr_rings);
3639                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3640                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3641                 if (!bnapi)
3642                         return -ENOMEM;
3643
3644                 bp->bnapi = bnapi;
3645                 bnapi += arr_size;
3646                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3647                         bp->bnapi[i] = bnapi;
3648                         bp->bnapi[i]->index = i;
3649                         bp->bnapi[i]->bp = bp;
3650                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3651                                 struct bnxt_cp_ring_info *cpr =
3652                                         &bp->bnapi[i]->cp_ring;
3653
3654                                 cpr->cp_ring_struct.ring_mem.flags =
3655                                         BNXT_RMEM_RING_PTE_FLAG;
3656                         }
3657                 }
3658
3659                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3660                                       sizeof(struct bnxt_rx_ring_info),
3661                                       GFP_KERNEL);
3662                 if (!bp->rx_ring)
3663                         return -ENOMEM;
3664
3665                 for (i = 0; i < bp->rx_nr_rings; i++) {
3666                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3667
3668                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3669                                 rxr->rx_ring_struct.ring_mem.flags =
3670                                         BNXT_RMEM_RING_PTE_FLAG;
3671                                 rxr->rx_agg_ring_struct.ring_mem.flags =
3672                                         BNXT_RMEM_RING_PTE_FLAG;
3673                         }
3674                         rxr->bnapi = bp->bnapi[i];
3675                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3676                 }
3677
3678                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3679                                       sizeof(struct bnxt_tx_ring_info),
3680                                       GFP_KERNEL);
3681                 if (!bp->tx_ring)
3682                         return -ENOMEM;
3683
3684                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3685                                           GFP_KERNEL);
3686
3687                 if (!bp->tx_ring_map)
3688                         return -ENOMEM;
3689
3690                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3691                         j = 0;
3692                 else
3693                         j = bp->rx_nr_rings;
3694
3695                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3696                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3697
3698                         if (bp->flags & BNXT_FLAG_CHIP_P5)
3699                                 txr->tx_ring_struct.ring_mem.flags =
3700                                         BNXT_RMEM_RING_PTE_FLAG;
3701                         txr->bnapi = bp->bnapi[j];
3702                         bp->bnapi[j]->tx_ring = txr;
3703                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3704                         if (i >= bp->tx_nr_rings_xdp) {
3705                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
3706                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3707                         } else {
3708                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3709                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3710                         }
3711                 }
3712
3713                 rc = bnxt_alloc_stats(bp);
3714                 if (rc)
3715                         goto alloc_mem_err;
3716
3717                 rc = bnxt_alloc_ntp_fltrs(bp);
3718                 if (rc)
3719                         goto alloc_mem_err;
3720
3721                 rc = bnxt_alloc_vnics(bp);
3722                 if (rc)
3723                         goto alloc_mem_err;
3724         }
3725
3726         bnxt_init_ring_struct(bp);
3727
3728         rc = bnxt_alloc_rx_rings(bp);
3729         if (rc)
3730                 goto alloc_mem_err;
3731
3732         rc = bnxt_alloc_tx_rings(bp);
3733         if (rc)
3734                 goto alloc_mem_err;
3735
3736         rc = bnxt_alloc_cp_rings(bp);
3737         if (rc)
3738                 goto alloc_mem_err;
3739
3740         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3741                                   BNXT_VNIC_UCAST_FLAG;
3742         rc = bnxt_alloc_vnic_attributes(bp);
3743         if (rc)
3744                 goto alloc_mem_err;
3745         return 0;
3746
3747 alloc_mem_err:
3748         bnxt_free_mem(bp, true);
3749         return rc;
3750 }
3751
3752 static void bnxt_disable_int(struct bnxt *bp)
3753 {
3754         int i;
3755
3756         if (!bp->bnapi)
3757                 return;
3758
3759         for (i = 0; i < bp->cp_nr_rings; i++) {
3760                 struct bnxt_napi *bnapi = bp->bnapi[i];
3761                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3762                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3763
3764                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3765                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3766         }
3767 }
3768
3769 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3770 {
3771         struct bnxt_napi *bnapi = bp->bnapi[n];
3772         struct bnxt_cp_ring_info *cpr;
3773
3774         cpr = &bnapi->cp_ring;
3775         return cpr->cp_ring_struct.map_idx;
3776 }
3777
3778 static void bnxt_disable_int_sync(struct bnxt *bp)
3779 {
3780         int i;
3781
3782         atomic_inc(&bp->intr_sem);
3783
3784         bnxt_disable_int(bp);
3785         for (i = 0; i < bp->cp_nr_rings; i++) {
3786                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3787
3788                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3789         }
3790 }
3791
3792 static void bnxt_enable_int(struct bnxt *bp)
3793 {
3794         int i;
3795
3796         atomic_set(&bp->intr_sem, 0);
3797         for (i = 0; i < bp->cp_nr_rings; i++) {
3798                 struct bnxt_napi *bnapi = bp->bnapi[i];
3799                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3800
3801                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3802         }
3803 }
3804
3805 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3806                             u16 cmpl_ring, u16 target_id)
3807 {
3808         struct input *req = request;
3809
3810         req->req_type = cpu_to_le16(req_type);
3811         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3812         req->target_id = cpu_to_le16(target_id);
3813         if (bnxt_kong_hwrm_message(bp, req))
3814                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3815         else
3816                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3817 }
3818
3819 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3820                                  int timeout, bool silent)
3821 {
3822         int i, intr_process, rc, tmo_count;
3823         struct input *req = msg;
3824         u32 *data = msg;
3825         __le32 *resp_len;
3826         u8 *valid;
3827         u16 cp_ring_id, len = 0;
3828         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3829         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3830         struct hwrm_short_input short_input = {0};
3831         u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3832         u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3833         u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3834         u16 dst = BNXT_HWRM_CHNL_CHIMP;
3835
3836         if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3837                 if (msg_len > bp->hwrm_max_ext_req_len ||
3838                     !bp->hwrm_short_cmd_req_addr)
3839                         return -EINVAL;
3840         }
3841
3842         if (bnxt_hwrm_kong_chnl(bp, req)) {
3843                 dst = BNXT_HWRM_CHNL_KONG;
3844                 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3845                 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3846                 resp = bp->hwrm_cmd_kong_resp_addr;
3847                 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3848         }
3849
3850         memset(resp, 0, PAGE_SIZE);
3851         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3852         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3853
3854         req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3855         /* currently supports only one outstanding message */
3856         if (intr_process)
3857                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3858
3859         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3860             msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3861                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3862                 u16 max_msg_len;
3863
3864                 /* Set boundary for maximum extended request length for short
3865                  * cmd format. If passed up from device use the max supported
3866                  * internal req length.
3867                  */
3868                 max_msg_len = bp->hwrm_max_ext_req_len;
3869
3870                 memcpy(short_cmd_req, req, msg_len);
3871                 if (msg_len < max_msg_len)
3872                         memset(short_cmd_req + msg_len, 0,
3873                                max_msg_len - msg_len);
3874
3875                 short_input.req_type = req->req_type;
3876                 short_input.signature =
3877                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3878                 short_input.size = cpu_to_le16(msg_len);
3879                 short_input.req_addr =
3880                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3881
3882                 data = (u32 *)&short_input;
3883                 msg_len = sizeof(short_input);
3884
3885                 /* Sync memory write before updating doorbell */
3886                 wmb();
3887
3888                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3889         }
3890
3891         /* Write request msg to hwrm channel */
3892         __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3893
3894         for (i = msg_len; i < max_req_len; i += 4)
3895                 writel(0, bp->bar0 + bar_offset + i);
3896
3897         /* Ring channel doorbell */
3898         writel(1, bp->bar0 + doorbell_offset);
3899
3900         if (!timeout)
3901                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3902         /* convert timeout to usec */
3903         timeout *= 1000;
3904
3905         i = 0;
3906         /* Short timeout for the first few iterations:
3907          * number of loops = number of loops for short timeout +
3908          * number of loops for standard timeout.
3909          */
3910         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3911         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3912         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3913         resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3914
3915         if (intr_process) {
3916                 u16 seq_id = bp->hwrm_intr_seq_id;
3917
3918                 /* Wait until hwrm response cmpl interrupt is processed */
3919                 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3920                        i++ < tmo_count) {
3921                         /* on first few passes, just barely sleep */
3922                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3923                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3924                                              HWRM_SHORT_MAX_TIMEOUT);
3925                         else
3926                                 usleep_range(HWRM_MIN_TIMEOUT,
3927                                              HWRM_MAX_TIMEOUT);
3928                 }
3929
3930                 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3931                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3932                                    le16_to_cpu(req->req_type));
3933                         return -1;
3934                 }
3935                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3936                       HWRM_RESP_LEN_SFT;
3937                 valid = resp_addr + len - 1;
3938         } else {
3939                 int j;
3940
3941                 /* Check if response len is updated */
3942                 for (i = 0; i < tmo_count; i++) {
3943                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3944                               HWRM_RESP_LEN_SFT;
3945                         if (len)
3946                                 break;
3947                         /* on first few passes, just barely sleep */
3948                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3949                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3950                                              HWRM_SHORT_MAX_TIMEOUT);
3951                         else
3952                                 usleep_range(HWRM_MIN_TIMEOUT,
3953                                              HWRM_MAX_TIMEOUT);
3954                 }
3955
3956                 if (i >= tmo_count) {
3957                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3958                                    HWRM_TOTAL_TIMEOUT(i),
3959                                    le16_to_cpu(req->req_type),
3960                                    le16_to_cpu(req->seq_id), len);
3961                         return -1;
3962                 }
3963
3964                 /* Last byte of resp contains valid bit */
3965                 valid = resp_addr + len - 1;
3966                 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3967                         /* make sure we read from updated DMA memory */
3968                         dma_rmb();
3969                         if (*valid)
3970                                 break;
3971                         usleep_range(1, 5);
3972                 }
3973
3974                 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3975                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3976                                    HWRM_TOTAL_TIMEOUT(i),
3977                                    le16_to_cpu(req->req_type),
3978                                    le16_to_cpu(req->seq_id), len, *valid);
3979                         return -1;
3980                 }
3981         }
3982
3983         /* Zero valid bit for compatibility.  Valid bit in an older spec
3984          * may become a new field in a newer spec.  We must make sure that
3985          * a new field not implemented by old spec will read zero.
3986          */
3987         *valid = 0;
3988         rc = le16_to_cpu(resp->error_code);
3989         if (rc && !silent)
3990                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3991                            le16_to_cpu(resp->req_type),
3992                            le16_to_cpu(resp->seq_id), rc);
3993         return rc;
3994 }
3995
3996 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3997 {
3998         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3999 }
4000
4001 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4002                               int timeout)
4003 {
4004         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4005 }
4006
4007 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4008 {
4009         int rc;
4010
4011         mutex_lock(&bp->hwrm_cmd_lock);
4012         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4013         mutex_unlock(&bp->hwrm_cmd_lock);
4014         return rc;
4015 }
4016
4017 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4018                              int timeout)
4019 {
4020         int rc;
4021
4022         mutex_lock(&bp->hwrm_cmd_lock);
4023         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4024         mutex_unlock(&bp->hwrm_cmd_lock);
4025         return rc;
4026 }
4027
4028 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4029                                      int bmap_size)
4030 {
4031         struct hwrm_func_drv_rgtr_input req = {0};
4032         DECLARE_BITMAP(async_events_bmap, 256);
4033         u32 *events = (u32 *)async_events_bmap;
4034         int i;
4035
4036         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4037
4038         req.enables =
4039                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4040
4041         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4042         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4043                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4044
4045         if (bmap && bmap_size) {
4046                 for (i = 0; i < bmap_size; i++) {
4047                         if (test_bit(i, bmap))
4048                                 __set_bit(i, async_events_bmap);
4049                 }
4050         }
4051
4052         for (i = 0; i < 8; i++)
4053                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4054
4055         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4056 }
4057
4058 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4059 {
4060         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4061         struct hwrm_func_drv_rgtr_input req = {0};
4062         int rc;
4063
4064         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4065
4066         req.enables =
4067                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4068                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
4069
4070         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4071         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4072         req.ver_maj_8b = DRV_VER_MAJ;
4073         req.ver_min_8b = DRV_VER_MIN;
4074         req.ver_upd_8b = DRV_VER_UPD;
4075         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4076         req.ver_min = cpu_to_le16(DRV_VER_MIN);
4077         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4078
4079         if (BNXT_PF(bp)) {
4080                 u32 data[8];
4081                 int i;
4082
4083                 memset(data, 0, sizeof(data));
4084                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4085                         u16 cmd = bnxt_vf_req_snif[i];
4086                         unsigned int bit, idx;
4087
4088                         idx = cmd / 32;
4089                         bit = cmd % 32;
4090                         data[idx] |= 1 << bit;
4091                 }
4092
4093                 for (i = 0; i < 8; i++)
4094                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4095
4096                 req.enables |=
4097                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4098         }
4099
4100         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4101                 req.flags |= cpu_to_le32(
4102                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4103
4104         mutex_lock(&bp->hwrm_cmd_lock);
4105         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4106         if (rc)
4107                 rc = -EIO;
4108         else if (resp->flags &
4109                  cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4110                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4111         mutex_unlock(&bp->hwrm_cmd_lock);
4112         return rc;
4113 }
4114
4115 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4116 {
4117         struct hwrm_func_drv_unrgtr_input req = {0};
4118
4119         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4120         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4121 }
4122
4123 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4124 {
4125         u32 rc = 0;
4126         struct hwrm_tunnel_dst_port_free_input req = {0};
4127
4128         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4129         req.tunnel_type = tunnel_type;
4130
4131         switch (tunnel_type) {
4132         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4133                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4134                 break;
4135         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4136                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4137                 break;
4138         default:
4139                 break;
4140         }
4141
4142         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4143         if (rc)
4144                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4145                            rc);
4146         return rc;
4147 }
4148
4149 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4150                                            u8 tunnel_type)
4151 {
4152         u32 rc = 0;
4153         struct hwrm_tunnel_dst_port_alloc_input req = {0};
4154         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4155
4156         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4157
4158         req.tunnel_type = tunnel_type;
4159         req.tunnel_dst_port_val = port;
4160
4161         mutex_lock(&bp->hwrm_cmd_lock);
4162         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4163         if (rc) {
4164                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4165                            rc);
4166                 goto err_out;
4167         }
4168
4169         switch (tunnel_type) {
4170         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4171                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4172                 break;
4173         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4174                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4175                 break;
4176         default:
4177                 break;
4178         }
4179
4180 err_out:
4181         mutex_unlock(&bp->hwrm_cmd_lock);
4182         return rc;
4183 }
4184
4185 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4186 {
4187         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4188         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4189
4190         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4191         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4192
4193         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4194         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4195         req.mask = cpu_to_le32(vnic->rx_mask);
4196         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4197 }
4198
4199 #ifdef CONFIG_RFS_ACCEL
4200 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4201                                             struct bnxt_ntuple_filter *fltr)
4202 {
4203         struct hwrm_cfa_ntuple_filter_free_input req = {0};
4204
4205         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4206         req.ntuple_filter_id = fltr->filter_id;
4207         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4208 }
4209
4210 #define BNXT_NTP_FLTR_FLAGS                                     \
4211         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4212          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4213          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4214          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4215          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4216          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4217          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4218          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4219          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4220          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4221          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4222          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4223          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4224          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4225
4226 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4227                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4228
4229 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4230                                              struct bnxt_ntuple_filter *fltr)
4231 {
4232         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4233         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4234         struct flow_keys *keys = &fltr->fkeys;
4235         struct bnxt_vnic_info *vnic;
4236         u32 dst_ena = 0;
4237         int rc = 0;
4238
4239         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4240         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4241
4242         if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) {
4243                 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX;
4244                 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq);
4245                 vnic = &bp->vnic_info[0];
4246         } else {
4247                 vnic = &bp->vnic_info[fltr->rxq + 1];
4248         }
4249         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4250         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena);
4251
4252         req.ethertype = htons(ETH_P_IP);
4253         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4254         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4255         req.ip_protocol = keys->basic.ip_proto;
4256
4257         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4258                 int i;
4259
4260                 req.ethertype = htons(ETH_P_IPV6);
4261                 req.ip_addr_type =
4262                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4263                 *(struct in6_addr *)&req.src_ipaddr[0] =
4264                         keys->addrs.v6addrs.src;
4265                 *(struct in6_addr *)&req.dst_ipaddr[0] =
4266                         keys->addrs.v6addrs.dst;
4267                 for (i = 0; i < 4; i++) {
4268                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4269                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4270                 }
4271         } else {
4272                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4273                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4274                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4275                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4276         }
4277         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4278                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4279                 req.tunnel_type =
4280                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4281         }
4282
4283         req.src_port = keys->ports.src;
4284         req.src_port_mask = cpu_to_be16(0xffff);
4285         req.dst_port = keys->ports.dst;
4286         req.dst_port_mask = cpu_to_be16(0xffff);
4287
4288         mutex_lock(&bp->hwrm_cmd_lock);
4289         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4290         if (!rc) {
4291                 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4292                 fltr->filter_id = resp->ntuple_filter_id;
4293         }
4294         mutex_unlock(&bp->hwrm_cmd_lock);
4295         return rc;
4296 }
4297 #endif
4298
4299 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4300                                      u8 *mac_addr)
4301 {
4302         u32 rc = 0;
4303         struct hwrm_cfa_l2_filter_alloc_input req = {0};
4304         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4305
4306         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4307         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4308         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4309                 req.flags |=
4310                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4311         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4312         req.enables =
4313                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4314                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4315                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4316         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4317         req.l2_addr_mask[0] = 0xff;
4318         req.l2_addr_mask[1] = 0xff;
4319         req.l2_addr_mask[2] = 0xff;
4320         req.l2_addr_mask[3] = 0xff;
4321         req.l2_addr_mask[4] = 0xff;
4322         req.l2_addr_mask[5] = 0xff;
4323
4324         mutex_lock(&bp->hwrm_cmd_lock);
4325         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4326         if (!rc)
4327                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4328                                                         resp->l2_filter_id;
4329         mutex_unlock(&bp->hwrm_cmd_lock);
4330         return rc;
4331 }
4332
4333 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4334 {
4335         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4336         int rc = 0;
4337
4338         /* Any associated ntuple filters will also be cleared by firmware. */
4339         mutex_lock(&bp->hwrm_cmd_lock);
4340         for (i = 0; i < num_of_vnics; i++) {
4341                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4342
4343                 for (j = 0; j < vnic->uc_filter_count; j++) {
4344                         struct hwrm_cfa_l2_filter_free_input req = {0};
4345
4346                         bnxt_hwrm_cmd_hdr_init(bp, &req,
4347                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
4348
4349                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
4350
4351                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4352                                                 HWRM_CMD_TIMEOUT);
4353                 }
4354                 vnic->uc_filter_count = 0;
4355         }
4356         mutex_unlock(&bp->hwrm_cmd_lock);
4357
4358         return rc;
4359 }
4360
4361 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4362 {
4363         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4364         struct hwrm_vnic_tpa_cfg_input req = {0};
4365
4366         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4367                 return 0;
4368
4369         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4370
4371         if (tpa_flags) {
4372                 u16 mss = bp->dev->mtu - 40;
4373                 u32 nsegs, n, segs = 0, flags;
4374
4375                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4376                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4377                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4378                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4379                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4380                 if (tpa_flags & BNXT_FLAG_GRO)
4381                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4382
4383                 req.flags = cpu_to_le32(flags);
4384
4385                 req.enables =
4386                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4387                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4388                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4389
4390                 /* Number of segs are log2 units, and first packet is not
4391                  * included as part of this units.
4392                  */
4393                 if (mss <= BNXT_RX_PAGE_SIZE) {
4394                         n = BNXT_RX_PAGE_SIZE / mss;
4395                         nsegs = (MAX_SKB_FRAGS - 1) * n;
4396                 } else {
4397                         n = mss / BNXT_RX_PAGE_SIZE;
4398                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
4399                                 n++;
4400                         nsegs = (MAX_SKB_FRAGS - n) / n;
4401                 }
4402
4403                 segs = ilog2(nsegs);
4404                 req.max_agg_segs = cpu_to_le16(segs);
4405                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4406
4407                 req.min_agg_len = cpu_to_le32(512);
4408         }
4409         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4410
4411         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4412 }
4413
4414 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4415 {
4416         struct bnxt_ring_grp_info *grp_info;
4417
4418         grp_info = &bp->grp_info[ring->grp_idx];
4419         return grp_info->cp_fw_ring_id;
4420 }
4421
4422 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4423 {
4424         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4425                 struct bnxt_napi *bnapi = rxr->bnapi;
4426                 struct bnxt_cp_ring_info *cpr;
4427
4428                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4429                 return cpr->cp_ring_struct.fw_ring_id;
4430         } else {
4431                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4432         }
4433 }
4434
4435 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4436 {
4437         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4438                 struct bnxt_napi *bnapi = txr->bnapi;
4439                 struct bnxt_cp_ring_info *cpr;
4440
4441                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4442                 return cpr->cp_ring_struct.fw_ring_id;
4443         } else {
4444                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4445         }
4446 }
4447
4448 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4449 {
4450         u32 i, j, max_rings;
4451         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4452         struct hwrm_vnic_rss_cfg_input req = {0};
4453
4454         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4455             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4456                 return 0;
4457
4458         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4459         if (set_rss) {
4460                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4461                 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4462                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4463                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4464                                 max_rings = bp->rx_nr_rings - 1;
4465                         else
4466                                 max_rings = bp->rx_nr_rings;
4467                 } else {
4468                         max_rings = 1;
4469                 }
4470
4471                 /* Fill the RSS indirection table with ring group ids */
4472                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4473                         if (j == max_rings)
4474                                 j = 0;
4475                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4476                 }
4477
4478                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4479                 req.hash_key_tbl_addr =
4480                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4481         }
4482         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4483         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4484 }
4485
4486 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4487 {
4488         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4489         u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4490         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4491         struct hwrm_vnic_rss_cfg_input req = {0};
4492
4493         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4494         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4495         if (!set_rss) {
4496                 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4497                 return 0;
4498         }
4499         req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4500         req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4501         req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4502         req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4503         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4504         for (i = 0, k = 0; i < nr_ctxs; i++) {
4505                 __le16 *ring_tbl = vnic->rss_table;
4506                 int rc;
4507
4508                 req.ring_table_pair_index = i;
4509                 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4510                 for (j = 0; j < 64; j++) {
4511                         u16 ring_id;
4512
4513                         ring_id = rxr->rx_ring_struct.fw_ring_id;
4514                         *ring_tbl++ = cpu_to_le16(ring_id);
4515                         ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4516                         *ring_tbl++ = cpu_to_le16(ring_id);
4517                         rxr++;
4518                         k++;
4519                         if (k == max_rings) {
4520                                 k = 0;
4521                                 rxr = &bp->rx_ring[0];
4522                         }
4523                 }
4524                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4525                 if (rc)
4526                         return -EIO;
4527         }
4528         return 0;
4529 }
4530
4531 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4532 {
4533         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4534         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4535
4536         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4537         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4538                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4539                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4540         req.enables =
4541                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4542                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4543         /* thresholds not implemented in firmware yet */
4544         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4545         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4546         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4547         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4548 }
4549
4550 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4551                                         u16 ctx_idx)
4552 {
4553         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4554
4555         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4556         req.rss_cos_lb_ctx_id =
4557                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4558
4559         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4560         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4561 }
4562
4563 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4564 {
4565         int i, j;
4566
4567         for (i = 0; i < bp->nr_vnics; i++) {
4568                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4569
4570                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4571                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4572                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4573                 }
4574         }
4575         bp->rsscos_nr_ctxs = 0;
4576 }
4577
4578 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4579 {
4580         int rc;
4581         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4582         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4583                                                 bp->hwrm_cmd_resp_addr;
4584
4585         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4586                                -1);
4587
4588         mutex_lock(&bp->hwrm_cmd_lock);
4589         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4590         if (!rc)
4591                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4592                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4593         mutex_unlock(&bp->hwrm_cmd_lock);
4594
4595         return rc;
4596 }
4597
4598 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4599 {
4600         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4601                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4602         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4603 }
4604
4605 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4606 {
4607         unsigned int ring = 0, grp_idx;
4608         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4609         struct hwrm_vnic_cfg_input req = {0};
4610         u16 def_vlan = 0;
4611
4612         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4613
4614         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4615                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4616
4617                 req.default_rx_ring_id =
4618                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4619                 req.default_cmpl_ring_id =
4620                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4621                 req.enables =
4622                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4623                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4624                 goto vnic_mru;
4625         }
4626         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4627         /* Only RSS support for now TBD: COS & LB */
4628         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4629                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4630                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4631                                            VNIC_CFG_REQ_ENABLES_MRU);
4632         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4633                 req.rss_rule =
4634                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4635                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4636                                            VNIC_CFG_REQ_ENABLES_MRU);
4637                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4638         } else {
4639                 req.rss_rule = cpu_to_le16(0xffff);
4640         }
4641
4642         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4643             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4644                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4645                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4646         } else {
4647                 req.cos_rule = cpu_to_le16(0xffff);
4648         }
4649
4650         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4651                 ring = 0;
4652         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4653                 ring = vnic_id - 1;
4654         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4655                 ring = bp->rx_nr_rings - 1;
4656
4657         grp_idx = bp->rx_ring[ring].bnapi->index;
4658         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4659         req.lb_rule = cpu_to_le16(0xffff);
4660 vnic_mru:
4661         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4662                               VLAN_HLEN);
4663
4664         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4665 #ifdef CONFIG_BNXT_SRIOV
4666         if (BNXT_VF(bp))
4667                 def_vlan = bp->vf.vlan;
4668 #endif
4669         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4670                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4671         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4672                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4673
4674         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4675 }
4676
4677 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4678 {
4679         u32 rc = 0;
4680
4681         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4682                 struct hwrm_vnic_free_input req = {0};
4683
4684                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4685                 req.vnic_id =
4686                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4687
4688                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4689                 if (rc)
4690                         return rc;
4691                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4692         }
4693         return rc;
4694 }
4695
4696 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4697 {
4698         u16 i;
4699
4700         for (i = 0; i < bp->nr_vnics; i++)
4701                 bnxt_hwrm_vnic_free_one(bp, i);
4702 }
4703
4704 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4705                                 unsigned int start_rx_ring_idx,
4706                                 unsigned int nr_rings)
4707 {
4708         int rc = 0;
4709         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4710         struct hwrm_vnic_alloc_input req = {0};
4711         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4712         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4713
4714         if (bp->flags & BNXT_FLAG_CHIP_P5)
4715                 goto vnic_no_ring_grps;
4716
4717         /* map ring groups to this vnic */
4718         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4719                 grp_idx = bp->rx_ring[i].bnapi->index;
4720                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4721                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4722                                    j, nr_rings);
4723                         break;
4724                 }
4725                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4726         }
4727
4728 vnic_no_ring_grps:
4729         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4730                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4731         if (vnic_id == 0)
4732                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4733
4734         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4735
4736         mutex_lock(&bp->hwrm_cmd_lock);
4737         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4738         if (!rc)
4739                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4740         mutex_unlock(&bp->hwrm_cmd_lock);
4741         return rc;
4742 }
4743
4744 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4745 {
4746         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4747         struct hwrm_vnic_qcaps_input req = {0};
4748         int rc;
4749
4750         if (bp->hwrm_spec_code < 0x10600)
4751                 return 0;
4752
4753         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4754         mutex_lock(&bp->hwrm_cmd_lock);
4755         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4756         if (!rc) {
4757                 u32 flags = le32_to_cpu(resp->flags);
4758
4759                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4760                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4761                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4762                 if (flags &
4763                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4764                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4765         }
4766         mutex_unlock(&bp->hwrm_cmd_lock);
4767         return rc;
4768 }
4769
4770 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4771 {
4772         u16 i;
4773         u32 rc = 0;
4774
4775         if (bp->flags & BNXT_FLAG_CHIP_P5)
4776                 return 0;
4777
4778         mutex_lock(&bp->hwrm_cmd_lock);
4779         for (i = 0; i < bp->rx_nr_rings; i++) {
4780                 struct hwrm_ring_grp_alloc_input req = {0};
4781                 struct hwrm_ring_grp_alloc_output *resp =
4782                                         bp->hwrm_cmd_resp_addr;
4783                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4784
4785                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4786
4787                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4788                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4789                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4790                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4791
4792                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4793                                         HWRM_CMD_TIMEOUT);
4794                 if (rc)
4795                         break;
4796
4797                 bp->grp_info[grp_idx].fw_grp_id =
4798                         le32_to_cpu(resp->ring_group_id);
4799         }
4800         mutex_unlock(&bp->hwrm_cmd_lock);
4801         return rc;
4802 }
4803
4804 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4805 {
4806         u16 i;
4807         u32 rc = 0;
4808         struct hwrm_ring_grp_free_input req = {0};
4809
4810         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4811                 return 0;
4812
4813         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4814
4815         mutex_lock(&bp->hwrm_cmd_lock);
4816         for (i = 0; i < bp->cp_nr_rings; i++) {
4817                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4818                         continue;
4819                 req.ring_group_id =
4820                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4821
4822                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4823                                         HWRM_CMD_TIMEOUT);
4824                 if (rc)
4825                         break;
4826                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4827         }
4828         mutex_unlock(&bp->hwrm_cmd_lock);
4829         return rc;
4830 }
4831
4832 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4833                                     struct bnxt_ring_struct *ring,
4834                                     u32 ring_type, u32 map_index)
4835 {
4836         int rc = 0, err = 0;
4837         struct hwrm_ring_alloc_input req = {0};
4838         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4839         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4840         struct bnxt_ring_grp_info *grp_info;
4841         u16 ring_id;
4842
4843         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4844
4845         req.enables = 0;
4846         if (rmem->nr_pages > 1) {
4847                 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4848                 /* Page size is in log2 units */
4849                 req.page_size = BNXT_PAGE_SHIFT;
4850                 req.page_tbl_depth = 1;
4851         } else {
4852                 req.page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
4853         }
4854         req.fbo = 0;
4855         /* Association of ring index with doorbell index and MSIX number */
4856         req.logical_id = cpu_to_le16(map_index);
4857
4858         switch (ring_type) {
4859         case HWRM_RING_ALLOC_TX: {
4860                 struct bnxt_tx_ring_info *txr;
4861
4862                 txr = container_of(ring, struct bnxt_tx_ring_info,
4863                                    tx_ring_struct);
4864                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4865                 /* Association of transmit ring with completion ring */
4866                 grp_info = &bp->grp_info[ring->grp_idx];
4867                 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4868                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4869                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4870                 req.queue_id = cpu_to_le16(ring->queue_id);
4871                 break;
4872         }
4873         case HWRM_RING_ALLOC_RX:
4874                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4875                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4876                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4877                         u16 flags = 0;
4878
4879                         /* Association of rx ring with stats context */
4880                         grp_info = &bp->grp_info[ring->grp_idx];
4881                         req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4882                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4883                         req.enables |= cpu_to_le32(
4884                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4885                         if (NET_IP_ALIGN == 2)
4886                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4887                         req.flags = cpu_to_le16(flags);
4888                 }
4889                 break;
4890         case HWRM_RING_ALLOC_AGG:
4891                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4892                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4893                         /* Association of agg ring with rx ring */
4894                         grp_info = &bp->grp_info[ring->grp_idx];
4895                         req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4896                         req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4897                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4898                         req.enables |= cpu_to_le32(
4899                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4900                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4901                 } else {
4902                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4903                 }
4904                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4905                 break;
4906         case HWRM_RING_ALLOC_CMPL:
4907                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4908                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4909                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4910                         /* Association of cp ring with nq */
4911                         grp_info = &bp->grp_info[map_index];
4912                         req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4913                         req.cq_handle = cpu_to_le64(ring->handle);
4914                         req.enables |= cpu_to_le32(
4915                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4916                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4917                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4918                 }
4919                 break;
4920         case HWRM_RING_ALLOC_NQ:
4921                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4922                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4923                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4924                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4925                 break;
4926         default:
4927                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4928                            ring_type);
4929                 return -1;
4930         }
4931
4932         mutex_lock(&bp->hwrm_cmd_lock);
4933         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4934         err = le16_to_cpu(resp->error_code);
4935         ring_id = le16_to_cpu(resp->ring_id);
4936         mutex_unlock(&bp->hwrm_cmd_lock);
4937
4938         if (rc || err) {
4939                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4940                            ring_type, rc, err);
4941                 return -EIO;
4942         }
4943         ring->fw_ring_id = ring_id;
4944         return rc;
4945 }
4946
4947 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4948 {
4949         int rc;
4950
4951         if (BNXT_PF(bp)) {
4952                 struct hwrm_func_cfg_input req = {0};
4953
4954                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4955                 req.fid = cpu_to_le16(0xffff);
4956                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4957                 req.async_event_cr = cpu_to_le16(idx);
4958                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4959         } else {
4960                 struct hwrm_func_vf_cfg_input req = {0};
4961
4962                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4963                 req.enables =
4964                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4965                 req.async_event_cr = cpu_to_le16(idx);
4966                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4967         }
4968         return rc;
4969 }
4970
4971 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4972                         u32 map_idx, u32 xid)
4973 {
4974         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4975                 if (BNXT_PF(bp))
4976                         db->doorbell = bp->bar1 + 0x10000;
4977                 else
4978                         db->doorbell = bp->bar1 + 0x4000;
4979                 switch (ring_type) {
4980                 case HWRM_RING_ALLOC_TX:
4981                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4982                         break;
4983                 case HWRM_RING_ALLOC_RX:
4984                 case HWRM_RING_ALLOC_AGG:
4985                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4986                         break;
4987                 case HWRM_RING_ALLOC_CMPL:
4988                         db->db_key64 = DBR_PATH_L2;
4989                         break;
4990                 case HWRM_RING_ALLOC_NQ:
4991                         db->db_key64 = DBR_PATH_L2;
4992                         break;
4993                 }
4994                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4995         } else {
4996                 db->doorbell = bp->bar1 + map_idx * 0x80;
4997                 switch (ring_type) {
4998                 case HWRM_RING_ALLOC_TX:
4999                         db->db_key32 = DB_KEY_TX;
5000                         break;
5001                 case HWRM_RING_ALLOC_RX:
5002                 case HWRM_RING_ALLOC_AGG:
5003                         db->db_key32 = DB_KEY_RX;
5004                         break;
5005                 case HWRM_RING_ALLOC_CMPL:
5006                         db->db_key32 = DB_KEY_CP;
5007                         break;
5008                 }
5009         }
5010 }
5011
5012 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5013 {
5014         int i, rc = 0;
5015         u32 type;
5016
5017         if (bp->flags & BNXT_FLAG_CHIP_P5)
5018                 type = HWRM_RING_ALLOC_NQ;
5019         else
5020                 type = HWRM_RING_ALLOC_CMPL;
5021         for (i = 0; i < bp->cp_nr_rings; i++) {
5022                 struct bnxt_napi *bnapi = bp->bnapi[i];
5023                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5024                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5025                 u32 map_idx = ring->map_idx;
5026                 unsigned int vector;
5027
5028                 vector = bp->irq_tbl[map_idx].vector;
5029                 disable_irq_nosync(vector);
5030                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5031                 if (rc) {
5032                         enable_irq(vector);
5033                         goto err_out;
5034                 }
5035                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5036                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5037                 enable_irq(vector);
5038                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5039
5040                 if (!i) {
5041                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5042                         if (rc)
5043                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5044                 }
5045         }
5046
5047         type = HWRM_RING_ALLOC_TX;
5048         for (i = 0; i < bp->tx_nr_rings; i++) {
5049                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5050                 struct bnxt_ring_struct *ring;
5051                 u32 map_idx;
5052
5053                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5054                         struct bnxt_napi *bnapi = txr->bnapi;
5055                         struct bnxt_cp_ring_info *cpr, *cpr2;
5056                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5057
5058                         cpr = &bnapi->cp_ring;
5059                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5060                         ring = &cpr2->cp_ring_struct;
5061                         ring->handle = BNXT_TX_HDL;
5062                         map_idx = bnapi->index;
5063                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5064                         if (rc)
5065                                 goto err_out;
5066                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5067                                     ring->fw_ring_id);
5068                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5069                 }
5070                 ring = &txr->tx_ring_struct;
5071                 map_idx = i;
5072                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5073                 if (rc)
5074                         goto err_out;
5075                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5076         }
5077
5078         type = HWRM_RING_ALLOC_RX;
5079         for (i = 0; i < bp->rx_nr_rings; i++) {
5080                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5081                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5082                 struct bnxt_napi *bnapi = rxr->bnapi;
5083                 u32 map_idx = bnapi->index;
5084
5085                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5086                 if (rc)
5087                         goto err_out;
5088                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5089                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5090                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5091                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5092                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5093                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5094                         struct bnxt_cp_ring_info *cpr2;
5095
5096                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5097                         ring = &cpr2->cp_ring_struct;
5098                         ring->handle = BNXT_RX_HDL;
5099                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5100                         if (rc)
5101                                 goto err_out;
5102                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5103                                     ring->fw_ring_id);
5104                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5105                 }
5106         }
5107
5108         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5109                 type = HWRM_RING_ALLOC_AGG;
5110                 for (i = 0; i < bp->rx_nr_rings; i++) {
5111                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5112                         struct bnxt_ring_struct *ring =
5113                                                 &rxr->rx_agg_ring_struct;
5114                         u32 grp_idx = ring->grp_idx;
5115                         u32 map_idx = grp_idx + bp->rx_nr_rings;
5116
5117                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5118                         if (rc)
5119                                 goto err_out;
5120
5121                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5122                                     ring->fw_ring_id);
5123                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5124                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5125                 }
5126         }
5127 err_out:
5128         return rc;
5129 }
5130
5131 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5132                                    struct bnxt_ring_struct *ring,
5133                                    u32 ring_type, int cmpl_ring_id)
5134 {
5135         int rc;
5136         struct hwrm_ring_free_input req = {0};
5137         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5138         u16 error_code;
5139
5140         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5141         req.ring_type = ring_type;
5142         req.ring_id = cpu_to_le16(ring->fw_ring_id);
5143
5144         mutex_lock(&bp->hwrm_cmd_lock);
5145         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5146         error_code = le16_to_cpu(resp->error_code);
5147         mutex_unlock(&bp->hwrm_cmd_lock);
5148
5149         if (rc || error_code) {
5150                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5151                            ring_type, rc, error_code);
5152                 return -EIO;
5153         }
5154         return 0;
5155 }
5156
5157 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5158 {
5159         u32 type;
5160         int i;
5161
5162         if (!bp->bnapi)
5163                 return;
5164
5165         for (i = 0; i < bp->tx_nr_rings; i++) {
5166                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5167                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5168
5169                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5170                         u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5171
5172                         hwrm_ring_free_send_msg(bp, ring,
5173                                                 RING_FREE_REQ_RING_TYPE_TX,
5174                                                 close_path ? cmpl_ring_id :
5175                                                 INVALID_HW_RING_ID);
5176                         ring->fw_ring_id = INVALID_HW_RING_ID;
5177                 }
5178         }
5179
5180         for (i = 0; i < bp->rx_nr_rings; i++) {
5181                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5182                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5183                 u32 grp_idx = rxr->bnapi->index;
5184
5185                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5186                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5187
5188                         hwrm_ring_free_send_msg(bp, ring,
5189                                                 RING_FREE_REQ_RING_TYPE_RX,
5190                                                 close_path ? cmpl_ring_id :
5191                                                 INVALID_HW_RING_ID);
5192                         ring->fw_ring_id = INVALID_HW_RING_ID;
5193                         bp->grp_info[grp_idx].rx_fw_ring_id =
5194                                 INVALID_HW_RING_ID;
5195                 }
5196         }
5197
5198         if (bp->flags & BNXT_FLAG_CHIP_P5)
5199                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5200         else
5201                 type = RING_FREE_REQ_RING_TYPE_RX;
5202         for (i = 0; i < bp->rx_nr_rings; i++) {
5203                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5204                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5205                 u32 grp_idx = rxr->bnapi->index;
5206
5207                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5208                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5209
5210                         hwrm_ring_free_send_msg(bp, ring, type,
5211                                                 close_path ? cmpl_ring_id :
5212                                                 INVALID_HW_RING_ID);
5213                         ring->fw_ring_id = INVALID_HW_RING_ID;
5214                         bp->grp_info[grp_idx].agg_fw_ring_id =
5215                                 INVALID_HW_RING_ID;
5216                 }
5217         }
5218
5219         /* The completion rings are about to be freed.  After that the
5220          * IRQ doorbell will not work anymore.  So we need to disable
5221          * IRQ here.
5222          */
5223         bnxt_disable_int_sync(bp);
5224
5225         if (bp->flags & BNXT_FLAG_CHIP_P5)
5226                 type = RING_FREE_REQ_RING_TYPE_NQ;
5227         else
5228                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5229         for (i = 0; i < bp->cp_nr_rings; i++) {
5230                 struct bnxt_napi *bnapi = bp->bnapi[i];
5231                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5232                 struct bnxt_ring_struct *ring;
5233                 int j;
5234
5235                 for (j = 0; j < 2; j++) {
5236                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5237
5238                         if (cpr2) {
5239                                 ring = &cpr2->cp_ring_struct;
5240                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5241                                         continue;
5242                                 hwrm_ring_free_send_msg(bp, ring,
5243                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
5244                                         INVALID_HW_RING_ID);
5245                                 ring->fw_ring_id = INVALID_HW_RING_ID;
5246                         }
5247                 }
5248                 ring = &cpr->cp_ring_struct;
5249                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5250                         hwrm_ring_free_send_msg(bp, ring, type,
5251                                                 INVALID_HW_RING_ID);
5252                         ring->fw_ring_id = INVALID_HW_RING_ID;
5253                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5254                 }
5255         }
5256 }
5257
5258 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5259                            bool shared);
5260
5261 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5262 {
5263         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5264         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5265         struct hwrm_func_qcfg_input req = {0};
5266         int rc;
5267
5268         if (bp->hwrm_spec_code < 0x10601)
5269                 return 0;
5270
5271         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5272         req.fid = cpu_to_le16(0xffff);
5273         mutex_lock(&bp->hwrm_cmd_lock);
5274         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5275         if (rc) {
5276                 mutex_unlock(&bp->hwrm_cmd_lock);
5277                 return -EIO;
5278         }
5279
5280         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5281         if (BNXT_NEW_RM(bp)) {
5282                 u16 cp, stats;
5283
5284                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5285                 hw_resc->resv_hw_ring_grps =
5286                         le32_to_cpu(resp->alloc_hw_ring_grps);
5287                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5288                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5289                 stats = le16_to_cpu(resp->alloc_stat_ctx);
5290                 hw_resc->resv_irqs = cp;
5291                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5292                         int rx = hw_resc->resv_rx_rings;
5293                         int tx = hw_resc->resv_tx_rings;
5294
5295                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5296                                 rx >>= 1;
5297                         if (cp < (rx + tx)) {
5298                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5299                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5300                                         rx <<= 1;
5301                                 hw_resc->resv_rx_rings = rx;
5302                                 hw_resc->resv_tx_rings = tx;
5303                         }
5304                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5305                         hw_resc->resv_hw_ring_grps = rx;
5306                 }
5307                 hw_resc->resv_cp_rings = cp;
5308                 hw_resc->resv_stat_ctxs = stats;
5309         }
5310         mutex_unlock(&bp->hwrm_cmd_lock);
5311         return 0;
5312 }
5313
5314 /* Caller must hold bp->hwrm_cmd_lock */
5315 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5316 {
5317         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5318         struct hwrm_func_qcfg_input req = {0};
5319         int rc;
5320
5321         if (bp->hwrm_spec_code < 0x10601)
5322                 return 0;
5323
5324         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5325         req.fid = cpu_to_le16(fid);
5326         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5327         if (!rc)
5328                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5329
5330         return rc;
5331 }
5332
5333 static bool bnxt_rfs_supported(struct bnxt *bp);
5334
5335 static void
5336 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5337                              int tx_rings, int rx_rings, int ring_grps,
5338                              int cp_rings, int stats, int vnics)
5339 {
5340         u32 enables = 0;
5341
5342         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5343         req->fid = cpu_to_le16(0xffff);
5344         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5345         req->num_tx_rings = cpu_to_le16(tx_rings);
5346         if (BNXT_NEW_RM(bp)) {
5347                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5348                 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5349                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5350                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5351                         enables |= tx_rings + ring_grps ?
5352                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5353                         enables |= rx_rings ?
5354                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5355                 } else {
5356                         enables |= cp_rings ?
5357                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5358                         enables |= ring_grps ?
5359                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5360                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5361                 }
5362                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5363
5364                 req->num_rx_rings = cpu_to_le16(rx_rings);
5365                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5366                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5367                         req->num_msix = cpu_to_le16(cp_rings);
5368                         req->num_rsscos_ctxs =
5369                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5370                 } else {
5371                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
5372                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5373                         req->num_rsscos_ctxs = cpu_to_le16(1);
5374                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5375                             bnxt_rfs_supported(bp))
5376                                 req->num_rsscos_ctxs =
5377                                         cpu_to_le16(ring_grps + 1);
5378                 }
5379                 req->num_stat_ctxs = cpu_to_le16(stats);
5380                 req->num_vnics = cpu_to_le16(vnics);
5381         }
5382         req->enables = cpu_to_le32(enables);
5383 }
5384
5385 static void
5386 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5387                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
5388                              int rx_rings, int ring_grps, int cp_rings,
5389                              int stats, int vnics)
5390 {
5391         u32 enables = 0;
5392
5393         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5394         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5395         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5396                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5397         enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5398         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5399                 enables |= tx_rings + ring_grps ?
5400                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5401         } else {
5402                 enables |= cp_rings ?
5403                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5404                 enables |= ring_grps ?
5405                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5406         }
5407         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5408         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5409
5410         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5411         req->num_tx_rings = cpu_to_le16(tx_rings);
5412         req->num_rx_rings = cpu_to_le16(rx_rings);
5413         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5414                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5415                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5416         } else {
5417                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5418                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5419                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5420         }
5421         req->num_stat_ctxs = cpu_to_le16(stats);
5422         req->num_vnics = cpu_to_le16(vnics);
5423
5424         req->enables = cpu_to_le32(enables);
5425 }
5426
5427 static int
5428 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5429                            int ring_grps, int cp_rings, int stats, int vnics)
5430 {
5431         struct hwrm_func_cfg_input req = {0};
5432         int rc;
5433
5434         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5435                                      cp_rings, stats, vnics);
5436         if (!req.enables)
5437                 return 0;
5438
5439         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5440         if (rc)
5441                 return -ENOMEM;
5442
5443         if (bp->hwrm_spec_code < 0x10601)
5444                 bp->hw_resc.resv_tx_rings = tx_rings;
5445
5446         rc = bnxt_hwrm_get_rings(bp);
5447         return rc;
5448 }
5449
5450 static int
5451 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5452                            int ring_grps, int cp_rings, int stats, int vnics)
5453 {
5454         struct hwrm_func_vf_cfg_input req = {0};
5455         int rc;
5456
5457         if (!BNXT_NEW_RM(bp)) {
5458                 bp->hw_resc.resv_tx_rings = tx_rings;
5459                 return 0;
5460         }
5461
5462         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5463                                      cp_rings, stats, vnics);
5464         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5465         if (rc)
5466                 return -ENOMEM;
5467
5468         rc = bnxt_hwrm_get_rings(bp);
5469         return rc;
5470 }
5471
5472 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5473                                    int cp, int stat, int vnic)
5474 {
5475         if (BNXT_PF(bp))
5476                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5477                                                   vnic);
5478         else
5479                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5480                                                   vnic);
5481 }
5482
5483 int bnxt_nq_rings_in_use(struct bnxt *bp)
5484 {
5485         int cp = bp->cp_nr_rings;
5486         int ulp_msix, ulp_base;
5487
5488         ulp_msix = bnxt_get_ulp_msix_num(bp);
5489         if (ulp_msix) {
5490                 ulp_base = bnxt_get_ulp_msix_base(bp);
5491                 cp += ulp_msix;
5492                 if ((ulp_base + ulp_msix) > cp)
5493                         cp = ulp_base + ulp_msix;
5494         }
5495         return cp;
5496 }
5497
5498 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5499 {
5500         int cp;
5501
5502         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5503                 return bnxt_nq_rings_in_use(bp);
5504
5505         cp = bp->tx_nr_rings + bp->rx_nr_rings;
5506         return cp;
5507 }
5508
5509 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5510 {
5511         int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
5512         int cp = bp->cp_nr_rings;
5513
5514         if (!ulp_stat)
5515                 return cp;
5516
5517         if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
5518                 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
5519
5520         return cp + ulp_stat;
5521 }
5522
5523 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5524 {
5525         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5526         int cp = bnxt_cp_rings_in_use(bp);
5527         int nq = bnxt_nq_rings_in_use(bp);
5528         int rx = bp->rx_nr_rings, stat;
5529         int vnic = 1, grp = rx;
5530
5531         if (bp->hwrm_spec_code < 0x10601)
5532                 return false;
5533
5534         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5535                 return true;
5536
5537         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5538                 vnic = rx + 1;
5539         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5540                 rx <<= 1;
5541         stat = bnxt_get_func_stat_ctxs(bp);
5542         if (BNXT_NEW_RM(bp) &&
5543             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5544              hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
5545              (hw_resc->resv_hw_ring_grps != grp &&
5546               !(bp->flags & BNXT_FLAG_CHIP_P5))))
5547                 return true;
5548         if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
5549             hw_resc->resv_irqs != nq)
5550                 return true;
5551         return false;
5552 }
5553
5554 static int __bnxt_reserve_rings(struct bnxt *bp)
5555 {
5556         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5557         int cp = bnxt_nq_rings_in_use(bp);
5558         int tx = bp->tx_nr_rings;
5559         int rx = bp->rx_nr_rings;
5560         int grp, rx_rings, rc;
5561         int vnic = 1, stat;
5562         bool sh = false;
5563
5564         if (!bnxt_need_reserve_rings(bp))
5565                 return 0;
5566
5567         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5568                 sh = true;
5569         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5570                 vnic = rx + 1;
5571         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5572                 rx <<= 1;
5573         grp = bp->rx_nr_rings;
5574         stat = bnxt_get_func_stat_ctxs(bp);
5575
5576         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5577         if (rc)
5578                 return rc;
5579
5580         tx = hw_resc->resv_tx_rings;
5581         if (BNXT_NEW_RM(bp)) {
5582                 rx = hw_resc->resv_rx_rings;
5583                 cp = hw_resc->resv_irqs;
5584                 grp = hw_resc->resv_hw_ring_grps;
5585                 vnic = hw_resc->resv_vnics;
5586                 stat = hw_resc->resv_stat_ctxs;
5587         }
5588
5589         rx_rings = rx;
5590         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5591                 if (rx >= 2) {
5592                         rx_rings = rx >> 1;
5593                 } else {
5594                         if (netif_running(bp->dev))
5595                                 return -ENOMEM;
5596
5597                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5598                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5599                         bp->dev->hw_features &= ~NETIF_F_LRO;
5600                         bp->dev->features &= ~NETIF_F_LRO;
5601                         bnxt_set_ring_params(bp);
5602                 }
5603         }
5604         rx_rings = min_t(int, rx_rings, grp);
5605         cp = min_t(int, cp, bp->cp_nr_rings);
5606         if (stat > bnxt_get_ulp_stat_ctxs(bp))
5607                 stat -= bnxt_get_ulp_stat_ctxs(bp);
5608         cp = min_t(int, cp, stat);
5609         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5610         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5611                 rx = rx_rings << 1;
5612         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5613         bp->tx_nr_rings = tx;
5614         bp->rx_nr_rings = rx_rings;
5615         bp->cp_nr_rings = cp;
5616
5617         if (!tx || !rx || !cp || !grp || !vnic || !stat)
5618                 return -ENOMEM;
5619
5620         return rc;
5621 }
5622
5623 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5624                                     int ring_grps, int cp_rings, int stats,
5625                                     int vnics)
5626 {
5627         struct hwrm_func_vf_cfg_input req = {0};
5628         u32 flags;
5629         int rc;
5630
5631         if (!BNXT_NEW_RM(bp))
5632                 return 0;
5633
5634         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5635                                      cp_rings, stats, vnics);
5636         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5637                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5638                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5639                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5640                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5641                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5642         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5643                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5644
5645         req.flags = cpu_to_le32(flags);
5646         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5647         if (rc)
5648                 return -ENOMEM;
5649         return 0;
5650 }
5651
5652 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5653                                     int ring_grps, int cp_rings, int stats,
5654                                     int vnics)
5655 {
5656         struct hwrm_func_cfg_input req = {0};
5657         u32 flags;
5658         int rc;
5659
5660         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5661                                      cp_rings, stats, vnics);
5662         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5663         if (BNXT_NEW_RM(bp)) {
5664                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5665                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5666                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5667                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5668                 if (bp->flags & BNXT_FLAG_CHIP_P5)
5669                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5670                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5671                 else
5672                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5673         }
5674
5675         req.flags = cpu_to_le32(flags);
5676         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5677         if (rc)
5678                 return -ENOMEM;
5679         return 0;
5680 }
5681
5682 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5683                                  int ring_grps, int cp_rings, int stats,
5684                                  int vnics)
5685 {
5686         if (bp->hwrm_spec_code < 0x10801)
5687                 return 0;
5688
5689         if (BNXT_PF(bp))
5690                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5691                                                 ring_grps, cp_rings, stats,
5692                                                 vnics);
5693
5694         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5695                                         cp_rings, stats, vnics);
5696 }
5697
5698 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5699 {
5700         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5701         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5702         struct hwrm_ring_aggint_qcaps_input req = {0};
5703         int rc;
5704
5705         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5706         coal_cap->num_cmpl_dma_aggr_max = 63;
5707         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5708         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5709         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5710         coal_cap->int_lat_tmr_min_max = 65535;
5711         coal_cap->int_lat_tmr_max_max = 65535;
5712         coal_cap->num_cmpl_aggr_int_max = 65535;
5713         coal_cap->timer_units = 80;
5714
5715         if (bp->hwrm_spec_code < 0x10902)
5716                 return;
5717
5718         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5719         mutex_lock(&bp->hwrm_cmd_lock);
5720         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5721         if (!rc) {
5722                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5723                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5724                 coal_cap->num_cmpl_dma_aggr_max =
5725                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5726                 coal_cap->num_cmpl_dma_aggr_during_int_max =
5727                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5728                 coal_cap->cmpl_aggr_dma_tmr_max =
5729                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5730                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5731                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5732                 coal_cap->int_lat_tmr_min_max =
5733                         le16_to_cpu(resp->int_lat_tmr_min_max);
5734                 coal_cap->int_lat_tmr_max_max =
5735                         le16_to_cpu(resp->int_lat_tmr_max_max);
5736                 coal_cap->num_cmpl_aggr_int_max =
5737                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
5738                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5739         }
5740         mutex_unlock(&bp->hwrm_cmd_lock);
5741 }
5742
5743 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5744 {
5745         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5746
5747         return usec * 1000 / coal_cap->timer_units;
5748 }
5749
5750 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5751         struct bnxt_coal *hw_coal,
5752         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5753 {
5754         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5755         u32 cmpl_params = coal_cap->cmpl_params;
5756         u16 val, tmr, max, flags = 0;
5757
5758         max = hw_coal->bufs_per_record * 128;
5759         if (hw_coal->budget)
5760                 max = hw_coal->bufs_per_record * hw_coal->budget;
5761         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5762
5763         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5764         req->num_cmpl_aggr_int = cpu_to_le16(val);
5765
5766         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5767         req->num_cmpl_dma_aggr = cpu_to_le16(val);
5768
5769         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5770                       coal_cap->num_cmpl_dma_aggr_during_int_max);
5771         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5772
5773         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5774         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5775         req->int_lat_tmr_max = cpu_to_le16(tmr);
5776
5777         /* min timer set to 1/2 of interrupt timer */
5778         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5779                 val = tmr / 2;
5780                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5781                 req->int_lat_tmr_min = cpu_to_le16(val);
5782                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5783         }
5784
5785         /* buf timer set to 1/4 of interrupt timer */
5786         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5787         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5788
5789         if (cmpl_params &
5790             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5791                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5792                 val = clamp_t(u16, tmr, 1,
5793                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5794                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5795                 req->enables |=
5796                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5797         }
5798
5799         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5800                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5801         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5802             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5803                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5804         req->flags = cpu_to_le16(flags);
5805         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5806 }
5807
5808 /* Caller holds bp->hwrm_cmd_lock */
5809 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5810                                    struct bnxt_coal *hw_coal)
5811 {
5812         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5813         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5814         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5815         u32 nq_params = coal_cap->nq_params;
5816         u16 tmr;
5817
5818         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5819                 return 0;
5820
5821         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5822                                -1, -1);
5823         req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5824         req.flags =
5825                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5826
5827         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5828         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5829         req.int_lat_tmr_min = cpu_to_le16(tmr);
5830         req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5831         return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5832 }
5833
5834 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5835 {
5836         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5837         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5838         struct bnxt_coal coal;
5839
5840         /* Tick values in micro seconds.
5841          * 1 coal_buf x bufs_per_record = 1 completion record.
5842          */
5843         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5844
5845         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5846         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5847
5848         if (!bnapi->rx_ring)
5849                 return -ENODEV;
5850
5851         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5852                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5853
5854         bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5855
5856         req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5857
5858         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5859                                  HWRM_CMD_TIMEOUT);
5860 }
5861
5862 int bnxt_hwrm_set_coal(struct bnxt *bp)
5863 {
5864         int i, rc = 0;
5865         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5866                                                            req_tx = {0}, *req;
5867
5868         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5869                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5870         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5871                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5872
5873         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5874         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5875
5876         mutex_lock(&bp->hwrm_cmd_lock);
5877         for (i = 0; i < bp->cp_nr_rings; i++) {
5878                 struct bnxt_napi *bnapi = bp->bnapi[i];
5879                 struct bnxt_coal *hw_coal;
5880                 u16 ring_id;
5881
5882                 req = &req_rx;
5883                 if (!bnapi->rx_ring) {
5884                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5885                         req = &req_tx;
5886                 } else {
5887                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5888                 }
5889                 req->ring_id = cpu_to_le16(ring_id);
5890
5891                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5892                                         HWRM_CMD_TIMEOUT);
5893                 if (rc)
5894                         break;
5895
5896                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5897                         continue;
5898
5899                 if (bnapi->rx_ring && bnapi->tx_ring) {
5900                         req = &req_tx;
5901                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5902                         req->ring_id = cpu_to_le16(ring_id);
5903                         rc = _hwrm_send_message(bp, req, sizeof(*req),
5904                                                 HWRM_CMD_TIMEOUT);
5905                         if (rc)
5906                                 break;
5907                 }
5908                 if (bnapi->rx_ring)
5909                         hw_coal = &bp->rx_coal;
5910                 else
5911                         hw_coal = &bp->tx_coal;
5912                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5913         }
5914         mutex_unlock(&bp->hwrm_cmd_lock);
5915         return rc;
5916 }
5917
5918 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5919 {
5920         int rc = 0, i;
5921         struct hwrm_stat_ctx_free_input req = {0};
5922
5923         if (!bp->bnapi)
5924                 return 0;
5925
5926         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5927                 return 0;
5928
5929         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5930
5931         mutex_lock(&bp->hwrm_cmd_lock);
5932         for (i = 0; i < bp->cp_nr_rings; i++) {
5933                 struct bnxt_napi *bnapi = bp->bnapi[i];
5934                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5935
5936                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5937                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5938
5939                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5940                                                 HWRM_CMD_TIMEOUT);
5941                         if (rc)
5942                                 break;
5943
5944                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5945                 }
5946         }
5947         mutex_unlock(&bp->hwrm_cmd_lock);
5948         return rc;
5949 }
5950
5951 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5952 {
5953         int rc = 0, i;
5954         struct hwrm_stat_ctx_alloc_input req = {0};
5955         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5956
5957         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5958                 return 0;
5959
5960         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5961
5962         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5963
5964         mutex_lock(&bp->hwrm_cmd_lock);
5965         for (i = 0; i < bp->cp_nr_rings; i++) {
5966                 struct bnxt_napi *bnapi = bp->bnapi[i];
5967                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5968
5969                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5970
5971                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5972                                         HWRM_CMD_TIMEOUT);
5973                 if (rc)
5974                         break;
5975
5976                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5977
5978                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5979         }
5980         mutex_unlock(&bp->hwrm_cmd_lock);
5981         return rc;
5982 }
5983
5984 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5985 {
5986         struct hwrm_func_qcfg_input req = {0};
5987         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5988         u16 flags;
5989         int rc;
5990
5991         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5992         req.fid = cpu_to_le16(0xffff);
5993         mutex_lock(&bp->hwrm_cmd_lock);
5994         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5995         if (rc)
5996                 goto func_qcfg_exit;
5997
5998 #ifdef CONFIG_BNXT_SRIOV
5999         if (BNXT_VF(bp)) {
6000                 struct bnxt_vf_info *vf = &bp->vf;
6001
6002                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6003         }
6004 #endif
6005         flags = le16_to_cpu(resp->flags);
6006         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6007                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6008                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6009                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6010                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6011         }
6012         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6013                 bp->flags |= BNXT_FLAG_MULTI_HOST;
6014
6015         switch (resp->port_partition_type) {
6016         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6017         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6018         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6019                 bp->port_partition_type = resp->port_partition_type;
6020                 break;
6021         }
6022         if (bp->hwrm_spec_code < 0x10707 ||
6023             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6024                 bp->br_mode = BRIDGE_MODE_VEB;
6025         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6026                 bp->br_mode = BRIDGE_MODE_VEPA;
6027         else
6028                 bp->br_mode = BRIDGE_MODE_UNDEF;
6029
6030         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6031         if (!bp->max_mtu)
6032                 bp->max_mtu = BNXT_MAX_MTU;
6033
6034 func_qcfg_exit:
6035         mutex_unlock(&bp->hwrm_cmd_lock);
6036         return rc;
6037 }
6038
6039 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6040 {
6041         struct hwrm_func_backing_store_qcaps_input req = {0};
6042         struct hwrm_func_backing_store_qcaps_output *resp =
6043                 bp->hwrm_cmd_resp_addr;
6044         int rc;
6045
6046         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6047                 return 0;
6048
6049         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6050         mutex_lock(&bp->hwrm_cmd_lock);
6051         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6052         if (!rc) {
6053                 struct bnxt_ctx_pg_info *ctx_pg;
6054                 struct bnxt_ctx_mem_info *ctx;
6055                 int i;
6056
6057                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6058                 if (!ctx) {
6059                         rc = -ENOMEM;
6060                         goto ctx_err;
6061                 }
6062                 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6063                 if (!ctx_pg) {
6064                         kfree(ctx);
6065                         rc = -ENOMEM;
6066                         goto ctx_err;
6067                 }
6068                 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6069                         ctx->tqm_mem[i] = ctx_pg;
6070
6071                 bp->ctx = ctx;
6072                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6073                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6074                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6075                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6076                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6077                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6078                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6079                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6080                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6081                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6082                 ctx->vnic_max_vnic_entries =
6083                         le16_to_cpu(resp->vnic_max_vnic_entries);
6084                 ctx->vnic_max_ring_table_entries =
6085                         le16_to_cpu(resp->vnic_max_ring_table_entries);
6086                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6087                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6088                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6089                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6090                 ctx->tqm_min_entries_per_ring =
6091                         le32_to_cpu(resp->tqm_min_entries_per_ring);
6092                 ctx->tqm_max_entries_per_ring =
6093                         le32_to_cpu(resp->tqm_max_entries_per_ring);
6094                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6095                 if (!ctx->tqm_entries_multiple)
6096                         ctx->tqm_entries_multiple = 1;
6097                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6098                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6099                 ctx->mrav_num_entries_units =
6100                         le16_to_cpu(resp->mrav_num_entries_units);
6101                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6102                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6103         } else {
6104                 rc = 0;
6105         }
6106 ctx_err:
6107         mutex_unlock(&bp->hwrm_cmd_lock);
6108         return rc;
6109 }
6110
6111 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6112                                   __le64 *pg_dir)
6113 {
6114         u8 pg_size = 0;
6115
6116         if (BNXT_PAGE_SHIFT == 13)
6117                 pg_size = 1 << 4;
6118         else if (BNXT_PAGE_SIZE == 16)
6119                 pg_size = 2 << 4;
6120
6121         *pg_attr = pg_size;
6122         if (rmem->depth >= 1) {
6123                 if (rmem->depth == 2)
6124                         *pg_attr |= 2;
6125                 else
6126                         *pg_attr |= 1;
6127                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6128         } else {
6129                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6130         }
6131 }
6132
6133 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
6134         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
6135          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
6136          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
6137          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
6138          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6139
6140 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6141 {
6142         struct hwrm_func_backing_store_cfg_input req = {0};
6143         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6144         struct bnxt_ctx_pg_info *ctx_pg;
6145         __le32 *num_entries;
6146         __le64 *pg_dir;
6147         u32 flags = 0;
6148         u8 *pg_attr;
6149         int i, rc;
6150         u32 ena;
6151
6152         if (!ctx)
6153                 return 0;
6154
6155         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6156         req.enables = cpu_to_le32(enables);
6157
6158         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6159                 ctx_pg = &ctx->qp_mem;
6160                 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6161                 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6162                 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6163                 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6164                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6165                                       &req.qpc_pg_size_qpc_lvl,
6166                                       &req.qpc_page_dir);
6167         }
6168         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6169                 ctx_pg = &ctx->srq_mem;
6170                 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6171                 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6172                 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6173                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6174                                       &req.srq_pg_size_srq_lvl,
6175                                       &req.srq_page_dir);
6176         }
6177         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6178                 ctx_pg = &ctx->cq_mem;
6179                 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6180                 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6181                 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6182                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6183                                       &req.cq_page_dir);
6184         }
6185         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6186                 ctx_pg = &ctx->vnic_mem;
6187                 req.vnic_num_vnic_entries =
6188                         cpu_to_le16(ctx->vnic_max_vnic_entries);
6189                 req.vnic_num_ring_table_entries =
6190                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
6191                 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6192                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6193                                       &req.vnic_pg_size_vnic_lvl,
6194                                       &req.vnic_page_dir);
6195         }
6196         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6197                 ctx_pg = &ctx->stat_mem;
6198                 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6199                 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6200                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6201                                       &req.stat_pg_size_stat_lvl,
6202                                       &req.stat_page_dir);
6203         }
6204         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6205                 ctx_pg = &ctx->mrav_mem;
6206                 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6207                 if (ctx->mrav_num_entries_units)
6208                         flags |=
6209                         FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6210                 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6211                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6212                                       &req.mrav_pg_size_mrav_lvl,
6213                                       &req.mrav_page_dir);
6214         }
6215         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6216                 ctx_pg = &ctx->tim_mem;
6217                 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6218                 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6219                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6220                                       &req.tim_pg_size_tim_lvl,
6221                                       &req.tim_page_dir);
6222         }
6223         for (i = 0, num_entries = &req.tqm_sp_num_entries,
6224              pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6225              pg_dir = &req.tqm_sp_page_dir,
6226              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6227              i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6228                 if (!(enables & ena))
6229                         continue;
6230
6231                 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6232                 ctx_pg = ctx->tqm_mem[i];
6233                 *num_entries = cpu_to_le32(ctx_pg->entries);
6234                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6235         }
6236         req.flags = cpu_to_le32(flags);
6237         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6238         if (rc)
6239                 rc = -EIO;
6240         return rc;
6241 }
6242
6243 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6244                                   struct bnxt_ctx_pg_info *ctx_pg)
6245 {
6246         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6247
6248         rmem->page_size = BNXT_PAGE_SIZE;
6249         rmem->pg_arr = ctx_pg->ctx_pg_arr;
6250         rmem->dma_arr = ctx_pg->ctx_dma_arr;
6251         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6252         if (rmem->depth >= 1)
6253                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6254         return bnxt_alloc_ring(bp, rmem);
6255 }
6256
6257 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6258                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6259                                   u8 depth)
6260 {
6261         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6262         int rc;
6263
6264         if (!mem_size)
6265                 return 0;
6266
6267         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6268         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6269                 ctx_pg->nr_pages = 0;
6270                 return -EINVAL;
6271         }
6272         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6273                 int nr_tbls, i;
6274
6275                 rmem->depth = 2;
6276                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6277                                              GFP_KERNEL);
6278                 if (!ctx_pg->ctx_pg_tbl)
6279                         return -ENOMEM;
6280                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6281                 rmem->nr_pages = nr_tbls;
6282                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6283                 if (rc)
6284                         return rc;
6285                 for (i = 0; i < nr_tbls; i++) {
6286                         struct bnxt_ctx_pg_info *pg_tbl;
6287
6288                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6289                         if (!pg_tbl)
6290                                 return -ENOMEM;
6291                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6292                         rmem = &pg_tbl->ring_mem;
6293                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6294                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6295                         rmem->depth = 1;
6296                         rmem->nr_pages = MAX_CTX_PAGES;
6297                         if (i == (nr_tbls - 1)) {
6298                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6299
6300                                 if (rem)
6301                                         rmem->nr_pages = rem;
6302                         }
6303                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6304                         if (rc)
6305                                 break;
6306                 }
6307         } else {
6308                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6309                 if (rmem->nr_pages > 1 || depth)
6310                         rmem->depth = 1;
6311                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6312         }
6313         return rc;
6314 }
6315
6316 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6317                                   struct bnxt_ctx_pg_info *ctx_pg)
6318 {
6319         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6320
6321         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6322             ctx_pg->ctx_pg_tbl) {
6323                 int i, nr_tbls = rmem->nr_pages;
6324
6325                 for (i = 0; i < nr_tbls; i++) {
6326                         struct bnxt_ctx_pg_info *pg_tbl;
6327                         struct bnxt_ring_mem_info *rmem2;
6328
6329                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
6330                         if (!pg_tbl)
6331                                 continue;
6332                         rmem2 = &pg_tbl->ring_mem;
6333                         bnxt_free_ring(bp, rmem2);
6334                         ctx_pg->ctx_pg_arr[i] = NULL;
6335                         kfree(pg_tbl);
6336                         ctx_pg->ctx_pg_tbl[i] = NULL;
6337                 }
6338                 kfree(ctx_pg->ctx_pg_tbl);
6339                 ctx_pg->ctx_pg_tbl = NULL;
6340         }
6341         bnxt_free_ring(bp, rmem);
6342         ctx_pg->nr_pages = 0;
6343 }
6344
6345 static void bnxt_free_ctx_mem(struct bnxt *bp)
6346 {
6347         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6348         int i;
6349
6350         if (!ctx)
6351                 return;
6352
6353         if (ctx->tqm_mem[0]) {
6354                 for (i = 0; i < bp->max_q + 1; i++)
6355                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6356                 kfree(ctx->tqm_mem[0]);
6357                 ctx->tqm_mem[0] = NULL;
6358         }
6359
6360         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6361         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6362         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6363         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6364         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6365         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6366         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6367         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6368 }
6369
6370 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6371 {
6372         struct bnxt_ctx_pg_info *ctx_pg;
6373         struct bnxt_ctx_mem_info *ctx;
6374         u32 mem_size, ena, entries;
6375         u32 num_mr, num_ah;
6376         u32 extra_srqs = 0;
6377         u32 extra_qps = 0;
6378         u8 pg_lvl = 1;
6379         int i, rc;
6380
6381         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6382         if (rc) {
6383                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6384                            rc);
6385                 return rc;
6386         }
6387         ctx = bp->ctx;
6388         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6389                 return 0;
6390
6391         if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
6392                 pg_lvl = 2;
6393                 extra_qps = 65536;
6394                 extra_srqs = 8192;
6395         }
6396
6397         ctx_pg = &ctx->qp_mem;
6398         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6399                           extra_qps;
6400         mem_size = ctx->qp_entry_size * ctx_pg->entries;
6401         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6402         if (rc)
6403                 return rc;
6404
6405         ctx_pg = &ctx->srq_mem;
6406         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6407         mem_size = ctx->srq_entry_size * ctx_pg->entries;
6408         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6409         if (rc)
6410                 return rc;
6411
6412         ctx_pg = &ctx->cq_mem;
6413         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6414         mem_size = ctx->cq_entry_size * ctx_pg->entries;
6415         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6416         if (rc)
6417                 return rc;
6418
6419         ctx_pg = &ctx->vnic_mem;
6420         ctx_pg->entries = ctx->vnic_max_vnic_entries +
6421                           ctx->vnic_max_ring_table_entries;
6422         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6423         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6424         if (rc)
6425                 return rc;
6426
6427         ctx_pg = &ctx->stat_mem;
6428         ctx_pg->entries = ctx->stat_max_entries;
6429         mem_size = ctx->stat_entry_size * ctx_pg->entries;
6430         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6431         if (rc)
6432                 return rc;
6433
6434         ena = 0;
6435         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6436                 goto skip_rdma;
6437
6438         ctx_pg = &ctx->mrav_mem;
6439         /* 128K extra is needed to accommodate static AH context
6440          * allocation by f/w.
6441          */
6442         num_mr = 1024 * 256;
6443         num_ah = 1024 * 128;
6444         ctx_pg->entries = num_mr + num_ah;
6445         mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6446         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6447         if (rc)
6448                 return rc;
6449         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6450         if (ctx->mrav_num_entries_units)
6451                 ctx_pg->entries =
6452                         ((num_mr / ctx->mrav_num_entries_units) << 16) |
6453                          (num_ah / ctx->mrav_num_entries_units);
6454
6455         ctx_pg = &ctx->tim_mem;
6456         ctx_pg->entries = ctx->qp_mem.entries;
6457         mem_size = ctx->tim_entry_size * ctx_pg->entries;
6458         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6459         if (rc)
6460                 return rc;
6461         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6462
6463 skip_rdma:
6464         entries = ctx->qp_max_l2_entries + extra_qps;
6465         entries = roundup(entries, ctx->tqm_entries_multiple);
6466         entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6467                           ctx->tqm_max_entries_per_ring);
6468         for (i = 0; i < bp->max_q + 1; i++) {
6469                 ctx_pg = ctx->tqm_mem[i];
6470                 ctx_pg->entries = entries;
6471                 mem_size = ctx->tqm_entry_size * entries;
6472                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6473                 if (rc)
6474                         return rc;
6475                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6476         }
6477         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6478         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6479         if (rc)
6480                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6481                            rc);
6482         else
6483                 ctx->flags |= BNXT_CTX_FLAG_INITED;
6484
6485         return 0;
6486 }
6487
6488 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6489 {
6490         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6491         struct hwrm_func_resource_qcaps_input req = {0};
6492         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6493         int rc;
6494
6495         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6496         req.fid = cpu_to_le16(0xffff);
6497
6498         mutex_lock(&bp->hwrm_cmd_lock);
6499         rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6500                                        HWRM_CMD_TIMEOUT);
6501         if (rc) {
6502                 rc = -EIO;
6503                 goto hwrm_func_resc_qcaps_exit;
6504         }
6505
6506         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6507         if (!all)
6508                 goto hwrm_func_resc_qcaps_exit;
6509
6510         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6511         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6512         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6513         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6514         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6515         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6516         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6517         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6518         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6519         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6520         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6521         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6522         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6523         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6524         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6525         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6526
6527         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6528                 u16 max_msix = le16_to_cpu(resp->max_msix);
6529
6530                 hw_resc->max_nqs = max_msix;
6531                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6532         }
6533
6534         if (BNXT_PF(bp)) {
6535                 struct bnxt_pf_info *pf = &bp->pf;
6536
6537                 pf->vf_resv_strategy =
6538                         le16_to_cpu(resp->vf_reservation_strategy);
6539                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6540                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6541         }
6542 hwrm_func_resc_qcaps_exit:
6543         mutex_unlock(&bp->hwrm_cmd_lock);
6544         return rc;
6545 }
6546
6547 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6548 {
6549         int rc = 0;
6550         struct hwrm_func_qcaps_input req = {0};
6551         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6552         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6553         u32 flags;
6554
6555         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6556         req.fid = cpu_to_le16(0xffff);
6557
6558         mutex_lock(&bp->hwrm_cmd_lock);
6559         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6560         if (rc)
6561                 goto hwrm_func_qcaps_exit;
6562
6563         flags = le32_to_cpu(resp->flags);
6564         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6565                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6566         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6567                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6568         if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
6569                 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
6570         if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
6571                 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
6572
6573         bp->tx_push_thresh = 0;
6574         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6575                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6576
6577         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6578         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6579         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6580         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6581         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6582         if (!hw_resc->max_hw_ring_grps)
6583                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6584         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6585         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6586         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6587
6588         if (BNXT_PF(bp)) {
6589                 struct bnxt_pf_info *pf = &bp->pf;
6590
6591                 pf->fw_fid = le16_to_cpu(resp->fid);
6592                 pf->port_id = le16_to_cpu(resp->port_id);
6593                 bp->dev->dev_port = pf->port_id;
6594                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6595                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6596                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6597                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6598                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6599                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6600                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6601                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6602                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6603                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6604                         bp->flags |= BNXT_FLAG_WOL_CAP;
6605         } else {
6606 #ifdef CONFIG_BNXT_SRIOV
6607                 struct bnxt_vf_info *vf = &bp->vf;
6608
6609                 vf->fw_fid = le16_to_cpu(resp->fid);
6610                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6611 #endif
6612         }
6613
6614 hwrm_func_qcaps_exit:
6615         mutex_unlock(&bp->hwrm_cmd_lock);
6616         return rc;
6617 }
6618
6619 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6620
6621 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6622 {
6623         int rc;
6624
6625         rc = __bnxt_hwrm_func_qcaps(bp);
6626         if (rc)
6627                 return rc;
6628         rc = bnxt_hwrm_queue_qportcfg(bp);
6629         if (rc) {
6630                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6631                 return rc;
6632         }
6633         if (bp->hwrm_spec_code >= 0x10803) {
6634                 rc = bnxt_alloc_ctx_mem(bp);
6635                 if (rc)
6636                         return rc;
6637                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6638                 if (!rc)
6639                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6640         }
6641         return 0;
6642 }
6643
6644 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
6645 {
6646         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6647         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
6648         int rc = 0;
6649         u32 flags;
6650
6651         if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
6652                 return 0;
6653
6654         resp = bp->hwrm_cmd_resp_addr;
6655         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
6656
6657         mutex_lock(&bp->hwrm_cmd_lock);
6658         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6659         if (rc)
6660                 goto hwrm_cfa_adv_qcaps_exit;
6661
6662         flags = le32_to_cpu(resp->flags);
6663         if (flags &
6664             CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED)
6665                 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX;
6666
6667 hwrm_cfa_adv_qcaps_exit:
6668         mutex_unlock(&bp->hwrm_cmd_lock);
6669         return rc;
6670 }
6671
6672 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6673 {
6674         struct hwrm_func_reset_input req = {0};
6675
6676         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6677         req.enables = 0;
6678
6679         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6680 }
6681
6682 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6683 {
6684         int rc = 0;
6685         struct hwrm_queue_qportcfg_input req = {0};
6686         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6687         u8 i, j, *qptr;
6688         bool no_rdma;
6689
6690         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6691
6692         mutex_lock(&bp->hwrm_cmd_lock);
6693         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6694         if (rc)
6695                 goto qportcfg_exit;
6696
6697         if (!resp->max_configurable_queues) {
6698                 rc = -EINVAL;
6699                 goto qportcfg_exit;
6700         }
6701         bp->max_tc = resp->max_configurable_queues;
6702         bp->max_lltc = resp->max_configurable_lossless_queues;
6703         if (bp->max_tc > BNXT_MAX_QUEUE)
6704                 bp->max_tc = BNXT_MAX_QUEUE;
6705
6706         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6707         qptr = &resp->queue_id0;
6708         for (i = 0, j = 0; i < bp->max_tc; i++) {
6709                 bp->q_info[j].queue_id = *qptr;
6710                 bp->q_ids[i] = *qptr++;
6711                 bp->q_info[j].queue_profile = *qptr++;
6712                 bp->tc_to_qidx[j] = j;
6713                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6714                     (no_rdma && BNXT_PF(bp)))
6715                         j++;
6716         }
6717         bp->max_q = bp->max_tc;
6718         bp->max_tc = max_t(u8, j, 1);
6719
6720         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6721                 bp->max_tc = 1;
6722
6723         if (bp->max_lltc > bp->max_tc)
6724                 bp->max_lltc = bp->max_tc;
6725
6726 qportcfg_exit:
6727         mutex_unlock(&bp->hwrm_cmd_lock);
6728         return rc;
6729 }
6730
6731 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6732 {
6733         int rc;
6734         struct hwrm_ver_get_input req = {0};
6735         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6736         u32 dev_caps_cfg;
6737
6738         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6739         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6740         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6741         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6742         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6743         mutex_lock(&bp->hwrm_cmd_lock);
6744         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6745         if (rc)
6746                 goto hwrm_ver_get_exit;
6747
6748         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6749
6750         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6751                              resp->hwrm_intf_min_8b << 8 |
6752                              resp->hwrm_intf_upd_8b;
6753         if (resp->hwrm_intf_maj_8b < 1) {
6754                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6755                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6756                             resp->hwrm_intf_upd_8b);
6757                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6758         }
6759         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6760                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6761                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6762
6763         if (strlen(resp->active_pkg_name)) {
6764                 int fw_ver_len = strlen(bp->fw_ver_str);
6765
6766                 snprintf(bp->fw_ver_str + fw_ver_len,
6767                          FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
6768                          resp->active_pkg_name);
6769                 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
6770         }
6771
6772         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6773         if (!bp->hwrm_cmd_timeout)
6774                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6775
6776         if (resp->hwrm_intf_maj_8b >= 1) {
6777                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6778                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6779         }
6780         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6781                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6782
6783         bp->chip_num = le16_to_cpu(resp->chip_num);
6784         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6785             !resp->chip_metal)
6786                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6787
6788         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6789         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6790             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6791                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6792
6793         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6794                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6795
6796         if (dev_caps_cfg &
6797             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6798                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6799
6800         if (dev_caps_cfg &
6801             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6802                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6803
6804         if (dev_caps_cfg &
6805             VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
6806                 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
6807
6808 hwrm_ver_get_exit:
6809         mutex_unlock(&bp->hwrm_cmd_lock);
6810         return rc;
6811 }
6812
6813 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6814 {
6815         struct hwrm_fw_set_time_input req = {0};
6816         struct tm tm;
6817         time64_t now = ktime_get_real_seconds();
6818
6819         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6820             bp->hwrm_spec_code < 0x10400)
6821                 return -EOPNOTSUPP;
6822
6823         time64_to_tm(now, 0, &tm);
6824         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6825         req.year = cpu_to_le16(1900 + tm.tm_year);
6826         req.month = 1 + tm.tm_mon;
6827         req.day = tm.tm_mday;
6828         req.hour = tm.tm_hour;
6829         req.minute = tm.tm_min;
6830         req.second = tm.tm_sec;
6831         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6832 }
6833
6834 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6835 {
6836         int rc;
6837         struct bnxt_pf_info *pf = &bp->pf;
6838         struct hwrm_port_qstats_input req = {0};
6839
6840         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6841                 return 0;
6842
6843         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6844         req.port_id = cpu_to_le16(pf->port_id);
6845         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6846         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6847         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6848         return rc;
6849 }
6850
6851 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6852 {
6853         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6854         struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6855         struct hwrm_port_qstats_ext_input req = {0};
6856         struct bnxt_pf_info *pf = &bp->pf;
6857         u32 tx_stat_size;
6858         int rc;
6859
6860         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6861                 return 0;
6862
6863         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6864         req.port_id = cpu_to_le16(pf->port_id);
6865         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6866         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6867         tx_stat_size = bp->hw_tx_port_stats_ext ?
6868                        sizeof(*bp->hw_tx_port_stats_ext) : 0;
6869         req.tx_stat_size = cpu_to_le16(tx_stat_size);
6870         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6871         mutex_lock(&bp->hwrm_cmd_lock);
6872         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6873         if (!rc) {
6874                 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6875                 bp->fw_tx_stats_ext_size = tx_stat_size ?
6876                         le16_to_cpu(resp->tx_stat_size) / 8 : 0;
6877         } else {
6878                 bp->fw_rx_stats_ext_size = 0;
6879                 bp->fw_tx_stats_ext_size = 0;
6880         }
6881         if (bp->fw_tx_stats_ext_size <=
6882             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6883                 mutex_unlock(&bp->hwrm_cmd_lock);
6884                 bp->pri2cos_valid = 0;
6885                 return rc;
6886         }
6887
6888         bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6889         req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6890
6891         rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6892         if (!rc) {
6893                 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6894                 u8 *pri2cos;
6895                 int i, j;
6896
6897                 resp2 = bp->hwrm_cmd_resp_addr;
6898                 pri2cos = &resp2->pri0_cos_queue_id;
6899                 for (i = 0; i < 8; i++) {
6900                         u8 queue_id = pri2cos[i];
6901
6902                         for (j = 0; j < bp->max_q; j++) {
6903                                 if (bp->q_ids[j] == queue_id)
6904                                         bp->pri2cos[i] = j;
6905                         }
6906                 }
6907                 bp->pri2cos_valid = 1;
6908         }
6909         mutex_unlock(&bp->hwrm_cmd_lock);
6910         return rc;
6911 }
6912
6913 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp)
6914 {
6915         struct hwrm_pcie_qstats_input req = {0};
6916
6917         if (!(bp->flags & BNXT_FLAG_PCIE_STATS))
6918                 return 0;
6919
6920         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
6921         req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats));
6922         req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map);
6923         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6924 }
6925
6926 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6927 {
6928         if (bp->vxlan_port_cnt) {
6929                 bnxt_hwrm_tunnel_dst_port_free(
6930                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6931         }
6932         bp->vxlan_port_cnt = 0;
6933         if (bp->nge_port_cnt) {
6934                 bnxt_hwrm_tunnel_dst_port_free(
6935                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6936         }
6937         bp->nge_port_cnt = 0;
6938 }
6939
6940 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6941 {
6942         int rc, i;
6943         u32 tpa_flags = 0;
6944
6945         if (set_tpa)
6946                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6947         for (i = 0; i < bp->nr_vnics; i++) {
6948                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6949                 if (rc) {
6950                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6951                                    i, rc);
6952                         return rc;
6953                 }
6954         }
6955         return 0;
6956 }
6957
6958 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6959 {
6960         int i;
6961
6962         for (i = 0; i < bp->nr_vnics; i++)
6963                 bnxt_hwrm_vnic_set_rss(bp, i, false);
6964 }
6965
6966 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6967                                     bool irq_re_init)
6968 {
6969         if (bp->vnic_info) {
6970                 bnxt_hwrm_clear_vnic_filter(bp);
6971                 /* clear all RSS setting before free vnic ctx */
6972                 bnxt_hwrm_clear_vnic_rss(bp);
6973                 bnxt_hwrm_vnic_ctx_free(bp);
6974                 /* before free the vnic, undo the vnic tpa settings */
6975                 if (bp->flags & BNXT_FLAG_TPA)
6976                         bnxt_set_tpa(bp, false);
6977                 bnxt_hwrm_vnic_free(bp);
6978         }
6979         bnxt_hwrm_ring_free(bp, close_path);
6980         bnxt_hwrm_ring_grp_free(bp);
6981         if (irq_re_init) {
6982                 bnxt_hwrm_stat_ctx_free(bp);
6983                 bnxt_hwrm_free_tunnel_ports(bp);
6984         }
6985 }
6986
6987 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6988 {
6989         struct hwrm_func_cfg_input req = {0};
6990         int rc;
6991
6992         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6993         req.fid = cpu_to_le16(0xffff);
6994         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6995         if (br_mode == BRIDGE_MODE_VEB)
6996                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6997         else if (br_mode == BRIDGE_MODE_VEPA)
6998                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6999         else
7000                 return -EINVAL;
7001         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7002         if (rc)
7003                 rc = -EIO;
7004         return rc;
7005 }
7006
7007 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
7008 {
7009         struct hwrm_func_cfg_input req = {0};
7010         int rc;
7011
7012         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
7013                 return 0;
7014
7015         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7016         req.fid = cpu_to_le16(0xffff);
7017         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
7018         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
7019         if (size == 128)
7020                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
7021
7022         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7023         if (rc)
7024                 rc = -EIO;
7025         return rc;
7026 }
7027
7028 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7029 {
7030         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
7031         int rc;
7032
7033         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
7034                 goto skip_rss_ctx;
7035
7036         /* allocate context for vnic */
7037         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
7038         if (rc) {
7039                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7040                            vnic_id, rc);
7041                 goto vnic_setup_err;
7042         }
7043         bp->rsscos_nr_ctxs++;
7044
7045         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7046                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
7047                 if (rc) {
7048                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
7049                                    vnic_id, rc);
7050                         goto vnic_setup_err;
7051                 }
7052                 bp->rsscos_nr_ctxs++;
7053         }
7054
7055 skip_rss_ctx:
7056         /* configure default vnic, ring grp */
7057         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7058         if (rc) {
7059                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7060                            vnic_id, rc);
7061                 goto vnic_setup_err;
7062         }
7063
7064         /* Enable RSS hashing on vnic */
7065         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
7066         if (rc) {
7067                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
7068                            vnic_id, rc);
7069                 goto vnic_setup_err;
7070         }
7071
7072         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7073                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7074                 if (rc) {
7075                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7076                                    vnic_id, rc);
7077                 }
7078         }
7079
7080 vnic_setup_err:
7081         return rc;
7082 }
7083
7084 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
7085 {
7086         int rc, i, nr_ctxs;
7087
7088         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
7089         for (i = 0; i < nr_ctxs; i++) {
7090                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
7091                 if (rc) {
7092                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
7093                                    vnic_id, i, rc);
7094                         break;
7095                 }
7096                 bp->rsscos_nr_ctxs++;
7097         }
7098         if (i < nr_ctxs)
7099                 return -ENOMEM;
7100
7101         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
7102         if (rc) {
7103                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
7104                            vnic_id, rc);
7105                 return rc;
7106         }
7107         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7108         if (rc) {
7109                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7110                            vnic_id, rc);
7111                 return rc;
7112         }
7113         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7114                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7115                 if (rc) {
7116                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7117                                    vnic_id, rc);
7118                 }
7119         }
7120         return rc;
7121 }
7122
7123 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7124 {
7125         if (bp->flags & BNXT_FLAG_CHIP_P5)
7126                 return __bnxt_setup_vnic_p5(bp, vnic_id);
7127         else
7128                 return __bnxt_setup_vnic(bp, vnic_id);
7129 }
7130
7131 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7132 {
7133 #ifdef CONFIG_RFS_ACCEL
7134         int i, rc = 0;
7135
7136         for (i = 0; i < bp->rx_nr_rings; i++) {
7137                 struct bnxt_vnic_info *vnic;
7138                 u16 vnic_id = i + 1;
7139                 u16 ring_id = i;
7140
7141                 if (vnic_id >= bp->nr_vnics)
7142                         break;
7143
7144                 vnic = &bp->vnic_info[vnic_id];
7145                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7146                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7147                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7148                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7149                 if (rc) {
7150                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7151                                    vnic_id, rc);
7152                         break;
7153                 }
7154                 rc = bnxt_setup_vnic(bp, vnic_id);
7155                 if (rc)
7156                         break;
7157         }
7158         return rc;
7159 #else
7160         return 0;
7161 #endif
7162 }
7163
7164 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7165 static bool bnxt_promisc_ok(struct bnxt *bp)
7166 {
7167 #ifdef CONFIG_BNXT_SRIOV
7168         if (BNXT_VF(bp) && !bp->vf.vlan)
7169                 return false;
7170 #endif
7171         return true;
7172 }
7173
7174 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7175 {
7176         unsigned int rc = 0;
7177
7178         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7179         if (rc) {
7180                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7181                            rc);
7182                 return rc;
7183         }
7184
7185         rc = bnxt_hwrm_vnic_cfg(bp, 1);
7186         if (rc) {
7187                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7188                            rc);
7189                 return rc;
7190         }
7191         return rc;
7192 }
7193
7194 static int bnxt_cfg_rx_mode(struct bnxt *);
7195 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7196
7197 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7198 {
7199         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7200         int rc = 0;
7201         unsigned int rx_nr_rings = bp->rx_nr_rings;
7202
7203         if (irq_re_init) {
7204                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7205                 if (rc) {
7206                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7207                                    rc);
7208                         goto err_out;
7209                 }
7210         }
7211
7212         rc = bnxt_hwrm_ring_alloc(bp);
7213         if (rc) {
7214                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7215                 goto err_out;
7216         }
7217
7218         rc = bnxt_hwrm_ring_grp_alloc(bp);
7219         if (rc) {
7220                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7221                 goto err_out;
7222         }
7223
7224         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7225                 rx_nr_rings--;
7226
7227         /* default vnic 0 */
7228         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7229         if (rc) {
7230                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7231                 goto err_out;
7232         }
7233
7234         rc = bnxt_setup_vnic(bp, 0);
7235         if (rc)
7236                 goto err_out;
7237
7238         if (bp->flags & BNXT_FLAG_RFS) {
7239                 rc = bnxt_alloc_rfs_vnics(bp);
7240                 if (rc)
7241                         goto err_out;
7242         }
7243
7244         if (bp->flags & BNXT_FLAG_TPA) {
7245                 rc = bnxt_set_tpa(bp, true);
7246                 if (rc)
7247                         goto err_out;
7248         }
7249
7250         if (BNXT_VF(bp))
7251                 bnxt_update_vf_mac(bp);
7252
7253         /* Filter for default vnic 0 */
7254         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7255         if (rc) {
7256                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7257                 goto err_out;
7258         }
7259         vnic->uc_filter_count = 1;
7260
7261         vnic->rx_mask = 0;
7262         if (bp->dev->flags & IFF_BROADCAST)
7263                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7264
7265         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7266                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7267
7268         if (bp->dev->flags & IFF_ALLMULTI) {
7269                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7270                 vnic->mc_list_count = 0;
7271         } else {
7272                 u32 mask = 0;
7273
7274                 bnxt_mc_list_updated(bp, &mask);
7275                 vnic->rx_mask |= mask;
7276         }
7277
7278         rc = bnxt_cfg_rx_mode(bp);
7279         if (rc)
7280                 goto err_out;
7281
7282         rc = bnxt_hwrm_set_coal(bp);
7283         if (rc)
7284                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7285                                 rc);
7286
7287         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7288                 rc = bnxt_setup_nitroa0_vnic(bp);
7289                 if (rc)
7290                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7291                                    rc);
7292         }
7293
7294         if (BNXT_VF(bp)) {
7295                 bnxt_hwrm_func_qcfg(bp);
7296                 netdev_update_features(bp->dev);
7297         }
7298
7299         return 0;
7300
7301 err_out:
7302         bnxt_hwrm_resource_free(bp, 0, true);
7303
7304         return rc;
7305 }
7306
7307 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7308 {
7309         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7310         return 0;
7311 }
7312
7313 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7314 {
7315         bnxt_init_cp_rings(bp);
7316         bnxt_init_rx_rings(bp);
7317         bnxt_init_tx_rings(bp);
7318         bnxt_init_ring_grps(bp, irq_re_init);
7319         bnxt_init_vnics(bp);
7320
7321         return bnxt_init_chip(bp, irq_re_init);
7322 }
7323
7324 static int bnxt_set_real_num_queues(struct bnxt *bp)
7325 {
7326         int rc;
7327         struct net_device *dev = bp->dev;
7328
7329         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7330                                           bp->tx_nr_rings_xdp);
7331         if (rc)
7332                 return rc;
7333
7334         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7335         if (rc)
7336                 return rc;
7337
7338 #ifdef CONFIG_RFS_ACCEL
7339         if (bp->flags & BNXT_FLAG_RFS)
7340                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7341 #endif
7342
7343         return rc;
7344 }
7345
7346 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7347                            bool shared)
7348 {
7349         int _rx = *rx, _tx = *tx;
7350
7351         if (shared) {
7352                 *rx = min_t(int, _rx, max);
7353                 *tx = min_t(int, _tx, max);
7354         } else {
7355                 if (max < 2)
7356                         return -ENOMEM;
7357
7358                 while (_rx + _tx > max) {
7359                         if (_rx > _tx && _rx > 1)
7360                                 _rx--;
7361                         else if (_tx > 1)
7362                                 _tx--;
7363                 }
7364                 *rx = _rx;
7365                 *tx = _tx;
7366         }
7367         return 0;
7368 }
7369
7370 static void bnxt_setup_msix(struct bnxt *bp)
7371 {
7372         const int len = sizeof(bp->irq_tbl[0].name);
7373         struct net_device *dev = bp->dev;
7374         int tcs, i;
7375
7376         tcs = netdev_get_num_tc(dev);
7377         if (tcs > 1) {
7378                 int i, off, count;
7379
7380                 for (i = 0; i < tcs; i++) {
7381                         count = bp->tx_nr_rings_per_tc;
7382                         off = i * count;
7383                         netdev_set_tc_queue(dev, i, count, off);
7384                 }
7385         }
7386
7387         for (i = 0; i < bp->cp_nr_rings; i++) {
7388                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7389                 char *attr;
7390
7391                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7392                         attr = "TxRx";
7393                 else if (i < bp->rx_nr_rings)
7394                         attr = "rx";
7395                 else
7396                         attr = "tx";
7397
7398                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7399                          attr, i);
7400                 bp->irq_tbl[map_idx].handler = bnxt_msix;
7401         }
7402 }
7403
7404 static void bnxt_setup_inta(struct bnxt *bp)
7405 {
7406         const int len = sizeof(bp->irq_tbl[0].name);
7407
7408         if (netdev_get_num_tc(bp->dev))
7409                 netdev_reset_tc(bp->dev);
7410
7411         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7412                  0);
7413         bp->irq_tbl[0].handler = bnxt_inta;
7414 }
7415
7416 static int bnxt_setup_int_mode(struct bnxt *bp)
7417 {
7418         int rc;
7419
7420         if (bp->flags & BNXT_FLAG_USING_MSIX)
7421                 bnxt_setup_msix(bp);
7422         else
7423                 bnxt_setup_inta(bp);
7424
7425         rc = bnxt_set_real_num_queues(bp);
7426         return rc;
7427 }
7428
7429 #ifdef CONFIG_RFS_ACCEL
7430 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7431 {
7432         return bp->hw_resc.max_rsscos_ctxs;
7433 }
7434
7435 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7436 {
7437         return bp->hw_resc.max_vnics;
7438 }
7439 #endif
7440
7441 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7442 {
7443         return bp->hw_resc.max_stat_ctxs;
7444 }
7445
7446 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7447 {
7448         return bp->hw_resc.max_cp_rings;
7449 }
7450
7451 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7452 {
7453         unsigned int cp = bp->hw_resc.max_cp_rings;
7454
7455         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7456                 cp -= bnxt_get_ulp_msix_num(bp);
7457
7458         return cp;
7459 }
7460
7461 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7462 {
7463         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7464
7465         if (bp->flags & BNXT_FLAG_CHIP_P5)
7466                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7467
7468         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7469 }
7470
7471 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7472 {
7473         bp->hw_resc.max_irqs = max_irqs;
7474 }
7475
7476 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7477 {
7478         unsigned int cp;
7479
7480         cp = bnxt_get_max_func_cp_rings_for_en(bp);
7481         if (bp->flags & BNXT_FLAG_CHIP_P5)
7482                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7483         else
7484                 return cp - bp->cp_nr_rings;
7485 }
7486
7487 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7488 {
7489         return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
7490 }
7491
7492 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7493 {
7494         int max_cp = bnxt_get_max_func_cp_rings(bp);
7495         int max_irq = bnxt_get_max_func_irqs(bp);
7496         int total_req = bp->cp_nr_rings + num;
7497         int max_idx, avail_msix;
7498
7499         max_idx = bp->total_irqs;
7500         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7501                 max_idx = min_t(int, bp->total_irqs, max_cp);
7502         avail_msix = max_idx - bp->cp_nr_rings;
7503         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7504                 return avail_msix;
7505
7506         if (max_irq < total_req) {
7507                 num = max_irq - bp->cp_nr_rings;
7508                 if (num <= 0)
7509                         return 0;
7510         }
7511         return num;
7512 }
7513
7514 static int bnxt_get_num_msix(struct bnxt *bp)
7515 {
7516         if (!BNXT_NEW_RM(bp))
7517                 return bnxt_get_max_func_irqs(bp);
7518
7519         return bnxt_nq_rings_in_use(bp);
7520 }
7521
7522 static int bnxt_init_msix(struct bnxt *bp)
7523 {
7524         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7525         struct msix_entry *msix_ent;
7526
7527         total_vecs = bnxt_get_num_msix(bp);
7528         max = bnxt_get_max_func_irqs(bp);
7529         if (total_vecs > max)
7530                 total_vecs = max;
7531
7532         if (!total_vecs)
7533                 return 0;
7534
7535         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7536         if (!msix_ent)
7537                 return -ENOMEM;
7538
7539         for (i = 0; i < total_vecs; i++) {
7540                 msix_ent[i].entry = i;
7541                 msix_ent[i].vector = 0;
7542         }
7543
7544         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7545                 min = 2;
7546
7547         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7548         ulp_msix = bnxt_get_ulp_msix_num(bp);
7549         if (total_vecs < 0 || total_vecs < ulp_msix) {
7550                 rc = -ENODEV;
7551                 goto msix_setup_exit;
7552         }
7553
7554         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7555         if (bp->irq_tbl) {
7556                 for (i = 0; i < total_vecs; i++)
7557                         bp->irq_tbl[i].vector = msix_ent[i].vector;
7558
7559                 bp->total_irqs = total_vecs;
7560                 /* Trim rings based upon num of vectors allocated */
7561                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7562                                      total_vecs - ulp_msix, min == 1);
7563                 if (rc)
7564                         goto msix_setup_exit;
7565
7566                 bp->cp_nr_rings = (min == 1) ?
7567                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7568                                   bp->tx_nr_rings + bp->rx_nr_rings;
7569
7570         } else {
7571                 rc = -ENOMEM;
7572                 goto msix_setup_exit;
7573         }
7574         bp->flags |= BNXT_FLAG_USING_MSIX;
7575         kfree(msix_ent);
7576         return 0;
7577
7578 msix_setup_exit:
7579         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7580         kfree(bp->irq_tbl);
7581         bp->irq_tbl = NULL;
7582         pci_disable_msix(bp->pdev);
7583         kfree(msix_ent);
7584         return rc;
7585 }
7586
7587 static int bnxt_init_inta(struct bnxt *bp)
7588 {
7589         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7590         if (!bp->irq_tbl)
7591                 return -ENOMEM;
7592
7593         bp->total_irqs = 1;
7594         bp->rx_nr_rings = 1;
7595         bp->tx_nr_rings = 1;
7596         bp->cp_nr_rings = 1;
7597         bp->flags |= BNXT_FLAG_SHARED_RINGS;
7598         bp->irq_tbl[0].vector = bp->pdev->irq;
7599         return 0;
7600 }
7601
7602 static int bnxt_init_int_mode(struct bnxt *bp)
7603 {
7604         int rc = 0;
7605
7606         if (bp->flags & BNXT_FLAG_MSIX_CAP)
7607                 rc = bnxt_init_msix(bp);
7608
7609         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7610                 /* fallback to INTA */
7611                 rc = bnxt_init_inta(bp);
7612         }
7613         return rc;
7614 }
7615
7616 static void bnxt_clear_int_mode(struct bnxt *bp)
7617 {
7618         if (bp->flags & BNXT_FLAG_USING_MSIX)
7619                 pci_disable_msix(bp->pdev);
7620
7621         kfree(bp->irq_tbl);
7622         bp->irq_tbl = NULL;
7623         bp->flags &= ~BNXT_FLAG_USING_MSIX;
7624 }
7625
7626 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
7627 {
7628         int tcs = netdev_get_num_tc(bp->dev);
7629         bool irq_cleared = false;
7630         int rc;
7631
7632         if (!bnxt_need_reserve_rings(bp))
7633                 return 0;
7634
7635         if (irq_re_init && BNXT_NEW_RM(bp) &&
7636             bnxt_get_num_msix(bp) != bp->total_irqs) {
7637                 bnxt_ulp_irq_stop(bp);
7638                 bnxt_clear_int_mode(bp);
7639                 irq_cleared = true;
7640         }
7641         rc = __bnxt_reserve_rings(bp);
7642         if (irq_cleared) {
7643                 if (!rc)
7644                         rc = bnxt_init_int_mode(bp);
7645                 bnxt_ulp_irq_restart(bp, rc);
7646         }
7647         if (rc) {
7648                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7649                 return rc;
7650         }
7651         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7652                 netdev_err(bp->dev, "tx ring reservation failure\n");
7653                 netdev_reset_tc(bp->dev);
7654                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7655                 return -ENOMEM;
7656         }
7657         return 0;
7658 }
7659
7660 static void bnxt_free_irq(struct bnxt *bp)
7661 {
7662         struct bnxt_irq *irq;
7663         int i;
7664
7665 #ifdef CONFIG_RFS_ACCEL
7666         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7667         bp->dev->rx_cpu_rmap = NULL;
7668 #endif
7669         if (!bp->irq_tbl || !bp->bnapi)
7670                 return;
7671
7672         for (i = 0; i < bp->cp_nr_rings; i++) {
7673                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7674
7675                 irq = &bp->irq_tbl[map_idx];
7676                 if (irq->requested) {
7677                         if (irq->have_cpumask) {
7678                                 irq_set_affinity_hint(irq->vector, NULL);
7679                                 free_cpumask_var(irq->cpu_mask);
7680                                 irq->have_cpumask = 0;
7681                         }
7682                         free_irq(irq->vector, bp->bnapi[i]);
7683                 }
7684
7685                 irq->requested = 0;
7686         }
7687 }
7688
7689 static int bnxt_request_irq(struct bnxt *bp)
7690 {
7691         int i, j, rc = 0;
7692         unsigned long flags = 0;
7693 #ifdef CONFIG_RFS_ACCEL
7694         struct cpu_rmap *rmap;
7695 #endif
7696
7697         rc = bnxt_setup_int_mode(bp);
7698         if (rc) {
7699                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7700                            rc);
7701                 return rc;
7702         }
7703 #ifdef CONFIG_RFS_ACCEL
7704         rmap = bp->dev->rx_cpu_rmap;
7705 #endif
7706         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7707                 flags = IRQF_SHARED;
7708
7709         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7710                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7711                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7712
7713 #ifdef CONFIG_RFS_ACCEL
7714                 if (rmap && bp->bnapi[i]->rx_ring) {
7715                         rc = irq_cpu_rmap_add(rmap, irq->vector);
7716                         if (rc)
7717                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7718                                             j);
7719                         j++;
7720                 }
7721 #endif
7722                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7723                                  bp->bnapi[i]);
7724                 if (rc)
7725                         break;
7726
7727                 irq->requested = 1;
7728
7729                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7730                         int numa_node = dev_to_node(&bp->pdev->dev);
7731
7732                         irq->have_cpumask = 1;
7733                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7734                                         irq->cpu_mask);
7735                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7736                         if (rc) {
7737                                 netdev_warn(bp->dev,
7738                                             "Set affinity failed, IRQ = %d\n",
7739                                             irq->vector);
7740                                 break;
7741                         }
7742                 }
7743         }
7744         return rc;
7745 }
7746
7747 static void bnxt_del_napi(struct bnxt *bp)
7748 {
7749         int i;
7750
7751         if (!bp->bnapi)
7752                 return;
7753
7754         for (i = 0; i < bp->cp_nr_rings; i++) {
7755                 struct bnxt_napi *bnapi = bp->bnapi[i];
7756
7757                 napi_hash_del(&bnapi->napi);
7758                 netif_napi_del(&bnapi->napi);
7759         }
7760         /* We called napi_hash_del() before netif_napi_del(), we need
7761          * to respect an RCU grace period before freeing napi structures.
7762          */
7763         synchronize_net();
7764 }
7765
7766 static void bnxt_init_napi(struct bnxt *bp)
7767 {
7768         int i;
7769         unsigned int cp_nr_rings = bp->cp_nr_rings;
7770         struct bnxt_napi *bnapi;
7771
7772         if (bp->flags & BNXT_FLAG_USING_MSIX) {
7773                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7774
7775                 if (bp->flags & BNXT_FLAG_CHIP_P5)
7776                         poll_fn = bnxt_poll_p5;
7777                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7778                         cp_nr_rings--;
7779                 for (i = 0; i < cp_nr_rings; i++) {
7780                         bnapi = bp->bnapi[i];
7781                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7782                 }
7783                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7784                         bnapi = bp->bnapi[cp_nr_rings];
7785                         netif_napi_add(bp->dev, &bnapi->napi,
7786                                        bnxt_poll_nitroa0, 64);
7787                 }
7788         } else {
7789                 bnapi = bp->bnapi[0];
7790                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7791         }
7792 }
7793
7794 static void bnxt_disable_napi(struct bnxt *bp)
7795 {
7796         int i;
7797
7798         if (!bp->bnapi)
7799                 return;
7800
7801         for (i = 0; i < bp->cp_nr_rings; i++) {
7802                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7803
7804                 if (bp->bnapi[i]->rx_ring)
7805                         cancel_work_sync(&cpr->dim.work);
7806
7807                 napi_disable(&bp->bnapi[i]->napi);
7808         }
7809 }
7810
7811 static void bnxt_enable_napi(struct bnxt *bp)
7812 {
7813         int i;
7814
7815         for (i = 0; i < bp->cp_nr_rings; i++) {
7816                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7817                 bp->bnapi[i]->in_reset = false;
7818
7819                 if (bp->bnapi[i]->rx_ring) {
7820                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7821                         cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7822                 }
7823                 napi_enable(&bp->bnapi[i]->napi);
7824         }
7825 }
7826
7827 void bnxt_tx_disable(struct bnxt *bp)
7828 {
7829         int i;
7830         struct bnxt_tx_ring_info *txr;
7831
7832         if (bp->tx_ring) {
7833                 for (i = 0; i < bp->tx_nr_rings; i++) {
7834                         txr = &bp->tx_ring[i];
7835                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
7836                 }
7837         }
7838         /* Stop all TX queues */
7839         netif_tx_disable(bp->dev);
7840         netif_carrier_off(bp->dev);
7841 }
7842
7843 void bnxt_tx_enable(struct bnxt *bp)
7844 {
7845         int i;
7846         struct bnxt_tx_ring_info *txr;
7847
7848         for (i = 0; i < bp->tx_nr_rings; i++) {
7849                 txr = &bp->tx_ring[i];
7850                 txr->dev_state = 0;
7851         }
7852         netif_tx_wake_all_queues(bp->dev);
7853         if (bp->link_info.link_up)
7854                 netif_carrier_on(bp->dev);
7855 }
7856
7857 static void bnxt_report_link(struct bnxt *bp)
7858 {
7859         if (bp->link_info.link_up) {
7860                 const char *duplex;
7861                 const char *flow_ctrl;
7862                 u32 speed;
7863                 u16 fec;
7864
7865                 netif_carrier_on(bp->dev);
7866                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7867                         duplex = "full";
7868                 else
7869                         duplex = "half";
7870                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7871                         flow_ctrl = "ON - receive & transmit";
7872                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7873                         flow_ctrl = "ON - transmit";
7874                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7875                         flow_ctrl = "ON - receive";
7876                 else
7877                         flow_ctrl = "none";
7878                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7879                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7880                             speed, duplex, flow_ctrl);
7881                 if (bp->flags & BNXT_FLAG_EEE_CAP)
7882                         netdev_info(bp->dev, "EEE is %s\n",
7883                                     bp->eee.eee_active ? "active" :
7884                                                          "not active");
7885                 fec = bp->link_info.fec_cfg;
7886                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7887                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7888                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7889                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7890                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7891         } else {
7892                 netif_carrier_off(bp->dev);
7893                 netdev_err(bp->dev, "NIC Link is Down\n");
7894         }
7895 }
7896
7897 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7898 {
7899         int rc = 0;
7900         struct hwrm_port_phy_qcaps_input req = {0};
7901         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7902         struct bnxt_link_info *link_info = &bp->link_info;
7903
7904         if (bp->hwrm_spec_code < 0x10201)
7905                 return 0;
7906
7907         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7908
7909         mutex_lock(&bp->hwrm_cmd_lock);
7910         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7911         if (rc)
7912                 goto hwrm_phy_qcaps_exit;
7913
7914         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7915                 struct ethtool_eee *eee = &bp->eee;
7916                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7917
7918                 bp->flags |= BNXT_FLAG_EEE_CAP;
7919                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7920                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7921                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7922                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7923                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7924         }
7925         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7926                 if (bp->test_info)
7927                         bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7928         }
7929         if (resp->supported_speeds_auto_mode)
7930                 link_info->support_auto_speeds =
7931                         le16_to_cpu(resp->supported_speeds_auto_mode);
7932
7933         bp->port_count = resp->port_cnt;
7934
7935 hwrm_phy_qcaps_exit:
7936         mutex_unlock(&bp->hwrm_cmd_lock);
7937         return rc;
7938 }
7939
7940 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7941 {
7942         int rc = 0;
7943         struct bnxt_link_info *link_info = &bp->link_info;
7944         struct hwrm_port_phy_qcfg_input req = {0};
7945         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7946         u8 link_up = link_info->link_up;
7947         u16 diff;
7948
7949         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7950
7951         mutex_lock(&bp->hwrm_cmd_lock);
7952         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7953         if (rc) {
7954                 mutex_unlock(&bp->hwrm_cmd_lock);
7955                 return rc;
7956         }
7957
7958         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7959         link_info->phy_link_status = resp->link;
7960         link_info->duplex = resp->duplex_cfg;
7961         if (bp->hwrm_spec_code >= 0x10800)
7962                 link_info->duplex = resp->duplex_state;
7963         link_info->pause = resp->pause;
7964         link_info->auto_mode = resp->auto_mode;
7965         link_info->auto_pause_setting = resp->auto_pause;
7966         link_info->lp_pause = resp->link_partner_adv_pause;
7967         link_info->force_pause_setting = resp->force_pause;
7968         link_info->duplex_setting = resp->duplex_cfg;
7969         if (link_info->phy_link_status == BNXT_LINK_LINK)
7970                 link_info->link_speed = le16_to_cpu(resp->link_speed);
7971         else
7972                 link_info->link_speed = 0;
7973         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
7974         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7975         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
7976         link_info->lp_auto_link_speeds =
7977                 le16_to_cpu(resp->link_partner_adv_speeds);
7978         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7979         link_info->phy_ver[0] = resp->phy_maj;
7980         link_info->phy_ver[1] = resp->phy_min;
7981         link_info->phy_ver[2] = resp->phy_bld;
7982         link_info->media_type = resp->media_type;
7983         link_info->phy_type = resp->phy_type;
7984         link_info->transceiver = resp->xcvr_pkg_type;
7985         link_info->phy_addr = resp->eee_config_phy_addr &
7986                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
7987         link_info->module_status = resp->module_status;
7988
7989         if (bp->flags & BNXT_FLAG_EEE_CAP) {
7990                 struct ethtool_eee *eee = &bp->eee;
7991                 u16 fw_speeds;
7992
7993                 eee->eee_active = 0;
7994                 if (resp->eee_config_phy_addr &
7995                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7996                         eee->eee_active = 1;
7997                         fw_speeds = le16_to_cpu(
7998                                 resp->link_partner_adv_eee_link_speed_mask);
7999                         eee->lp_advertised =
8000                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8001                 }
8002
8003                 /* Pull initial EEE config */
8004                 if (!chng_link_state) {
8005                         if (resp->eee_config_phy_addr &
8006                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
8007                                 eee->eee_enabled = 1;
8008
8009                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
8010                         eee->advertised =
8011                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8012
8013                         if (resp->eee_config_phy_addr &
8014                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
8015                                 __le32 tmr;
8016
8017                                 eee->tx_lpi_enabled = 1;
8018                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
8019                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
8020                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
8021                         }
8022                 }
8023         }
8024
8025         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
8026         if (bp->hwrm_spec_code >= 0x10504)
8027                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
8028
8029         /* TODO: need to add more logic to report VF link */
8030         if (chng_link_state) {
8031                 if (link_info->phy_link_status == BNXT_LINK_LINK)
8032                         link_info->link_up = 1;
8033                 else
8034                         link_info->link_up = 0;
8035                 if (link_up != link_info->link_up)
8036                         bnxt_report_link(bp);
8037         } else {
8038                 /* alwasy link down if not require to update link state */
8039                 link_info->link_up = 0;
8040         }
8041         mutex_unlock(&bp->hwrm_cmd_lock);
8042
8043         if (!BNXT_SINGLE_PF(bp))
8044                 return 0;
8045
8046         diff = link_info->support_auto_speeds ^ link_info->advertising;
8047         if ((link_info->support_auto_speeds | diff) !=
8048             link_info->support_auto_speeds) {
8049                 /* An advertised speed is no longer supported, so we need to
8050                  * update the advertisement settings.  Caller holds RTNL
8051                  * so we can modify link settings.
8052                  */
8053                 link_info->advertising = link_info->support_auto_speeds;
8054                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
8055                         bnxt_hwrm_set_link_setting(bp, true, false);
8056         }
8057         return 0;
8058 }
8059
8060 static void bnxt_get_port_module_status(struct bnxt *bp)
8061 {
8062         struct bnxt_link_info *link_info = &bp->link_info;
8063         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
8064         u8 module_status;
8065
8066         if (bnxt_update_link(bp, true))
8067                 return;
8068
8069         module_status = link_info->module_status;
8070         switch (module_status) {
8071         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
8072         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
8073         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
8074                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
8075                             bp->pf.port_id);
8076                 if (bp->hwrm_spec_code >= 0x10201) {
8077                         netdev_warn(bp->dev, "Module part number %s\n",
8078                                     resp->phy_vendor_partnumber);
8079                 }
8080                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
8081                         netdev_warn(bp->dev, "TX is disabled\n");
8082                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
8083                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
8084         }
8085 }
8086
8087 static void
8088 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
8089 {
8090         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
8091                 if (bp->hwrm_spec_code >= 0x10201)
8092                         req->auto_pause =
8093                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
8094                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8095                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
8096                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8097                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
8098                 req->enables |=
8099                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8100         } else {
8101                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8102                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
8103                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8104                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
8105                 req->enables |=
8106                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
8107                 if (bp->hwrm_spec_code >= 0x10201) {
8108                         req->auto_pause = req->force_pause;
8109                         req->enables |= cpu_to_le32(
8110                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8111                 }
8112         }
8113 }
8114
8115 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8116                                       struct hwrm_port_phy_cfg_input *req)
8117 {
8118         u8 autoneg = bp->link_info.autoneg;
8119         u16 fw_link_speed = bp->link_info.req_link_speed;
8120         u16 advertising = bp->link_info.advertising;
8121
8122         if (autoneg & BNXT_AUTONEG_SPEED) {
8123                 req->auto_mode |=
8124                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8125
8126                 req->enables |= cpu_to_le32(
8127                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8128                 req->auto_link_speed_mask = cpu_to_le16(advertising);
8129
8130                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8131                 req->flags |=
8132                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8133         } else {
8134                 req->force_link_speed = cpu_to_le16(fw_link_speed);
8135                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8136         }
8137
8138         /* tell chimp that the setting takes effect immediately */
8139         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8140 }
8141
8142 int bnxt_hwrm_set_pause(struct bnxt *bp)
8143 {
8144         struct hwrm_port_phy_cfg_input req = {0};
8145         int rc;
8146
8147         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8148         bnxt_hwrm_set_pause_common(bp, &req);
8149
8150         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8151             bp->link_info.force_link_chng)
8152                 bnxt_hwrm_set_link_common(bp, &req);
8153
8154         mutex_lock(&bp->hwrm_cmd_lock);
8155         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8156         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8157                 /* since changing of pause setting doesn't trigger any link
8158                  * change event, the driver needs to update the current pause
8159                  * result upon successfully return of the phy_cfg command
8160                  */
8161                 bp->link_info.pause =
8162                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8163                 bp->link_info.auto_pause_setting = 0;
8164                 if (!bp->link_info.force_link_chng)
8165                         bnxt_report_link(bp);
8166         }
8167         bp->link_info.force_link_chng = false;
8168         mutex_unlock(&bp->hwrm_cmd_lock);
8169         return rc;
8170 }
8171
8172 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8173                               struct hwrm_port_phy_cfg_input *req)
8174 {
8175         struct ethtool_eee *eee = &bp->eee;
8176
8177         if (eee->eee_enabled) {
8178                 u16 eee_speeds;
8179                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8180
8181                 if (eee->tx_lpi_enabled)
8182                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8183                 else
8184                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8185
8186                 req->flags |= cpu_to_le32(flags);
8187                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8188                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8189                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8190         } else {
8191                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8192         }
8193 }
8194
8195 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8196 {
8197         struct hwrm_port_phy_cfg_input req = {0};
8198
8199         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8200         if (set_pause)
8201                 bnxt_hwrm_set_pause_common(bp, &req);
8202
8203         bnxt_hwrm_set_link_common(bp, &req);
8204
8205         if (set_eee)
8206                 bnxt_hwrm_set_eee(bp, &req);
8207         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8208 }
8209
8210 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8211 {
8212         struct hwrm_port_phy_cfg_input req = {0};
8213
8214         if (!BNXT_SINGLE_PF(bp))
8215                 return 0;
8216
8217         if (pci_num_vf(bp->pdev))
8218                 return 0;
8219
8220         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8221         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8222         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8223 }
8224
8225 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8226 {
8227         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8228         struct hwrm_func_drv_if_change_input req = {0};
8229         bool resc_reinit = false;
8230         int rc;
8231
8232         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8233                 return 0;
8234
8235         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8236         if (up)
8237                 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8238         mutex_lock(&bp->hwrm_cmd_lock);
8239         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8240         if (!rc && (resp->flags &
8241                     cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8242                 resc_reinit = true;
8243         mutex_unlock(&bp->hwrm_cmd_lock);
8244
8245         if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8246                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8247
8248                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8249                 hw_resc->resv_cp_rings = 0;
8250                 hw_resc->resv_stat_ctxs = 0;
8251                 hw_resc->resv_irqs = 0;
8252                 hw_resc->resv_tx_rings = 0;
8253                 hw_resc->resv_rx_rings = 0;
8254                 hw_resc->resv_hw_ring_grps = 0;
8255                 hw_resc->resv_vnics = 0;
8256                 bp->tx_nr_rings = 0;
8257                 bp->rx_nr_rings = 0;
8258         }
8259         return rc;
8260 }
8261
8262 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8263 {
8264         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8265         struct hwrm_port_led_qcaps_input req = {0};
8266         struct bnxt_pf_info *pf = &bp->pf;
8267         int rc;
8268
8269         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8270                 return 0;
8271
8272         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8273         req.port_id = cpu_to_le16(pf->port_id);
8274         mutex_lock(&bp->hwrm_cmd_lock);
8275         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8276         if (rc) {
8277                 mutex_unlock(&bp->hwrm_cmd_lock);
8278                 return rc;
8279         }
8280         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8281                 int i;
8282
8283                 bp->num_leds = resp->num_leds;
8284                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8285                                                  bp->num_leds);
8286                 for (i = 0; i < bp->num_leds; i++) {
8287                         struct bnxt_led_info *led = &bp->leds[i];
8288                         __le16 caps = led->led_state_caps;
8289
8290                         if (!led->led_group_id ||
8291                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
8292                                 bp->num_leds = 0;
8293                                 break;
8294                         }
8295                 }
8296         }
8297         mutex_unlock(&bp->hwrm_cmd_lock);
8298         return 0;
8299 }
8300
8301 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8302 {
8303         struct hwrm_wol_filter_alloc_input req = {0};
8304         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8305         int rc;
8306
8307         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8308         req.port_id = cpu_to_le16(bp->pf.port_id);
8309         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8310         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8311         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8312         mutex_lock(&bp->hwrm_cmd_lock);
8313         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8314         if (!rc)
8315                 bp->wol_filter_id = resp->wol_filter_id;
8316         mutex_unlock(&bp->hwrm_cmd_lock);
8317         return rc;
8318 }
8319
8320 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8321 {
8322         struct hwrm_wol_filter_free_input req = {0};
8323         int rc;
8324
8325         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8326         req.port_id = cpu_to_le16(bp->pf.port_id);
8327         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8328         req.wol_filter_id = bp->wol_filter_id;
8329         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8330         return rc;
8331 }
8332
8333 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8334 {
8335         struct hwrm_wol_filter_qcfg_input req = {0};
8336         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8337         u16 next_handle = 0;
8338         int rc;
8339
8340         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8341         req.port_id = cpu_to_le16(bp->pf.port_id);
8342         req.handle = cpu_to_le16(handle);
8343         mutex_lock(&bp->hwrm_cmd_lock);
8344         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8345         if (!rc) {
8346                 next_handle = le16_to_cpu(resp->next_handle);
8347                 if (next_handle != 0) {
8348                         if (resp->wol_type ==
8349                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8350                                 bp->wol = 1;
8351                                 bp->wol_filter_id = resp->wol_filter_id;
8352                         }
8353                 }
8354         }
8355         mutex_unlock(&bp->hwrm_cmd_lock);
8356         return next_handle;
8357 }
8358
8359 static void bnxt_get_wol_settings(struct bnxt *bp)
8360 {
8361         u16 handle = 0;
8362
8363         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8364                 return;
8365
8366         do {
8367                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8368         } while (handle && handle != 0xffff);
8369 }
8370
8371 #ifdef CONFIG_BNXT_HWMON
8372 static ssize_t bnxt_show_temp(struct device *dev,
8373                               struct device_attribute *devattr, char *buf)
8374 {
8375         struct hwrm_temp_monitor_query_input req = {0};
8376         struct hwrm_temp_monitor_query_output *resp;
8377         struct bnxt *bp = dev_get_drvdata(dev);
8378         u32 temp = 0;
8379
8380         resp = bp->hwrm_cmd_resp_addr;
8381         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8382         mutex_lock(&bp->hwrm_cmd_lock);
8383         if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8384                 temp = resp->temp * 1000; /* display millidegree */
8385         mutex_unlock(&bp->hwrm_cmd_lock);
8386
8387         return sprintf(buf, "%u\n", temp);
8388 }
8389 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8390
8391 static struct attribute *bnxt_attrs[] = {
8392         &sensor_dev_attr_temp1_input.dev_attr.attr,
8393         NULL
8394 };
8395 ATTRIBUTE_GROUPS(bnxt);
8396
8397 static void bnxt_hwmon_close(struct bnxt *bp)
8398 {
8399         if (bp->hwmon_dev) {
8400                 hwmon_device_unregister(bp->hwmon_dev);
8401                 bp->hwmon_dev = NULL;
8402         }
8403 }
8404
8405 static void bnxt_hwmon_open(struct bnxt *bp)
8406 {
8407         struct pci_dev *pdev = bp->pdev;
8408
8409         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8410                                                           DRV_MODULE_NAME, bp,
8411                                                           bnxt_groups);
8412         if (IS_ERR(bp->hwmon_dev)) {
8413                 bp->hwmon_dev = NULL;
8414                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8415         }
8416 }
8417 #else
8418 static void bnxt_hwmon_close(struct bnxt *bp)
8419 {
8420 }
8421
8422 static void bnxt_hwmon_open(struct bnxt *bp)
8423 {
8424 }
8425 #endif
8426
8427 static bool bnxt_eee_config_ok(struct bnxt *bp)
8428 {
8429         struct ethtool_eee *eee = &bp->eee;
8430         struct bnxt_link_info *link_info = &bp->link_info;
8431
8432         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8433                 return true;
8434
8435         if (eee->eee_enabled) {
8436                 u32 advertising =
8437                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8438
8439                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8440                         eee->eee_enabled = 0;
8441                         return false;
8442                 }
8443                 if (eee->advertised & ~advertising) {
8444                         eee->advertised = advertising & eee->supported;
8445                         return false;
8446                 }
8447         }
8448         return true;
8449 }
8450
8451 static int bnxt_update_phy_setting(struct bnxt *bp)
8452 {
8453         int rc;
8454         bool update_link = false;
8455         bool update_pause = false;
8456         bool update_eee = false;
8457         struct bnxt_link_info *link_info = &bp->link_info;
8458
8459         rc = bnxt_update_link(bp, true);
8460         if (rc) {
8461                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8462                            rc);
8463                 return rc;
8464         }
8465         if (!BNXT_SINGLE_PF(bp))
8466                 return 0;
8467
8468         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8469             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8470             link_info->req_flow_ctrl)
8471                 update_pause = true;
8472         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8473             link_info->force_pause_setting != link_info->req_flow_ctrl)
8474                 update_pause = true;
8475         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8476                 if (BNXT_AUTO_MODE(link_info->auto_mode))
8477                         update_link = true;
8478                 if (link_info->req_link_speed != link_info->force_link_speed)
8479                         update_link = true;
8480                 if (link_info->req_duplex != link_info->duplex_setting)
8481                         update_link = true;
8482         } else {
8483                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8484                         update_link = true;
8485                 if (link_info->advertising != link_info->auto_link_speeds)
8486                         update_link = true;
8487         }
8488
8489         /* The last close may have shutdown the link, so need to call
8490          * PHY_CFG to bring it back up.
8491          */
8492         if (!netif_carrier_ok(bp->dev))
8493                 update_link = true;
8494
8495         if (!bnxt_eee_config_ok(bp))
8496                 update_eee = true;
8497
8498         if (update_link)
8499                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8500         else if (update_pause)
8501                 rc = bnxt_hwrm_set_pause(bp);
8502         if (rc) {
8503                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8504                            rc);
8505                 return rc;
8506         }
8507
8508         return rc;
8509 }
8510
8511 /* Common routine to pre-map certain register block to different GRC window.
8512  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8513  * in PF and 3 windows in VF that can be customized to map in different
8514  * register blocks.
8515  */
8516 static void bnxt_preset_reg_win(struct bnxt *bp)
8517 {
8518         if (BNXT_PF(bp)) {
8519                 /* CAG registers map to GRC window #4 */
8520                 writel(BNXT_CAG_REG_BASE,
8521                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8522         }
8523 }
8524
8525 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8526
8527 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8528 {
8529         int rc = 0;
8530
8531         bnxt_preset_reg_win(bp);
8532         netif_carrier_off(bp->dev);
8533         if (irq_re_init) {
8534                 /* Reserve rings now if none were reserved at driver probe. */
8535                 rc = bnxt_init_dflt_ring_mode(bp);
8536                 if (rc) {
8537                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8538                         return rc;
8539                 }
8540         }
8541         rc = bnxt_reserve_rings(bp, irq_re_init);
8542         if (rc)
8543                 return rc;
8544         if ((bp->flags & BNXT_FLAG_RFS) &&
8545             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8546                 /* disable RFS if falling back to INTA */
8547                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8548                 bp->flags &= ~BNXT_FLAG_RFS;
8549         }
8550
8551         rc = bnxt_alloc_mem(bp, irq_re_init);
8552         if (rc) {
8553                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8554                 goto open_err_free_mem;
8555         }
8556
8557         if (irq_re_init) {
8558                 bnxt_init_napi(bp);
8559                 rc = bnxt_request_irq(bp);
8560                 if (rc) {
8561                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8562                         goto open_err_irq;
8563                 }
8564         }
8565
8566         bnxt_enable_napi(bp);
8567         bnxt_debug_dev_init(bp);
8568
8569         rc = bnxt_init_nic(bp, irq_re_init);
8570         if (rc) {
8571                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8572                 goto open_err;
8573         }
8574
8575         if (link_re_init) {
8576                 mutex_lock(&bp->link_lock);
8577                 rc = bnxt_update_phy_setting(bp);
8578                 mutex_unlock(&bp->link_lock);
8579                 if (rc) {
8580                         netdev_warn(bp->dev, "failed to update phy settings\n");
8581                         if (BNXT_SINGLE_PF(bp)) {
8582                                 bp->link_info.phy_retry = true;
8583                                 bp->link_info.phy_retry_expires =
8584                                         jiffies + 5 * HZ;
8585                         }
8586                 }
8587         }
8588
8589         if (irq_re_init)
8590                 udp_tunnel_get_rx_info(bp->dev);
8591
8592         set_bit(BNXT_STATE_OPEN, &bp->state);
8593         bnxt_enable_int(bp);
8594         /* Enable TX queues */
8595         bnxt_tx_enable(bp);
8596         mod_timer(&bp->timer, jiffies + bp->current_interval);
8597         /* Poll link status and check for SFP+ module status */
8598         bnxt_get_port_module_status(bp);
8599
8600         /* VF-reps may need to be re-opened after the PF is re-opened */
8601         if (BNXT_PF(bp))
8602                 bnxt_vf_reps_open(bp);
8603         return 0;
8604
8605 open_err:
8606         bnxt_debug_dev_exit(bp);
8607         bnxt_disable_napi(bp);
8608
8609 open_err_irq:
8610         bnxt_del_napi(bp);
8611
8612 open_err_free_mem:
8613         bnxt_free_skbs(bp);
8614         bnxt_free_irq(bp);
8615         bnxt_free_mem(bp, true);
8616         return rc;
8617 }
8618
8619 /* rtnl_lock held */
8620 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8621 {
8622         int rc = 0;
8623
8624         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8625         if (rc) {
8626                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8627                 dev_close(bp->dev);
8628         }
8629         return rc;
8630 }
8631
8632 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8633  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
8634  * self tests.
8635  */
8636 int bnxt_half_open_nic(struct bnxt *bp)
8637 {
8638         int rc = 0;
8639
8640         rc = bnxt_alloc_mem(bp, false);
8641         if (rc) {
8642                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8643                 goto half_open_err;
8644         }
8645         rc = bnxt_init_nic(bp, false);
8646         if (rc) {
8647                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8648                 goto half_open_err;
8649         }
8650         return 0;
8651
8652 half_open_err:
8653         bnxt_free_skbs(bp);
8654         bnxt_free_mem(bp, false);
8655         dev_close(bp->dev);
8656         return rc;
8657 }
8658
8659 /* rtnl_lock held, this call can only be made after a previous successful
8660  * call to bnxt_half_open_nic().
8661  */
8662 void bnxt_half_close_nic(struct bnxt *bp)
8663 {
8664         bnxt_hwrm_resource_free(bp, false, false);
8665         bnxt_free_skbs(bp);
8666         bnxt_free_mem(bp, false);
8667 }
8668
8669 static int bnxt_open(struct net_device *dev)
8670 {
8671         struct bnxt *bp = netdev_priv(dev);
8672         int rc;
8673
8674         bnxt_hwrm_if_change(bp, true);
8675         rc = __bnxt_open_nic(bp, true, true);
8676         if (rc)
8677                 bnxt_hwrm_if_change(bp, false);
8678
8679         bnxt_hwmon_open(bp);
8680
8681         return rc;
8682 }
8683
8684 static bool bnxt_drv_busy(struct bnxt *bp)
8685 {
8686         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8687                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8688 }
8689
8690 static void bnxt_get_ring_stats(struct bnxt *bp,
8691                                 struct rtnl_link_stats64 *stats);
8692
8693 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8694                              bool link_re_init)
8695 {
8696         /* Close the VF-reps before closing PF */
8697         if (BNXT_PF(bp))
8698                 bnxt_vf_reps_close(bp);
8699
8700         /* Change device state to avoid TX queue wake up's */
8701         bnxt_tx_disable(bp);
8702
8703         clear_bit(BNXT_STATE_OPEN, &bp->state);
8704         smp_mb__after_atomic();
8705         while (bnxt_drv_busy(bp))
8706                 msleep(20);
8707
8708         /* Flush rings and and disable interrupts */
8709         bnxt_shutdown_nic(bp, irq_re_init);
8710
8711         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8712
8713         bnxt_debug_dev_exit(bp);
8714         bnxt_disable_napi(bp);
8715         del_timer_sync(&bp->timer);
8716         bnxt_free_skbs(bp);
8717
8718         /* Save ring stats before shutdown */
8719         if (bp->bnapi)
8720                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8721         if (irq_re_init) {
8722                 bnxt_free_irq(bp);
8723                 bnxt_del_napi(bp);
8724         }
8725         bnxt_free_mem(bp, irq_re_init);
8726 }
8727
8728 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8729 {
8730         int rc = 0;
8731
8732 #ifdef CONFIG_BNXT_SRIOV
8733         if (bp->sriov_cfg) {
8734                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8735                                                       !bp->sriov_cfg,
8736                                                       BNXT_SRIOV_CFG_WAIT_TMO);
8737                 if (rc)
8738                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8739         }
8740 #endif
8741         __bnxt_close_nic(bp, irq_re_init, link_re_init);
8742         return rc;
8743 }
8744
8745 static int bnxt_close(struct net_device *dev)
8746 {
8747         struct bnxt *bp = netdev_priv(dev);
8748
8749         bnxt_hwmon_close(bp);
8750         bnxt_close_nic(bp, true, true);
8751         bnxt_hwrm_shutdown_link(bp);
8752         bnxt_hwrm_if_change(bp, false);
8753         return 0;
8754 }
8755
8756 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8757                                    u16 *val)
8758 {
8759         struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8760         struct hwrm_port_phy_mdio_read_input req = {0};
8761         int rc;
8762
8763         if (bp->hwrm_spec_code < 0x10a00)
8764                 return -EOPNOTSUPP;
8765
8766         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8767         req.port_id = cpu_to_le16(bp->pf.port_id);
8768         req.phy_addr = phy_addr;
8769         req.reg_addr = cpu_to_le16(reg & 0x1f);
8770         if (mdio_phy_id_is_c45(phy_addr)) {
8771                 req.cl45_mdio = 1;
8772                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8773                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8774                 req.reg_addr = cpu_to_le16(reg);
8775         }
8776
8777         mutex_lock(&bp->hwrm_cmd_lock);
8778         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8779         if (!rc)
8780                 *val = le16_to_cpu(resp->reg_data);
8781         mutex_unlock(&bp->hwrm_cmd_lock);
8782         return rc;
8783 }
8784
8785 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8786                                     u16 val)
8787 {
8788         struct hwrm_port_phy_mdio_write_input req = {0};
8789
8790         if (bp->hwrm_spec_code < 0x10a00)
8791                 return -EOPNOTSUPP;
8792
8793         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8794         req.port_id = cpu_to_le16(bp->pf.port_id);
8795         req.phy_addr = phy_addr;
8796         req.reg_addr = cpu_to_le16(reg & 0x1f);
8797         if (mdio_phy_id_is_c45(phy_addr)) {
8798                 req.cl45_mdio = 1;
8799                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8800                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8801                 req.reg_addr = cpu_to_le16(reg);
8802         }
8803         req.reg_data = cpu_to_le16(val);
8804
8805         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8806 }
8807
8808 /* rtnl_lock held */
8809 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8810 {
8811         struct mii_ioctl_data *mdio = if_mii(ifr);
8812         struct bnxt *bp = netdev_priv(dev);
8813         int rc;
8814
8815         switch (cmd) {
8816         case SIOCGMIIPHY:
8817                 mdio->phy_id = bp->link_info.phy_addr;
8818
8819                 /* fallthru */
8820         case SIOCGMIIREG: {
8821                 u16 mii_regval = 0;
8822
8823                 if (!netif_running(dev))
8824                         return -EAGAIN;
8825
8826                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8827                                              &mii_regval);
8828                 mdio->val_out = mii_regval;
8829                 return rc;
8830         }
8831
8832         case SIOCSMIIREG:
8833                 if (!netif_running(dev))
8834                         return -EAGAIN;
8835
8836                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8837                                                 mdio->val_in);
8838
8839         default:
8840                 /* do nothing */
8841                 break;
8842         }
8843         return -EOPNOTSUPP;
8844 }
8845
8846 static void bnxt_get_ring_stats(struct bnxt *bp,
8847                                 struct rtnl_link_stats64 *stats)
8848 {
8849         int i;
8850
8851
8852         for (i = 0; i < bp->cp_nr_rings; i++) {
8853                 struct bnxt_napi *bnapi = bp->bnapi[i];
8854                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8855                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8856
8857                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8858                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8859                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8860
8861                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8862                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8863                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8864
8865                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8866                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8867                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8868
8869                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8870                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8871                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8872
8873                 stats->rx_missed_errors +=
8874                         le64_to_cpu(hw_stats->rx_discard_pkts);
8875
8876                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8877
8878                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8879         }
8880 }
8881
8882 static void bnxt_add_prev_stats(struct bnxt *bp,
8883                                 struct rtnl_link_stats64 *stats)
8884 {
8885         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8886
8887         stats->rx_packets += prev_stats->rx_packets;
8888         stats->tx_packets += prev_stats->tx_packets;
8889         stats->rx_bytes += prev_stats->rx_bytes;
8890         stats->tx_bytes += prev_stats->tx_bytes;
8891         stats->rx_missed_errors += prev_stats->rx_missed_errors;
8892         stats->multicast += prev_stats->multicast;
8893         stats->tx_dropped += prev_stats->tx_dropped;
8894 }
8895
8896 static void
8897 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8898 {
8899         struct bnxt *bp = netdev_priv(dev);
8900
8901         set_bit(BNXT_STATE_READ_STATS, &bp->state);
8902         /* Make sure bnxt_close_nic() sees that we are reading stats before
8903          * we check the BNXT_STATE_OPEN flag.
8904          */
8905         smp_mb__after_atomic();
8906         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8907                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8908                 *stats = bp->net_stats_prev;
8909                 return;
8910         }
8911
8912         bnxt_get_ring_stats(bp, stats);
8913         bnxt_add_prev_stats(bp, stats);
8914
8915         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8916                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8917                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8918
8919                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8920                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8921                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8922                                           le64_to_cpu(rx->rx_ovrsz_frames) +
8923                                           le64_to_cpu(rx->rx_runt_frames);
8924                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8925                                    le64_to_cpu(rx->rx_jbr_frames);
8926                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8927                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8928                 stats->tx_errors = le64_to_cpu(tx->tx_err);
8929         }
8930         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8931 }
8932
8933 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8934 {
8935         struct net_device *dev = bp->dev;
8936         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8937         struct netdev_hw_addr *ha;
8938         u8 *haddr;
8939         int mc_count = 0;
8940         bool update = false;
8941         int off = 0;
8942
8943         netdev_for_each_mc_addr(ha, dev) {
8944                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8945                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8946                         vnic->mc_list_count = 0;
8947                         return false;
8948                 }
8949                 haddr = ha->addr;
8950                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8951                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8952                         update = true;
8953                 }
8954                 off += ETH_ALEN;
8955                 mc_count++;
8956         }
8957         if (mc_count)
8958                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8959
8960         if (mc_count != vnic->mc_list_count) {
8961                 vnic->mc_list_count = mc_count;
8962                 update = true;
8963         }
8964         return update;
8965 }
8966
8967 static bool bnxt_uc_list_updated(struct bnxt *bp)
8968 {
8969         struct net_device *dev = bp->dev;
8970         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8971         struct netdev_hw_addr *ha;
8972         int off = 0;
8973
8974         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8975                 return true;
8976
8977         netdev_for_each_uc_addr(ha, dev) {
8978                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8979                         return true;
8980
8981                 off += ETH_ALEN;
8982         }
8983         return false;
8984 }
8985
8986 static void bnxt_set_rx_mode(struct net_device *dev)
8987 {
8988         struct bnxt *bp = netdev_priv(dev);
8989         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8990         u32 mask = vnic->rx_mask;
8991         bool mc_update = false;
8992         bool uc_update;
8993
8994         if (!netif_running(dev))
8995                 return;
8996
8997         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8998                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
8999                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
9000                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
9001
9002         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
9003                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9004
9005         uc_update = bnxt_uc_list_updated(bp);
9006
9007         if (dev->flags & IFF_BROADCAST)
9008                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
9009         if (dev->flags & IFF_ALLMULTI) {
9010                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9011                 vnic->mc_list_count = 0;
9012         } else {
9013                 mc_update = bnxt_mc_list_updated(bp, &mask);
9014         }
9015
9016         if (mask != vnic->rx_mask || uc_update || mc_update) {
9017                 vnic->rx_mask = mask;
9018
9019                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
9020                 bnxt_queue_sp_work(bp);
9021         }
9022 }
9023
9024 static int bnxt_cfg_rx_mode(struct bnxt *bp)
9025 {
9026         struct net_device *dev = bp->dev;
9027         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9028         struct netdev_hw_addr *ha;
9029         int i, off = 0, rc;
9030         bool uc_update;
9031
9032         netif_addr_lock_bh(dev);
9033         uc_update = bnxt_uc_list_updated(bp);
9034         netif_addr_unlock_bh(dev);
9035
9036         if (!uc_update)
9037                 goto skip_uc;
9038
9039         mutex_lock(&bp->hwrm_cmd_lock);
9040         for (i = 1; i < vnic->uc_filter_count; i++) {
9041                 struct hwrm_cfa_l2_filter_free_input req = {0};
9042
9043                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
9044                                        -1);
9045
9046                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
9047
9048                 rc = _hwrm_send_message(bp, &req, sizeof(req),
9049                                         HWRM_CMD_TIMEOUT);
9050         }
9051         mutex_unlock(&bp->hwrm_cmd_lock);
9052
9053         vnic->uc_filter_count = 1;
9054
9055         netif_addr_lock_bh(dev);
9056         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
9057                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9058         } else {
9059                 netdev_for_each_uc_addr(ha, dev) {
9060                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
9061                         off += ETH_ALEN;
9062                         vnic->uc_filter_count++;
9063                 }
9064         }
9065         netif_addr_unlock_bh(dev);
9066
9067         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
9068                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
9069                 if (rc) {
9070                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
9071                                    rc);
9072                         vnic->uc_filter_count = i;
9073                         return rc;
9074                 }
9075         }
9076
9077 skip_uc:
9078         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9079         if (rc && vnic->mc_list_count) {
9080                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
9081                             rc);
9082                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9083                 vnic->mc_list_count = 0;
9084                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9085         }
9086         if (rc)
9087                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
9088                            rc);
9089
9090         return rc;
9091 }
9092
9093 static bool bnxt_can_reserve_rings(struct bnxt *bp)
9094 {
9095 #ifdef CONFIG_BNXT_SRIOV
9096         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
9097                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9098
9099                 /* No minimum rings were provisioned by the PF.  Don't
9100                  * reserve rings by default when device is down.
9101                  */
9102                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
9103                         return true;
9104
9105                 if (!netif_running(bp->dev))
9106                         return false;
9107         }
9108 #endif
9109         return true;
9110 }
9111
9112 /* If the chip and firmware supports RFS */
9113 static bool bnxt_rfs_supported(struct bnxt *bp)
9114 {
9115         if (bp->flags & BNXT_FLAG_CHIP_P5) {
9116                 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX)
9117                         return true;
9118                 return false;
9119         }
9120         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
9121                 return true;
9122         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9123                 return true;
9124         return false;
9125 }
9126
9127 /* If runtime conditions support RFS */
9128 static bool bnxt_rfs_capable(struct bnxt *bp)
9129 {
9130 #ifdef CONFIG_RFS_ACCEL
9131         int vnics, max_vnics, max_rss_ctxs;
9132
9133         if (bp->flags & BNXT_FLAG_CHIP_P5)
9134                 return bnxt_rfs_supported(bp);
9135         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9136                 return false;
9137
9138         vnics = 1 + bp->rx_nr_rings;
9139         max_vnics = bnxt_get_max_func_vnics(bp);
9140         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9141
9142         /* RSS contexts not a limiting factor */
9143         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9144                 max_rss_ctxs = max_vnics;
9145         if (vnics > max_vnics || vnics > max_rss_ctxs) {
9146                 if (bp->rx_nr_rings > 1)
9147                         netdev_warn(bp->dev,
9148                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9149                                     min(max_rss_ctxs - 1, max_vnics - 1));
9150                 return false;
9151         }
9152
9153         if (!BNXT_NEW_RM(bp))
9154                 return true;
9155
9156         if (vnics == bp->hw_resc.resv_vnics)
9157                 return true;
9158
9159         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9160         if (vnics <= bp->hw_resc.resv_vnics)
9161                 return true;
9162
9163         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9164         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9165         return false;
9166 #else
9167         return false;
9168 #endif
9169 }
9170
9171 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9172                                            netdev_features_t features)
9173 {
9174         struct bnxt *bp = netdev_priv(dev);
9175
9176         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9177                 features &= ~NETIF_F_NTUPLE;
9178
9179         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9180                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9181
9182         if (!(features & NETIF_F_GRO))
9183                 features &= ~NETIF_F_GRO_HW;
9184
9185         if (features & NETIF_F_GRO_HW)
9186                 features &= ~NETIF_F_LRO;
9187
9188         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9189          * turned on or off together.
9190          */
9191         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9192             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9193                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9194                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9195                                       NETIF_F_HW_VLAN_STAG_RX);
9196                 else
9197                         features |= NETIF_F_HW_VLAN_CTAG_RX |
9198                                     NETIF_F_HW_VLAN_STAG_RX;
9199         }
9200 #ifdef CONFIG_BNXT_SRIOV
9201         if (BNXT_VF(bp)) {
9202                 if (bp->vf.vlan) {
9203                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9204                                       NETIF_F_HW_VLAN_STAG_RX);
9205                 }
9206         }
9207 #endif
9208         return features;
9209 }
9210
9211 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9212 {
9213         struct bnxt *bp = netdev_priv(dev);
9214         u32 flags = bp->flags;
9215         u32 changes;
9216         int rc = 0;
9217         bool re_init = false;
9218         bool update_tpa = false;
9219
9220         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9221         if (features & NETIF_F_GRO_HW)
9222                 flags |= BNXT_FLAG_GRO;
9223         else if (features & NETIF_F_LRO)
9224                 flags |= BNXT_FLAG_LRO;
9225
9226         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9227                 flags &= ~BNXT_FLAG_TPA;
9228
9229         if (features & NETIF_F_HW_VLAN_CTAG_RX)
9230                 flags |= BNXT_FLAG_STRIP_VLAN;
9231
9232         if (features & NETIF_F_NTUPLE)
9233                 flags |= BNXT_FLAG_RFS;
9234
9235         changes = flags ^ bp->flags;
9236         if (changes & BNXT_FLAG_TPA) {
9237                 update_tpa = true;
9238                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9239                     (flags & BNXT_FLAG_TPA) == 0)
9240                         re_init = true;
9241         }
9242
9243         if (changes & ~BNXT_FLAG_TPA)
9244                 re_init = true;
9245
9246         if (flags != bp->flags) {
9247                 u32 old_flags = bp->flags;
9248
9249                 bp->flags = flags;
9250
9251                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9252                         if (update_tpa)
9253                                 bnxt_set_ring_params(bp);
9254                         return rc;
9255                 }
9256
9257                 if (re_init) {
9258                         bnxt_close_nic(bp, false, false);
9259                         if (update_tpa)
9260                                 bnxt_set_ring_params(bp);
9261
9262                         return bnxt_open_nic(bp, false, false);
9263                 }
9264                 if (update_tpa) {
9265                         rc = bnxt_set_tpa(bp,
9266                                           (flags & BNXT_FLAG_TPA) ?
9267                                           true : false);
9268                         if (rc)
9269                                 bp->flags = old_flags;
9270                 }
9271         }
9272         return rc;
9273 }
9274
9275 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9276                                        u32 ring_id, u32 *prod, u32 *cons)
9277 {
9278         struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9279         struct hwrm_dbg_ring_info_get_input req = {0};
9280         int rc;
9281
9282         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9283         req.ring_type = ring_type;
9284         req.fw_ring_id = cpu_to_le32(ring_id);
9285         mutex_lock(&bp->hwrm_cmd_lock);
9286         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9287         if (!rc) {
9288                 *prod = le32_to_cpu(resp->producer_index);
9289                 *cons = le32_to_cpu(resp->consumer_index);
9290         }
9291         mutex_unlock(&bp->hwrm_cmd_lock);
9292         return rc;
9293 }
9294
9295 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9296 {
9297         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9298         int i = bnapi->index;
9299
9300         if (!txr)
9301                 return;
9302
9303         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9304                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9305                     txr->tx_cons);
9306 }
9307
9308 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9309 {
9310         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9311         int i = bnapi->index;
9312
9313         if (!rxr)
9314                 return;
9315
9316         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9317                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9318                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9319                     rxr->rx_sw_agg_prod);
9320 }
9321
9322 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9323 {
9324         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9325         int i = bnapi->index;
9326
9327         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9328                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9329 }
9330
9331 static void bnxt_dbg_dump_states(struct bnxt *bp)
9332 {
9333         int i;
9334         struct bnxt_napi *bnapi;
9335
9336         for (i = 0; i < bp->cp_nr_rings; i++) {
9337                 bnapi = bp->bnapi[i];
9338                 if (netif_msg_drv(bp)) {
9339                         bnxt_dump_tx_sw_state(bnapi);
9340                         bnxt_dump_rx_sw_state(bnapi);
9341                         bnxt_dump_cp_sw_state(bnapi);
9342                 }
9343         }
9344 }
9345
9346 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9347 {
9348         if (!silent)
9349                 bnxt_dbg_dump_states(bp);
9350         if (netif_running(bp->dev)) {
9351                 int rc;
9352
9353                 if (!silent)
9354                         bnxt_ulp_stop(bp);
9355                 bnxt_close_nic(bp, false, false);
9356                 rc = bnxt_open_nic(bp, false, false);
9357                 if (!silent && !rc)
9358                         bnxt_ulp_start(bp);
9359         }
9360 }
9361
9362 static void bnxt_tx_timeout(struct net_device *dev)
9363 {
9364         struct bnxt *bp = netdev_priv(dev);
9365
9366         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
9367         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9368         bnxt_queue_sp_work(bp);
9369 }
9370
9371 static void bnxt_timer(struct timer_list *t)
9372 {
9373         struct bnxt *bp = from_timer(bp, t, timer);
9374         struct net_device *dev = bp->dev;
9375
9376         if (!netif_running(dev))
9377                 return;
9378
9379         if (atomic_read(&bp->intr_sem) != 0)
9380                 goto bnxt_restart_timer;
9381
9382         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9383             bp->stats_coal_ticks) {
9384                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9385                 bnxt_queue_sp_work(bp);
9386         }
9387
9388         if (bnxt_tc_flower_enabled(bp)) {
9389                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9390                 bnxt_queue_sp_work(bp);
9391         }
9392
9393         if (bp->link_info.phy_retry) {
9394                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9395                         bp->link_info.phy_retry = 0;
9396                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9397                 } else {
9398                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9399                         bnxt_queue_sp_work(bp);
9400                 }
9401         }
9402
9403         if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9404                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9405                 bnxt_queue_sp_work(bp);
9406         }
9407 bnxt_restart_timer:
9408         mod_timer(&bp->timer, jiffies + bp->current_interval);
9409 }
9410
9411 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9412 {
9413         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9414          * set.  If the device is being closed, bnxt_close() may be holding
9415          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
9416          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9417          */
9418         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9419         rtnl_lock();
9420 }
9421
9422 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9423 {
9424         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9425         rtnl_unlock();
9426 }
9427
9428 /* Only called from bnxt_sp_task() */
9429 static void bnxt_reset(struct bnxt *bp, bool silent)
9430 {
9431         bnxt_rtnl_lock_sp(bp);
9432         if (test_bit(BNXT_STATE_OPEN, &bp->state))
9433                 bnxt_reset_task(bp, silent);
9434         bnxt_rtnl_unlock_sp(bp);
9435 }
9436
9437 static void bnxt_chk_missed_irq(struct bnxt *bp)
9438 {
9439         int i;
9440
9441         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9442                 return;
9443
9444         for (i = 0; i < bp->cp_nr_rings; i++) {
9445                 struct bnxt_napi *bnapi = bp->bnapi[i];
9446                 struct bnxt_cp_ring_info *cpr;
9447                 u32 fw_ring_id;
9448                 int j;
9449
9450                 if (!bnapi)
9451                         continue;
9452
9453                 cpr = &bnapi->cp_ring;
9454                 for (j = 0; j < 2; j++) {
9455                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9456                         u32 val[2];
9457
9458                         if (!cpr2 || cpr2->has_more_work ||
9459                             !bnxt_has_work(bp, cpr2))
9460                                 continue;
9461
9462                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9463                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9464                                 continue;
9465                         }
9466                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9467                         bnxt_dbg_hwrm_ring_info_get(bp,
9468                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9469                                 fw_ring_id, &val[0], &val[1]);
9470                         cpr->missed_irqs++;
9471                 }
9472         }
9473 }
9474
9475 static void bnxt_cfg_ntp_filters(struct bnxt *);
9476
9477 static void bnxt_sp_task(struct work_struct *work)
9478 {
9479         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9480
9481         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9482         smp_mb__after_atomic();
9483         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9484                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9485                 return;
9486         }
9487
9488         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9489                 bnxt_cfg_rx_mode(bp);
9490
9491         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9492                 bnxt_cfg_ntp_filters(bp);
9493         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9494                 bnxt_hwrm_exec_fwd_req(bp);
9495         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9496                 bnxt_hwrm_tunnel_dst_port_alloc(
9497                         bp, bp->vxlan_port,
9498                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9499         }
9500         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9501                 bnxt_hwrm_tunnel_dst_port_free(
9502                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9503         }
9504         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9505                 bnxt_hwrm_tunnel_dst_port_alloc(
9506                         bp, bp->nge_port,
9507                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9508         }
9509         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9510                 bnxt_hwrm_tunnel_dst_port_free(
9511                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9512         }
9513         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9514                 bnxt_hwrm_port_qstats(bp);
9515                 bnxt_hwrm_port_qstats_ext(bp);
9516                 bnxt_hwrm_pcie_qstats(bp);
9517         }
9518
9519         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9520                 int rc;
9521
9522                 mutex_lock(&bp->link_lock);
9523                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9524                                        &bp->sp_event))
9525                         bnxt_hwrm_phy_qcaps(bp);
9526
9527                 rc = bnxt_update_link(bp, true);
9528                 mutex_unlock(&bp->link_lock);
9529                 if (rc)
9530                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9531                                    rc);
9532         }
9533         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9534                 int rc;
9535
9536                 mutex_lock(&bp->link_lock);
9537                 rc = bnxt_update_phy_setting(bp);
9538                 mutex_unlock(&bp->link_lock);
9539                 if (rc) {
9540                         netdev_warn(bp->dev, "update phy settings retry failed\n");
9541                 } else {
9542                         bp->link_info.phy_retry = false;
9543                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
9544                 }
9545         }
9546         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9547                 mutex_lock(&bp->link_lock);
9548                 bnxt_get_port_module_status(bp);
9549                 mutex_unlock(&bp->link_lock);
9550         }
9551
9552         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9553                 bnxt_tc_flow_stats_work(bp);
9554
9555         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9556                 bnxt_chk_missed_irq(bp);
9557
9558         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
9559          * must be the last functions to be called before exiting.
9560          */
9561         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9562                 bnxt_reset(bp, false);
9563
9564         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9565                 bnxt_reset(bp, true);
9566
9567         smp_mb__before_atomic();
9568         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9569 }
9570
9571 /* Under rtnl_lock */
9572 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9573                      int tx_xdp)
9574 {
9575         int max_rx, max_tx, tx_sets = 1;
9576         int tx_rings_needed, stats;
9577         int rx_rings = rx;
9578         int cp, vnics, rc;
9579
9580         if (tcs)
9581                 tx_sets = tcs;
9582
9583         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9584         if (rc)
9585                 return rc;
9586
9587         if (max_rx < rx)
9588                 return -ENOMEM;
9589
9590         tx_rings_needed = tx * tx_sets + tx_xdp;
9591         if (max_tx < tx_rings_needed)
9592                 return -ENOMEM;
9593
9594         vnics = 1;
9595         if (bp->flags & BNXT_FLAG_RFS)
9596                 vnics += rx_rings;
9597
9598         if (bp->flags & BNXT_FLAG_AGG_RINGS)
9599                 rx_rings <<= 1;
9600         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9601         stats = cp;
9602         if (BNXT_NEW_RM(bp)) {
9603                 cp += bnxt_get_ulp_msix_num(bp);
9604                 stats += bnxt_get_ulp_stat_ctxs(bp);
9605         }
9606         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9607                                      stats, vnics);
9608 }
9609
9610 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9611 {
9612         if (bp->bar2) {
9613                 pci_iounmap(pdev, bp->bar2);
9614                 bp->bar2 = NULL;
9615         }
9616
9617         if (bp->bar1) {
9618                 pci_iounmap(pdev, bp->bar1);
9619                 bp->bar1 = NULL;
9620         }
9621
9622         if (bp->bar0) {
9623                 pci_iounmap(pdev, bp->bar0);
9624                 bp->bar0 = NULL;
9625         }
9626 }
9627
9628 static void bnxt_cleanup_pci(struct bnxt *bp)
9629 {
9630         bnxt_unmap_bars(bp, bp->pdev);
9631         pci_release_regions(bp->pdev);
9632         pci_disable_device(bp->pdev);
9633 }
9634
9635 static void bnxt_init_dflt_coal(struct bnxt *bp)
9636 {
9637         struct bnxt_coal *coal;
9638
9639         /* Tick values in micro seconds.
9640          * 1 coal_buf x bufs_per_record = 1 completion record.
9641          */
9642         coal = &bp->rx_coal;
9643         coal->coal_ticks = 10;
9644         coal->coal_bufs = 30;
9645         coal->coal_ticks_irq = 1;
9646         coal->coal_bufs_irq = 2;
9647         coal->idle_thresh = 50;
9648         coal->bufs_per_record = 2;
9649         coal->budget = 64;              /* NAPI budget */
9650
9651         coal = &bp->tx_coal;
9652         coal->coal_ticks = 28;
9653         coal->coal_bufs = 30;
9654         coal->coal_ticks_irq = 2;
9655         coal->coal_bufs_irq = 2;
9656         coal->bufs_per_record = 1;
9657
9658         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9659 }
9660
9661 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9662 {
9663         int rc;
9664         struct bnxt *bp = netdev_priv(dev);
9665
9666         SET_NETDEV_DEV(dev, &pdev->dev);
9667
9668         /* enable device (incl. PCI PM wakeup), and bus-mastering */
9669         rc = pci_enable_device(pdev);
9670         if (rc) {
9671                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9672                 goto init_err;
9673         }
9674
9675         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9676                 dev_err(&pdev->dev,
9677                         "Cannot find PCI device base address, aborting\n");
9678                 rc = -ENODEV;
9679                 goto init_err_disable;
9680         }
9681
9682         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9683         if (rc) {
9684                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9685                 goto init_err_disable;
9686         }
9687
9688         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9689             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9690                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9691                 goto init_err_disable;
9692         }
9693
9694         pci_set_master(pdev);
9695
9696         bp->dev = dev;
9697         bp->pdev = pdev;
9698
9699         bp->bar0 = pci_ioremap_bar(pdev, 0);
9700         if (!bp->bar0) {
9701                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9702                 rc = -ENOMEM;
9703                 goto init_err_release;
9704         }
9705
9706         bp->bar1 = pci_ioremap_bar(pdev, 2);
9707         if (!bp->bar1) {
9708                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9709                 rc = -ENOMEM;
9710                 goto init_err_release;
9711         }
9712
9713         bp->bar2 = pci_ioremap_bar(pdev, 4);
9714         if (!bp->bar2) {
9715                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9716                 rc = -ENOMEM;
9717                 goto init_err_release;
9718         }
9719
9720         pci_enable_pcie_error_reporting(pdev);
9721
9722         INIT_WORK(&bp->sp_task, bnxt_sp_task);
9723
9724         spin_lock_init(&bp->ntp_fltr_lock);
9725 #if BITS_PER_LONG == 32
9726         spin_lock_init(&bp->db_lock);
9727 #endif
9728
9729         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9730         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9731
9732         bnxt_init_dflt_coal(bp);
9733
9734         timer_setup(&bp->timer, bnxt_timer, 0);
9735         bp->current_interval = BNXT_TIMER_INTERVAL;
9736
9737         clear_bit(BNXT_STATE_OPEN, &bp->state);
9738         return 0;
9739
9740 init_err_release:
9741         bnxt_unmap_bars(bp, pdev);
9742         pci_release_regions(pdev);
9743
9744 init_err_disable:
9745         pci_disable_device(pdev);
9746
9747 init_err:
9748         return rc;
9749 }
9750
9751 /* rtnl_lock held */
9752 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9753 {
9754         struct sockaddr *addr = p;
9755         struct bnxt *bp = netdev_priv(dev);
9756         int rc = 0;
9757
9758         if (!is_valid_ether_addr(addr->sa_data))
9759                 return -EADDRNOTAVAIL;
9760
9761         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9762                 return 0;
9763
9764         rc = bnxt_approve_mac(bp, addr->sa_data, true);
9765         if (rc)
9766                 return rc;
9767
9768         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9769         if (netif_running(dev)) {
9770                 bnxt_close_nic(bp, false, false);
9771                 rc = bnxt_open_nic(bp, false, false);
9772         }
9773
9774         return rc;
9775 }
9776
9777 /* rtnl_lock held */
9778 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9779 {
9780         struct bnxt *bp = netdev_priv(dev);
9781
9782         if (netif_running(dev))
9783                 bnxt_close_nic(bp, false, false);
9784
9785         dev->mtu = new_mtu;
9786         bnxt_set_ring_params(bp);
9787
9788         if (netif_running(dev))
9789                 return bnxt_open_nic(bp, false, false);
9790
9791         return 0;
9792 }
9793
9794 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9795 {
9796         struct bnxt *bp = netdev_priv(dev);
9797         bool sh = false;
9798         int rc;
9799
9800         if (tc > bp->max_tc) {
9801                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9802                            tc, bp->max_tc);
9803                 return -EINVAL;
9804         }
9805
9806         if (netdev_get_num_tc(dev) == tc)
9807                 return 0;
9808
9809         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9810                 sh = true;
9811
9812         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9813                               sh, tc, bp->tx_nr_rings_xdp);
9814         if (rc)
9815                 return rc;
9816
9817         /* Needs to close the device and do hw resource re-allocations */
9818         if (netif_running(bp->dev))
9819                 bnxt_close_nic(bp, true, false);
9820
9821         if (tc) {
9822                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9823                 netdev_set_num_tc(dev, tc);
9824         } else {
9825                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9826                 netdev_reset_tc(dev);
9827         }
9828         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9829         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9830                                bp->tx_nr_rings + bp->rx_nr_rings;
9831
9832         if (netif_running(bp->dev))
9833                 return bnxt_open_nic(bp, true, false);
9834
9835         return 0;
9836 }
9837
9838 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9839                                   void *cb_priv)
9840 {
9841         struct bnxt *bp = cb_priv;
9842
9843         if (!bnxt_tc_flower_enabled(bp) ||
9844             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9845                 return -EOPNOTSUPP;
9846
9847         switch (type) {
9848         case TC_SETUP_CLSFLOWER:
9849                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9850         default:
9851                 return -EOPNOTSUPP;
9852         }
9853 }
9854
9855 static int bnxt_setup_tc_block(struct net_device *dev,
9856                                struct tc_block_offload *f)
9857 {
9858         struct bnxt *bp = netdev_priv(dev);
9859
9860         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9861                 return -EOPNOTSUPP;
9862
9863         switch (f->command) {
9864         case TC_BLOCK_BIND:
9865                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9866                                              bp, bp, f->extack);
9867         case TC_BLOCK_UNBIND:
9868                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9869                 return 0;
9870         default:
9871                 return -EOPNOTSUPP;
9872         }
9873 }
9874
9875 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9876                          void *type_data)
9877 {
9878         switch (type) {
9879         case TC_SETUP_BLOCK:
9880                 return bnxt_setup_tc_block(dev, type_data);
9881         case TC_SETUP_QDISC_MQPRIO: {
9882                 struct tc_mqprio_qopt *mqprio = type_data;
9883
9884                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9885
9886                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9887         }
9888         default:
9889                 return -EOPNOTSUPP;
9890         }
9891 }
9892
9893 #ifdef CONFIG_RFS_ACCEL
9894 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9895                             struct bnxt_ntuple_filter *f2)
9896 {
9897         struct flow_keys *keys1 = &f1->fkeys;
9898         struct flow_keys *keys2 = &f2->fkeys;
9899
9900         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9901             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9902             keys1->ports.ports == keys2->ports.ports &&
9903             keys1->basic.ip_proto == keys2->basic.ip_proto &&
9904             keys1->basic.n_proto == keys2->basic.n_proto &&
9905             keys1->control.flags == keys2->control.flags &&
9906             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9907             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9908                 return true;
9909
9910         return false;
9911 }
9912
9913 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9914                               u16 rxq_index, u32 flow_id)
9915 {
9916         struct bnxt *bp = netdev_priv(dev);
9917         struct bnxt_ntuple_filter *fltr, *new_fltr;
9918         struct flow_keys *fkeys;
9919         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9920         int rc = 0, idx, bit_id, l2_idx = 0;
9921         struct hlist_head *head;
9922
9923         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9924                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9925                 int off = 0, j;
9926
9927                 netif_addr_lock_bh(dev);
9928                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9929                         if (ether_addr_equal(eth->h_dest,
9930                                              vnic->uc_list + off)) {
9931                                 l2_idx = j + 1;
9932                                 break;
9933                         }
9934                 }
9935                 netif_addr_unlock_bh(dev);
9936                 if (!l2_idx)
9937                         return -EINVAL;
9938         }
9939         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9940         if (!new_fltr)
9941                 return -ENOMEM;
9942
9943         fkeys = &new_fltr->fkeys;
9944         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9945                 rc = -EPROTONOSUPPORT;
9946                 goto err_free;
9947         }
9948
9949         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9950              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9951             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9952              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9953                 rc = -EPROTONOSUPPORT;
9954                 goto err_free;
9955         }
9956         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9957             bp->hwrm_spec_code < 0x10601) {
9958                 rc = -EPROTONOSUPPORT;
9959                 goto err_free;
9960         }
9961         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9962             bp->hwrm_spec_code < 0x10601) {
9963                 rc = -EPROTONOSUPPORT;
9964                 goto err_free;
9965         }
9966
9967         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
9968         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9969
9970         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9971         head = &bp->ntp_fltr_hash_tbl[idx];
9972         rcu_read_lock();
9973         hlist_for_each_entry_rcu(fltr, head, hash) {
9974                 if (bnxt_fltr_match(fltr, new_fltr)) {
9975                         rcu_read_unlock();
9976                         rc = 0;
9977                         goto err_free;
9978                 }
9979         }
9980         rcu_read_unlock();
9981
9982         spin_lock_bh(&bp->ntp_fltr_lock);
9983         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9984                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
9985         if (bit_id < 0) {
9986                 spin_unlock_bh(&bp->ntp_fltr_lock);
9987                 rc = -ENOMEM;
9988                 goto err_free;
9989         }
9990
9991         new_fltr->sw_id = (u16)bit_id;
9992         new_fltr->flow_id = flow_id;
9993         new_fltr->l2_fltr_idx = l2_idx;
9994         new_fltr->rxq = rxq_index;
9995         hlist_add_head_rcu(&new_fltr->hash, head);
9996         bp->ntp_fltr_count++;
9997         spin_unlock_bh(&bp->ntp_fltr_lock);
9998
9999         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
10000         bnxt_queue_sp_work(bp);
10001
10002         return new_fltr->sw_id;
10003
10004 err_free:
10005         kfree(new_fltr);
10006         return rc;
10007 }
10008
10009 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10010 {
10011         int i;
10012
10013         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
10014                 struct hlist_head *head;
10015                 struct hlist_node *tmp;
10016                 struct bnxt_ntuple_filter *fltr;
10017                 int rc;
10018
10019                 head = &bp->ntp_fltr_hash_tbl[i];
10020                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
10021                         bool del = false;
10022
10023                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
10024                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
10025                                                         fltr->flow_id,
10026                                                         fltr->sw_id)) {
10027                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
10028                                                                          fltr);
10029                                         del = true;
10030                                 }
10031                         } else {
10032                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
10033                                                                        fltr);
10034                                 if (rc)
10035                                         del = true;
10036                                 else
10037                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
10038                         }
10039
10040                         if (del) {
10041                                 spin_lock_bh(&bp->ntp_fltr_lock);
10042                                 hlist_del_rcu(&fltr->hash);
10043                                 bp->ntp_fltr_count--;
10044                                 spin_unlock_bh(&bp->ntp_fltr_lock);
10045                                 synchronize_rcu();
10046                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
10047                                 kfree(fltr);
10048                         }
10049                 }
10050         }
10051         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
10052                 netdev_info(bp->dev, "Receive PF driver unload event!");
10053 }
10054
10055 #else
10056
10057 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10058 {
10059 }
10060
10061 #endif /* CONFIG_RFS_ACCEL */
10062
10063 static void bnxt_udp_tunnel_add(struct net_device *dev,
10064                                 struct udp_tunnel_info *ti)
10065 {
10066         struct bnxt *bp = netdev_priv(dev);
10067
10068         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10069                 return;
10070
10071         if (!netif_running(dev))
10072                 return;
10073
10074         switch (ti->type) {
10075         case UDP_TUNNEL_TYPE_VXLAN:
10076                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
10077                         return;
10078
10079                 bp->vxlan_port_cnt++;
10080                 if (bp->vxlan_port_cnt == 1) {
10081                         bp->vxlan_port = ti->port;
10082                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
10083                         bnxt_queue_sp_work(bp);
10084                 }
10085                 break;
10086         case UDP_TUNNEL_TYPE_GENEVE:
10087                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
10088                         return;
10089
10090                 bp->nge_port_cnt++;
10091                 if (bp->nge_port_cnt == 1) {
10092                         bp->nge_port = ti->port;
10093                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
10094                 }
10095                 break;
10096         default:
10097                 return;
10098         }
10099
10100         bnxt_queue_sp_work(bp);
10101 }
10102
10103 static void bnxt_udp_tunnel_del(struct net_device *dev,
10104                                 struct udp_tunnel_info *ti)
10105 {
10106         struct bnxt *bp = netdev_priv(dev);
10107
10108         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10109                 return;
10110
10111         if (!netif_running(dev))
10112                 return;
10113
10114         switch (ti->type) {
10115         case UDP_TUNNEL_TYPE_VXLAN:
10116                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
10117                         return;
10118                 bp->vxlan_port_cnt--;
10119
10120                 if (bp->vxlan_port_cnt != 0)
10121                         return;
10122
10123                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
10124                 break;
10125         case UDP_TUNNEL_TYPE_GENEVE:
10126                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
10127                         return;
10128                 bp->nge_port_cnt--;
10129
10130                 if (bp->nge_port_cnt != 0)
10131                         return;
10132
10133                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10134                 break;
10135         default:
10136                 return;
10137         }
10138
10139         bnxt_queue_sp_work(bp);
10140 }
10141
10142 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10143                                struct net_device *dev, u32 filter_mask,
10144                                int nlflags)
10145 {
10146         struct bnxt *bp = netdev_priv(dev);
10147
10148         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10149                                        nlflags, filter_mask, NULL);
10150 }
10151
10152 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10153                                u16 flags, struct netlink_ext_ack *extack)
10154 {
10155         struct bnxt *bp = netdev_priv(dev);
10156         struct nlattr *attr, *br_spec;
10157         int rem, rc = 0;
10158
10159         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10160                 return -EOPNOTSUPP;
10161
10162         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10163         if (!br_spec)
10164                 return -EINVAL;
10165
10166         nla_for_each_nested(attr, br_spec, rem) {
10167                 u16 mode;
10168
10169                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10170                         continue;
10171
10172                 if (nla_len(attr) < sizeof(mode))
10173                         return -EINVAL;
10174
10175                 mode = nla_get_u16(attr);
10176                 if (mode == bp->br_mode)
10177                         break;
10178
10179                 rc = bnxt_hwrm_set_br_mode(bp, mode);
10180                 if (!rc)
10181                         bp->br_mode = mode;
10182                 break;
10183         }
10184         return rc;
10185 }
10186
10187 int bnxt_get_port_parent_id(struct net_device *dev,
10188                             struct netdev_phys_item_id *ppid)
10189 {
10190         struct bnxt *bp = netdev_priv(dev);
10191
10192         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10193                 return -EOPNOTSUPP;
10194
10195         /* The PF and it's VF-reps only support the switchdev framework */
10196         if (!BNXT_PF(bp))
10197                 return -EOPNOTSUPP;
10198
10199         ppid->id_len = sizeof(bp->switch_id);
10200         memcpy(ppid->id, bp->switch_id, ppid->id_len);
10201
10202         return 0;
10203 }
10204
10205 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10206 {
10207         struct bnxt *bp = netdev_priv(dev);
10208
10209         return &bp->dl_port;
10210 }
10211
10212 static const struct net_device_ops bnxt_netdev_ops = {
10213         .ndo_open               = bnxt_open,
10214         .ndo_start_xmit         = bnxt_start_xmit,
10215         .ndo_stop               = bnxt_close,
10216         .ndo_get_stats64        = bnxt_get_stats64,
10217         .ndo_set_rx_mode        = bnxt_set_rx_mode,
10218         .ndo_do_ioctl           = bnxt_ioctl,
10219         .ndo_validate_addr      = eth_validate_addr,
10220         .ndo_set_mac_address    = bnxt_change_mac_addr,
10221         .ndo_change_mtu         = bnxt_change_mtu,
10222         .ndo_fix_features       = bnxt_fix_features,
10223         .ndo_set_features       = bnxt_set_features,
10224         .ndo_tx_timeout         = bnxt_tx_timeout,
10225 #ifdef CONFIG_BNXT_SRIOV
10226         .ndo_get_vf_config      = bnxt_get_vf_config,
10227         .ndo_set_vf_mac         = bnxt_set_vf_mac,
10228         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
10229         .ndo_set_vf_rate        = bnxt_set_vf_bw,
10230         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
10231         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
10232         .ndo_set_vf_trust       = bnxt_set_vf_trust,
10233 #endif
10234         .ndo_setup_tc           = bnxt_setup_tc,
10235 #ifdef CONFIG_RFS_ACCEL
10236         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
10237 #endif
10238         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
10239         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
10240         .ndo_bpf                = bnxt_xdp,
10241         .ndo_bridge_getlink     = bnxt_bridge_getlink,
10242         .ndo_bridge_setlink     = bnxt_bridge_setlink,
10243         .ndo_get_devlink_port   = bnxt_get_devlink_port,
10244 };
10245
10246 static void bnxt_remove_one(struct pci_dev *pdev)
10247 {
10248         struct net_device *dev = pci_get_drvdata(pdev);
10249         struct bnxt *bp = netdev_priv(dev);
10250
10251         if (BNXT_PF(bp)) {
10252                 bnxt_sriov_disable(bp);
10253                 bnxt_dl_unregister(bp);
10254         }
10255
10256         pci_disable_pcie_error_reporting(pdev);
10257         unregister_netdev(dev);
10258         bnxt_shutdown_tc(bp);
10259         bnxt_cancel_sp_work(bp);
10260         bp->sp_event = 0;
10261
10262         bnxt_clear_int_mode(bp);
10263         bnxt_hwrm_func_drv_unrgtr(bp);
10264         bnxt_free_hwrm_resources(bp);
10265         bnxt_free_hwrm_short_cmd_req(bp);
10266         bnxt_ethtool_free(bp);
10267         bnxt_dcb_free(bp);
10268         kfree(bp->edev);
10269         bp->edev = NULL;
10270         bnxt_cleanup_pci(bp);
10271         bnxt_free_ctx_mem(bp);
10272         kfree(bp->ctx);
10273         bp->ctx = NULL;
10274         bnxt_free_port_stats(bp);
10275         free_netdev(dev);
10276 }
10277
10278 static int bnxt_probe_phy(struct bnxt *bp)
10279 {
10280         int rc = 0;
10281         struct bnxt_link_info *link_info = &bp->link_info;
10282
10283         rc = bnxt_hwrm_phy_qcaps(bp);
10284         if (rc) {
10285                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10286                            rc);
10287                 return rc;
10288         }
10289         mutex_init(&bp->link_lock);
10290
10291         rc = bnxt_update_link(bp, false);
10292         if (rc) {
10293                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10294                            rc);
10295                 return rc;
10296         }
10297
10298         /* Older firmware does not have supported_auto_speeds, so assume
10299          * that all supported speeds can be autonegotiated.
10300          */
10301         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10302                 link_info->support_auto_speeds = link_info->support_speeds;
10303
10304         /*initialize the ethool setting copy with NVM settings */
10305         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10306                 link_info->autoneg = BNXT_AUTONEG_SPEED;
10307                 if (bp->hwrm_spec_code >= 0x10201) {
10308                         if (link_info->auto_pause_setting &
10309                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10310                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10311                 } else {
10312                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10313                 }
10314                 link_info->advertising = link_info->auto_link_speeds;
10315         } else {
10316                 link_info->req_link_speed = link_info->force_link_speed;
10317                 link_info->req_duplex = link_info->duplex_setting;
10318         }
10319         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10320                 link_info->req_flow_ctrl =
10321                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10322         else
10323                 link_info->req_flow_ctrl = link_info->force_pause_setting;
10324         return rc;
10325 }
10326
10327 static int bnxt_get_max_irq(struct pci_dev *pdev)
10328 {
10329         u16 ctrl;
10330
10331         if (!pdev->msix_cap)
10332                 return 1;
10333
10334         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10335         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10336 }
10337
10338 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10339                                 int *max_cp)
10340 {
10341         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10342         int max_ring_grps = 0, max_irq;
10343
10344         *max_tx = hw_resc->max_tx_rings;
10345         *max_rx = hw_resc->max_rx_rings;
10346         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10347         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10348                         bnxt_get_ulp_msix_num(bp),
10349                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10350         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10351                 *max_cp = min_t(int, *max_cp, max_irq);
10352         max_ring_grps = hw_resc->max_hw_ring_grps;
10353         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10354                 *max_cp -= 1;
10355                 *max_rx -= 2;
10356         }
10357         if (bp->flags & BNXT_FLAG_AGG_RINGS)
10358                 *max_rx >>= 1;
10359         if (bp->flags & BNXT_FLAG_CHIP_P5) {
10360                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10361                 /* On P5 chips, max_cp output param should be available NQs */
10362                 *max_cp = max_irq;
10363         }
10364         *max_rx = min_t(int, *max_rx, max_ring_grps);
10365 }
10366
10367 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10368 {
10369         int rx, tx, cp;
10370
10371         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10372         *max_rx = rx;
10373         *max_tx = tx;
10374         if (!rx || !tx || !cp)
10375                 return -ENOMEM;
10376
10377         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10378 }
10379
10380 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10381                                bool shared)
10382 {
10383         int rc;
10384
10385         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10386         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10387                 /* Not enough rings, try disabling agg rings. */
10388                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10389                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10390                 if (rc) {
10391                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
10392                         bp->flags |= BNXT_FLAG_AGG_RINGS;
10393                         return rc;
10394                 }
10395                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10396                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10397                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10398                 bnxt_set_ring_params(bp);
10399         }
10400
10401         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10402                 int max_cp, max_stat, max_irq;
10403
10404                 /* Reserve minimum resources for RoCE */
10405                 max_cp = bnxt_get_max_func_cp_rings(bp);
10406                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10407                 max_irq = bnxt_get_max_func_irqs(bp);
10408                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10409                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10410                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10411                         return 0;
10412
10413                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10414                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10415                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10416                 max_cp = min_t(int, max_cp, max_irq);
10417                 max_cp = min_t(int, max_cp, max_stat);
10418                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10419                 if (rc)
10420                         rc = 0;
10421         }
10422         return rc;
10423 }
10424
10425 /* In initial default shared ring setting, each shared ring must have a
10426  * RX/TX ring pair.
10427  */
10428 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10429 {
10430         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10431         bp->rx_nr_rings = bp->cp_nr_rings;
10432         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10433         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10434 }
10435
10436 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10437 {
10438         int dflt_rings, max_rx_rings, max_tx_rings, rc;
10439
10440         if (!bnxt_can_reserve_rings(bp))
10441                 return 0;
10442
10443         if (sh)
10444                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10445         dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
10446         /* Reduce default rings on multi-port cards so that total default
10447          * rings do not exceed CPU count.
10448          */
10449         if (bp->port_count > 1) {
10450                 int max_rings =
10451                         max_t(int, num_online_cpus() / bp->port_count, 1);
10452
10453                 dflt_rings = min_t(int, dflt_rings, max_rings);
10454         }
10455         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10456         if (rc)
10457                 return rc;
10458         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10459         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10460         if (sh)
10461                 bnxt_trim_dflt_sh_rings(bp);
10462         else
10463                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10464         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10465
10466         rc = __bnxt_reserve_rings(bp);
10467         if (rc)
10468                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10469         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10470         if (sh)
10471                 bnxt_trim_dflt_sh_rings(bp);
10472
10473         /* Rings may have been trimmed, re-reserve the trimmed rings. */
10474         if (bnxt_need_reserve_rings(bp)) {
10475                 rc = __bnxt_reserve_rings(bp);
10476                 if (rc)
10477                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10478                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10479         }
10480         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10481                 bp->rx_nr_rings++;
10482                 bp->cp_nr_rings++;
10483         }
10484         return rc;
10485 }
10486
10487 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10488 {
10489         int rc;
10490
10491         if (bp->tx_nr_rings)
10492                 return 0;
10493
10494         bnxt_ulp_irq_stop(bp);
10495         bnxt_clear_int_mode(bp);
10496         rc = bnxt_set_dflt_rings(bp, true);
10497         if (rc) {
10498                 netdev_err(bp->dev, "Not enough rings available.\n");
10499                 goto init_dflt_ring_err;
10500         }
10501         rc = bnxt_init_int_mode(bp);
10502         if (rc)
10503                 goto init_dflt_ring_err;
10504
10505         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10506         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10507                 bp->flags |= BNXT_FLAG_RFS;
10508                 bp->dev->features |= NETIF_F_NTUPLE;
10509         }
10510 init_dflt_ring_err:
10511         bnxt_ulp_irq_restart(bp, rc);
10512         return rc;
10513 }
10514
10515 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10516 {
10517         int rc;
10518
10519         ASSERT_RTNL();
10520         bnxt_hwrm_func_qcaps(bp);
10521
10522         if (netif_running(bp->dev))
10523                 __bnxt_close_nic(bp, true, false);
10524
10525         bnxt_ulp_irq_stop(bp);
10526         bnxt_clear_int_mode(bp);
10527         rc = bnxt_init_int_mode(bp);
10528         bnxt_ulp_irq_restart(bp, rc);
10529
10530         if (netif_running(bp->dev)) {
10531                 if (rc)
10532                         dev_close(bp->dev);
10533                 else
10534                         rc = bnxt_open_nic(bp, true, false);
10535         }
10536
10537         return rc;
10538 }
10539
10540 static int bnxt_init_mac_addr(struct bnxt *bp)
10541 {
10542         int rc = 0;
10543
10544         if (BNXT_PF(bp)) {
10545                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10546         } else {
10547 #ifdef CONFIG_BNXT_SRIOV
10548                 struct bnxt_vf_info *vf = &bp->vf;
10549                 bool strict_approval = true;
10550
10551                 if (is_valid_ether_addr(vf->mac_addr)) {
10552                         /* overwrite netdev dev_addr with admin VF MAC */
10553                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10554                         /* Older PF driver or firmware may not approve this
10555                          * correctly.
10556                          */
10557                         strict_approval = false;
10558                 } else {
10559                         eth_hw_addr_random(bp->dev);
10560                 }
10561                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10562 #endif
10563         }
10564         return rc;
10565 }
10566
10567 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
10568 {
10569         struct pci_dev *pdev = bp->pdev;
10570         int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
10571         u32 dw;
10572
10573         if (!pos) {
10574                 netdev_info(bp->dev, "Unable do read adapter's DSN");
10575                 return -EOPNOTSUPP;
10576         }
10577
10578         /* DSN (two dw) is at an offset of 4 from the cap pos */
10579         pos += 4;
10580         pci_read_config_dword(pdev, pos, &dw);
10581         put_unaligned_le32(dw, &dsn[0]);
10582         pci_read_config_dword(pdev, pos + 4, &dw);
10583         put_unaligned_le32(dw, &dsn[4]);
10584         return 0;
10585 }
10586
10587 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10588 {
10589         static int version_printed;
10590         struct net_device *dev;
10591         struct bnxt *bp;
10592         int rc, max_irqs;
10593
10594         if (pci_is_bridge(pdev))
10595                 return -ENODEV;
10596
10597         if (version_printed++ == 0)
10598                 pr_info("%s", version);
10599
10600         max_irqs = bnxt_get_max_irq(pdev);
10601         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10602         if (!dev)
10603                 return -ENOMEM;
10604
10605         bp = netdev_priv(dev);
10606         bnxt_set_max_func_irqs(bp, max_irqs);
10607
10608         if (bnxt_vf_pciid(ent->driver_data))
10609                 bp->flags |= BNXT_FLAG_VF;
10610
10611         if (pdev->msix_cap)
10612                 bp->flags |= BNXT_FLAG_MSIX_CAP;
10613
10614         rc = bnxt_init_board(pdev, dev);
10615         if (rc < 0)
10616                 goto init_err_free;
10617
10618         dev->netdev_ops = &bnxt_netdev_ops;
10619         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10620         dev->ethtool_ops = &bnxt_ethtool_ops;
10621         pci_set_drvdata(pdev, dev);
10622
10623         rc = bnxt_alloc_hwrm_resources(bp);
10624         if (rc)
10625                 goto init_err_pci_clean;
10626
10627         mutex_init(&bp->hwrm_cmd_lock);
10628         rc = bnxt_hwrm_ver_get(bp);
10629         if (rc)
10630                 goto init_err_pci_clean;
10631
10632         if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10633                 rc = bnxt_alloc_kong_hwrm_resources(bp);
10634                 if (rc)
10635                         bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10636         }
10637
10638         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10639             bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10640                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10641                 if (rc)
10642                         goto init_err_pci_clean;
10643         }
10644
10645         if (BNXT_CHIP_P5(bp))
10646                 bp->flags |= BNXT_FLAG_CHIP_P5;
10647
10648         rc = bnxt_hwrm_func_reset(bp);
10649         if (rc)
10650                 goto init_err_pci_clean;
10651
10652         bnxt_hwrm_fw_set_time(bp);
10653
10654         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10655                            NETIF_F_TSO | NETIF_F_TSO6 |
10656                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10657                            NETIF_F_GSO_IPXIP4 |
10658                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10659                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10660                            NETIF_F_RXCSUM | NETIF_F_GRO;
10661
10662         if (BNXT_SUPPORTS_TPA(bp))
10663                 dev->hw_features |= NETIF_F_LRO;
10664
10665         dev->hw_enc_features =
10666                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10667                         NETIF_F_TSO | NETIF_F_TSO6 |
10668                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10669                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10670                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10671         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10672                                     NETIF_F_GSO_GRE_CSUM;
10673         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10674         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10675                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10676         if (BNXT_SUPPORTS_TPA(bp))
10677                 dev->hw_features |= NETIF_F_GRO_HW;
10678         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10679         if (dev->features & NETIF_F_GRO_HW)
10680                 dev->features &= ~NETIF_F_LRO;
10681         dev->priv_flags |= IFF_UNICAST_FLT;
10682
10683 #ifdef CONFIG_BNXT_SRIOV
10684         init_waitqueue_head(&bp->sriov_cfg_wait);
10685         mutex_init(&bp->sriov_lock);
10686 #endif
10687         if (BNXT_SUPPORTS_TPA(bp)) {
10688                 bp->gro_func = bnxt_gro_func_5730x;
10689                 if (BNXT_CHIP_P4(bp))
10690                         bp->gro_func = bnxt_gro_func_5731x;
10691         }
10692         if (!BNXT_CHIP_P4_PLUS(bp))
10693                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10694
10695         rc = bnxt_hwrm_func_drv_rgtr(bp);
10696         if (rc)
10697                 goto init_err_pci_clean;
10698
10699         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10700         if (rc)
10701                 goto init_err_pci_clean;
10702
10703         bp->ulp_probe = bnxt_ulp_probe;
10704
10705         rc = bnxt_hwrm_queue_qportcfg(bp);
10706         if (rc) {
10707                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10708                            rc);
10709                 rc = -1;
10710                 goto init_err_pci_clean;
10711         }
10712         /* Get the MAX capabilities for this function */
10713         rc = bnxt_hwrm_func_qcaps(bp);
10714         if (rc) {
10715                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10716                            rc);
10717                 rc = -1;
10718                 goto init_err_pci_clean;
10719         }
10720
10721         rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
10722         if (rc)
10723                 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
10724                             rc);
10725
10726         rc = bnxt_init_mac_addr(bp);
10727         if (rc) {
10728                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10729                 rc = -EADDRNOTAVAIL;
10730                 goto init_err_pci_clean;
10731         }
10732
10733         if (BNXT_PF(bp)) {
10734                 /* Read the adapter's DSN to use as the eswitch switch_id */
10735                 rc = bnxt_pcie_dsn_get(bp, bp->switch_id);
10736                 if (rc)
10737                         goto init_err_pci_clean;
10738         }
10739         bnxt_hwrm_func_qcfg(bp);
10740         bnxt_hwrm_vnic_qcaps(bp);
10741         bnxt_hwrm_port_led_qcaps(bp);
10742         bnxt_ethtool_init(bp);
10743         bnxt_dcb_init(bp);
10744
10745         /* MTU range: 60 - FW defined max */
10746         dev->min_mtu = ETH_ZLEN;
10747         dev->max_mtu = bp->max_mtu;
10748
10749         rc = bnxt_probe_phy(bp);
10750         if (rc)
10751                 goto init_err_pci_clean;
10752
10753         bnxt_set_rx_skb_mode(bp, false);
10754         bnxt_set_tpa_flags(bp);
10755         bnxt_set_ring_params(bp);
10756         rc = bnxt_set_dflt_rings(bp, true);
10757         if (rc) {
10758                 netdev_err(bp->dev, "Not enough rings available.\n");
10759                 rc = -ENOMEM;
10760                 goto init_err_pci_clean;
10761         }
10762
10763         /* Default RSS hash cfg. */
10764         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10765                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10766                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10767                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10768         if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10769                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10770                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10771                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10772         }
10773
10774         if (bnxt_rfs_supported(bp)) {
10775                 dev->hw_features |= NETIF_F_NTUPLE;
10776                 if (bnxt_rfs_capable(bp)) {
10777                         bp->flags |= BNXT_FLAG_RFS;
10778                         dev->features |= NETIF_F_NTUPLE;
10779                 }
10780         }
10781
10782         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10783                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10784
10785         rc = bnxt_init_int_mode(bp);
10786         if (rc)
10787                 goto init_err_pci_clean;
10788
10789         /* No TC has been set yet and rings may have been trimmed due to
10790          * limited MSIX, so we re-initialize the TX rings per TC.
10791          */
10792         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10793
10794         bnxt_get_wol_settings(bp);
10795         if (bp->flags & BNXT_FLAG_WOL_CAP)
10796                 device_set_wakeup_enable(&pdev->dev, bp->wol);
10797         else
10798                 device_set_wakeup_capable(&pdev->dev, false);
10799
10800         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10801
10802         bnxt_hwrm_coal_params_qcaps(bp);
10803
10804         if (BNXT_PF(bp)) {
10805                 if (!bnxt_pf_wq) {
10806                         bnxt_pf_wq =
10807                                 create_singlethread_workqueue("bnxt_pf_wq");
10808                         if (!bnxt_pf_wq) {
10809                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10810                                 goto init_err_pci_clean;
10811                         }
10812                 }
10813                 bnxt_init_tc(bp);
10814         }
10815
10816         rc = register_netdev(dev);
10817         if (rc)
10818                 goto init_err_cleanup_tc;
10819
10820         if (BNXT_PF(bp))
10821                 bnxt_dl_register(bp);
10822
10823         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10824                     board_info[ent->driver_data].name,
10825                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
10826         pcie_print_link_status(pdev);
10827
10828         return 0;
10829
10830 init_err_cleanup_tc:
10831         bnxt_shutdown_tc(bp);
10832         bnxt_clear_int_mode(bp);
10833
10834 init_err_pci_clean:
10835         bnxt_free_hwrm_short_cmd_req(bp);
10836         bnxt_free_hwrm_resources(bp);
10837         bnxt_free_ctx_mem(bp);
10838         kfree(bp->ctx);
10839         bp->ctx = NULL;
10840         bnxt_cleanup_pci(bp);
10841
10842 init_err_free:
10843         free_netdev(dev);
10844         return rc;
10845 }
10846
10847 static void bnxt_shutdown(struct pci_dev *pdev)
10848 {
10849         struct net_device *dev = pci_get_drvdata(pdev);
10850         struct bnxt *bp;
10851
10852         if (!dev)
10853                 return;
10854
10855         rtnl_lock();
10856         bp = netdev_priv(dev);
10857         if (!bp)
10858                 goto shutdown_exit;
10859
10860         if (netif_running(dev))
10861                 dev_close(dev);
10862
10863         bnxt_ulp_shutdown(bp);
10864
10865         if (system_state == SYSTEM_POWER_OFF) {
10866                 bnxt_clear_int_mode(bp);
10867                 pci_disable_device(pdev);
10868                 pci_wake_from_d3(pdev, bp->wol);
10869                 pci_set_power_state(pdev, PCI_D3hot);
10870         }
10871
10872 shutdown_exit:
10873         rtnl_unlock();
10874 }
10875
10876 #ifdef CONFIG_PM_SLEEP
10877 static int bnxt_suspend(struct device *device)
10878 {
10879         struct pci_dev *pdev = to_pci_dev(device);
10880         struct net_device *dev = pci_get_drvdata(pdev);
10881         struct bnxt *bp = netdev_priv(dev);
10882         int rc = 0;
10883
10884         rtnl_lock();
10885         if (netif_running(dev)) {
10886                 netif_device_detach(dev);
10887                 rc = bnxt_close(dev);
10888         }
10889         bnxt_hwrm_func_drv_unrgtr(bp);
10890         rtnl_unlock();
10891         return rc;
10892 }
10893
10894 static int bnxt_resume(struct device *device)
10895 {
10896         struct pci_dev *pdev = to_pci_dev(device);
10897         struct net_device *dev = pci_get_drvdata(pdev);
10898         struct bnxt *bp = netdev_priv(dev);
10899         int rc = 0;
10900
10901         rtnl_lock();
10902         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10903                 rc = -ENODEV;
10904                 goto resume_exit;
10905         }
10906         rc = bnxt_hwrm_func_reset(bp);
10907         if (rc) {
10908                 rc = -EBUSY;
10909                 goto resume_exit;
10910         }
10911         bnxt_get_wol_settings(bp);
10912         if (netif_running(dev)) {
10913                 rc = bnxt_open(dev);
10914                 if (!rc)
10915                         netif_device_attach(dev);
10916         }
10917
10918 resume_exit:
10919         rtnl_unlock();
10920         return rc;
10921 }
10922
10923 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10924 #define BNXT_PM_OPS (&bnxt_pm_ops)
10925
10926 #else
10927
10928 #define BNXT_PM_OPS NULL
10929
10930 #endif /* CONFIG_PM_SLEEP */
10931
10932 /**
10933  * bnxt_io_error_detected - called when PCI error is detected
10934  * @pdev: Pointer to PCI device
10935  * @state: The current pci connection state
10936  *
10937  * This function is called after a PCI bus error affecting
10938  * this device has been detected.
10939  */
10940 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10941                                                pci_channel_state_t state)
10942 {
10943         struct net_device *netdev = pci_get_drvdata(pdev);
10944         struct bnxt *bp = netdev_priv(netdev);
10945
10946         netdev_info(netdev, "PCI I/O error detected\n");
10947
10948         rtnl_lock();
10949         netif_device_detach(netdev);
10950
10951         bnxt_ulp_stop(bp);
10952
10953         if (state == pci_channel_io_perm_failure) {
10954                 rtnl_unlock();
10955                 return PCI_ERS_RESULT_DISCONNECT;
10956         }
10957
10958         if (netif_running(netdev))
10959                 bnxt_close(netdev);
10960
10961         pci_disable_device(pdev);
10962         rtnl_unlock();
10963
10964         /* Request a slot slot reset. */
10965         return PCI_ERS_RESULT_NEED_RESET;
10966 }
10967
10968 /**
10969  * bnxt_io_slot_reset - called after the pci bus has been reset.
10970  * @pdev: Pointer to PCI device
10971  *
10972  * Restart the card from scratch, as if from a cold-boot.
10973  * At this point, the card has exprienced a hard reset,
10974  * followed by fixups by BIOS, and has its config space
10975  * set up identically to what it was at cold boot.
10976  */
10977 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10978 {
10979         struct net_device *netdev = pci_get_drvdata(pdev);
10980         struct bnxt *bp = netdev_priv(netdev);
10981         int err = 0;
10982         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10983
10984         netdev_info(bp->dev, "PCI Slot Reset\n");
10985
10986         rtnl_lock();
10987
10988         if (pci_enable_device(pdev)) {
10989                 dev_err(&pdev->dev,
10990                         "Cannot re-enable PCI device after reset.\n");
10991         } else {
10992                 pci_set_master(pdev);
10993
10994                 err = bnxt_hwrm_func_reset(bp);
10995                 if (!err && netif_running(netdev))
10996                         err = bnxt_open(netdev);
10997
10998                 if (!err) {
10999                         result = PCI_ERS_RESULT_RECOVERED;
11000                         bnxt_ulp_start(bp);
11001                 }
11002         }
11003
11004         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
11005                 dev_close(netdev);
11006
11007         rtnl_unlock();
11008
11009         return PCI_ERS_RESULT_RECOVERED;
11010 }
11011
11012 /**
11013  * bnxt_io_resume - called when traffic can start flowing again.
11014  * @pdev: Pointer to PCI device
11015  *
11016  * This callback is called when the error recovery driver tells
11017  * us that its OK to resume normal operation.
11018  */
11019 static void bnxt_io_resume(struct pci_dev *pdev)
11020 {
11021         struct net_device *netdev = pci_get_drvdata(pdev);
11022
11023         rtnl_lock();
11024
11025         netif_device_attach(netdev);
11026
11027         rtnl_unlock();
11028 }
11029
11030 static const struct pci_error_handlers bnxt_err_handler = {
11031         .error_detected = bnxt_io_error_detected,
11032         .slot_reset     = bnxt_io_slot_reset,
11033         .resume         = bnxt_io_resume
11034 };
11035
11036 static struct pci_driver bnxt_pci_driver = {
11037         .name           = DRV_MODULE_NAME,
11038         .id_table       = bnxt_pci_tbl,
11039         .probe          = bnxt_init_one,
11040         .remove         = bnxt_remove_one,
11041         .shutdown       = bnxt_shutdown,
11042         .driver.pm      = BNXT_PM_OPS,
11043         .err_handler    = &bnxt_err_handler,
11044 #if defined(CONFIG_BNXT_SRIOV)
11045         .sriov_configure = bnxt_sriov_configure,
11046 #endif
11047 };
11048
11049 static int __init bnxt_init(void)
11050 {
11051         bnxt_debug_init();
11052         return pci_register_driver(&bnxt_pci_driver);
11053 }
11054
11055 static void __exit bnxt_exit(void)
11056 {
11057         pci_unregister_driver(&bnxt_pci_driver);
11058         if (bnxt_pf_wq)
11059                 destroy_workqueue(bnxt_pf_wq);
11060         bnxt_debug_exit();
11061 }
11062
11063 module_init(bnxt_init);
11064 module_exit(bnxt_exit);