1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
16 * Original driver contributed by SLS.
17 * Major updates contributed by GlobalLogic
20 #include <linux/atomic.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/if_vlan.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/mii.h>
30 #include <linux/netdevice.h>
31 #include <linux/of_device.h>
32 #include <linux/of_mdio.h>
33 #include <linux/of_net.h>
34 #include <linux/of_platform.h>
35 #include <linux/pcs-altera-tse.h>
36 #include <linux/phy.h>
37 #include <linux/platform_device.h>
38 #include <linux/skbuff.h>
39 #include <asm/cacheflush.h>
41 #include "altera_utils.h"
42 #include "altera_tse.h"
43 #include "altera_sgdma.h"
44 #include "altera_msgdma.h"
46 static atomic_t instance_count = ATOMIC_INIT(~0);
47 /* Module parameters */
48 static int debug = -1;
49 module_param(debug, int, 0644);
50 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
52 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
53 NETIF_MSG_LINK | NETIF_MSG_IFUP |
56 #define RX_DESCRIPTORS 64
57 static int dma_rx_num = RX_DESCRIPTORS;
58 module_param(dma_rx_num, int, 0644);
59 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
61 #define TX_DESCRIPTORS 64
62 static int dma_tx_num = TX_DESCRIPTORS;
63 module_param(dma_tx_num, int, 0644);
64 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
69 /* Make sure DMA buffer size is larger than the max frame size
70 * plus some alignment offset and a VLAN header. If the max frame size is
71 * 1518, a VLAN header would be additional 4 bytes and additional
72 * headroom for alignment is 2 bytes, 2048 is just fine.
74 #define ALTERA_RXDMABUFFER_SIZE 2048
76 /* Allow network stack to resume queuing packets after we've
77 * finished transmitting at least 1/4 of the packets in the queue.
79 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
81 #define TXQUEUESTOP_THRESHHOLD 2
83 static const struct of_device_id altera_tse_ids[];
85 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
87 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
90 /* MDIO specific functions
92 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
94 struct net_device *ndev = bus->priv;
95 struct altera_tse_private *priv = netdev_priv(ndev);
97 /* set MDIO address */
98 csrwr32((mii_id & 0x1f), priv->mac_dev,
99 tse_csroffs(mdio_phy1_addr));
102 return csrrd32(priv->mac_dev,
103 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
106 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
109 struct net_device *ndev = bus->priv;
110 struct altera_tse_private *priv = netdev_priv(ndev);
112 /* set MDIO address */
113 csrwr32((mii_id & 0x1f), priv->mac_dev,
114 tse_csroffs(mdio_phy1_addr));
117 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
121 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
123 struct altera_tse_private *priv = netdev_priv(dev);
124 struct device_node *mdio_node = NULL;
125 struct device_node *child_node = NULL;
126 struct mii_bus *mdio = NULL;
129 for_each_child_of_node(priv->device->of_node, child_node) {
130 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
131 mdio_node = child_node;
137 netdev_dbg(dev, "FOUND MDIO subnode\n");
139 netdev_dbg(dev, "NO MDIO subnode\n");
143 mdio = mdiobus_alloc();
145 netdev_err(dev, "Error allocating MDIO bus\n");
150 mdio->name = ALTERA_TSE_RESOURCE_NAME;
151 mdio->read = &altera_tse_mdio_read;
152 mdio->write = &altera_tse_mdio_write;
153 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
156 mdio->parent = priv->device;
158 ret = of_mdiobus_register(mdio, mdio_node);
160 netdev_err(dev, "Cannot register MDIO bus %s\n",
164 of_node_put(mdio_node);
166 if (netif_msg_drv(priv))
167 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
175 of_node_put(mdio_node);
179 static void altera_tse_mdio_destroy(struct net_device *dev)
181 struct altera_tse_private *priv = netdev_priv(dev);
183 if (priv->mdio == NULL)
186 if (netif_msg_drv(priv))
187 netdev_info(dev, "MDIO bus %s: removed\n",
190 mdiobus_unregister(priv->mdio);
191 mdiobus_free(priv->mdio);
195 static int tse_init_rx_buffer(struct altera_tse_private *priv,
196 struct tse_buffer *rxbuffer, int len)
198 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
202 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
206 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
207 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
208 dev_kfree_skb_any(rxbuffer->skb);
211 rxbuffer->dma_addr &= (dma_addr_t)~3;
216 static void tse_free_rx_buffer(struct altera_tse_private *priv,
217 struct tse_buffer *rxbuffer)
219 dma_addr_t dma_addr = rxbuffer->dma_addr;
220 struct sk_buff *skb = rxbuffer->skb;
224 dma_unmap_single(priv->device, dma_addr,
227 dev_kfree_skb_any(skb);
228 rxbuffer->skb = NULL;
229 rxbuffer->dma_addr = 0;
233 /* Unmap and free Tx buffer resources
235 static void tse_free_tx_buffer(struct altera_tse_private *priv,
236 struct tse_buffer *buffer)
238 if (buffer->dma_addr) {
239 if (buffer->mapped_as_page)
240 dma_unmap_page(priv->device, buffer->dma_addr,
241 buffer->len, DMA_TO_DEVICE);
243 dma_unmap_single(priv->device, buffer->dma_addr,
244 buffer->len, DMA_TO_DEVICE);
245 buffer->dma_addr = 0;
248 dev_kfree_skb_any(buffer->skb);
253 static int alloc_init_skbufs(struct altera_tse_private *priv)
255 unsigned int rx_descs = priv->rx_ring_size;
256 unsigned int tx_descs = priv->tx_ring_size;
260 /* Create Rx ring buffer */
261 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
266 /* Create Tx ring buffer */
267 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
276 for (i = 0; i < rx_descs; i++) {
277 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
278 priv->rx_dma_buf_sz);
280 goto err_init_rx_buffers;
289 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
290 kfree(priv->tx_ring);
292 kfree(priv->rx_ring);
297 static void free_skbufs(struct net_device *dev)
299 struct altera_tse_private *priv = netdev_priv(dev);
300 unsigned int rx_descs = priv->rx_ring_size;
301 unsigned int tx_descs = priv->tx_ring_size;
304 /* Release the DMA TX/RX socket buffers */
305 for (i = 0; i < rx_descs; i++)
306 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
307 for (i = 0; i < tx_descs; i++)
308 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
311 kfree(priv->tx_ring);
314 /* Reallocate the skb for the reception process
316 static inline void tse_rx_refill(struct altera_tse_private *priv)
318 unsigned int rxsize = priv->rx_ring_size;
322 for (; priv->rx_cons - priv->rx_prod > 0;
324 entry = priv->rx_prod % rxsize;
325 if (likely(priv->rx_ring[entry].skb == NULL)) {
326 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
327 priv->rx_dma_buf_sz);
328 if (unlikely(ret != 0))
330 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
335 /* Pull out the VLAN tag and fix up the packet
337 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
339 struct ethhdr *eth_hdr;
342 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
343 !__vlan_get_tag(skb, &vid)) {
344 eth_hdr = (struct ethhdr *)skb->data;
345 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
346 skb_pull(skb, VLAN_HLEN);
347 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
351 /* Receive a packet: retrieve and pass over to upper levels
353 static int tse_rx(struct altera_tse_private *priv, int limit)
355 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
356 unsigned int next_entry;
357 unsigned int count = 0;
363 /* Check for count < limit first as get_rx_status is changing
364 * the response-fifo so we must process the next packet
365 * after calling get_rx_status if a response is pending.
366 * (reading the last byte of the response pops the value from the fifo.)
368 while ((count < limit) &&
369 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
370 pktstatus = rxstatus >> 16;
371 pktlength = rxstatus & 0xffff;
373 if ((pktstatus & 0xFF) || (pktlength == 0))
374 netdev_err(priv->dev,
375 "RCV pktstatus %08X pktlength %08X\n",
376 pktstatus, pktlength);
378 /* DMA transfer from TSE starts with 2 additional bytes for
379 * IP payload alignment. Status returned by get_rx_status()
380 * contains DMA transfer length. Packet is 2 bytes shorter.
385 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
387 skb = priv->rx_ring[entry].skb;
388 if (unlikely(!skb)) {
389 netdev_err(priv->dev,
390 "%s: Inconsistent Rx descriptor chain\n",
392 priv->dev->stats.rx_dropped++;
395 priv->rx_ring[entry].skb = NULL;
397 skb_put(skb, pktlength);
399 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
400 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
402 if (netif_msg_pktdata(priv)) {
403 netdev_info(priv->dev, "frame received %d bytes\n",
405 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
406 16, 1, skb->data, pktlength, true);
409 tse_rx_vlan(priv->dev, skb);
411 skb->protocol = eth_type_trans(skb, priv->dev);
412 skb_checksum_none_assert(skb);
414 napi_gro_receive(&priv->napi, skb);
416 priv->dev->stats.rx_packets++;
417 priv->dev->stats.rx_bytes += pktlength;
427 /* Reclaim resources after transmission completes
429 static int tse_tx_complete(struct altera_tse_private *priv)
431 unsigned int txsize = priv->tx_ring_size;
432 struct tse_buffer *tx_buff;
437 spin_lock(&priv->tx_lock);
439 ready = priv->dmaops->tx_completions(priv);
441 /* Free sent buffers */
442 while (ready && (priv->tx_cons != priv->tx_prod)) {
443 entry = priv->tx_cons % txsize;
444 tx_buff = &priv->tx_ring[entry];
446 if (netif_msg_tx_done(priv))
447 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
448 __func__, priv->tx_prod, priv->tx_cons);
450 if (likely(tx_buff->skb))
451 priv->dev->stats.tx_packets++;
453 tse_free_tx_buffer(priv, tx_buff);
460 if (unlikely(netif_queue_stopped(priv->dev) &&
461 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
462 if (netif_queue_stopped(priv->dev) &&
463 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
464 if (netif_msg_tx_done(priv))
465 netdev_dbg(priv->dev, "%s: restart transmit\n",
467 netif_wake_queue(priv->dev);
471 spin_unlock(&priv->tx_lock);
475 /* NAPI polling function
477 static int tse_poll(struct napi_struct *napi, int budget)
479 struct altera_tse_private *priv =
480 container_of(napi, struct altera_tse_private, napi);
481 unsigned long int flags;
484 tse_tx_complete(priv);
486 rxcomplete = tse_rx(priv, budget);
488 if (rxcomplete < budget) {
490 napi_complete_done(napi, rxcomplete);
492 netdev_dbg(priv->dev,
493 "NAPI Complete, did %d packets with budget %d\n",
496 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
497 priv->dmaops->enable_rxirq(priv);
498 priv->dmaops->enable_txirq(priv);
499 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
504 /* DMA TX & RX FIFO interrupt routing
506 static irqreturn_t altera_isr(int irq, void *dev_id)
508 struct net_device *dev = dev_id;
509 struct altera_tse_private *priv;
511 if (unlikely(!dev)) {
512 pr_err("%s: invalid dev pointer\n", __func__);
515 priv = netdev_priv(dev);
517 spin_lock(&priv->rxdma_irq_lock);
519 priv->dmaops->clear_rxirq(priv);
520 priv->dmaops->clear_txirq(priv);
521 spin_unlock(&priv->rxdma_irq_lock);
523 if (likely(napi_schedule_prep(&priv->napi))) {
524 spin_lock(&priv->rxdma_irq_lock);
525 priv->dmaops->disable_rxirq(priv);
526 priv->dmaops->disable_txirq(priv);
527 spin_unlock(&priv->rxdma_irq_lock);
528 __napi_schedule(&priv->napi);
535 /* Transmit a packet (called by the kernel). Dispatches
536 * either the SGDMA method for transmitting or the
537 * MSGDMA method, assumes no scatter/gather support,
538 * implying an assumption that there's only one
539 * physically contiguous fragment starting at
540 * skb->data, for length of skb_headlen(skb).
542 static netdev_tx_t tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
544 struct altera_tse_private *priv = netdev_priv(dev);
545 unsigned int nopaged_len = skb_headlen(skb);
546 unsigned int txsize = priv->tx_ring_size;
547 int nfrags = skb_shinfo(skb)->nr_frags;
548 struct tse_buffer *buffer = NULL;
549 netdev_tx_t ret = NETDEV_TX_OK;
553 spin_lock_bh(&priv->tx_lock);
555 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
556 if (!netif_queue_stopped(dev)) {
557 netif_stop_queue(dev);
558 /* This is a hard error, log it. */
559 netdev_err(priv->dev,
560 "%s: Tx list full when queue awake\n",
563 ret = NETDEV_TX_BUSY;
567 /* Map the first skb fragment */
568 entry = priv->tx_prod % txsize;
569 buffer = &priv->tx_ring[entry];
571 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
573 if (dma_mapping_error(priv->device, dma_addr)) {
574 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
580 buffer->dma_addr = dma_addr;
581 buffer->len = nopaged_len;
583 priv->dmaops->tx_buffer(priv, buffer);
585 skb_tx_timestamp(skb);
588 dev->stats.tx_bytes += skb->len;
590 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
591 if (netif_msg_hw(priv))
592 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
594 netif_stop_queue(dev);
598 spin_unlock_bh(&priv->tx_lock);
603 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
605 struct altera_tse_private *priv = netdev_priv(dev);
606 struct device_node *np = priv->device->of_node;
609 ret = of_get_phy_mode(np, &priv->phy_iface);
611 /* Avoid get phy addr and create mdio if no phy is present */
615 /* try to get PHY address from device tree, use PHY autodetection if
616 * no valid address is given
619 if (of_property_read_u32(priv->device->of_node, "phy-addr",
621 priv->phy_addr = POLL_PHY;
624 if (!((priv->phy_addr == POLL_PHY) ||
625 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
626 netdev_err(dev, "invalid phy-addr specified %d\n",
631 /* Create/attach to MDIO bus */
632 ret = altera_tse_mdio_create(dev,
633 atomic_add_return(1, &instance_count));
641 static void tse_update_mac_addr(struct altera_tse_private *priv, const u8 *addr)
646 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
647 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
649 /* Set primary MAC address */
650 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
651 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
654 /* MAC software reset.
655 * When reset is triggered, the MAC function completes the current
656 * transmission or reception, and subsequently disables the transmit and
657 * receive logic, flushes the receive FIFO buffer, and resets the statistics
660 static int reset_mac(struct altera_tse_private *priv)
665 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
666 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
667 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
668 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
671 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
672 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
673 MAC_CMDCFG_SW_RESET))
678 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
679 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
680 dat &= ~MAC_CMDCFG_SW_RESET;
681 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
687 /* Initialize MAC core registers
689 static int init_mac(struct altera_tse_private *priv)
691 unsigned int cmd = 0;
695 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
696 priv->mac_dev, tse_csroffs(rx_section_empty));
698 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
699 tse_csroffs(rx_section_full));
701 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
702 tse_csroffs(rx_almost_empty));
704 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
705 tse_csroffs(rx_almost_full));
708 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
709 priv->mac_dev, tse_csroffs(tx_section_empty));
711 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
712 tse_csroffs(tx_section_full));
714 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
715 tse_csroffs(tx_almost_empty));
717 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
718 tse_csroffs(tx_almost_full));
720 /* MAC Address Configuration */
721 tse_update_mac_addr(priv, priv->dev->dev_addr);
723 /* MAC Function Configuration */
724 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
725 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
727 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
728 tse_csroffs(tx_ipg_length));
730 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
733 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
734 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
736 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
737 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
738 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
740 /* Set the MAC options */
741 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
742 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
743 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
744 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
747 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
748 cmd &= ~MAC_CMDCFG_TX_ENA;
749 cmd &= ~MAC_CMDCFG_RX_ENA;
751 /* Default speed and duplex setting, full/100 */
752 cmd &= ~MAC_CMDCFG_HD_ENA;
753 cmd &= ~MAC_CMDCFG_ETH_SPEED;
754 cmd &= ~MAC_CMDCFG_ENA_10;
756 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
758 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
759 tse_csroffs(pause_quanta));
761 if (netif_msg_hw(priv))
762 dev_dbg(priv->device,
763 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
768 /* Start/stop MAC transmission logic
770 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
772 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
775 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
777 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
779 csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
784 static int tse_change_mtu(struct net_device *dev, int new_mtu)
786 if (netif_running(dev)) {
787 netdev_err(dev, "must be stopped to change its MTU\n");
792 netdev_update_features(dev);
797 static void altera_tse_set_mcfilter(struct net_device *dev)
799 struct altera_tse_private *priv = netdev_priv(dev);
800 struct netdev_hw_addr *ha;
803 /* clear the hash filter */
804 for (i = 0; i < 64; i++)
805 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
807 netdev_for_each_mc_addr(ha, dev) {
808 unsigned int hash = 0;
811 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
812 unsigned char xor_bit = 0;
813 unsigned char octet = ha->addr[mac_octet];
814 unsigned int bitshift;
816 for (bitshift = 0; bitshift < 8; bitshift++)
817 xor_bit ^= ((octet >> bitshift) & 0x01);
819 hash = (hash << 1) | xor_bit;
821 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
826 static void altera_tse_set_mcfilterall(struct net_device *dev)
828 struct altera_tse_private *priv = netdev_priv(dev);
831 /* set the hash filter */
832 for (i = 0; i < 64; i++)
833 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
836 /* Set or clear the multicast filter for this adapter
838 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
840 struct altera_tse_private *priv = netdev_priv(dev);
842 spin_lock(&priv->mac_cfg_lock);
844 if (dev->flags & IFF_PROMISC)
845 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
846 MAC_CMDCFG_PROMIS_EN);
848 if (dev->flags & IFF_ALLMULTI)
849 altera_tse_set_mcfilterall(dev);
851 altera_tse_set_mcfilter(dev);
853 spin_unlock(&priv->mac_cfg_lock);
856 /* Set or clear the multicast filter for this adapter
858 static void tse_set_rx_mode(struct net_device *dev)
860 struct altera_tse_private *priv = netdev_priv(dev);
862 spin_lock(&priv->mac_cfg_lock);
864 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
865 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
866 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
867 MAC_CMDCFG_PROMIS_EN);
869 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
870 MAC_CMDCFG_PROMIS_EN);
872 spin_unlock(&priv->mac_cfg_lock);
875 /* Open and initialize the interface
877 static int tse_open(struct net_device *dev)
879 struct altera_tse_private *priv = netdev_priv(dev);
884 /* Reset and configure TSE MAC and probe associated PHY */
885 ret = priv->dmaops->init_dma(priv);
887 netdev_err(dev, "Cannot initialize DMA\n");
891 if (netif_msg_ifup(priv))
892 netdev_warn(dev, "device MAC address %pM\n",
895 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
896 netdev_warn(dev, "TSE revision %x\n", priv->revision);
898 spin_lock(&priv->mac_cfg_lock);
900 ret = reset_mac(priv);
901 /* Note that reset_mac will fail if the clocks are gated by the PHY
902 * due to the PHY being put into isolation or power down mode.
903 * This is not an error if reset fails due to no clock.
906 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
908 ret = init_mac(priv);
909 spin_unlock(&priv->mac_cfg_lock);
911 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
912 goto alloc_skbuf_error;
915 priv->dmaops->reset_dma(priv);
917 /* Create and initialize the TX/RX descriptors chains. */
918 priv->rx_ring_size = dma_rx_num;
919 priv->tx_ring_size = dma_tx_num;
920 ret = alloc_init_skbufs(priv);
922 netdev_err(dev, "DMA descriptors initialization failed\n");
923 goto alloc_skbuf_error;
927 /* Register RX interrupt */
928 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
931 netdev_err(dev, "Unable to register RX interrupt %d\n",
936 /* Register TX interrupt */
937 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
940 netdev_err(dev, "Unable to register TX interrupt %d\n",
942 goto tx_request_irq_error;
945 /* Enable DMA interrupts */
946 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
947 priv->dmaops->enable_rxirq(priv);
948 priv->dmaops->enable_txirq(priv);
950 /* Setup RX descriptor chain */
951 for (i = 0; i < priv->rx_ring_size; i++)
952 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
954 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
956 ret = phylink_of_phy_connect(priv->phylink, priv->device->of_node, 0);
958 netdev_err(dev, "could not connect phylink (%d)\n", ret);
959 goto tx_request_irq_error;
961 phylink_start(priv->phylink);
963 napi_enable(&priv->napi);
964 netif_start_queue(dev);
966 priv->dmaops->start_rxdma(priv);
968 /* Start MAC Rx/Tx */
969 spin_lock(&priv->mac_cfg_lock);
970 tse_set_mac(priv, true);
971 spin_unlock(&priv->mac_cfg_lock);
975 tx_request_irq_error:
976 free_irq(priv->rx_irq, dev);
984 /* Stop TSE MAC interface and put the device in an inactive state
986 static int tse_shutdown(struct net_device *dev)
988 struct altera_tse_private *priv = netdev_priv(dev);
989 unsigned long int flags;
992 phylink_stop(priv->phylink);
993 netif_stop_queue(dev);
994 napi_disable(&priv->napi);
996 /* Disable DMA interrupts */
997 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
998 priv->dmaops->disable_rxirq(priv);
999 priv->dmaops->disable_txirq(priv);
1000 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1002 /* Free the IRQ lines */
1003 free_irq(priv->rx_irq, dev);
1004 free_irq(priv->tx_irq, dev);
1006 /* disable and reset the MAC, empties fifo */
1007 spin_lock(&priv->mac_cfg_lock);
1008 spin_lock(&priv->tx_lock);
1010 ret = reset_mac(priv);
1011 /* Note that reset_mac will fail if the clocks are gated by the PHY
1012 * due to the PHY being put into isolation or power down mode.
1013 * This is not an error if reset fails due to no clock.
1016 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1017 priv->dmaops->reset_dma(priv);
1020 spin_unlock(&priv->tx_lock);
1021 spin_unlock(&priv->mac_cfg_lock);
1023 priv->dmaops->uninit_dma(priv);
1028 static struct net_device_ops altera_tse_netdev_ops = {
1029 .ndo_open = tse_open,
1030 .ndo_stop = tse_shutdown,
1031 .ndo_start_xmit = tse_start_xmit,
1032 .ndo_set_mac_address = eth_mac_addr,
1033 .ndo_set_rx_mode = tse_set_rx_mode,
1034 .ndo_change_mtu = tse_change_mtu,
1035 .ndo_validate_addr = eth_validate_addr,
1038 static void alt_tse_mac_an_restart(struct phylink_config *config)
1042 static void alt_tse_mac_config(struct phylink_config *config, unsigned int mode,
1043 const struct phylink_link_state *state)
1045 struct net_device *ndev = to_net_dev(config->dev);
1046 struct altera_tse_private *priv = netdev_priv(ndev);
1048 spin_lock(&priv->mac_cfg_lock);
1050 tse_set_mac(priv, true);
1051 spin_unlock(&priv->mac_cfg_lock);
1054 static void alt_tse_mac_link_down(struct phylink_config *config,
1055 unsigned int mode, phy_interface_t interface)
1059 static void alt_tse_mac_link_up(struct phylink_config *config,
1060 struct phy_device *phy, unsigned int mode,
1061 phy_interface_t interface, int speed,
1062 int duplex, bool tx_pause, bool rx_pause)
1064 struct net_device *ndev = to_net_dev(config->dev);
1065 struct altera_tse_private *priv = netdev_priv(ndev);
1068 ctrl = csrrd32(priv->mac_dev, tse_csroffs(command_config));
1069 ctrl &= ~(MAC_CMDCFG_ENA_10 | MAC_CMDCFG_ETH_SPEED | MAC_CMDCFG_HD_ENA);
1071 if (duplex == DUPLEX_HALF)
1072 ctrl |= MAC_CMDCFG_HD_ENA;
1074 if (speed == SPEED_1000)
1075 ctrl |= MAC_CMDCFG_ETH_SPEED;
1076 else if (speed == SPEED_10)
1077 ctrl |= MAC_CMDCFG_ENA_10;
1079 spin_lock(&priv->mac_cfg_lock);
1080 csrwr32(ctrl, priv->mac_dev, tse_csroffs(command_config));
1081 spin_unlock(&priv->mac_cfg_lock);
1084 static struct phylink_pcs *alt_tse_select_pcs(struct phylink_config *config,
1085 phy_interface_t interface)
1087 struct net_device *ndev = to_net_dev(config->dev);
1088 struct altera_tse_private *priv = netdev_priv(ndev);
1090 if (interface == PHY_INTERFACE_MODE_SGMII ||
1091 interface == PHY_INTERFACE_MODE_1000BASEX)
1097 static const struct phylink_mac_ops alt_tse_phylink_ops = {
1098 .validate = phylink_generic_validate,
1099 .mac_an_restart = alt_tse_mac_an_restart,
1100 .mac_config = alt_tse_mac_config,
1101 .mac_link_down = alt_tse_mac_link_down,
1102 .mac_link_up = alt_tse_mac_link_up,
1103 .mac_select_pcs = alt_tse_select_pcs,
1106 static int request_and_map(struct platform_device *pdev, const char *name,
1107 struct resource **res, void __iomem **ptr)
1109 struct device *device = &pdev->dev;
1110 struct resource *region;
1112 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1114 dev_err(device, "resource %s not defined\n", name);
1118 region = devm_request_mem_region(device, (*res)->start,
1119 resource_size(*res), dev_name(device));
1120 if (region == NULL) {
1121 dev_err(device, "unable to request %s\n", name);
1125 *ptr = devm_ioremap(device, region->start,
1126 resource_size(region));
1128 dev_err(device, "ioremap of %s failed!", name);
1135 /* Probe Altera TSE MAC device
1137 static int altera_tse_probe(struct platform_device *pdev)
1139 const struct of_device_id *of_id = NULL;
1140 struct altera_tse_private *priv;
1141 struct resource *control_port;
1142 struct resource *dma_res;
1143 struct resource *pcs_res;
1144 struct net_device *ndev;
1145 void __iomem *descmap;
1146 int pcs_reg_width = 2;
1149 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1151 dev_err(&pdev->dev, "Could not allocate network device\n");
1155 SET_NETDEV_DEV(ndev, &pdev->dev);
1157 priv = netdev_priv(ndev);
1158 priv->device = &pdev->dev;
1160 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1162 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1165 priv->dmaops = (struct altera_dmaops *)of_id->data;
1169 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1170 /* Get the mapped address to the SGDMA descriptor memory */
1171 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1173 goto err_free_netdev;
1175 /* Start of that memory is for transmit descriptors */
1176 priv->tx_dma_desc = descmap;
1178 /* First half is for tx descriptors, other half for tx */
1179 priv->txdescmem = resource_size(dma_res)/2;
1181 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1183 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1185 priv->rxdescmem = resource_size(dma_res)/2;
1186 priv->rxdescmem_busaddr = dma_res->start;
1187 priv->rxdescmem_busaddr += priv->txdescmem;
1189 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1190 dev_dbg(priv->device,
1191 "SGDMA bus addresses greater than 32-bits\n");
1193 goto err_free_netdev;
1195 if (upper_32_bits(priv->txdescmem_busaddr)) {
1196 dev_dbg(priv->device,
1197 "SGDMA bus addresses greater than 32-bits\n");
1199 goto err_free_netdev;
1201 } else if (priv->dmaops &&
1202 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1203 ret = request_and_map(pdev, "rx_resp", &dma_res,
1204 &priv->rx_dma_resp);
1206 goto err_free_netdev;
1208 ret = request_and_map(pdev, "tx_desc", &dma_res,
1209 &priv->tx_dma_desc);
1211 goto err_free_netdev;
1213 priv->txdescmem = resource_size(dma_res);
1214 priv->txdescmem_busaddr = dma_res->start;
1216 ret = request_and_map(pdev, "rx_desc", &dma_res,
1217 &priv->rx_dma_desc);
1219 goto err_free_netdev;
1221 priv->rxdescmem = resource_size(dma_res);
1222 priv->rxdescmem_busaddr = dma_res->start;
1226 goto err_free_netdev;
1229 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) {
1230 dma_set_coherent_mask(priv->device,
1231 DMA_BIT_MASK(priv->dmaops->dmamask));
1232 } else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) {
1233 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1236 goto err_free_netdev;
1239 /* MAC address space */
1240 ret = request_and_map(pdev, "control_port", &control_port,
1241 (void __iomem **)&priv->mac_dev);
1243 goto err_free_netdev;
1245 /* xSGDMA Rx Dispatcher address space */
1246 ret = request_and_map(pdev, "rx_csr", &dma_res,
1249 goto err_free_netdev;
1252 /* xSGDMA Tx Dispatcher address space */
1253 ret = request_and_map(pdev, "tx_csr", &dma_res,
1256 goto err_free_netdev;
1258 /* SGMII PCS address space. The location can vary depending on how the
1259 * IP is integrated. We can have a resource dedicated to it at a specific
1260 * address space, but if it's not the case, we fallback to the mdiophy0
1261 * from the MAC's address space
1263 ret = request_and_map(pdev, "pcs", &pcs_res,
1266 priv->pcs_base = priv->mac_dev + tse_csroffs(mdio_phy0);
1271 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1272 if (priv->rx_irq == -ENXIO) {
1273 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1275 goto err_free_netdev;
1279 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1280 if (priv->tx_irq == -ENXIO) {
1281 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1283 goto err_free_netdev;
1286 /* get FIFO depths from device tree */
1287 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1288 &priv->rx_fifo_depth)) {
1289 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1291 goto err_free_netdev;
1294 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1295 &priv->tx_fifo_depth)) {
1296 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1298 goto err_free_netdev;
1301 /* get hash filter settings for this instance */
1303 of_property_read_bool(pdev->dev.of_node,
1304 "altr,has-hash-multicast-filter");
1306 /* Set hash filter to not set for now until the
1307 * multicast filter receive issue is debugged
1309 priv->hash_filter = 0;
1311 /* get supplemental address settings for this instance */
1312 priv->added_unicast =
1313 of_property_read_bool(pdev->dev.of_node,
1314 "altr,has-supplementary-unicast");
1316 priv->dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
1317 /* Max MTU is 1500, ETH_DATA_LEN */
1318 priv->dev->max_mtu = ETH_DATA_LEN;
1320 /* Get the max mtu from the device tree. Note that the
1321 * "max-frame-size" parameter is actually max mtu. Definition
1322 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1324 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1325 &priv->dev->max_mtu);
1327 /* The DMA buffer size already accounts for an alignment bias
1328 * to avoid unaligned access exceptions for the NIOS processor,
1330 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1332 /* get default MAC address from device tree */
1333 ret = of_get_ethdev_address(pdev->dev.of_node, ndev);
1335 eth_hw_addr_random(ndev);
1337 /* get phy addr and create mdio */
1338 ret = altera_tse_phy_get_addr_mdio_create(ndev);
1341 goto err_free_netdev;
1343 /* initialize netdev */
1344 ndev->mem_start = control_port->start;
1345 ndev->mem_end = control_port->end;
1346 ndev->netdev_ops = &altera_tse_netdev_ops;
1347 altera_tse_set_ethtool_ops(ndev);
1349 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1351 if (priv->hash_filter)
1352 altera_tse_netdev_ops.ndo_set_rx_mode =
1353 tse_set_rx_mode_hashfilter;
1355 /* Scatter/gather IO is not supported,
1356 * so it is turned off
1358 ndev->hw_features &= ~NETIF_F_SG;
1359 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1361 /* VLAN offloading of tagging, stripping and filtering is not
1362 * supported by hardware, but driver will accommodate the
1363 * extra 4-byte VLAN tag for processing by upper layers
1365 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1367 /* setup NAPI interface */
1368 netif_napi_add(ndev, &priv->napi, tse_poll);
1370 spin_lock_init(&priv->mac_cfg_lock);
1371 spin_lock_init(&priv->tx_lock);
1372 spin_lock_init(&priv->rxdma_irq_lock);
1374 netif_carrier_off(ndev);
1375 ret = register_netdev(ndev);
1377 dev_err(&pdev->dev, "failed to register TSE net device\n");
1378 goto err_register_netdev;
1381 platform_set_drvdata(pdev, ndev);
1383 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1385 if (netif_msg_probe(priv))
1386 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1387 (priv->revision >> 8) & 0xff,
1388 priv->revision & 0xff,
1389 (unsigned long) control_port->start, priv->rx_irq,
1392 priv->pcs = alt_tse_pcs_create(ndev, priv->pcs_base, pcs_reg_width);
1394 priv->phylink_config.dev = &ndev->dev;
1395 priv->phylink_config.type = PHYLINK_NETDEV;
1396 priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
1397 MAC_100 | MAC_1000FD;
1399 phy_interface_set_rgmii(priv->phylink_config.supported_interfaces);
1400 __set_bit(PHY_INTERFACE_MODE_MII,
1401 priv->phylink_config.supported_interfaces);
1402 __set_bit(PHY_INTERFACE_MODE_GMII,
1403 priv->phylink_config.supported_interfaces);
1404 __set_bit(PHY_INTERFACE_MODE_SGMII,
1405 priv->phylink_config.supported_interfaces);
1406 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
1407 priv->phylink_config.supported_interfaces);
1409 priv->phylink = phylink_create(&priv->phylink_config,
1410 of_fwnode_handle(priv->device->of_node),
1411 priv->phy_iface, &alt_tse_phylink_ops);
1412 if (IS_ERR(priv->phylink)) {
1413 dev_err(&pdev->dev, "failed to create phylink\n");
1414 ret = PTR_ERR(priv->phylink);
1421 unregister_netdev(ndev);
1422 err_register_netdev:
1423 netif_napi_del(&priv->napi);
1424 altera_tse_mdio_destroy(ndev);
1430 /* Remove Altera TSE MAC device
1432 static int altera_tse_remove(struct platform_device *pdev)
1434 struct net_device *ndev = platform_get_drvdata(pdev);
1435 struct altera_tse_private *priv = netdev_priv(ndev);
1437 platform_set_drvdata(pdev, NULL);
1438 altera_tse_mdio_destroy(ndev);
1439 unregister_netdev(ndev);
1440 phylink_destroy(priv->phylink);
1446 static const struct altera_dmaops altera_dtype_sgdma = {
1447 .altera_dtype = ALTERA_DTYPE_SGDMA,
1449 .reset_dma = sgdma_reset,
1450 .enable_txirq = sgdma_enable_txirq,
1451 .enable_rxirq = sgdma_enable_rxirq,
1452 .disable_txirq = sgdma_disable_txirq,
1453 .disable_rxirq = sgdma_disable_rxirq,
1454 .clear_txirq = sgdma_clear_txirq,
1455 .clear_rxirq = sgdma_clear_rxirq,
1456 .tx_buffer = sgdma_tx_buffer,
1457 .tx_completions = sgdma_tx_completions,
1458 .add_rx_desc = sgdma_add_rx_desc,
1459 .get_rx_status = sgdma_rx_status,
1460 .init_dma = sgdma_initialize,
1461 .uninit_dma = sgdma_uninitialize,
1462 .start_rxdma = sgdma_start_rxdma,
1465 static const struct altera_dmaops altera_dtype_msgdma = {
1466 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1468 .reset_dma = msgdma_reset,
1469 .enable_txirq = msgdma_enable_txirq,
1470 .enable_rxirq = msgdma_enable_rxirq,
1471 .disable_txirq = msgdma_disable_txirq,
1472 .disable_rxirq = msgdma_disable_rxirq,
1473 .clear_txirq = msgdma_clear_txirq,
1474 .clear_rxirq = msgdma_clear_rxirq,
1475 .tx_buffer = msgdma_tx_buffer,
1476 .tx_completions = msgdma_tx_completions,
1477 .add_rx_desc = msgdma_add_rx_desc,
1478 .get_rx_status = msgdma_rx_status,
1479 .init_dma = msgdma_initialize,
1480 .uninit_dma = msgdma_uninitialize,
1481 .start_rxdma = msgdma_start_rxdma,
1484 static const struct of_device_id altera_tse_ids[] = {
1485 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1486 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1487 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1490 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1492 static struct platform_driver altera_tse_driver = {
1493 .probe = altera_tse_probe,
1494 .remove = altera_tse_remove,
1498 .name = ALTERA_TSE_RESOURCE_NAME,
1499 .of_match_table = altera_tse_ids,
1503 module_platform_driver(altera_tse_driver);
1505 MODULE_AUTHOR("Altera Corporation");
1506 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1507 MODULE_LICENSE("GPL v2");