2 * Marvell 88E6xxx Ethernet switch single-chip definition
4 * Copyright (c) 2008 Marvell Semiconductor
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #ifndef _MV88E6XXX_CHIP_H
13 #define _MV88E6XXX_CHIP_H
15 #include <linux/if_vlan.h>
16 #include <linux/irq.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/kthread.h>
19 #include <linux/phy.h>
20 #include <linux/ptp_clock_kernel.h>
21 #include <linux/timecounter.h>
25 #define SMI_CMD_BUSY BIT(15)
26 #define SMI_CMD_CLAUSE_22 BIT(12)
27 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
28 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
29 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
30 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
31 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
32 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
35 #define MV88E6XXX_N_FID 4096
37 /* PVT limits for 4-bit port and 5-bit switch */
38 #define MV88E6XXX_MAX_PVT_SWITCHES 32
39 #define MV88E6XXX_MAX_PVT_PORTS 16
41 #define MV88E6XXX_MAX_GPIO 16
43 enum mv88e6xxx_egress_mode {
44 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
45 MV88E6XXX_EGRESS_MODE_UNTAGGED,
46 MV88E6XXX_EGRESS_MODE_TAGGED,
47 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
50 enum mv88e6xxx_frame_mode {
51 MV88E6XXX_FRAME_MODE_NORMAL,
52 MV88E6XXX_FRAME_MODE_DSA,
53 MV88E6XXX_FRAME_MODE_PROVIDER,
54 MV88E6XXX_FRAME_MODE_ETHERTYPE,
57 /* List of supported models */
58 enum mv88e6xxx_model {
87 enum mv88e6xxx_family {
88 MV88E6XXX_FAMILY_NONE,
89 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
90 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
91 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
92 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
93 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
94 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
95 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
96 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
97 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
98 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
101 struct mv88e6xxx_ops;
103 struct mv88e6xxx_info {
104 enum mv88e6xxx_family family;
107 unsigned int num_databases;
108 unsigned int num_ports;
109 unsigned int num_internal_phys;
110 unsigned int num_gpio;
111 unsigned int max_vid;
112 unsigned int port_base_addr;
113 unsigned int phy_base_addr;
114 unsigned int global1_addr;
115 unsigned int global2_addr;
116 unsigned int age_time_coeff;
117 unsigned int g1_irqs;
118 unsigned int g2_irqs;
121 /* Multi-chip Addressing Mode.
122 * Some chips respond to only 2 registers of its own SMI device address
123 * when it is non-zero, and use indirect access to internal registers.
126 enum dsa_tag_protocol tag_protocol;
128 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
129 * operation. 0 means that the ATU Move operation is not supported.
131 u8 atu_move_port_mask;
132 const struct mv88e6xxx_ops *ops;
138 struct mv88e6xxx_atu_entry {
145 struct mv88e6xxx_vtu_entry {
150 u8 member[DSA_MAX_PORTS];
151 u8 state[DSA_MAX_PORTS];
154 struct mv88e6xxx_bus_ops;
155 struct mv88e6xxx_irq_ops;
156 struct mv88e6xxx_gpio_ops;
157 struct mv88e6xxx_avb_ops;
158 struct mv88e6xxx_ptp_ops;
160 struct mv88e6xxx_irq {
162 struct irq_chip chip;
163 struct irq_domain *domain;
167 /* state flags for mv88e6xxx_port_hwtstamp::state */
169 MV88E6XXX_HWTSTAMP_ENABLED,
170 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
173 struct mv88e6xxx_port_hwtstamp {
177 /* Timestamping state */
180 /* Resources for receive timestamping */
181 struct sk_buff_head rx_queue;
182 struct sk_buff_head rx_queue2;
184 /* Resources for transmit timestamping */
185 unsigned long tx_tstamp_start;
186 struct sk_buff *tx_skb;
189 /* Current timestamp configuration */
190 struct hwtstamp_config tstamp_config;
193 struct mv88e6xxx_port {
195 u64 atu_member_violation;
196 u64 atu_miss_violation;
197 u64 atu_full_violation;
198 u64 vtu_member_violation;
199 u64 vtu_miss_violation;
202 struct mv88e6xxx_chip {
203 const struct mv88e6xxx_info *info;
205 /* The dsa_switch this private structure is related to */
206 struct dsa_switch *ds;
208 /* The device this structure is associated to */
211 /* This mutex protects the access to the switch registers */
212 struct mutex reg_lock;
214 /* The MII bus and the address on the bus that is used to
215 * communication with the switch
217 const struct mv88e6xxx_bus_ops *smi_ops;
221 /* Handles automatic disabling and re-enabling of the PHY
224 const struct mv88e6xxx_bus_ops *phy_ops;
225 struct mutex ppu_mutex;
227 struct work_struct ppu_work;
228 struct timer_list ppu_timer;
230 /* This mutex serialises access to the statistics unit.
231 * Hold this mutex over snapshot + dump sequences.
233 struct mutex stats_mutex;
235 /* A switch may have a GPIO line tied to its reset pin. Parse
236 * this from the device tree, and use it before performing
239 struct gpio_desc *reset;
241 /* set to size of eeprom if supported by the switch */
244 /* List of mdio busses */
245 struct list_head mdios;
247 /* There can be two interrupt controllers, which are chained
248 * off a GPIO as interrupt source
250 struct mv88e6xxx_irq g1_irq;
251 struct mv88e6xxx_irq g2_irq;
258 struct kthread_worker *kworker;
259 struct kthread_delayed_work irq_poll_work;
264 /* This cyclecounter abstracts the switch PTP time.
265 * reg_lock must be held for any operation that read()s.
267 struct cyclecounter tstamp_cc;
268 struct timecounter tstamp_tc;
269 struct delayed_work overflow_work;
271 struct ptp_clock *ptp_clock;
272 struct ptp_clock_info ptp_clock_info;
273 struct delayed_work tai_event_work;
274 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
278 /* Per-port timestamping resources. */
279 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
281 /* Array of port structures. */
282 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
285 struct mv88e6xxx_bus_ops {
286 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
287 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
290 struct mv88e6xxx_mdio_bus {
292 struct mv88e6xxx_chip *chip;
293 struct list_head list;
297 struct mv88e6xxx_ops {
298 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
299 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
301 /* Ingress Rate Limit unit (IRL) operations */
302 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
304 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
305 struct ethtool_eeprom *eeprom, u8 *data);
306 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
307 struct ethtool_eeprom *eeprom, u8 *data);
309 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
311 int (*phy_read)(struct mv88e6xxx_chip *chip,
313 int addr, int reg, u16 *val);
314 int (*phy_write)(struct mv88e6xxx_chip *chip,
316 int addr, int reg, u16 val);
318 /* Priority Override Table operations */
319 int (*pot_clear)(struct mv88e6xxx_chip *chip);
321 /* PHY Polling Unit (PPU) operations */
322 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
323 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
325 /* Switch Software Reset */
326 int (*reset)(struct mv88e6xxx_chip *chip);
328 /* RGMII Receive/Transmit Timing Control
329 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
331 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
332 phy_interface_t mode);
334 #define LINK_FORCED_DOWN 0
335 #define LINK_FORCED_UP 1
336 #define LINK_UNFORCED -2
338 /* Port's MAC link state
339 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
340 * or LINK_UNFORCED for normal link detection.
342 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
344 #define DUPLEX_UNFORCED -2
346 /* Port's MAC duplex mode
348 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
349 * or DUPLEX_UNFORCED for normal duplex detection.
351 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
353 #define SPEED_MAX INT_MAX
354 #define SPEED_UNFORCED -2
356 /* Port's MAC speed (in Mbps)
358 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
359 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
361 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
363 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
365 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
366 enum mv88e6xxx_frame_mode mode);
367 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
368 bool unicast, bool multicast);
369 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
371 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
374 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
375 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
377 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
378 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
380 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
381 * Some chips allow this to be configured on specific ports.
383 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
384 phy_interface_t mode);
386 /* Some devices have a per port register indicating what is
387 * the upstream port this port should forward to.
389 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
392 /* Snapshot the statistics for a port. The statistics can then
393 * be read back a leisure but still with a consistent view.
395 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
397 /* Set the histogram mode for statistics, when the control registers
398 * are separated out of the STATS_OP register.
400 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
402 /* Return the number of strings describing statistics */
403 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
404 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
405 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
407 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
408 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
410 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
411 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
413 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
415 const struct mv88e6xxx_irq_ops *watchdog_ops;
417 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
419 /* Power on/off a SERDES interface */
420 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
422 /* Statistics from the SERDES interface */
423 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
424 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
426 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
429 /* VLAN Translation Unit operations */
430 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
431 struct mv88e6xxx_vtu_entry *entry);
432 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
433 struct mv88e6xxx_vtu_entry *entry);
435 /* GPIO operations */
436 const struct mv88e6xxx_gpio_ops *gpio_ops;
438 /* Interface to the AVB/PTP registers */
439 const struct mv88e6xxx_avb_ops *avb_ops;
441 /* Remote Management Unit operations */
442 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
444 /* Precision Time Protocol operations */
445 const struct mv88e6xxx_ptp_ops *ptp_ops;
448 struct mv88e6xxx_irq_ops {
449 /* Action to be performed when the interrupt happens */
450 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
451 /* Setup the hardware to generate the interrupt */
452 int (*irq_setup)(struct mv88e6xxx_chip *chip);
453 /* Reset the hardware to stop generating the interrupt */
454 void (*irq_free)(struct mv88e6xxx_chip *chip);
457 struct mv88e6xxx_gpio_ops {
458 /* Get/set data on GPIO pin */
459 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
460 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
463 /* get/set GPIO direction */
464 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
465 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
468 /* get/set GPIO pin control */
469 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
471 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
475 struct mv88e6xxx_avb_ops {
476 /* Access port-scoped Precision Time Protocol registers */
477 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
479 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
482 /* Access global Precision Time Protocol registers */
483 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
485 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
487 /* Access global Time Application Interface registers */
488 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
490 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
493 struct mv88e6xxx_ptp_ops {
494 u64 (*clock_read)(const struct cyclecounter *cc);
495 int (*ptp_enable)(struct ptp_clock_info *ptp,
496 struct ptp_clock_request *rq, int on);
497 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
498 enum ptp_pin_function func, unsigned int chan);
499 void (*event_work)(struct work_struct *ugly);
500 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
501 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
508 #define STATS_TYPE_PORT BIT(0)
509 #define STATS_TYPE_BANK0 BIT(1)
510 #define STATS_TYPE_BANK1 BIT(2)
512 struct mv88e6xxx_hw_stat {
513 char string[ETH_GSTRING_LEN];
519 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
521 return chip->info->pvt;
524 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
526 return chip->info->num_databases;
529 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
531 return chip->info->num_ports;
534 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
536 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
539 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
541 return chip->info->num_gpio;
544 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
545 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
546 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
548 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
549 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
551 #endif /* _MV88E6XXX_CHIP_H */