drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/if_bridge.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/list.h>
  22 #include <linux/mdio.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/platform_data/mv88e6xxx.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/gpio/consumer.h>
  30 #include <linux/phy.h>
  31 #include <linux/phylink.h>
  32 #include <net/dsa.h>
  33
  34 #include "chip.h"
  35 #include "global1.h"
  36 #include "global2.h"
  37 #include "hwtstamp.h"
  38 #include "phy.h"
  39 #include "port.h"
  40 #include "ptp.h"
  41 #include "serdes.h"
  42 #include "smi.h"
  43
  44 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  45 {
  46         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  47                 dev_err(chip->dev, "Switch registers lock not held!\n");
  48                 dump_stack();
  49         }
  50 }
  51
  52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  53 {
  54         int err;
  55
  56         assert_reg_lock(chip);
  57
  58         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  59         if (err)
  60                 return err;
  61
  62         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  63                 addr, reg, *val);
  64
  65         return 0;
  66 }
  67
  68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  69 {
  70         int err;
  71
  72         assert_reg_lock(chip);
  73
  74         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  75         if (err)
  76                 return err;
  77
  78         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  79                 addr, reg, val);
  80
  81         return 0;
  82 }
  83
  84 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
  85 {
  86         struct mv88e6xxx_mdio_bus *mdio_bus;
  87
  88         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
  89                                     list);
  90         if (!mdio_bus)
  91                 return NULL;
  92
  93         return mdio_bus->bus;
  94 }
  95
  96 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
  97 {
  98         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
  99         unsigned int n = d->hwirq;
 100
 101         chip->g1_irq.masked |= (1 << n);
 102 }
 103
 104 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 105 {
 106         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 107         unsigned int n = d->hwirq;
 108
 109         chip->g1_irq.masked &= ~(1 << n);
 110 }
 111
 112 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 113 {
 114         unsigned int nhandled = 0;
 115         unsigned int sub_irq;
 116         unsigned int n;
 117         u16 reg;
 118         u16 ctl1;
 119         int err;
 120
 121         mv88e6xxx_reg_lock(chip);
 122         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 123         mv88e6xxx_reg_unlock(chip);
 124
 125         if (err)
 126                 goto out;
 127
 128         do {
 129                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 130                         if (reg & (1 << n)) {
 131                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 132                                                            n);
 133                                 handle_nested_irq(sub_irq);
 134                                 ++nhandled;
 135                         }
 136                 }
 137
 138                 mv88e6xxx_reg_lock(chip);
 139                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 140                 if (err)
 141                         goto unlock;
 142                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 143 unlock:
 144                 mv88e6xxx_reg_unlock(chip);
 145                 if (err)
 146                         goto out;
 147                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 148         } while (reg & ctl1);
 149
 150 out:
 151         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 152 }
 153
 154 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 155 {
 156         struct mv88e6xxx_chip *chip = dev_id;
 157
 158         return mv88e6xxx_g1_irq_thread_work(chip);
 159 }
 160
 161 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 162 {
 163         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 164
 165         mv88e6xxx_reg_lock(chip);
 166 }
 167
 168 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 169 {
 170         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 171         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 172         u16 reg;
 173         int err;
 174
 175         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 176         if (err)
 177                 goto out;
 178
 179         reg &= ~mask;
 180         reg |= (~chip->g1_irq.masked & mask);
 181
 182         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 183         if (err)
 184                 goto out;
 185
 186 out:
 187         mv88e6xxx_reg_unlock(chip);
 188 }
 189
 190 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 191         .name                   = "mv88e6xxx-g1",
 192         .irq_mask               = mv88e6xxx_g1_irq_mask,
 193         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 194         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 195         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 196 };
 197
 198 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 199                                        unsigned int irq,
 200                                        irq_hw_number_t hwirq)
 201 {
 202         struct mv88e6xxx_chip *chip = d->host_data;
 203
 204         irq_set_chip_data(irq, d->host_data);
 205         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 206         irq_set_noprobe(irq);
 207
 208         return 0;
 209 }
 210
 211 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 212         .map    = mv88e6xxx_g1_irq_domain_map,
 213         .xlate  = irq_domain_xlate_twocell,
 214 };
 215
 216 /* To be called with reg_lock held */
 217 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 218 {
 219         int irq, virq;
 220         u16 mask;
 221
 222         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 223         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 224         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 225
 226         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 227                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 228                 irq_dispose_mapping(virq);
 229         }
 230
 231         irq_domain_remove(chip->g1_irq.domain);
 232 }
 233
 234 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 235 {
 236         /*
 237          * free_irq must be called without reg_lock taken because the irq
 238          * handler takes this lock, too.
 239          */
 240         free_irq(chip->irq, chip);
 241
 242         mv88e6xxx_reg_lock(chip);
 243         mv88e6xxx_g1_irq_free_common(chip);
 244         mv88e6xxx_reg_unlock(chip);
 245 }
 246
 247 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 248 {
 249         int err, irq, virq;
 250         u16 reg, mask;
 251
 252         chip->g1_irq.nirqs = chip->info->g1_irqs;
 253         chip->g1_irq.domain = irq_domain_add_simple(
 254                 NULL, chip->g1_irq.nirqs, 0,
 255                 &mv88e6xxx_g1_irq_domain_ops, chip);
 256         if (!chip->g1_irq.domain)
 257                 return -ENOMEM;
 258
 259         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 260                 irq_create_mapping(chip->g1_irq.domain, irq);
 261
 262         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 263         chip->g1_irq.masked = ~0;
 264
 265         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 266         if (err)
 267                 goto out_mapping;
 268
 269         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 270
 271         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 272         if (err)
 273                 goto out_disable;
 274
 275         /* Reading the interrupt status clears (most of) them */
 276         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 277         if (err)
 278                 goto out_disable;
 279
 280         return 0;
 281
 282 out_disable:
 283         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 284         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 285
 286 out_mapping:
 287         for (irq = 0; irq < 16; irq++) {
 288                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 289                 irq_dispose_mapping(virq);
 290         }
 291
 292         irq_domain_remove(chip->g1_irq.domain);
 293
 294         return err;
 295 }
 296
 297 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 298 {
 299         static struct lock_class_key lock_key;
 300         static struct lock_class_key request_key;
 301         int err;
 302
 303         err = mv88e6xxx_g1_irq_setup_common(chip);
 304         if (err)
 305                 return err;
 306
 307         /* These lock classes tells lockdep that global 1 irqs are in
 308          * a different category than their parent GPIO, so it won't
 309          * report false recursion.
 310          */
 311         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 312
 313         mv88e6xxx_reg_unlock(chip);
 314         err = request_threaded_irq(chip->irq, NULL,
 315                                    mv88e6xxx_g1_irq_thread_fn,
 316                                    IRQF_ONESHOT | IRQF_SHARED,
 317                                    dev_name(chip->dev), chip);
 318         mv88e6xxx_reg_lock(chip);
 319         if (err)
 320                 mv88e6xxx_g1_irq_free_common(chip);
 321
 322         return err;
 323 }
 324
 325 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 326 {
 327         struct mv88e6xxx_chip *chip = container_of(work,
 328                                                    struct mv88e6xxx_chip,
 329                                                    irq_poll_work.work);
 330         mv88e6xxx_g1_irq_thread_work(chip);
 331
 332         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 333                                    msecs_to_jiffies(100));
 334 }
 335
 336 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 337 {
 338         int err;
 339
 340         err = mv88e6xxx_g1_irq_setup_common(chip);
 341         if (err)
 342                 return err;
 343
 344         kthread_init_delayed_work(&chip->irq_poll_work,
 345                                   mv88e6xxx_irq_poll);
 346
 347         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 348         if (IS_ERR(chip->kworker))
 349                 return PTR_ERR(chip->kworker);
 350
 351         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 352                                    msecs_to_jiffies(100));
 353
 354         return 0;
 355 }
 356
 357 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 358 {
 359         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 360         kthread_destroy_worker(chip->kworker);
 361
 362         mv88e6xxx_reg_lock(chip);
 363         mv88e6xxx_g1_irq_free_common(chip);
 364         mv88e6xxx_reg_unlock(chip);
 365 }
 366
 367 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
 368 {
 369         int i;
 370
 371         for (i = 0; i < 16; i++) {
 372                 u16 val;
 373                 int err;
 374
 375                 err = mv88e6xxx_read(chip, addr, reg, &val);
 376                 if (err)
 377                         return err;
 378
 379                 if (!(val & mask))
 380                         return 0;
 381
 382                 usleep_range(1000, 2000);
 383         }
 384
 385         dev_err(chip->dev, "Timeout while waiting for switch\n");
 386         return -ETIMEDOUT;
 387 }
 388
 389 /* Indirect write to single pointer-data register with an Update bit */
 390 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
 391 {
 392         u16 val;
 393         int err;
 394
 395         /* Wait until the previous operation is completed */
 396         err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
 397         if (err)
 398                 return err;
 399
 400         /* Set the Update bit to trigger a write operation */
 401         val = BIT(15) | update;
 402
 403         return mv88e6xxx_write(chip, addr, reg, val);
 404 }
 405
 406 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
 407                              int speed, int duplex, int pause,
 408                              phy_interface_t mode)
 409 {
 410         struct phylink_link_state state;
 411         int err;
 412
 413         if (!chip->info->ops->port_set_link)
 414                 return 0;
 415
 416         if (!chip->info->ops->port_link_state)
 417                 return 0;
 418
 419         err = chip->info->ops->port_link_state(chip, port, &state);
 420         if (err)
 421                 return err;
 422
 423         /* Has anything actually changed? We don't expect the
 424          * interface mode to change without one of the other
 425          * parameters also changing
 426          */
 427         if (state.link == link &&
 428             state.speed == speed &&
 429             state.duplex == duplex)
 430                 return 0;
 431
 432         /* Port's MAC control must not be changed unless the link is down */
 433         err = chip->info->ops->port_set_link(chip, port, 0);
 434         if (err)
 435                 return err;
 436
 437         if (chip->info->ops->port_set_speed) {
 438                 err = chip->info->ops->port_set_speed(chip, port, speed);
 439                 if (err && err != -EOPNOTSUPP)
 440                         goto restore_link;
 441         }
 442
 443         if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
 444                 mode = chip->info->ops->port_max_speed_mode(port);
 445
 446         if (chip->info->ops->port_set_pause) {
 447                 err = chip->info->ops->port_set_pause(chip, port, pause);
 448                 if (err)
 449                         goto restore_link;
 450         }
 451
 452         if (chip->info->ops->port_set_duplex) {
 453                 err = chip->info->ops->port_set_duplex(chip, port, duplex);
 454                 if (err && err != -EOPNOTSUPP)
 455                         goto restore_link;
 456         }
 457
 458         if (chip->info->ops->port_set_rgmii_delay) {
 459                 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
 460                 if (err && err != -EOPNOTSUPP)
 461                         goto restore_link;
 462         }
 463
 464         if (chip->info->ops->port_set_cmode) {
 465                 err = chip->info->ops->port_set_cmode(chip, port, mode);
 466                 if (err && err != -EOPNOTSUPP)
 467                         goto restore_link;
 468         }
 469
 470         err = 0;
 471 restore_link:
 472         if (chip->info->ops->port_set_link(chip, port, link))
 473                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 474
 475         return err;
 476 }
 477
 478 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 479 {
 480         struct mv88e6xxx_chip *chip = ds->priv;
 481
 482         return port < chip->info->num_internal_phys;
 483 }
 484
 485 /* We expect the switch to perform auto negotiation if there is a real
 486  * phy. However, in the case of a fixed link phy, we force the port
 487  * settings from the fixed link settings.
 488  */
 489 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 490                                   struct phy_device *phydev)
 491 {
 492         struct mv88e6xxx_chip *chip = ds->priv;
 493         int err;
 494
 495         if (!phy_is_pseudo_fixed_link(phydev) &&
 496             mv88e6xxx_phy_is_internal(ds, port))
 497                 return;
 498
 499         mv88e6xxx_reg_lock(chip);
 500         err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
 501                                        phydev->duplex, phydev->pause,
 502                                        phydev->interface);
 503         mv88e6xxx_reg_unlock(chip);
 504
 505         if (err && err != -EOPNOTSUPP)
 506                 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
 507 }
 508
 509 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 510                                        unsigned long *mask,
 511                                        struct phylink_link_state *state)
 512 {
 513         if (!phy_interface_mode_is_8023z(state->interface)) {
 514                 /* 10M and 100M are only supported in non-802.3z mode */
 515                 phylink_set(mask, 10baseT_Half);
 516                 phylink_set(mask, 10baseT_Full);
 517                 phylink_set(mask, 100baseT_Half);
 518                 phylink_set(mask, 100baseT_Full);
 519         }
 520 }
 521
 522 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 523                                        unsigned long *mask,
 524                                        struct phylink_link_state *state)
 525 {
 526         /* FIXME: if the port is in 1000Base-X mode, then it only supports
 527          * 1000M FD speeds.  In this case, CMODE will indicate 5.
 528          */
 529         phylink_set(mask, 1000baseT_Full);
 530         phylink_set(mask, 1000baseX_Full);
 531
 532         mv88e6065_phylink_validate(chip, port, mask, state);
 533 }
 534
 535 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 536                                        unsigned long *mask,
 537                                        struct phylink_link_state *state)
 538 {
 539         if (port >= 5)
 540                 phylink_set(mask, 2500baseX_Full);
 541
 542         /* No ethtool bits for 200Mbps */
 543         phylink_set(mask, 1000baseT_Full);
 544         phylink_set(mask, 1000baseX_Full);
 545
 546         mv88e6065_phylink_validate(chip, port, mask, state);
 547 }
 548
 549 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 550                                        unsigned long *mask,
 551                                        struct phylink_link_state *state)
 552 {
 553         /* No ethtool bits for 200Mbps */
 554         phylink_set(mask, 1000baseT_Full);
 555         phylink_set(mask, 1000baseX_Full);
 556
 557         mv88e6065_phylink_validate(chip, port, mask, state);
 558 }
 559
 560 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 561                                        unsigned long *mask,
 562                                        struct phylink_link_state *state)
 563 {
 564         if (port >= 9) {
 565                 phylink_set(mask, 2500baseX_Full);
 566                 phylink_set(mask, 2500baseT_Full);
 567         }
 568
 569         /* No ethtool bits for 200Mbps */
 570         phylink_set(mask, 1000baseT_Full);
 571         phylink_set(mask, 1000baseX_Full);
 572
 573         mv88e6065_phylink_validate(chip, port, mask, state);
 574 }
 575
 576 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 577                                         unsigned long *mask,
 578                                         struct phylink_link_state *state)
 579 {
 580         if (port >= 9) {
 581                 phylink_set(mask, 10000baseT_Full);
 582                 phylink_set(mask, 10000baseKR_Full);
 583         }
 584
 585         mv88e6390_phylink_validate(chip, port, mask, state);
 586 }
 587
 588 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
 589                                unsigned long *supported,
 590                                struct phylink_link_state *state)
 591 {
 592         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 593         struct mv88e6xxx_chip *chip = ds->priv;
 594
 595         /* Allow all the expected bits */
 596         phylink_set(mask, Autoneg);
 597         phylink_set(mask, Pause);
 598         phylink_set_port_modes(mask);
 599
 600         if (chip->info->ops->phylink_validate)
 601                 chip->info->ops->phylink_validate(chip, port, mask, state);
 602
 603         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 604         bitmap_and(state->advertising, state->advertising, mask,
 605                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 606
 607         /* We can only operate at 2500BaseX or 1000BaseX.  If requested
 608          * to advertise both, only report advertising at 2500BaseX.
 609          */
 610         phylink_helper_basex_speed(state);
 611 }
 612
 613 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
 614                                 struct phylink_link_state *state)
 615 {
 616         struct mv88e6xxx_chip *chip = ds->priv;
 617         int err;
 618
 619         mv88e6xxx_reg_lock(chip);
 620         if (chip->info->ops->port_link_state)
 621                 err = chip->info->ops->port_link_state(chip, port, state);
 622         else
 623                 err = -EOPNOTSUPP;
 624         mv88e6xxx_reg_unlock(chip);
 625
 626         return err;
 627 }
 628
 629 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 630                                  unsigned int mode,
 631                                  const struct phylink_link_state *state)
 632 {
 633         struct mv88e6xxx_chip *chip = ds->priv;
 634         int speed, duplex, link, pause, err;
 635
 636         if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
 637                 return;
 638
 639         if (mode == MLO_AN_FIXED) {
 640                 link = LINK_FORCED_UP;
 641                 speed = state->speed;
 642                 duplex = state->duplex;
 643         } else if (!mv88e6xxx_phy_is_internal(ds, port)) {
 644                 link = state->link;
 645                 speed = state->speed;
 646                 duplex = state->duplex;
 647         } else {
 648                 speed = SPEED_UNFORCED;
 649                 duplex = DUPLEX_UNFORCED;
 650                 link = LINK_UNFORCED;
 651         }
 652         pause = !!phylink_test(state->advertising, Pause);
 653
 654         mv88e6xxx_reg_lock(chip);
 655         err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
 656                                        state->interface);
 657         mv88e6xxx_reg_unlock(chip);
 658
 659         if (err && err != -EOPNOTSUPP)
 660                 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
 661 }
 662
 663 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
 664 {
 665         struct mv88e6xxx_chip *chip = ds->priv;
 666         int err;
 667
 668         mv88e6xxx_reg_lock(chip);
 669         err = chip->info->ops->port_set_link(chip, port, link);
 670         mv88e6xxx_reg_unlock(chip);
 671
 672         if (err)
 673                 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
 674 }
 675
 676 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 677                                     unsigned int mode,
 678                                     phy_interface_t interface)
 679 {
 680         if (mode == MLO_AN_FIXED)
 681                 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
 682 }
 683
 684 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 685                                   unsigned int mode, phy_interface_t interface,
 686                                   struct phy_device *phydev)
 687 {
 688         if (mode == MLO_AN_FIXED)
 689                 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
 690 }
 691
 692 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 693 {
 694         if (!chip->info->ops->stats_snapshot)
 695                 return -EOPNOTSUPP;
 696
 697         return chip->info->ops->stats_snapshot(chip, port);
 698 }
 699
 700 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 701         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 702         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 703         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 704         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 705         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 706         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 707         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 708         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 709         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 710         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 711         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 712         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 713         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 714         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 715         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 716         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 717         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 718         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 719         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 720         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 721         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 722         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 723         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 724         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 725         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 726         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 727         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 728         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 729         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 730         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 731         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 732         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 733         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 734         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 735         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 736         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 737         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 738         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 739         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 740         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 741         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 742         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 743         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 744         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 745         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 746         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 747         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 748         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 749         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 750         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 751         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 752         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 753         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 754         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 755         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 756         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 757         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 758         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 759         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
 760 };
 761
 762 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 763                                             struct mv88e6xxx_hw_stat *s,
 764                                             int port, u16 bank1_select,
 765                                             u16 histogram)
 766 {
 767         u32 low;
 768         u32 high = 0;
 769         u16 reg = 0;
 770         int err;
 771         u64 value;
 772
 773         switch (s->type) {
 774         case STATS_TYPE_PORT:
 775                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 776                 if (err)
 777                         return U64_MAX;
 778
 779                 low = reg;
 780                 if (s->size == 4) {
 781                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 782                         if (err)
 783                                 return U64_MAX;
 784                         low |= ((u32)reg) << 16;
 785                 }
 786                 break;
 787         case STATS_TYPE_BANK1:
 788                 reg = bank1_select;
 789                 /* fall through */
 790         case STATS_TYPE_BANK0:
 791                 reg |= s->reg | histogram;
 792                 mv88e6xxx_g1_stats_read(chip, reg, &low);
 793                 if (s->size == 8)
 794                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
 795                 break;
 796         default:
 797                 return U64_MAX;
 798         }
 799         value = (((u64)high) << 32) | low;
 800         return value;
 801 }
 802
 803 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
 804                                        uint8_t *data, int types)
 805 {
 806         struct mv88e6xxx_hw_stat *stat;
 807         int i, j;
 808
 809         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 810                 stat = &mv88e6xxx_hw_stats[i];
 811                 if (stat->type & types) {
 812                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 813                                ETH_GSTRING_LEN);
 814                         j++;
 815                 }
 816         }
 817
 818         return j;
 819 }
 820
 821 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
 822                                        uint8_t *data)
 823 {
 824         return mv88e6xxx_stats_get_strings(chip, data,
 825                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
 826 }
 827
 828 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
 829                                        uint8_t *data)
 830 {
 831         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
 832 }
 833
 834 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
 835                                        uint8_t *data)
 836 {
 837         return mv88e6xxx_stats_get_strings(chip, data,
 838                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
 839 }
 840
 841 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
 842         "atu_member_violation",
 843         "atu_miss_violation",
 844         "atu_full_violation",
 845         "vtu_member_violation",
 846         "vtu_miss_violation",
 847 };
 848
 849 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
 850 {
 851         unsigned int i;
 852
 853         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
 854                 strlcpy(data + i * ETH_GSTRING_LEN,
 855                         mv88e6xxx_atu_vtu_stats_strings[i],
 856                         ETH_GSTRING_LEN);
 857 }
 858
 859 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 860                                   u32 stringset, uint8_t *data)
 861 {
 862         struct mv88e6xxx_chip *chip = ds->priv;
 863         int count = 0;
 864
 865         if (stringset != ETH_SS_STATS)
 866                 return;
 867
 868         mv88e6xxx_reg_lock(chip);
 869
 870         if (chip->info->ops->stats_get_strings)
 871                 count = chip->info->ops->stats_get_strings(chip, data);
 872
 873         if (chip->info->ops->serdes_get_strings) {
 874                 data += count * ETH_GSTRING_LEN;
 875                 count = chip->info->ops->serdes_get_strings(chip, port, data);
 876         }
 877
 878         data += count * ETH_GSTRING_LEN;
 879         mv88e6xxx_atu_vtu_get_strings(data);
 880
 881         mv88e6xxx_reg_unlock(chip);
 882 }
 883
 884 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
 885                                           int types)
 886 {
 887         struct mv88e6xxx_hw_stat *stat;
 888         int i, j;
 889
 890         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 891                 stat = &mv88e6xxx_hw_stats[i];
 892                 if (stat->type & types)
 893                         j++;
 894         }
 895         return j;
 896 }
 897
 898 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 899 {
 900         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 901                                               STATS_TYPE_PORT);
 902 }
 903
 904 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 905 {
 906         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
 907 }
 908
 909 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 910 {
 911         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 912                                               STATS_TYPE_BANK1);
 913 }
 914
 915 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
 916 {
 917         struct mv88e6xxx_chip *chip = ds->priv;
 918         int serdes_count = 0;
 919         int count = 0;
 920
 921         if (sset != ETH_SS_STATS)
 922                 return 0;
 923
 924         mv88e6xxx_reg_lock(chip);
 925         if (chip->info->ops->stats_get_sset_count)
 926                 count = chip->info->ops->stats_get_sset_count(chip);
 927         if (count < 0)
 928                 goto out;
 929
 930         if (chip->info->ops->serdes_get_sset_count)
 931                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
 932                                                                       port);
 933         if (serdes_count < 0) {
 934                 count = serdes_count;
 935                 goto out;
 936         }
 937         count += serdes_count;
 938         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
 939
 940 out:
 941         mv88e6xxx_reg_unlock(chip);
 942
 943         return count;
 944 }
 945
 946 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 947                                      uint64_t *data, int types,
 948                                      u16 bank1_select, u16 histogram)
 949 {
 950         struct mv88e6xxx_hw_stat *stat;
 951         int i, j;
 952
 953         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 954                 stat = &mv88e6xxx_hw_stats[i];
 955                 if (stat->type & types) {
 956                         mv88e6xxx_reg_lock(chip);
 957                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
 958                                                               bank1_select,
 959                                                               histogram);
 960                         mv88e6xxx_reg_unlock(chip);
 961
 962                         j++;
 963                 }
 964         }
 965         return j;
 966 }
 967
 968 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 969                                      uint64_t *data)
 970 {
 971         return mv88e6xxx_stats_get_stats(chip, port, data,
 972                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
 973                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 974 }
 975
 976 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 977                                      uint64_t *data)
 978 {
 979         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
 980                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 981 }
 982
 983 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 984                                      uint64_t *data)
 985 {
 986         return mv88e6xxx_stats_get_stats(chip, port, data,
 987                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
 988                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
 989                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 990 }
 991
 992 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 993                                      uint64_t *data)
 994 {
 995         return mv88e6xxx_stats_get_stats(chip, port, data,
 996                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
 997                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
 998                                          0);
 999 }
1000
1001 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1002                                         uint64_t *data)
1003 {
1004         *data++ = chip->ports[port].atu_member_violation;
1005         *data++ = chip->ports[port].atu_miss_violation;
1006         *data++ = chip->ports[port].atu_full_violation;
1007         *data++ = chip->ports[port].vtu_member_violation;
1008         *data++ = chip->ports[port].vtu_miss_violation;
1009 }
1010
1011 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1012                                 uint64_t *data)
1013 {
1014         int count = 0;
1015
1016         if (chip->info->ops->stats_get_stats)
1017                 count = chip->info->ops->stats_get_stats(chip, port, data);
1018
1019         mv88e6xxx_reg_lock(chip);
1020         if (chip->info->ops->serdes_get_stats) {
1021                 data += count;
1022                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1023         }
1024         data += count;
1025         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1026         mv88e6xxx_reg_unlock(chip);
1027 }
1028
1029 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1030                                         uint64_t *data)
1031 {
1032         struct mv88e6xxx_chip *chip = ds->priv;
1033         int ret;
1034
1035         mv88e6xxx_reg_lock(chip);
1036
1037         ret = mv88e6xxx_stats_snapshot(chip, port);
1038         mv88e6xxx_reg_unlock(chip);
1039
1040         if (ret < 0)
1041                 return;
1042
1043         mv88e6xxx_get_stats(chip, port, data);
1044
1045 }
1046
1047 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1048 {
1049         return 32 * sizeof(u16);
1050 }
1051
1052 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1053                                struct ethtool_regs *regs, void *_p)
1054 {
1055         struct mv88e6xxx_chip *chip = ds->priv;
1056         int err;
1057         u16 reg;
1058         u16 *p = _p;
1059         int i;
1060
1061         regs->version = chip->info->prod_num;
1062
1063         memset(p, 0xff, 32 * sizeof(u16));
1064
1065         mv88e6xxx_reg_lock(chip);
1066
1067         for (i = 0; i < 32; i++) {
1068
1069                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1070                 if (!err)
1071                         p[i] = reg;
1072         }
1073
1074         mv88e6xxx_reg_unlock(chip);
1075 }
1076
1077 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1078                                  struct ethtool_eee *e)
1079 {
1080         /* Nothing to do on the port's MAC */
1081         return 0;
1082 }
1083
1084 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1085                                  struct ethtool_eee *e)
1086 {
1087         /* Nothing to do on the port's MAC */
1088         return 0;
1089 }
1090
1091 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1092 {
1093         struct dsa_switch *ds = NULL;
1094         struct net_device *br;
1095         u16 pvlan;
1096         int i;
1097
1098         if (dev < DSA_MAX_SWITCHES)
1099                 ds = chip->ds->dst->ds[dev];
1100
1101         /* Prevent frames from unknown switch or port */
1102         if (!ds || port >= ds->num_ports)
1103                 return 0;
1104
1105         /* Frames from DSA links and CPU ports can egress any local port */
1106         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1107                 return mv88e6xxx_port_mask(chip);
1108
1109         br = ds->ports[port].bridge_dev;
1110         pvlan = 0;
1111
1112         /* Frames from user ports can egress any local DSA links and CPU ports,
1113          * as well as any local member of their bridge group.
1114          */
1115         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1116                 if (dsa_is_cpu_port(chip->ds, i) ||
1117                     dsa_is_dsa_port(chip->ds, i) ||
1118                     (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1119                         pvlan |= BIT(i);
1120
1121         return pvlan;
1122 }
1123
1124 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1125 {
1126         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1127
1128         /* prevent frames from going back out of the port they came in on */
1129         output_ports &= ~BIT(port);
1130
1131         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1132 }
1133
1134 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1135                                          u8 state)
1136 {
1137         struct mv88e6xxx_chip *chip = ds->priv;
1138         int err;
1139
1140         mv88e6xxx_reg_lock(chip);
1141         err = mv88e6xxx_port_set_state(chip, port, state);
1142         mv88e6xxx_reg_unlock(chip);
1143
1144         if (err)
1145                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1146 }
1147
1148 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1149 {
1150         int err;
1151
1152         if (chip->info->ops->ieee_pri_map) {
1153                 err = chip->info->ops->ieee_pri_map(chip);
1154                 if (err)
1155                         return err;
1156         }
1157
1158         if (chip->info->ops->ip_pri_map) {
1159                 err = chip->info->ops->ip_pri_map(chip);
1160                 if (err)
1161                         return err;
1162         }
1163
1164         return 0;
1165 }
1166
1167 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1168 {
1169         int target, port;
1170         int err;
1171
1172         if (!chip->info->global2_addr)
1173                 return 0;
1174
1175         /* Initialize the routing port to the 32 possible target devices */
1176         for (target = 0; target < 32; target++) {
1177                 port = 0x1f;
1178                 if (target < DSA_MAX_SWITCHES)
1179                         if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1180                                 port = chip->ds->rtable[target];
1181
1182                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1183                 if (err)
1184                         return err;
1185         }
1186
1187         if (chip->info->ops->set_cascade_port) {
1188                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1189                 err = chip->info->ops->set_cascade_port(chip, port);
1190                 if (err)
1191                         return err;
1192         }
1193
1194         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1195         if (err)
1196                 return err;
1197
1198         return 0;
1199 }
1200
1201 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1202 {
1203         /* Clear all trunk masks and mapping */
1204         if (chip->info->global2_addr)
1205                 return mv88e6xxx_g2_trunk_clear(chip);
1206
1207         return 0;
1208 }
1209
1210 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1211 {
1212         if (chip->info->ops->rmu_disable)
1213                 return chip->info->ops->rmu_disable(chip);
1214
1215         return 0;
1216 }
1217
1218 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1219 {
1220         if (chip->info->ops->pot_clear)
1221                 return chip->info->ops->pot_clear(chip);
1222
1223         return 0;
1224 }
1225
1226 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1227 {
1228         if (chip->info->ops->mgmt_rsvd2cpu)
1229                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1230
1231         return 0;
1232 }
1233
1234 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1235 {
1236         int err;
1237
1238         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1239         if (err)
1240                 return err;
1241
1242         err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1243         if (err)
1244                 return err;
1245
1246         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1247 }
1248
1249 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1250 {
1251         int port;
1252         int err;
1253
1254         if (!chip->info->ops->irl_init_all)
1255                 return 0;
1256
1257         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1258                 /* Disable ingress rate limiting by resetting all per port
1259                  * ingress rate limit resources to their initial state.
1260                  */
1261                 err = chip->info->ops->irl_init_all(chip, port);
1262                 if (err)
1263                         return err;
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1270 {
1271         if (chip->info->ops->set_switch_mac) {
1272                 u8 addr[ETH_ALEN];
1273
1274                 eth_random_addr(addr);
1275
1276                 return chip->info->ops->set_switch_mac(chip, addr);
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1283 {
1284         u16 pvlan = 0;
1285
1286         if (!mv88e6xxx_has_pvt(chip))
1287                 return -EOPNOTSUPP;
1288
1289         /* Skip the local source device, which uses in-chip port VLAN */
1290         if (dev != chip->ds->index)
1291                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1292
1293         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1294 }
1295
1296 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1297 {
1298         int dev, port;
1299         int err;
1300
1301         if (!mv88e6xxx_has_pvt(chip))
1302                 return 0;
1303
1304         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1305          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1306          */
1307         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1308         if (err)
1309                 return err;
1310
1311         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1312                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1313                         err = mv88e6xxx_pvt_map(chip, dev, port);
1314                         if (err)
1315                                 return err;
1316                 }
1317         }
1318
1319         return 0;
1320 }
1321
1322 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1323 {
1324         struct mv88e6xxx_chip *chip = ds->priv;
1325         int err;
1326
1327         mv88e6xxx_reg_lock(chip);
1328         err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1329         mv88e6xxx_reg_unlock(chip);
1330
1331         if (err)
1332                 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1333 }
1334
1335 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1336 {
1337         if (!chip->info->max_vid)
1338                 return 0;
1339
1340         return mv88e6xxx_g1_vtu_flush(chip);
1341 }
1342
1343 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1344                                  struct mv88e6xxx_vtu_entry *entry)
1345 {
1346         if (!chip->info->ops->vtu_getnext)
1347                 return -EOPNOTSUPP;
1348
1349         return chip->info->ops->vtu_getnext(chip, entry);
1350 }
1351
1352 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1353                                    struct mv88e6xxx_vtu_entry *entry)
1354 {
1355         if (!chip->info->ops->vtu_loadpurge)
1356                 return -EOPNOTSUPP;
1357
1358         return chip->info->ops->vtu_loadpurge(chip, entry);
1359 }
1360
1361 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1362 {
1363         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1364         struct mv88e6xxx_vtu_entry vlan = {
1365                 .vid = chip->info->max_vid,
1366         };
1367         int i, err;
1368
1369         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1370
1371         /* Set every FID bit used by the (un)bridged ports */
1372         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1373                 err = mv88e6xxx_port_get_fid(chip, i, fid);
1374                 if (err)
1375                         return err;
1376
1377                 set_bit(*fid, fid_bitmap);
1378         }
1379
1380         /* Set every FID bit used by the VLAN entries */
1381         do {
1382                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1383                 if (err)
1384                         return err;
1385
1386                 if (!vlan.valid)
1387                         break;
1388
1389                 set_bit(vlan.fid, fid_bitmap);
1390         } while (vlan.vid < chip->info->max_vid);
1391
1392         /* The reset value 0x000 is used to indicate that multiple address
1393          * databases are not needed. Return the next positive available.
1394          */
1395         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1396         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1397                 return -ENOSPC;
1398
1399         /* Clear the database */
1400         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1401 }
1402
1403 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1404                              struct mv88e6xxx_vtu_entry *entry, bool new)
1405 {
1406         int err;
1407
1408         if (!vid)
1409                 return -EOPNOTSUPP;
1410
1411         entry->vid = vid - 1;
1412         entry->valid = false;
1413
1414         err = mv88e6xxx_vtu_getnext(chip, entry);
1415         if (err)
1416                 return err;
1417
1418         if (entry->vid == vid && entry->valid)
1419                 return 0;
1420
1421         if (new) {
1422                 int i;
1423
1424                 /* Initialize a fresh VLAN entry */
1425                 memset(entry, 0, sizeof(*entry));
1426                 entry->valid = true;
1427                 entry->vid = vid;
1428
1429                 /* Exclude all ports */
1430                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1431                         entry->member[i] =
1432                                 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1433
1434                 return mv88e6xxx_atu_new(chip, &entry->fid);
1435         }
1436
1437         /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1438         return -EOPNOTSUPP;
1439 }
1440
1441 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1442                                         u16 vid_begin, u16 vid_end)
1443 {
1444         struct mv88e6xxx_chip *chip = ds->priv;
1445         struct mv88e6xxx_vtu_entry vlan = {
1446                 .vid = vid_begin - 1,
1447         };
1448         int i, err;
1449
1450         /* DSA and CPU ports have to be members of multiple vlans */
1451         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1452                 return 0;
1453
1454         if (!vid_begin)
1455                 return -EOPNOTSUPP;
1456
1457         mv88e6xxx_reg_lock(chip);
1458
1459         do {
1460                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1461                 if (err)
1462                         goto unlock;
1463
1464                 if (!vlan.valid)
1465                         break;
1466
1467                 if (vlan.vid > vid_end)
1468                         break;
1469
1470                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1471                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1472                                 continue;
1473
1474                         if (!ds->ports[i].slave)
1475                                 continue;
1476
1477                         if (vlan.member[i] ==
1478                             MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1479                                 continue;
1480
1481                         if (dsa_to_port(ds, i)->bridge_dev ==
1482                             ds->ports[port].bridge_dev)
1483                                 break; /* same bridge, check next VLAN */
1484
1485                         if (!dsa_to_port(ds, i)->bridge_dev)
1486                                 continue;
1487
1488                         dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1489                                 port, vlan.vid, i,
1490                                 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1491                         err = -EOPNOTSUPP;
1492                         goto unlock;
1493                 }
1494         } while (vlan.vid < vid_end);
1495
1496 unlock:
1497         mv88e6xxx_reg_unlock(chip);
1498
1499         return err;
1500 }
1501
1502 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1503                                          bool vlan_filtering)
1504 {
1505         struct mv88e6xxx_chip *chip = ds->priv;
1506         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1507                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1508         int err;
1509
1510         if (!chip->info->max_vid)
1511                 return -EOPNOTSUPP;
1512
1513         mv88e6xxx_reg_lock(chip);
1514         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1515         mv88e6xxx_reg_unlock(chip);
1516
1517         return err;
1518 }
1519
1520 static int
1521 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1522                             const struct switchdev_obj_port_vlan *vlan)
1523 {
1524         struct mv88e6xxx_chip *chip = ds->priv;
1525         int err;
1526
1527         if (!chip->info->max_vid)
1528                 return -EOPNOTSUPP;
1529
1530         /* If the requested port doesn't belong to the same bridge as the VLAN
1531          * members, do not support it (yet) and fallback to software VLAN.
1532          */
1533         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1534                                            vlan->vid_end);
1535         if (err)
1536                 return err;
1537
1538         /* We don't need any dynamic resource from the kernel (yet),
1539          * so skip the prepare phase.
1540          */
1541         return 0;
1542 }
1543
1544 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1545                                         const unsigned char *addr, u16 vid,
1546                                         u8 state)
1547 {
1548         struct mv88e6xxx_vtu_entry vlan;
1549         struct mv88e6xxx_atu_entry entry;
1550         int err;
1551
1552         /* Null VLAN ID corresponds to the port private database */
1553         if (vid == 0)
1554                 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1555         else
1556                 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1557         if (err)
1558                 return err;
1559
1560         entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1561         ether_addr_copy(entry.mac, addr);
1562         eth_addr_dec(entry.mac);
1563
1564         err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1565         if (err)
1566                 return err;
1567
1568         /* Initialize a fresh ATU entry if it isn't found */
1569         if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1570             !ether_addr_equal(entry.mac, addr)) {
1571                 memset(&entry, 0, sizeof(entry));
1572                 ether_addr_copy(entry.mac, addr);
1573         }
1574
1575         /* Purge the ATU entry only if no port is using it anymore */
1576         if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1577                 entry.portvec &= ~BIT(port);
1578                 if (!entry.portvec)
1579                         entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1580         } else {
1581                 entry.portvec |= BIT(port);
1582                 entry.state = state;
1583         }
1584
1585         return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1586 }
1587
1588 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1589                                         u16 vid)
1590 {
1591         const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1592         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1593
1594         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1595 }
1596
1597 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1598 {
1599         int port;
1600         int err;
1601
1602         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1603                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1604                 if (err)
1605                         return err;
1606         }
1607
1608         return 0;
1609 }
1610
1611 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1612                                     u16 vid, u8 member)
1613 {
1614         struct mv88e6xxx_vtu_entry vlan;
1615         int err;
1616
1617         err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1618         if (err)
1619                 return err;
1620
1621         vlan.member[port] = member;
1622
1623         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1624         if (err)
1625                 return err;
1626
1627         return mv88e6xxx_broadcast_setup(chip, vid);
1628 }
1629
1630 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1631                                     const struct switchdev_obj_port_vlan *vlan)
1632 {
1633         struct mv88e6xxx_chip *chip = ds->priv;
1634         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1635         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1636         u8 member;
1637         u16 vid;
1638
1639         if (!chip->info->max_vid)
1640                 return;
1641
1642         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1643                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1644         else if (untagged)
1645                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1646         else
1647                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1648
1649         mv88e6xxx_reg_lock(chip);
1650
1651         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1652                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1653                         dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1654                                 vid, untagged ? 'u' : 't');
1655
1656         if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1657                 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1658                         vlan->vid_end);
1659
1660         mv88e6xxx_reg_unlock(chip);
1661 }
1662
1663 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1664                                     int port, u16 vid)
1665 {
1666         struct mv88e6xxx_vtu_entry vlan;
1667         int i, err;
1668
1669         err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1670         if (err)
1671                 return err;
1672
1673         /* Tell switchdev if this VLAN is handled in software */
1674         if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1675                 return -EOPNOTSUPP;
1676
1677         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1678
1679         /* keep the VLAN unless all ports are excluded */
1680         vlan.valid = false;
1681         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1682                 if (vlan.member[i] !=
1683                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1684                         vlan.valid = true;
1685                         break;
1686                 }
1687         }
1688
1689         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1690         if (err)
1691                 return err;
1692
1693         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1694 }
1695
1696 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1697                                    const struct switchdev_obj_port_vlan *vlan)
1698 {
1699         struct mv88e6xxx_chip *chip = ds->priv;
1700         u16 pvid, vid;
1701         int err = 0;
1702
1703         if (!chip->info->max_vid)
1704                 return -EOPNOTSUPP;
1705
1706         mv88e6xxx_reg_lock(chip);
1707
1708         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1709         if (err)
1710                 goto unlock;
1711
1712         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1713                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1714                 if (err)
1715                         goto unlock;
1716
1717                 if (vid == pvid) {
1718                         err = mv88e6xxx_port_set_pvid(chip, port, 0);
1719                         if (err)
1720                                 goto unlock;
1721                 }
1722         }
1723
1724 unlock:
1725         mv88e6xxx_reg_unlock(chip);
1726
1727         return err;
1728 }
1729
1730 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1731                                   const unsigned char *addr, u16 vid)
1732 {
1733         struct mv88e6xxx_chip *chip = ds->priv;
1734         int err;
1735
1736         mv88e6xxx_reg_lock(chip);
1737         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1738                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1739         mv88e6xxx_reg_unlock(chip);
1740
1741         return err;
1742 }
1743
1744 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1745                                   const unsigned char *addr, u16 vid)
1746 {
1747         struct mv88e6xxx_chip *chip = ds->priv;
1748         int err;
1749
1750         mv88e6xxx_reg_lock(chip);
1751         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1752                                            MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1753         mv88e6xxx_reg_unlock(chip);
1754
1755         return err;
1756 }
1757
1758 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1759                                       u16 fid, u16 vid, int port,
1760                                       dsa_fdb_dump_cb_t *cb, void *data)
1761 {
1762         struct mv88e6xxx_atu_entry addr;
1763         bool is_static;
1764         int err;
1765
1766         addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1767         eth_broadcast_addr(addr.mac);
1768
1769         do {
1770                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1771                 if (err)
1772                         return err;
1773
1774                 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1775                         break;
1776
1777                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1778                         continue;
1779
1780                 if (!is_unicast_ether_addr(addr.mac))
1781                         continue;
1782
1783                 is_static = (addr.state ==
1784                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1785                 err = cb(addr.mac, vid, is_static, data);
1786                 if (err)
1787                         return err;
1788         } while (!is_broadcast_ether_addr(addr.mac));
1789
1790         return err;
1791 }
1792
1793 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1794                                   dsa_fdb_dump_cb_t *cb, void *data)
1795 {
1796         struct mv88e6xxx_vtu_entry vlan = {
1797                 .vid = chip->info->max_vid,
1798         };
1799         u16 fid;
1800         int err;
1801
1802         /* Dump port's default Filtering Information Database (VLAN ID 0) */
1803         err = mv88e6xxx_port_get_fid(chip, port, &fid);
1804         if (err)
1805                 return err;
1806
1807         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1808         if (err)
1809                 return err;
1810
1811         /* Dump VLANs' Filtering Information Databases */
1812         do {
1813                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1814                 if (err)
1815                         return err;
1816
1817                 if (!vlan.valid)
1818                         break;
1819
1820                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1821                                                  cb, data);
1822                 if (err)
1823                         return err;
1824         } while (vlan.vid < chip->info->max_vid);
1825
1826         return err;
1827 }
1828
1829 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1830                                    dsa_fdb_dump_cb_t *cb, void *data)
1831 {
1832         struct mv88e6xxx_chip *chip = ds->priv;
1833         int err;
1834
1835         mv88e6xxx_reg_lock(chip);
1836         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
1837         mv88e6xxx_reg_unlock(chip);
1838
1839         return err;
1840 }
1841
1842 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1843                                 struct net_device *br)
1844 {
1845         struct dsa_switch *ds;
1846         int port;
1847         int dev;
1848         int err;
1849
1850         /* Remap the Port VLAN of each local bridge group member */
1851         for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1852                 if (chip->ds->ports[port].bridge_dev == br) {
1853                         err = mv88e6xxx_port_vlan_map(chip, port);
1854                         if (err)
1855                                 return err;
1856                 }
1857         }
1858
1859         if (!mv88e6xxx_has_pvt(chip))
1860                 return 0;
1861
1862         /* Remap the Port VLAN of each cross-chip bridge group member */
1863         for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1864                 ds = chip->ds->dst->ds[dev];
1865                 if (!ds)
1866                         break;
1867
1868                 for (port = 0; port < ds->num_ports; ++port) {
1869                         if (ds->ports[port].bridge_dev == br) {
1870                                 err = mv88e6xxx_pvt_map(chip, dev, port);
1871                                 if (err)
1872                                         return err;
1873                         }
1874                 }
1875         }
1876
1877         return 0;
1878 }
1879
1880 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1881                                       struct net_device *br)
1882 {
1883         struct mv88e6xxx_chip *chip = ds->priv;
1884         int err;
1885
1886         mv88e6xxx_reg_lock(chip);
1887         err = mv88e6xxx_bridge_map(chip, br);
1888         mv88e6xxx_reg_unlock(chip);
1889
1890         return err;
1891 }
1892
1893 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1894                                         struct net_device *br)
1895 {
1896         struct mv88e6xxx_chip *chip = ds->priv;
1897
1898         mv88e6xxx_reg_lock(chip);
1899         if (mv88e6xxx_bridge_map(chip, br) ||
1900             mv88e6xxx_port_vlan_map(chip, port))
1901                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1902         mv88e6xxx_reg_unlock(chip);
1903 }
1904
1905 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1906                                            int port, struct net_device *br)
1907 {
1908         struct mv88e6xxx_chip *chip = ds->priv;
1909         int err;
1910
1911         if (!mv88e6xxx_has_pvt(chip))
1912                 return 0;
1913
1914         mv88e6xxx_reg_lock(chip);
1915         err = mv88e6xxx_pvt_map(chip, dev, port);
1916         mv88e6xxx_reg_unlock(chip);
1917
1918         return err;
1919 }
1920
1921 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1922                                              int port, struct net_device *br)
1923 {
1924         struct mv88e6xxx_chip *chip = ds->priv;
1925
1926         if (!mv88e6xxx_has_pvt(chip))
1927                 return;
1928
1929         mv88e6xxx_reg_lock(chip);
1930         if (mv88e6xxx_pvt_map(chip, dev, port))
1931                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1932         mv88e6xxx_reg_unlock(chip);
1933 }
1934
1935 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1936 {
1937         if (chip->info->ops->reset)
1938                 return chip->info->ops->reset(chip);
1939
1940         return 0;
1941 }
1942
1943 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1944 {
1945         struct gpio_desc *gpiod = chip->reset;
1946
1947         /* If there is a GPIO connected to the reset pin, toggle it */
1948         if (gpiod) {
1949                 gpiod_set_value_cansleep(gpiod, 1);
1950                 usleep_range(10000, 20000);
1951                 gpiod_set_value_cansleep(gpiod, 0);
1952                 usleep_range(10000, 20000);
1953         }
1954 }
1955
1956 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1957 {
1958         int i, err;
1959
1960         /* Set all ports to the Disabled state */
1961         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1962                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1963                 if (err)
1964                         return err;
1965         }
1966
1967         /* Wait for transmit queues to drain,
1968          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1969          */
1970         usleep_range(2000, 4000);
1971
1972         return 0;
1973 }
1974
1975 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1976 {
1977         int err;
1978
1979         err = mv88e6xxx_disable_ports(chip);
1980         if (err)
1981                 return err;
1982
1983         mv88e6xxx_hardware_reset(chip);
1984
1985         return mv88e6xxx_software_reset(chip);
1986 }
1987
1988 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1989                                    enum mv88e6xxx_frame_mode frame,
1990                                    enum mv88e6xxx_egress_mode egress, u16 etype)
1991 {
1992         int err;
1993
1994         if (!chip->info->ops->port_set_frame_mode)
1995                 return -EOPNOTSUPP;
1996
1997         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1998         if (err)
1999                 return err;
2000
2001         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2002         if (err)
2003                 return err;
2004
2005         if (chip->info->ops->port_set_ether_type)
2006                 return chip->info->ops->port_set_ether_type(chip, port, etype);
2007
2008         return 0;
2009 }
2010
2011 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2012 {
2013         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2014                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2015                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2016 }
2017
2018 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2019 {
2020         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2021                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2022                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2023 }
2024
2025 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2026 {
2027         return mv88e6xxx_set_port_mode(chip, port,
2028                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
2029                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2030                                        ETH_P_EDSA);
2031 }
2032
2033 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2034 {
2035         if (dsa_is_dsa_port(chip->ds, port))
2036                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2037
2038         if (dsa_is_user_port(chip->ds, port))
2039                 return mv88e6xxx_set_port_mode_normal(chip, port);
2040
2041         /* Setup CPU port mode depending on its supported tag format */
2042         if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2043                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2044
2045         if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2046                 return mv88e6xxx_set_port_mode_edsa(chip, port);
2047
2048         return -EINVAL;
2049 }
2050
2051 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2052 {
2053         bool message = dsa_is_dsa_port(chip->ds, port);
2054
2055         return mv88e6xxx_port_set_message_port(chip, port, message);
2056 }
2057
2058 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2059 {
2060         struct dsa_switch *ds = chip->ds;
2061         bool flood;
2062
2063         /* Upstream ports flood frames with unknown unicast or multicast DA */
2064         flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2065         if (chip->info->ops->port_set_egress_floods)
2066                 return chip->info->ops->port_set_egress_floods(chip, port,
2067                                                                flood, flood);
2068
2069         return 0;
2070 }
2071
2072 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2073                                   bool on)
2074 {
2075         if (chip->info->ops->serdes_power)
2076                 return chip->info->ops->serdes_power(chip, port, on);
2077
2078         return 0;
2079 }
2080
2081 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2082 {
2083         struct dsa_switch *ds = chip->ds;
2084         int upstream_port;
2085         int err;
2086
2087         upstream_port = dsa_upstream_port(ds, port);
2088         if (chip->info->ops->port_set_upstream_port) {
2089                 err = chip->info->ops->port_set_upstream_port(chip, port,
2090                                                               upstream_port);
2091                 if (err)
2092                         return err;
2093         }
2094
2095         if (port == upstream_port) {
2096                 if (chip->info->ops->set_cpu_port) {
2097                         err = chip->info->ops->set_cpu_port(chip,
2098                                                             upstream_port);
2099                         if (err)
2100                                 return err;
2101                 }
2102
2103                 if (chip->info->ops->set_egress_port) {
2104                         err = chip->info->ops->set_egress_port(chip,
2105                                                                upstream_port);
2106                         if (err)
2107                                 return err;
2108                 }
2109         }
2110
2111         return 0;
2112 }
2113
2114 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2115 {
2116         struct dsa_switch *ds = chip->ds;
2117         int err;
2118         u16 reg;
2119
2120         chip->ports[port].chip = chip;
2121         chip->ports[port].port = port;
2122
2123         /* MAC Forcing register: don't force link, speed, duplex or flow control
2124          * state to any particular values on physical ports, but force the CPU
2125          * port and all DSA ports to their maximum bandwidth and full duplex.
2126          */
2127         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2128                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2129                                                SPEED_MAX, DUPLEX_FULL,
2130                                                PAUSE_OFF,
2131                                                PHY_INTERFACE_MODE_NA);
2132         else
2133                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2134                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2135                                                PAUSE_ON,
2136                                                PHY_INTERFACE_MODE_NA);
2137         if (err)
2138                 return err;
2139
2140         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2141          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2142          * tunneling, determine priority by looking at 802.1p and IP
2143          * priority fields (IP prio has precedence), and set STP state
2144          * to Forwarding.
2145          *
2146          * If this is the CPU link, use DSA or EDSA tagging depending
2147          * on which tagging mode was configured.
2148          *
2149          * If this is a link to another switch, use DSA tagging mode.
2150          *
2151          * If this is the upstream port for this switch, enable
2152          * forwarding of unknown unicasts and multicasts.
2153          */
2154         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2155                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2156                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2157         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2158         if (err)
2159                 return err;
2160
2161         err = mv88e6xxx_setup_port_mode(chip, port);
2162         if (err)
2163                 return err;
2164
2165         err = mv88e6xxx_setup_egress_floods(chip, port);
2166         if (err)
2167                 return err;
2168
2169         /* Enable the SERDES interface for DSA and CPU ports. Normal
2170          * ports SERDES are enabled when the port is enabled, thus
2171          * saving a bit of power.
2172          */
2173         if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
2174                 err = mv88e6xxx_serdes_power(chip, port, true);
2175                 if (err)
2176                         return err;
2177         }
2178
2179         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2180          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2181          * untagged frames on this port, do a destination address lookup on all
2182          * received packets as usual, disable ARP mirroring and don't send a
2183          * copy of all transmitted/received frames on this port to the CPU.
2184          */
2185         err = mv88e6xxx_port_set_map_da(chip, port);
2186         if (err)
2187                 return err;
2188
2189         err = mv88e6xxx_setup_upstream_port(chip, port);
2190         if (err)
2191                 return err;
2192
2193         err = mv88e6xxx_port_set_8021q_mode(chip, port,
2194                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2195         if (err)
2196                 return err;
2197
2198         if (chip->info->ops->port_set_jumbo_size) {
2199                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2200                 if (err)
2201                         return err;
2202         }
2203
2204         /* Port Association Vector: when learning source addresses
2205          * of packets, add the address to the address database using
2206          * a port bitmap that has only the bit for this port set and
2207          * the other bits clear.
2208          */
2209         reg = 1 << port;
2210         /* Disable learning for CPU port */
2211         if (dsa_is_cpu_port(ds, port))
2212                 reg = 0;
2213
2214         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2215                                    reg);
2216         if (err)
2217                 return err;
2218
2219         /* Egress rate control 2: disable egress rate control. */
2220         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2221                                    0x0000);
2222         if (err)
2223                 return err;
2224
2225         if (chip->info->ops->port_pause_limit) {
2226                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2227                 if (err)
2228                         return err;
2229         }
2230
2231         if (chip->info->ops->port_disable_learn_limit) {
2232                 err = chip->info->ops->port_disable_learn_limit(chip, port);
2233                 if (err)
2234                         return err;
2235         }
2236
2237         if (chip->info->ops->port_disable_pri_override) {
2238                 err = chip->info->ops->port_disable_pri_override(chip, port);
2239                 if (err)
2240                         return err;
2241         }
2242
2243         if (chip->info->ops->port_tag_remap) {
2244                 err = chip->info->ops->port_tag_remap(chip, port);
2245                 if (err)
2246                         return err;
2247         }
2248
2249         if (chip->info->ops->port_egress_rate_limiting) {
2250                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2251                 if (err)
2252                         return err;
2253         }
2254
2255         err = mv88e6xxx_setup_message_port(chip, port);
2256         if (err)
2257                 return err;
2258
2259         /* Port based VLAN map: give each port the same default address
2260          * database, and allow bidirectional communication between the
2261          * CPU and DSA port(s), and the other ports.
2262          */
2263         err = mv88e6xxx_port_set_fid(chip, port, 0);
2264         if (err)
2265                 return err;
2266
2267         err = mv88e6xxx_port_vlan_map(chip, port);
2268         if (err)
2269                 return err;
2270
2271         /* Default VLAN ID and priority: don't set a default VLAN
2272          * ID, and set the default packet priority to zero.
2273          */
2274         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2275 }
2276
2277 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2278                                  struct phy_device *phydev)
2279 {
2280         struct mv88e6xxx_chip *chip = ds->priv;
2281         int err;
2282
2283         mv88e6xxx_reg_lock(chip);
2284
2285         err = mv88e6xxx_serdes_power(chip, port, true);
2286
2287         if (!err && chip->info->ops->serdes_irq_setup)
2288                 err = chip->info->ops->serdes_irq_setup(chip, port);
2289
2290         mv88e6xxx_reg_unlock(chip);
2291
2292         return err;
2293 }
2294
2295 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2296 {
2297         struct mv88e6xxx_chip *chip = ds->priv;
2298
2299         mv88e6xxx_reg_lock(chip);
2300
2301         if (mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED))
2302                 dev_err(chip->dev, "failed to disable port\n");
2303
2304         if (chip->info->ops->serdes_irq_free)
2305                 chip->info->ops->serdes_irq_free(chip, port);
2306
2307         if (mv88e6xxx_serdes_power(chip, port, false))
2308                 dev_err(chip->dev, "failed to power off SERDES\n");
2309
2310         mv88e6xxx_reg_unlock(chip);
2311 }
2312
2313 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2314                                      unsigned int ageing_time)
2315 {
2316         struct mv88e6xxx_chip *chip = ds->priv;
2317         int err;
2318
2319         mv88e6xxx_reg_lock(chip);
2320         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2321         mv88e6xxx_reg_unlock(chip);
2322
2323         return err;
2324 }
2325
2326 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2327 {
2328         int err;
2329
2330         /* Initialize the statistics unit */
2331         if (chip->info->ops->stats_set_histogram) {
2332                 err = chip->info->ops->stats_set_histogram(chip);
2333                 if (err)
2334                         return err;
2335         }
2336
2337         return mv88e6xxx_g1_stats_clear(chip);
2338 }
2339
2340 /* The mv88e6390 has some hidden registers used for debug and
2341  * development. The errata also makes use of them.
2342  */
2343 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2344                                   int reg, u16 val)
2345 {
2346         u16 ctrl;
2347         int err;
2348
2349         err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2350                                    PORT_RESERVED_1A, val);
2351         if (err)
2352                 return err;
2353
2354         ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2355                PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2356                reg;
2357
2358         return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2359                                     PORT_RESERVED_1A, ctrl);
2360 }
2361
2362 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2363 {
2364         return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2365                               PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2366 }
2367
2368
2369 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2370                                   int reg, u16 *val)
2371 {
2372         u16 ctrl;
2373         int err;
2374
2375         ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2376                PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2377                reg;
2378
2379         err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2380                                    PORT_RESERVED_1A, ctrl);
2381         if (err)
2382                 return err;
2383
2384         err = mv88e6390_hidden_wait(chip);
2385         if (err)
2386                 return err;
2387
2388         return  mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2389                                     PORT_RESERVED_1A, val);
2390 }
2391
2392 /* Check if the errata has already been applied. */
2393 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2394 {
2395         int port;
2396         int err;
2397         u16 val;
2398
2399         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2400                 err = mv88e6390_hidden_read(chip, port, 0, &val);
2401                 if (err) {
2402                         dev_err(chip->dev,
2403                                 "Error reading hidden register: %d\n", err);
2404                         return false;
2405                 }
2406                 if (val != 0x01c0)
2407                         return false;
2408         }
2409
2410         return true;
2411 }
2412
2413 /* The 6390 copper ports have an errata which require poking magic
2414  * values into undocumented hidden registers and then performing a
2415  * software reset.
2416  */
2417 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2418 {
2419         int port;
2420         int err;
2421
2422         if (mv88e6390_setup_errata_applied(chip))
2423                 return 0;
2424
2425         /* Set the ports into blocking mode */
2426         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2427                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2428                 if (err)
2429                         return err;
2430         }
2431
2432         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2433                 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2434                 if (err)
2435                         return err;
2436         }
2437
2438         return mv88e6xxx_software_reset(chip);
2439 }
2440
2441 static int mv88e6xxx_setup(struct dsa_switch *ds)
2442 {
2443         struct mv88e6xxx_chip *chip = ds->priv;
2444         u8 cmode;
2445         int err;
2446         int i;
2447
2448         chip->ds = ds;
2449         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2450
2451         mv88e6xxx_reg_lock(chip);
2452
2453         if (chip->info->ops->setup_errata) {
2454                 err = chip->info->ops->setup_errata(chip);
2455                 if (err)
2456                         goto unlock;
2457         }
2458
2459         /* Cache the cmode of each port. */
2460         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2461                 if (chip->info->ops->port_get_cmode) {
2462                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2463                         if (err)
2464                                 goto unlock;
2465
2466                         chip->ports[i].cmode = cmode;
2467                 }
2468         }
2469
2470         /* Setup Switch Port Registers */
2471         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2472                 if (dsa_is_unused_port(ds, i)) {
2473                         err = mv88e6xxx_port_set_state(chip, i,
2474                                                        BR_STATE_DISABLED);
2475                         if (err)
2476                                 goto unlock;
2477
2478                         err = mv88e6xxx_serdes_power(chip, i, false);
2479                         if (err)
2480                                 goto unlock;
2481
2482                         continue;
2483                 }
2484
2485                 err = mv88e6xxx_setup_port(chip, i);
2486                 if (err)
2487                         goto unlock;
2488         }
2489
2490         err = mv88e6xxx_irl_setup(chip);
2491         if (err)
2492                 goto unlock;
2493
2494         err = mv88e6xxx_mac_setup(chip);
2495         if (err)
2496                 goto unlock;
2497
2498         err = mv88e6xxx_phy_setup(chip);
2499         if (err)
2500                 goto unlock;
2501
2502         err = mv88e6xxx_vtu_setup(chip);
2503         if (err)
2504                 goto unlock;
2505
2506         err = mv88e6xxx_pvt_setup(chip);
2507         if (err)
2508                 goto unlock;
2509
2510         err = mv88e6xxx_atu_setup(chip);
2511         if (err)
2512                 goto unlock;
2513
2514         err = mv88e6xxx_broadcast_setup(chip, 0);
2515         if (err)
2516                 goto unlock;
2517
2518         err = mv88e6xxx_pot_setup(chip);
2519         if (err)
2520                 goto unlock;
2521
2522         err = mv88e6xxx_rmu_setup(chip);
2523         if (err)
2524                 goto unlock;
2525
2526         err = mv88e6xxx_rsvd2cpu_setup(chip);
2527         if (err)
2528                 goto unlock;
2529
2530         err = mv88e6xxx_trunk_setup(chip);
2531         if (err)
2532                 goto unlock;
2533
2534         err = mv88e6xxx_devmap_setup(chip);
2535         if (err)
2536                 goto unlock;
2537
2538         err = mv88e6xxx_pri_setup(chip);
2539         if (err)
2540                 goto unlock;
2541
2542         /* Setup PTP Hardware Clock and timestamping */
2543         if (chip->info->ptp_support) {
2544                 err = mv88e6xxx_ptp_setup(chip);
2545                 if (err)
2546                         goto unlock;
2547
2548                 err = mv88e6xxx_hwtstamp_setup(chip);
2549                 if (err)
2550                         goto unlock;
2551         }
2552
2553         err = mv88e6xxx_stats_setup(chip);
2554         if (err)
2555                 goto unlock;
2556
2557 unlock:
2558         mv88e6xxx_reg_unlock(chip);
2559
2560         return err;
2561 }
2562
2563 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2564 {
2565         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2566         struct mv88e6xxx_chip *chip = mdio_bus->chip;
2567         u16 val;
2568         int err;
2569
2570         if (!chip->info->ops->phy_read)
2571                 return -EOPNOTSUPP;
2572
2573         mv88e6xxx_reg_lock(chip);
2574         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2575         mv88e6xxx_reg_unlock(chip);
2576
2577         if (reg == MII_PHYSID2) {
2578                 /* Some internal PHYs don't have a model number. */
2579                 if (chip->info->family != MV88E6XXX_FAMILY_6165)
2580                         /* Then there is the 6165 family. It gets is
2581                          * PHYs correct. But it can also have two
2582                          * SERDES interfaces in the PHY address
2583                          * space. And these don't have a model
2584                          * number. But they are not PHYs, so we don't
2585                          * want to give them something a PHY driver
2586                          * will recognise.
2587                          *
2588                          * Use the mv88e6390 family model number
2589                          * instead, for anything which really could be
2590                          * a PHY,
2591                          */
2592                         if (!(val & 0x3f0))
2593                                 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2594         }
2595
2596         return err ? err : val;
2597 }
2598
2599 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2600 {
2601         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2602         struct mv88e6xxx_chip *chip = mdio_bus->chip;
2603         int err;
2604
2605         if (!chip->info->ops->phy_write)
2606                 return -EOPNOTSUPP;
2607
2608         mv88e6xxx_reg_lock(chip);
2609         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2610         mv88e6xxx_reg_unlock(chip);
2611
2612         return err;
2613 }
2614
2615 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2616                                    struct device_node *np,
2617                                    bool external)
2618 {
2619         static int index;
2620         struct mv88e6xxx_mdio_bus *mdio_bus;
2621         struct mii_bus *bus;
2622         int err;
2623
2624         if (external) {
2625                 mv88e6xxx_reg_lock(chip);
2626                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2627                 mv88e6xxx_reg_unlock(chip);
2628
2629                 if (err)
2630                         return err;
2631         }
2632
2633         bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2634         if (!bus)
2635                 return -ENOMEM;
2636
2637         mdio_bus = bus->priv;
2638         mdio_bus->bus = bus;
2639         mdio_bus->chip = chip;
2640         INIT_LIST_HEAD(&mdio_bus->list);
2641         mdio_bus->external = external;
2642
2643         if (np) {
2644                 bus->name = np->full_name;
2645                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2646         } else {
2647                 bus->name = "mv88e6xxx SMI";
2648                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2649         }
2650
2651         bus->read = mv88e6xxx_mdio_read;
2652         bus->write = mv88e6xxx_mdio_write;
2653         bus->parent = chip->dev;
2654
2655         if (!external) {
2656                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2657                 if (err)
2658                         return err;
2659         }
2660
2661         err = of_mdiobus_register(bus, np);
2662         if (err) {
2663                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2664                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2665                 return err;
2666         }
2667
2668         if (external)
2669                 list_add_tail(&mdio_bus->list, &chip->mdios);
2670         else
2671                 list_add(&mdio_bus->list, &chip->mdios);
2672
2673         return 0;
2674 }
2675
2676 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2677         { .compatible = "marvell,mv88e6xxx-mdio-external",
2678           .data = (void *)true },
2679         { },
2680 };
2681
2682 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2683
2684 {
2685         struct mv88e6xxx_mdio_bus *mdio_bus;
2686         struct mii_bus *bus;
2687
2688         list_for_each_entry(mdio_bus, &chip->mdios, list) {
2689                 bus = mdio_bus->bus;
2690
2691                 if (!mdio_bus->external)
2692                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
2693
2694                 mdiobus_unregister(bus);
2695         }
2696 }
2697
2698 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2699                                     struct device_node *np)
2700 {
2701         const struct of_device_id *match;
2702         struct device_node *child;
2703         int err;
2704
2705         /* Always register one mdio bus for the internal/default mdio
2706          * bus. This maybe represented in the device tree, but is
2707          * optional.
2708          */
2709         child = of_get_child_by_name(np, "mdio");
2710         err = mv88e6xxx_mdio_register(chip, child, false);
2711         if (err)
2712                 return err;
2713
2714         /* Walk the device tree, and see if there are any other nodes
2715          * which say they are compatible with the external mdio
2716          * bus.
2717          */
2718         for_each_available_child_of_node(np, child) {
2719                 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2720                 if (match) {
2721                         err = mv88e6xxx_mdio_register(chip, child, true);
2722                         if (err) {
2723                                 mv88e6xxx_mdios_unregister(chip);
2724                                 return err;
2725                         }
2726                 }
2727         }
2728
2729         return 0;
2730 }
2731
2732 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2733 {
2734         struct mv88e6xxx_chip *chip = ds->priv;
2735
2736         return chip->eeprom_len;
2737 }
2738
2739 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2740                                 struct ethtool_eeprom *eeprom, u8 *data)
2741 {
2742         struct mv88e6xxx_chip *chip = ds->priv;
2743         int err;
2744
2745         if (!chip->info->ops->get_eeprom)
2746                 return -EOPNOTSUPP;
2747
2748         mv88e6xxx_reg_lock(chip);
2749         err = chip->info->ops->get_eeprom(chip, eeprom, data);
2750         mv88e6xxx_reg_unlock(chip);
2751
2752         if (err)
2753                 return err;
2754
2755         eeprom->magic = 0xc3ec4951;
2756
2757         return 0;
2758 }
2759
2760 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2761                                 struct ethtool_eeprom *eeprom, u8 *data)
2762 {
2763         struct mv88e6xxx_chip *chip = ds->priv;
2764         int err;
2765
2766         if (!chip->info->ops->set_eeprom)
2767                 return -EOPNOTSUPP;
2768
2769         if (eeprom->magic != 0xc3ec4951)
2770                 return -EINVAL;
2771
2772         mv88e6xxx_reg_lock(chip);
2773         err = chip->info->ops->set_eeprom(chip, eeprom, data);
2774         mv88e6xxx_reg_unlock(chip);
2775
2776         return err;
2777 }
2778
2779 static const struct mv88e6xxx_ops mv88e6085_ops = {
2780         /* MV88E6XXX_FAMILY_6097 */
2781         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2782         .ip_pri_map = mv88e6085_g1_ip_pri_map,
2783         .irl_init_all = mv88e6352_g2_irl_init_all,
2784         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2785         .phy_read = mv88e6185_phy_ppu_read,
2786         .phy_write = mv88e6185_phy_ppu_write,
2787         .port_set_link = mv88e6xxx_port_set_link,
2788         .port_set_duplex = mv88e6xxx_port_set_duplex,
2789         .port_set_speed = mv88e6185_port_set_speed,
2790         .port_tag_remap = mv88e6095_port_tag_remap,
2791         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2792         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2793         .port_set_ether_type = mv88e6351_port_set_ether_type,
2794         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2795         .port_pause_limit = mv88e6097_port_pause_limit,
2796         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2797         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2798         .port_link_state = mv88e6352_port_link_state,
2799         .port_get_cmode = mv88e6185_port_get_cmode,
2800         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2801         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2802         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2803         .stats_get_strings = mv88e6095_stats_get_strings,
2804         .stats_get_stats = mv88e6095_stats_get_stats,
2805         .set_cpu_port = mv88e6095_g1_set_cpu_port,
2806         .set_egress_port = mv88e6095_g1_set_egress_port,
2807         .watchdog_ops = &mv88e6097_watchdog_ops,
2808         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2809         .pot_clear = mv88e6xxx_g2_pot_clear,
2810         .ppu_enable = mv88e6185_g1_ppu_enable,
2811         .ppu_disable = mv88e6185_g1_ppu_disable,
2812         .reset = mv88e6185_g1_reset,
2813         .rmu_disable = mv88e6085_g1_rmu_disable,
2814         .vtu_getnext = mv88e6352_g1_vtu_getnext,
2815         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2816         .phylink_validate = mv88e6185_phylink_validate,
2817 };
2818
2819 static const struct mv88e6xxx_ops mv88e6095_ops = {
2820         /* MV88E6XXX_FAMILY_6095 */
2821         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2822         .ip_pri_map = mv88e6085_g1_ip_pri_map,
2823         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2824         .phy_read = mv88e6185_phy_ppu_read,
2825         .phy_write = mv88e6185_phy_ppu_write,
2826         .port_set_link = mv88e6xxx_port_set_link,
2827         .port_set_duplex = mv88e6xxx_port_set_duplex,
2828         .port_set_speed = mv88e6185_port_set_speed,
2829         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2830         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2831         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2832         .port_link_state = mv88e6185_port_link_state,
2833         .port_get_cmode = mv88e6185_port_get_cmode,
2834         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2835         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2836         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2837         .stats_get_strings = mv88e6095_stats_get_strings,
2838         .stats_get_stats = mv88e6095_stats_get_stats,
2839         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2840         .ppu_enable = mv88e6185_g1_ppu_enable,
2841         .ppu_disable = mv88e6185_g1_ppu_disable,
2842         .reset = mv88e6185_g1_reset,
2843         .vtu_getnext = mv88e6185_g1_vtu_getnext,
2844         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2845         .phylink_validate = mv88e6185_phylink_validate,
2846 };
2847
2848 static const struct mv88e6xxx_ops mv88e6097_ops = {
2849         /* MV88E6XXX_FAMILY_6097 */
2850         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2851         .ip_pri_map = mv88e6085_g1_ip_pri_map,
2852         .irl_init_all = mv88e6352_g2_irl_init_all,
2853         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2854         .phy_read = mv88e6xxx_g2_smi_phy_read,
2855         .phy_write = mv88e6xxx_g2_smi_phy_write,
2856         .port_set_link = mv88e6xxx_port_set_link,
2857         .port_set_duplex = mv88e6xxx_port_set_duplex,
2858         .port_set_speed = mv88e6185_port_set_speed,
2859         .port_tag_remap = mv88e6095_port_tag_remap,
2860         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2861         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2862         .port_set_ether_type = mv88e6351_port_set_ether_type,
2863         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2864         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2865         .port_pause_limit = mv88e6097_port_pause_limit,
2866         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2867         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2868         .port_link_state = mv88e6352_port_link_state,
2869         .port_get_cmode = mv88e6185_port_get_cmode,
2870         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2871         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2872         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2873         .stats_get_strings = mv88e6095_stats_get_strings,
2874         .stats_get_stats = mv88e6095_stats_get_stats,
2875         .set_cpu_port = mv88e6095_g1_set_cpu_port,
2876         .set_egress_port = mv88e6095_g1_set_egress_port,
2877         .watchdog_ops = &mv88e6097_watchdog_ops,
2878         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2879         .pot_clear = mv88e6xxx_g2_pot_clear,
2880         .reset = mv88e6352_g1_reset,
2881         .rmu_disable = mv88e6085_g1_rmu_disable,
2882         .vtu_getnext = mv88e6352_g1_vtu_getnext,
2883         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2884         .phylink_validate = mv88e6185_phylink_validate,
2885 };
2886
2887 static const struct mv88e6xxx_ops mv88e6123_ops = {
2888         /* MV88E6XXX_FAMILY_6165 */
2889         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2890         .ip_pri_map = mv88e6085_g1_ip_pri_map,
2891         .irl_init_all = mv88e6352_g2_irl_init_all,
2892         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2893         .phy_read = mv88e6xxx_g2_smi_phy_read,
2894         .phy_write = mv88e6xxx_g2_smi_phy_write,
2895         .port_set_link = mv88e6xxx_port_set_link,
2896         .port_set_duplex = mv88e6xxx_port_set_duplex,
2897         .port_set_speed = mv88e6185_port_set_speed,
2898         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2899         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2900         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2901         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2902         .port_link_state = mv88e6352_port_link_state,
2903         .port_get_cmode = mv88e6185_port_get_cmode,
2904         .stats_snapshot = mv88e6320_g1_stats_snapshot,
2905         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2906         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2907         .stats_get_strings = mv88e6095_stats_get_strings,
2908         .stats_get_stats = mv88e6095_stats_get_stats,
2909         .set_cpu_port = mv88e6095_g1_set_cpu_port,
2910         .set_egress_port = mv88e6095_g1_set_egress_port,
2911         .watchdog_ops = &mv88e6097_watchdog_ops,
2912         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2913         .pot_clear = mv88e6xxx_g2_pot_clear,
2914         .reset = mv88e6352_g1_reset,
2915         .vtu_getnext = mv88e6352_g1_vtu_getnext,
2916         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2917         .phylink_validate = mv88e6185_phylink_validate,
2918 };
2919
2920 static const struct mv88e6xxx_ops mv88e6131_ops = {
2921         /* MV88E6XXX_FAMILY_6185 */
2922         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2923         .ip_pri_map = mv88e6085_g1_ip_pri_map,
2924         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2925         .phy_read = mv88e6185_phy_ppu_read,
2926         .phy_write = mv88e6185_phy_ppu_write,
2927         .port_set_link = mv88e6xxx_port_set_link,
2928         .port_set_duplex = mv88e6xxx_port_set_duplex,
2929         .port_set_speed = mv88e6185_port_set_speed,
2930         .port_tag_remap = mv88e6095_port_tag_remap,
2931         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2932         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2933         .port_set_ether_type = mv88e6351_port_set_ether_type,
2934         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2935         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2936         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2937         .port_pause_limit = mv88e6097_port_pause_limit,
2938         .port_set_pause = mv88e6185_port_set_pause,
2939         .port_link_state = mv88e6352_port_link_state,
2940         .port_get_cmode = mv88e6185_port_get_cmode,
2941         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2942         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2943         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2944         .stats_get_strings = mv88e6095_stats_get_strings,
2945         .stats_get_stats = mv88e6095_stats_get_stats,
2946         .set_cpu_port = mv88e6095_g1_set_cpu_port,
2947         .set_egress_port = mv88e6095_g1_set_egress_port,
2948         .watchdog_ops = &mv88e6097_watchdog_ops,
2949         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2950         .ppu_enable = mv88e6185_g1_ppu_enable,
2951         .set_cascade_port = mv88e6185_g1_set_cascade_port,
2952         .ppu_disable = mv88e6185_g1_ppu_disable,
2953         .reset = mv88e6185_g1_reset,
2954         .vtu_getnext = mv88e6185_g1_vtu_getnext,
2955         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2956         .phylink_validate = mv88e6185_phylink_validate,
2957 };
2958
2959 static const struct mv88e6xxx_ops mv88e6141_ops = {
2960         /* MV88E6XXX_FAMILY_6341 */
2961         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2962         .ip_pri_map = mv88e6085_g1_ip_pri_map,
2963         .irl_init_all = mv88e6352_g2_irl_init_all,
2964         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2965         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2966         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2967         .phy_read = mv88e6xxx_g2_smi_phy_read,
2968         .phy_write = mv88e6xxx_g2_smi_phy_write,
2969         .port_set_link = mv88e6xxx_port_set_link,
2970         .port_set_duplex = mv88e6xxx_port_set_duplex,
2971         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2972         .port_set_speed = mv88e6341_port_set_speed,
2973         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
2974         .port_tag_remap = mv88e6095_port_tag_remap,
2975         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2976         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2977         .port_set_ether_type = mv88e6351_port_set_ether_type,
2978         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2979         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2980         .port_pause_limit = mv88e6097_port_pause_limit,
2981         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2982         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2983         .port_link_state = mv88e6352_port_link_state,
2984         .port_get_cmode = mv88e6352_port_get_cmode,
2985         .stats_snapshot = mv88e6390_g1_stats_snapshot,
2986         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2987         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2988         .stats_get_strings = mv88e6320_stats_get_strings,
2989         .stats_get_stats = mv88e6390_stats_get_stats,
2990         .set_cpu_port = mv88e6390_g1_set_cpu_port,
2991         .set_egress_port = mv88e6390_g1_set_egress_port,
2992         .watchdog_ops = &mv88e6390_watchdog_ops,
2993         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2994         .pot_clear = mv88e6xxx_g2_pot_clear,
2995         .reset = mv88e6352_g1_reset,
2996         .vtu_getnext = mv88e6352_g1_vtu_getnext,
2997         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2998         .serdes_power = mv88e6341_serdes_power,
2999         .gpio_ops = &mv88e6352_gpio_ops,
3000         .phylink_validate = mv88e6341_phylink_validate,
3001 };
3002
3003 static const struct mv88e6xxx_ops mv88e6161_ops = {
3004         /* MV88E6XXX_FAMILY_6165 */
3005         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3006         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3007         .irl_init_all = mv88e6352_g2_irl_init_all,
3008         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3009         .phy_read = mv88e6xxx_g2_smi_phy_read,
3010         .phy_write = mv88e6xxx_g2_smi_phy_write,
3011         .port_set_link = mv88e6xxx_port_set_link,
3012         .port_set_duplex = mv88e6xxx_port_set_duplex,
3013         .port_set_speed = mv88e6185_port_set_speed,
3014         .port_tag_remap = mv88e6095_port_tag_remap,
3015         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3016         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3017         .port_set_ether_type = mv88e6351_port_set_ether_type,
3018         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3019         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3020         .port_pause_limit = mv88e6097_port_pause_limit,
3021         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3022         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3023         .port_link_state = mv88e6352_port_link_state,
3024         .port_get_cmode = mv88e6185_port_get_cmode,
3025         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3026         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3027         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3028         .stats_get_strings = mv88e6095_stats_get_strings,
3029         .stats_get_stats = mv88e6095_stats_get_stats,
3030         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3031         .set_egress_port = mv88e6095_g1_set_egress_port,
3032         .watchdog_ops = &mv88e6097_watchdog_ops,
3033         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3034         .pot_clear = mv88e6xxx_g2_pot_clear,
3035         .reset = mv88e6352_g1_reset,
3036         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3037         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3038         .avb_ops = &mv88e6165_avb_ops,
3039         .ptp_ops = &mv88e6165_ptp_ops,
3040         .phylink_validate = mv88e6185_phylink_validate,
3041 };
3042
3043 static const struct mv88e6xxx_ops mv88e6165_ops = {
3044         /* MV88E6XXX_FAMILY_6165 */
3045         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3046         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3047         .irl_init_all = mv88e6352_g2_irl_init_all,
3048         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3049         .phy_read = mv88e6165_phy_read,
3050         .phy_write = mv88e6165_phy_write,
3051         .port_set_link = mv88e6xxx_port_set_link,
3052         .port_set_duplex = mv88e6xxx_port_set_duplex,
3053         .port_set_speed = mv88e6185_port_set_speed,
3054         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3055         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3056         .port_link_state = mv88e6352_port_link_state,
3057         .port_get_cmode = mv88e6185_port_get_cmode,
3058         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3059         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3060         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3061         .stats_get_strings = mv88e6095_stats_get_strings,
3062         .stats_get_stats = mv88e6095_stats_get_stats,
3063         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3064         .set_egress_port = mv88e6095_g1_set_egress_port,
3065         .watchdog_ops = &mv88e6097_watchdog_ops,
3066         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3067         .pot_clear = mv88e6xxx_g2_pot_clear,
3068         .reset = mv88e6352_g1_reset,
3069         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3070         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3071         .avb_ops = &mv88e6165_avb_ops,
3072         .ptp_ops = &mv88e6165_ptp_ops,
3073         .phylink_validate = mv88e6185_phylink_validate,
3074 };
3075
3076 static const struct mv88e6xxx_ops mv88e6171_ops = {
3077         /* MV88E6XXX_FAMILY_6351 */
3078         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3079         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3080         .irl_init_all = mv88e6352_g2_irl_init_all,
3081         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3082         .phy_read = mv88e6xxx_g2_smi_phy_read,
3083         .phy_write = mv88e6xxx_g2_smi_phy_write,
3084         .port_set_link = mv88e6xxx_port_set_link,
3085         .port_set_duplex = mv88e6xxx_port_set_duplex,
3086         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3087         .port_set_speed = mv88e6185_port_set_speed,
3088         .port_tag_remap = mv88e6095_port_tag_remap,
3089         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3090         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3091         .port_set_ether_type = mv88e6351_port_set_ether_type,
3092         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3093         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3094         .port_pause_limit = mv88e6097_port_pause_limit,
3095         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3096         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3097         .port_link_state = mv88e6352_port_link_state,
3098         .port_get_cmode = mv88e6352_port_get_cmode,
3099         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3100         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3101         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3102         .stats_get_strings = mv88e6095_stats_get_strings,
3103         .stats_get_stats = mv88e6095_stats_get_stats,
3104         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3105         .set_egress_port = mv88e6095_g1_set_egress_port,
3106         .watchdog_ops = &mv88e6097_watchdog_ops,
3107         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3108         .pot_clear = mv88e6xxx_g2_pot_clear,
3109         .reset = mv88e6352_g1_reset,
3110         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3111         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3112         .phylink_validate = mv88e6185_phylink_validate,
3113 };
3114
3115 static const struct mv88e6xxx_ops mv88e6172_ops = {
3116         /* MV88E6XXX_FAMILY_6352 */
3117         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3118         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3119         .irl_init_all = mv88e6352_g2_irl_init_all,
3120         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3121         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3122         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3123         .phy_read = mv88e6xxx_g2_smi_phy_read,
3124         .phy_write = mv88e6xxx_g2_smi_phy_write,
3125         .port_set_link = mv88e6xxx_port_set_link,
3126         .port_set_duplex = mv88e6xxx_port_set_duplex,
3127         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3128         .port_set_speed = mv88e6352_port_set_speed,
3129         .port_tag_remap = mv88e6095_port_tag_remap,
3130         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3131         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3132         .port_set_ether_type = mv88e6351_port_set_ether_type,
3133         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3134         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3135         .port_pause_limit = mv88e6097_port_pause_limit,
3136         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3137         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3138         .port_link_state = mv88e6352_port_link_state,
3139         .port_get_cmode = mv88e6352_port_get_cmode,
3140         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3141         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3142         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3143         .stats_get_strings = mv88e6095_stats_get_strings,
3144         .stats_get_stats = mv88e6095_stats_get_stats,
3145         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3146         .set_egress_port = mv88e6095_g1_set_egress_port,
3147         .watchdog_ops = &mv88e6097_watchdog_ops,
3148         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3149         .pot_clear = mv88e6xxx_g2_pot_clear,
3150         .reset = mv88e6352_g1_reset,
3151         .rmu_disable = mv88e6352_g1_rmu_disable,
3152         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3153         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3154         .serdes_power = mv88e6352_serdes_power,
3155         .gpio_ops = &mv88e6352_gpio_ops,
3156         .phylink_validate = mv88e6352_phylink_validate,
3157 };
3158
3159 static const struct mv88e6xxx_ops mv88e6175_ops = {
3160         /* MV88E6XXX_FAMILY_6351 */
3161         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3162         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3163         .irl_init_all = mv88e6352_g2_irl_init_all,
3164         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3165         .phy_read = mv88e6xxx_g2_smi_phy_read,
3166         .phy_write = mv88e6xxx_g2_smi_phy_write,
3167         .port_set_link = mv88e6xxx_port_set_link,
3168         .port_set_duplex = mv88e6xxx_port_set_duplex,
3169         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3170         .port_set_speed = mv88e6185_port_set_speed,
3171         .port_tag_remap = mv88e6095_port_tag_remap,
3172         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3173         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3174         .port_set_ether_type = mv88e6351_port_set_ether_type,
3175         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3176         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3177         .port_pause_limit = mv88e6097_port_pause_limit,
3178         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3179         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3180         .port_link_state = mv88e6352_port_link_state,
3181         .port_get_cmode = mv88e6352_port_get_cmode,
3182         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3183         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3184         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3185         .stats_get_strings = mv88e6095_stats_get_strings,
3186         .stats_get_stats = mv88e6095_stats_get_stats,
3187         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3188         .set_egress_port = mv88e6095_g1_set_egress_port,
3189         .watchdog_ops = &mv88e6097_watchdog_ops,
3190         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3191         .pot_clear = mv88e6xxx_g2_pot_clear,
3192         .reset = mv88e6352_g1_reset,
3193         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3194         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3195         .phylink_validate = mv88e6185_phylink_validate,
3196 };
3197
3198 static const struct mv88e6xxx_ops mv88e6176_ops = {
3199         /* MV88E6XXX_FAMILY_6352 */
3200         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3201         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3202         .irl_init_all = mv88e6352_g2_irl_init_all,
3203         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3204         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3205         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3206         .phy_read = mv88e6xxx_g2_smi_phy_read,
3207         .phy_write = mv88e6xxx_g2_smi_phy_write,
3208         .port_set_link = mv88e6xxx_port_set_link,
3209         .port_set_duplex = mv88e6xxx_port_set_duplex,
3210         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3211         .port_set_speed = mv88e6352_port_set_speed,
3212         .port_tag_remap = mv88e6095_port_tag_remap,
3213         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3214         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3215         .port_set_ether_type = mv88e6351_port_set_ether_type,
3216         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3217         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3218         .port_pause_limit = mv88e6097_port_pause_limit,
3219         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3220         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3221         .port_link_state = mv88e6352_port_link_state,
3222         .port_get_cmode = mv88e6352_port_get_cmode,
3223         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3224         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3225         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3226         .stats_get_strings = mv88e6095_stats_get_strings,
3227         .stats_get_stats = mv88e6095_stats_get_stats,
3228         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3229         .set_egress_port = mv88e6095_g1_set_egress_port,
3230         .watchdog_ops = &mv88e6097_watchdog_ops,
3231         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3232         .pot_clear = mv88e6xxx_g2_pot_clear,
3233         .reset = mv88e6352_g1_reset,
3234         .rmu_disable = mv88e6352_g1_rmu_disable,
3235         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3236         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3237         .serdes_power = mv88e6352_serdes_power,
3238         .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3239         .serdes_irq_free = mv88e6352_serdes_irq_free,
3240         .gpio_ops = &mv88e6352_gpio_ops,
3241         .phylink_validate = mv88e6352_phylink_validate,
3242 };
3243
3244 static const struct mv88e6xxx_ops mv88e6185_ops = {
3245         /* MV88E6XXX_FAMILY_6185 */
3246         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3247         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3248         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3249         .phy_read = mv88e6185_phy_ppu_read,
3250         .phy_write = mv88e6185_phy_ppu_write,
3251         .port_set_link = mv88e6xxx_port_set_link,
3252         .port_set_duplex = mv88e6xxx_port_set_duplex,
3253         .port_set_speed = mv88e6185_port_set_speed,
3254         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3255         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3256         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3257         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3258         .port_set_pause = mv88e6185_port_set_pause,
3259         .port_link_state = mv88e6185_port_link_state,
3260         .port_get_cmode = mv88e6185_port_get_cmode,
3261         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3262         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3263         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3264         .stats_get_strings = mv88e6095_stats_get_strings,
3265         .stats_get_stats = mv88e6095_stats_get_stats,
3266         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3267         .set_egress_port = mv88e6095_g1_set_egress_port,
3268         .watchdog_ops = &mv88e6097_watchdog_ops,
3269         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3270         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3271         .ppu_enable = mv88e6185_g1_ppu_enable,
3272         .ppu_disable = mv88e6185_g1_ppu_disable,
3273         .reset = mv88e6185_g1_reset,
3274         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3275         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3276         .phylink_validate = mv88e6185_phylink_validate,
3277 };
3278
3279 static const struct mv88e6xxx_ops mv88e6190_ops = {
3280         /* MV88E6XXX_FAMILY_6390 */
3281         .setup_errata = mv88e6390_setup_errata,
3282         .irl_init_all = mv88e6390_g2_irl_init_all,
3283         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3284         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3285         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3286         .phy_read = mv88e6xxx_g2_smi_phy_read,
3287         .phy_write = mv88e6xxx_g2_smi_phy_write,
3288         .port_set_link = mv88e6xxx_port_set_link,
3289         .port_set_duplex = mv88e6xxx_port_set_duplex,
3290         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3291         .port_set_speed = mv88e6390_port_set_speed,
3292         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3293         .port_tag_remap = mv88e6390_port_tag_remap,
3294         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3295         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3296         .port_set_ether_type = mv88e6351_port_set_ether_type,
3297         .port_pause_limit = mv88e6390_port_pause_limit,
3298         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3299         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3300         .port_link_state = mv88e6352_port_link_state,
3301         .port_get_cmode = mv88e6352_port_get_cmode,
3302         .port_set_cmode = mv88e6390_port_set_cmode,
3303         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3304         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3305         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3306         .stats_get_strings = mv88e6320_stats_get_strings,
3307         .stats_get_stats = mv88e6390_stats_get_stats,
3308         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3309         .set_egress_port = mv88e6390_g1_set_egress_port,
3310         .watchdog_ops = &mv88e6390_watchdog_ops,
3311         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3312         .pot_clear = mv88e6xxx_g2_pot_clear,
3313         .reset = mv88e6352_g1_reset,
3314         .rmu_disable = mv88e6390_g1_rmu_disable,
3315         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3316         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3317         .serdes_power = mv88e6390_serdes_power,
3318         .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3319         .serdes_irq_free = mv88e6390_serdes_irq_free,
3320         .gpio_ops = &mv88e6352_gpio_ops,
3321         .phylink_validate = mv88e6390_phylink_validate,
3322 };
3323
3324 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3325         /* MV88E6XXX_FAMILY_6390 */
3326         .setup_errata = mv88e6390_setup_errata,
3327         .irl_init_all = mv88e6390_g2_irl_init_all,
3328         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3329         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3330         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3331         .phy_read = mv88e6xxx_g2_smi_phy_read,
3332         .phy_write = mv88e6xxx_g2_smi_phy_write,
3333         .port_set_link = mv88e6xxx_port_set_link,
3334         .port_set_duplex = mv88e6xxx_port_set_duplex,
3335         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3336         .port_set_speed = mv88e6390x_port_set_speed,
3337         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3338         .port_tag_remap = mv88e6390_port_tag_remap,
3339         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3340         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3341         .port_set_ether_type = mv88e6351_port_set_ether_type,
3342         .port_pause_limit = mv88e6390_port_pause_limit,
3343         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3344         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3345         .port_link_state = mv88e6352_port_link_state,
3346         .port_get_cmode = mv88e6352_port_get_cmode,
3347         .port_set_cmode = mv88e6390x_port_set_cmode,
3348         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3349         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3350         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3351         .stats_get_strings = mv88e6320_stats_get_strings,
3352         .stats_get_stats = mv88e6390_stats_get_stats,
3353         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3354         .set_egress_port = mv88e6390_g1_set_egress_port,
3355         .watchdog_ops = &mv88e6390_watchdog_ops,
3356         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3357         .pot_clear = mv88e6xxx_g2_pot_clear,
3358         .reset = mv88e6352_g1_reset,
3359         .rmu_disable = mv88e6390_g1_rmu_disable,
3360         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3361         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3362         .serdes_power = mv88e6390x_serdes_power,
3363         .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3364         .serdes_irq_free = mv88e6390x_serdes_irq_free,
3365         .gpio_ops = &mv88e6352_gpio_ops,
3366         .phylink_validate = mv88e6390x_phylink_validate,
3367 };
3368
3369 static const struct mv88e6xxx_ops mv88e6191_ops = {
3370         /* MV88E6XXX_FAMILY_6390 */
3371         .setup_errata = mv88e6390_setup_errata,
3372         .irl_init_all = mv88e6390_g2_irl_init_all,
3373         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3374         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3375         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3376         .phy_read = mv88e6xxx_g2_smi_phy_read,
3377         .phy_write = mv88e6xxx_g2_smi_phy_write,
3378         .port_set_link = mv88e6xxx_port_set_link,
3379         .port_set_duplex = mv88e6xxx_port_set_duplex,
3380         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3381         .port_set_speed = mv88e6390_port_set_speed,
3382         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3383         .port_tag_remap = mv88e6390_port_tag_remap,
3384         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3385         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3386         .port_set_ether_type = mv88e6351_port_set_ether_type,
3387         .port_pause_limit = mv88e6390_port_pause_limit,
3388         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3389         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3390         .port_link_state = mv88e6352_port_link_state,
3391         .port_get_cmode = mv88e6352_port_get_cmode,
3392         .port_set_cmode = mv88e6390_port_set_cmode,
3393         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3394         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3395         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3396         .stats_get_strings = mv88e6320_stats_get_strings,
3397         .stats_get_stats = mv88e6390_stats_get_stats,
3398         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3399         .set_egress_port = mv88e6390_g1_set_egress_port,
3400         .watchdog_ops = &mv88e6390_watchdog_ops,
3401         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3402         .pot_clear = mv88e6xxx_g2_pot_clear,
3403         .reset = mv88e6352_g1_reset,
3404         .rmu_disable = mv88e6390_g1_rmu_disable,
3405         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3406         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3407         .serdes_power = mv88e6390_serdes_power,
3408         .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3409         .serdes_irq_free = mv88e6390_serdes_irq_free,
3410         .avb_ops = &mv88e6390_avb_ops,
3411         .ptp_ops = &mv88e6352_ptp_ops,
3412         .phylink_validate = mv88e6390_phylink_validate,
3413 };
3414
3415 static const struct mv88e6xxx_ops mv88e6240_ops = {
3416         /* MV88E6XXX_FAMILY_6352 */
3417         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3418         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3419         .irl_init_all = mv88e6352_g2_irl_init_all,
3420         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3421         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3422         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3423         .phy_read = mv88e6xxx_g2_smi_phy_read,
3424         .phy_write = mv88e6xxx_g2_smi_phy_write,
3425         .port_set_link = mv88e6xxx_port_set_link,
3426         .port_set_duplex = mv88e6xxx_port_set_duplex,
3427         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3428         .port_set_speed = mv88e6352_port_set_speed,
3429         .port_tag_remap = mv88e6095_port_tag_remap,
3430         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3431         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3432         .port_set_ether_type = mv88e6351_port_set_ether_type,
3433         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3434         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3435         .port_pause_limit = mv88e6097_port_pause_limit,
3436         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3437         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3438         .port_link_state = mv88e6352_port_link_state,
3439         .port_get_cmode = mv88e6352_port_get_cmode,
3440         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3441         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3442         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3443         .stats_get_strings = mv88e6095_stats_get_strings,
3444         .stats_get_stats = mv88e6095_stats_get_stats,
3445         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3446         .set_egress_port = mv88e6095_g1_set_egress_port,
3447         .watchdog_ops = &mv88e6097_watchdog_ops,
3448         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3449         .pot_clear = mv88e6xxx_g2_pot_clear,
3450         .reset = mv88e6352_g1_reset,
3451         .rmu_disable = mv88e6352_g1_rmu_disable,
3452         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3453         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3454         .serdes_power = mv88e6352_serdes_power,
3455         .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3456         .serdes_irq_free = mv88e6352_serdes_irq_free,
3457         .gpio_ops = &mv88e6352_gpio_ops,
3458         .avb_ops = &mv88e6352_avb_ops,
3459         .ptp_ops = &mv88e6352_ptp_ops,
3460         .phylink_validate = mv88e6352_phylink_validate,
3461 };
3462
3463 static const struct mv88e6xxx_ops mv88e6250_ops = {
3464         /* MV88E6XXX_FAMILY_6250 */
3465         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
3466         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3467         .irl_init_all = mv88e6352_g2_irl_init_all,
3468         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3469         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3470         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3471         .phy_read = mv88e6xxx_g2_smi_phy_read,
3472         .phy_write = mv88e6xxx_g2_smi_phy_write,
3473         .port_set_link = mv88e6xxx_port_set_link,
3474         .port_set_duplex = mv88e6xxx_port_set_duplex,
3475         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3476         .port_set_speed = mv88e6250_port_set_speed,
3477         .port_tag_remap = mv88e6095_port_tag_remap,
3478         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3479         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3480         .port_set_ether_type = mv88e6351_port_set_ether_type,
3481         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3482         .port_pause_limit = mv88e6097_port_pause_limit,
3483         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3484         .port_link_state = mv88e6250_port_link_state,
3485         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3486         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3487         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
3488         .stats_get_strings = mv88e6250_stats_get_strings,
3489         .stats_get_stats = mv88e6250_stats_get_stats,
3490         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3491         .set_egress_port = mv88e6095_g1_set_egress_port,
3492         .watchdog_ops = &mv88e6250_watchdog_ops,
3493         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3494         .pot_clear = mv88e6xxx_g2_pot_clear,
3495         .reset = mv88e6250_g1_reset,
3496         .vtu_getnext = mv88e6250_g1_vtu_getnext,
3497         .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
3498         .phylink_validate = mv88e6065_phylink_validate,
3499 };
3500
3501 static const struct mv88e6xxx_ops mv88e6290_ops = {
3502         /* MV88E6XXX_FAMILY_6390 */
3503         .setup_errata = mv88e6390_setup_errata,
3504         .irl_init_all = mv88e6390_g2_irl_init_all,
3505         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3506         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3507         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3508         .phy_read = mv88e6xxx_g2_smi_phy_read,
3509         .phy_write = mv88e6xxx_g2_smi_phy_write,
3510         .port_set_link = mv88e6xxx_port_set_link,
3511         .port_set_duplex = mv88e6xxx_port_set_duplex,
3512         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3513         .port_set_speed = mv88e6390_port_set_speed,
3514         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3515         .port_tag_remap = mv88e6390_port_tag_remap,
3516         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3517         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3518         .port_set_ether_type = mv88e6351_port_set_ether_type,
3519         .port_pause_limit = mv88e6390_port_pause_limit,
3520         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3521         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3522         .port_link_state = mv88e6352_port_link_state,
3523         .port_get_cmode = mv88e6352_port_get_cmode,
3524         .port_set_cmode = mv88e6390_port_set_cmode,
3525         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3526         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3527         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3528         .stats_get_strings = mv88e6320_stats_get_strings,
3529         .stats_get_stats = mv88e6390_stats_get_stats,
3530         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3531         .set_egress_port = mv88e6390_g1_set_egress_port,
3532         .watchdog_ops = &mv88e6390_watchdog_ops,
3533         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3534         .pot_clear = mv88e6xxx_g2_pot_clear,
3535         .reset = mv88e6352_g1_reset,
3536         .rmu_disable = mv88e6390_g1_rmu_disable,
3537         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3538         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3539         .serdes_power = mv88e6390_serdes_power,
3540         .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3541         .serdes_irq_free = mv88e6390_serdes_irq_free,
3542         .gpio_ops = &mv88e6352_gpio_ops,
3543         .avb_ops = &mv88e6390_avb_ops,
3544         .ptp_ops = &mv88e6352_ptp_ops,
3545         .phylink_validate = mv88e6390_phylink_validate,
3546 };
3547
3548 static const struct mv88e6xxx_ops mv88e6320_ops = {
3549         /* MV88E6XXX_FAMILY_6320 */
3550         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3551         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3552         .irl_init_all = mv88e6352_g2_irl_init_all,
3553         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3554         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3555         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3556         .phy_read = mv88e6xxx_g2_smi_phy_read,
3557         .phy_write = mv88e6xxx_g2_smi_phy_write,
3558         .port_set_link = mv88e6xxx_port_set_link,
3559         .port_set_duplex = mv88e6xxx_port_set_duplex,
3560         .port_set_speed = mv88e6185_port_set_speed,
3561         .port_tag_remap = mv88e6095_port_tag_remap,
3562         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3563         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3564         .port_set_ether_type = mv88e6351_port_set_ether_type,
3565         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3566         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3567         .port_pause_limit = mv88e6097_port_pause_limit,
3568         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3569         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3570         .port_link_state = mv88e6352_port_link_state,
3571         .port_get_cmode = mv88e6352_port_get_cmode,
3572         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3573         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3574         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3575         .stats_get_strings = mv88e6320_stats_get_strings,
3576         .stats_get_stats = mv88e6320_stats_get_stats,
3577         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3578         .set_egress_port = mv88e6095_g1_set_egress_port,
3579         .watchdog_ops = &mv88e6390_watchdog_ops,
3580         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3581         .pot_clear = mv88e6xxx_g2_pot_clear,
3582         .reset = mv88e6352_g1_reset,
3583         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3584         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3585         .gpio_ops = &mv88e6352_gpio_ops,
3586         .avb_ops = &mv88e6352_avb_ops,
3587         .ptp_ops = &mv88e6352_ptp_ops,
3588         .phylink_validate = mv88e6185_phylink_validate,
3589 };
3590
3591 static const struct mv88e6xxx_ops mv88e6321_ops = {
3592         /* MV88E6XXX_FAMILY_6320 */
3593         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3594         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3595         .irl_init_all = mv88e6352_g2_irl_init_all,
3596         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3597         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3598         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3599         .phy_read = mv88e6xxx_g2_smi_phy_read,
3600         .phy_write = mv88e6xxx_g2_smi_phy_write,
3601         .port_set_link = mv88e6xxx_port_set_link,
3602         .port_set_duplex = mv88e6xxx_port_set_duplex,
3603         .port_set_speed = mv88e6185_port_set_speed,
3604         .port_tag_remap = mv88e6095_port_tag_remap,
3605         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3606         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3607         .port_set_ether_type = mv88e6351_port_set_ether_type,
3608         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3609         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3610         .port_pause_limit = mv88e6097_port_pause_limit,
3611         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3612         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3613         .port_link_state = mv88e6352_port_link_state,
3614         .port_get_cmode = mv88e6352_port_get_cmode,
3615         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3616         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3617         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3618         .stats_get_strings = mv88e6320_stats_get_strings,
3619         .stats_get_stats = mv88e6320_stats_get_stats,
3620         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3621         .set_egress_port = mv88e6095_g1_set_egress_port,
3622         .watchdog_ops = &mv88e6390_watchdog_ops,
3623         .reset = mv88e6352_g1_reset,
3624         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3625         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3626         .gpio_ops = &mv88e6352_gpio_ops,
3627         .avb_ops = &mv88e6352_avb_ops,
3628         .ptp_ops = &mv88e6352_ptp_ops,
3629         .phylink_validate = mv88e6185_phylink_validate,
3630 };
3631
3632 static const struct mv88e6xxx_ops mv88e6341_ops = {
3633         /* MV88E6XXX_FAMILY_6341 */
3634         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3635         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3636         .irl_init_all = mv88e6352_g2_irl_init_all,
3637         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3638         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3639         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3640         .phy_read = mv88e6xxx_g2_smi_phy_read,
3641         .phy_write = mv88e6xxx_g2_smi_phy_write,
3642         .port_set_link = mv88e6xxx_port_set_link,
3643         .port_set_duplex = mv88e6xxx_port_set_duplex,
3644         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3645         .port_set_speed = mv88e6341_port_set_speed,
3646         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3647         .port_tag_remap = mv88e6095_port_tag_remap,
3648         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3649         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3650         .port_set_ether_type = mv88e6351_port_set_ether_type,
3651         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3652         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3653         .port_pause_limit = mv88e6097_port_pause_limit,
3654         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3655         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3656         .port_link_state = mv88e6352_port_link_state,
3657         .port_get_cmode = mv88e6352_port_get_cmode,
3658         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3659         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3660         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3661         .stats_get_strings = mv88e6320_stats_get_strings,
3662         .stats_get_stats = mv88e6390_stats_get_stats,
3663         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3664         .set_egress_port = mv88e6390_g1_set_egress_port,
3665         .watchdog_ops = &mv88e6390_watchdog_ops,
3666         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3667         .pot_clear = mv88e6xxx_g2_pot_clear,
3668         .reset = mv88e6352_g1_reset,
3669         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3670         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3671         .serdes_power = mv88e6341_serdes_power,
3672         .gpio_ops = &mv88e6352_gpio_ops,
3673         .avb_ops = &mv88e6390_avb_ops,
3674         .ptp_ops = &mv88e6352_ptp_ops,
3675         .phylink_validate = mv88e6341_phylink_validate,
3676 };
3677
3678 static const struct mv88e6xxx_ops mv88e6350_ops = {
3679         /* MV88E6XXX_FAMILY_6351 */
3680         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3681         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3682         .irl_init_all = mv88e6352_g2_irl_init_all,
3683         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3684         .phy_read = mv88e6xxx_g2_smi_phy_read,
3685         .phy_write = mv88e6xxx_g2_smi_phy_write,
3686         .port_set_link = mv88e6xxx_port_set_link,
3687         .port_set_duplex = mv88e6xxx_port_set_duplex,
3688         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3689         .port_set_speed = mv88e6185_port_set_speed,
3690         .port_tag_remap = mv88e6095_port_tag_remap,
3691         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3692         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3693         .port_set_ether_type = mv88e6351_port_set_ether_type,
3694         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3695         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3696         .port_pause_limit = mv88e6097_port_pause_limit,
3697         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3698         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3699         .port_link_state = mv88e6352_port_link_state,
3700         .port_get_cmode = mv88e6352_port_get_cmode,
3701         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3702         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3703         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3704         .stats_get_strings = mv88e6095_stats_get_strings,
3705         .stats_get_stats = mv88e6095_stats_get_stats,
3706         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3707         .set_egress_port = mv88e6095_g1_set_egress_port,
3708         .watchdog_ops = &mv88e6097_watchdog_ops,
3709         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3710         .pot_clear = mv88e6xxx_g2_pot_clear,
3711         .reset = mv88e6352_g1_reset,
3712         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3713         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3714         .phylink_validate = mv88e6185_phylink_validate,
3715 };
3716
3717 static const struct mv88e6xxx_ops mv88e6351_ops = {
3718         /* MV88E6XXX_FAMILY_6351 */
3719         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3720         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3721         .irl_init_all = mv88e6352_g2_irl_init_all,
3722         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3723         .phy_read = mv88e6xxx_g2_smi_phy_read,
3724         .phy_write = mv88e6xxx_g2_smi_phy_write,
3725         .port_set_link = mv88e6xxx_port_set_link,
3726         .port_set_duplex = mv88e6xxx_port_set_duplex,
3727         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3728         .port_set_speed = mv88e6185_port_set_speed,
3729         .port_tag_remap = mv88e6095_port_tag_remap,
3730         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3731         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3732         .port_set_ether_type = mv88e6351_port_set_ether_type,
3733         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3734         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3735         .port_pause_limit = mv88e6097_port_pause_limit,
3736         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3737         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3738         .port_link_state = mv88e6352_port_link_state,
3739         .port_get_cmode = mv88e6352_port_get_cmode,
3740         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3741         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3742         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3743         .stats_get_strings = mv88e6095_stats_get_strings,
3744         .stats_get_stats = mv88e6095_stats_get_stats,
3745         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3746         .set_egress_port = mv88e6095_g1_set_egress_port,
3747         .watchdog_ops = &mv88e6097_watchdog_ops,
3748         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3749         .pot_clear = mv88e6xxx_g2_pot_clear,
3750         .reset = mv88e6352_g1_reset,
3751         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3752         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3753         .avb_ops = &mv88e6352_avb_ops,
3754         .ptp_ops = &mv88e6352_ptp_ops,
3755         .phylink_validate = mv88e6185_phylink_validate,
3756 };
3757
3758 static const struct mv88e6xxx_ops mv88e6352_ops = {
3759         /* MV88E6XXX_FAMILY_6352 */
3760         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3761         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3762         .irl_init_all = mv88e6352_g2_irl_init_all,
3763         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3764         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3765         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3766         .phy_read = mv88e6xxx_g2_smi_phy_read,
3767         .phy_write = mv88e6xxx_g2_smi_phy_write,
3768         .port_set_link = mv88e6xxx_port_set_link,
3769         .port_set_duplex = mv88e6xxx_port_set_duplex,
3770         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3771         .port_set_speed = mv88e6352_port_set_speed,
3772         .port_tag_remap = mv88e6095_port_tag_remap,
3773         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3774         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3775         .port_set_ether_type = mv88e6351_port_set_ether_type,
3776         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3777         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3778         .port_pause_limit = mv88e6097_port_pause_limit,
3779         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3780         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3781         .port_link_state = mv88e6352_port_link_state,
3782         .port_get_cmode = mv88e6352_port_get_cmode,
3783         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3784         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3785         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3786         .stats_get_strings = mv88e6095_stats_get_strings,
3787         .stats_get_stats = mv88e6095_stats_get_stats,
3788         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3789         .set_egress_port = mv88e6095_g1_set_egress_port,
3790         .watchdog_ops = &mv88e6097_watchdog_ops,
3791         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3792         .pot_clear = mv88e6xxx_g2_pot_clear,
3793         .reset = mv88e6352_g1_reset,
3794         .rmu_disable = mv88e6352_g1_rmu_disable,
3795         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3796         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3797         .serdes_power = mv88e6352_serdes_power,
3798         .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3799         .serdes_irq_free = mv88e6352_serdes_irq_free,
3800         .gpio_ops = &mv88e6352_gpio_ops,
3801         .avb_ops = &mv88e6352_avb_ops,
3802         .ptp_ops = &mv88e6352_ptp_ops,
3803         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3804         .serdes_get_strings = mv88e6352_serdes_get_strings,
3805         .serdes_get_stats = mv88e6352_serdes_get_stats,
3806         .phylink_validate = mv88e6352_phylink_validate,
3807 };
3808
3809 static const struct mv88e6xxx_ops mv88e6390_ops = {
3810         /* MV88E6XXX_FAMILY_6390 */
3811         .setup_errata = mv88e6390_setup_errata,
3812         .irl_init_all = mv88e6390_g2_irl_init_all,
3813         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3814         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3815         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3816         .phy_read = mv88e6xxx_g2_smi_phy_read,
3817         .phy_write = mv88e6xxx_g2_smi_phy_write,
3818         .port_set_link = mv88e6xxx_port_set_link,
3819         .port_set_duplex = mv88e6xxx_port_set_duplex,
3820         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3821         .port_set_speed = mv88e6390_port_set_speed,
3822         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3823         .port_tag_remap = mv88e6390_port_tag_remap,
3824         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3825         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3826         .port_set_ether_type = mv88e6351_port_set_ether_type,
3827         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3828         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3829         .port_pause_limit = mv88e6390_port_pause_limit,
3830         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3831         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3832         .port_link_state = mv88e6352_port_link_state,
3833         .port_get_cmode = mv88e6352_port_get_cmode,
3834         .port_set_cmode = mv88e6390_port_set_cmode,
3835         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3836         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3837         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3838         .stats_get_strings = mv88e6320_stats_get_strings,
3839         .stats_get_stats = mv88e6390_stats_get_stats,
3840         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3841         .set_egress_port = mv88e6390_g1_set_egress_port,
3842         .watchdog_ops = &mv88e6390_watchdog_ops,
3843         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3844         .pot_clear = mv88e6xxx_g2_pot_clear,
3845         .reset = mv88e6352_g1_reset,
3846         .rmu_disable = mv88e6390_g1_rmu_disable,
3847         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3848         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3849         .serdes_power = mv88e6390_serdes_power,
3850         .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3851         .serdes_irq_free = mv88e6390_serdes_irq_free,
3852         .gpio_ops = &mv88e6352_gpio_ops,
3853         .avb_ops = &mv88e6390_avb_ops,
3854         .ptp_ops = &mv88e6352_ptp_ops,
3855         .phylink_validate = mv88e6390_phylink_validate,
3856 };
3857
3858 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3859         /* MV88E6XXX_FAMILY_6390 */
3860         .setup_errata = mv88e6390_setup_errata,
3861         .irl_init_all = mv88e6390_g2_irl_init_all,
3862         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3863         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3864         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3865         .phy_read = mv88e6xxx_g2_smi_phy_read,
3866         .phy_write = mv88e6xxx_g2_smi_phy_write,
3867         .port_set_link = mv88e6xxx_port_set_link,
3868         .port_set_duplex = mv88e6xxx_port_set_duplex,
3869         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3870         .port_set_speed = mv88e6390x_port_set_speed,
3871         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3872         .port_tag_remap = mv88e6390_port_tag_remap,
3873         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3874         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3875         .port_set_ether_type = mv88e6351_port_set_ether_type,
3876         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3877         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3878         .port_pause_limit = mv88e6390_port_pause_limit,
3879         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3880         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3881         .port_link_state = mv88e6352_port_link_state,
3882         .port_get_cmode = mv88e6352_port_get_cmode,
3883         .port_set_cmode = mv88e6390x_port_set_cmode,
3884         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3885         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3886         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3887         .stats_get_strings = mv88e6320_stats_get_strings,
3888         .stats_get_stats = mv88e6390_stats_get_stats,
3889         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3890         .set_egress_port = mv88e6390_g1_set_egress_port,
3891         .watchdog_ops = &mv88e6390_watchdog_ops,
3892         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3893         .pot_clear = mv88e6xxx_g2_pot_clear,
3894         .reset = mv88e6352_g1_reset,
3895         .rmu_disable = mv88e6390_g1_rmu_disable,
3896         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3897         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3898         .serdes_power = mv88e6390x_serdes_power,
3899         .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3900         .serdes_irq_free = mv88e6390x_serdes_irq_free,
3901         .gpio_ops = &mv88e6352_gpio_ops,
3902         .avb_ops = &mv88e6390_avb_ops,
3903         .ptp_ops = &mv88e6352_ptp_ops,
3904         .phylink_validate = mv88e6390x_phylink_validate,
3905 };
3906
3907 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3908         [MV88E6085] = {
3909                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3910                 .family = MV88E6XXX_FAMILY_6097,
3911                 .name = "Marvell 88E6085",
3912                 .num_databases = 4096,
3913                 .num_ports = 10,
3914                 .num_internal_phys = 5,
3915                 .max_vid = 4095,
3916                 .port_base_addr = 0x10,
3917                 .phy_base_addr = 0x0,
3918                 .global1_addr = 0x1b,
3919                 .global2_addr = 0x1c,
3920                 .age_time_coeff = 15000,
3921                 .g1_irqs = 8,
3922                 .g2_irqs = 10,
3923                 .atu_move_port_mask = 0xf,
3924                 .pvt = true,
3925                 .multi_chip = true,
3926                 .tag_protocol = DSA_TAG_PROTO_DSA,
3927                 .ops = &mv88e6085_ops,
3928         },
3929
3930         [MV88E6095] = {
3931                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3932                 .family = MV88E6XXX_FAMILY_6095,
3933                 .name = "Marvell 88E6095/88E6095F",
3934                 .num_databases = 256,
3935                 .num_ports = 11,
3936                 .num_internal_phys = 0,
3937                 .max_vid = 4095,
3938                 .port_base_addr = 0x10,
3939                 .phy_base_addr = 0x0,
3940                 .global1_addr = 0x1b,
3941                 .global2_addr = 0x1c,
3942                 .age_time_coeff = 15000,
3943                 .g1_irqs = 8,
3944                 .atu_move_port_mask = 0xf,
3945                 .multi_chip = true,
3946                 .tag_protocol = DSA_TAG_PROTO_DSA,
3947                 .ops = &mv88e6095_ops,
3948         },
3949
3950         [MV88E6097] = {
3951                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3952                 .family = MV88E6XXX_FAMILY_6097,
3953                 .name = "Marvell 88E6097/88E6097F",
3954                 .num_databases = 4096,
3955                 .num_ports = 11,
3956                 .num_internal_phys = 8,
3957                 .max_vid = 4095,
3958                 .port_base_addr = 0x10,
3959                 .phy_base_addr = 0x0,
3960                 .global1_addr = 0x1b,
3961                 .global2_addr = 0x1c,
3962                 .age_time_coeff = 15000,
3963                 .g1_irqs = 8,
3964                 .g2_irqs = 10,
3965                 .atu_move_port_mask = 0xf,
3966                 .pvt = true,
3967                 .multi_chip = true,
3968                 .tag_protocol = DSA_TAG_PROTO_EDSA,
3969                 .ops = &mv88e6097_ops,
3970         },
3971
3972         [MV88E6123] = {
3973                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3974                 .family = MV88E6XXX_FAMILY_6165,
3975                 .name = "Marvell 88E6123",
3976                 .num_databases = 4096,
3977                 .num_ports = 3,
3978                 .num_internal_phys = 5,
3979                 .max_vid = 4095,
3980                 .port_base_addr = 0x10,
3981                 .phy_base_addr = 0x0,
3982                 .global1_addr = 0x1b,
3983                 .global2_addr = 0x1c,
3984                 .age_time_coeff = 15000,
3985                 .g1_irqs = 9,
3986                 .g2_irqs = 10,
3987                 .atu_move_port_mask = 0xf,
3988                 .pvt = true,
3989                 .multi_chip = true,
3990                 .tag_protocol = DSA_TAG_PROTO_EDSA,
3991                 .ops = &mv88e6123_ops,
3992         },
3993
3994         [MV88E6131] = {
3995                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3996                 .family = MV88E6XXX_FAMILY_6185,
3997                 .name = "Marvell 88E6131",
3998                 .num_databases = 256,
3999                 .num_ports = 8,
4000                 .num_internal_phys = 0,
4001                 .max_vid = 4095,
4002                 .port_base_addr = 0x10,
4003                 .phy_base_addr = 0x0,
4004                 .global1_addr = 0x1b,
4005                 .global2_addr = 0x1c,
4006                 .age_time_coeff = 15000,
4007                 .g1_irqs = 9,
4008                 .atu_move_port_mask = 0xf,
4009                 .multi_chip = true,
4010                 .tag_protocol = DSA_TAG_PROTO_DSA,
4011                 .ops = &mv88e6131_ops,
4012         },
4013
4014         [MV88E6141] = {
4015                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4016                 .family = MV88E6XXX_FAMILY_6341,
4017                 .name = "Marvell 88E6141",
4018                 .num_databases = 4096,
4019                 .num_ports = 6,
4020                 .num_internal_phys = 5,
4021                 .num_gpio = 11,
4022                 .max_vid = 4095,
4023                 .port_base_addr = 0x10,
4024                 .phy_base_addr = 0x10,
4025                 .global1_addr = 0x1b,
4026                 .global2_addr = 0x1c,
4027                 .age_time_coeff = 3750,
4028                 .atu_move_port_mask = 0x1f,
4029                 .g1_irqs = 9,
4030                 .g2_irqs = 10,
4031                 .pvt = true,
4032                 .multi_chip = true,
4033                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4034                 .ops = &mv88e6141_ops,
4035         },
4036
4037         [MV88E6161] = {
4038                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4039                 .family = MV88E6XXX_FAMILY_6165,
4040                 .name = "Marvell 88E6161",
4041                 .num_databases = 4096,
4042                 .num_ports = 6,
4043                 .num_internal_phys = 5,
4044                 .max_vid = 4095,
4045                 .port_base_addr = 0x10,
4046                 .phy_base_addr = 0x0,
4047                 .global1_addr = 0x1b,
4048                 .global2_addr = 0x1c,
4049                 .age_time_coeff = 15000,
4050                 .g1_irqs = 9,
4051                 .g2_irqs = 10,
4052                 .atu_move_port_mask = 0xf,
4053                 .pvt = true,
4054                 .multi_chip = true,
4055                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4056                 .ptp_support = true,
4057                 .ops = &mv88e6161_ops,
4058         },
4059
4060         [MV88E6165] = {
4061                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4062                 .family = MV88E6XXX_FAMILY_6165,
4063                 .name = "Marvell 88E6165",
4064                 .num_databases = 4096,
4065                 .num_ports = 6,
4066                 .num_internal_phys = 0,
4067                 .max_vid = 4095,
4068                 .port_base_addr = 0x10,
4069                 .phy_base_addr = 0x0,
4070                 .global1_addr = 0x1b,
4071                 .global2_addr = 0x1c,
4072                 .age_time_coeff = 15000,
4073                 .g1_irqs = 9,
4074                 .g2_irqs = 10,
4075                 .atu_move_port_mask = 0xf,
4076                 .pvt = true,
4077                 .multi_chip = true,
4078                 .tag_protocol = DSA_TAG_PROTO_DSA,
4079                 .ptp_support = true,
4080                 .ops = &mv88e6165_ops,
4081         },
4082
4083         [MV88E6171] = {
4084                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4085                 .family = MV88E6XXX_FAMILY_6351,
4086                 .name = "Marvell 88E6171",
4087                 .num_databases = 4096,
4088                 .num_ports = 7,
4089                 .num_internal_phys = 5,
4090                 .max_vid = 4095,
4091                 .port_base_addr = 0x10,
4092                 .phy_base_addr = 0x0,
4093                 .global1_addr = 0x1b,
4094                 .global2_addr = 0x1c,
4095                 .age_time_coeff = 15000,
4096                 .g1_irqs = 9,
4097                 .g2_irqs = 10,
4098                 .atu_move_port_mask = 0xf,
4099                 .pvt = true,
4100                 .multi_chip = true,
4101                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4102                 .ops = &mv88e6171_ops,
4103         },
4104
4105         [MV88E6172] = {
4106                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4107                 .family = MV88E6XXX_FAMILY_6352,
4108                 .name = "Marvell 88E6172",
4109                 .num_databases = 4096,
4110                 .num_ports = 7,
4111                 .num_internal_phys = 5,
4112                 .num_gpio = 15,
4113                 .max_vid = 4095,
4114                 .port_base_addr = 0x10,
4115                 .phy_base_addr = 0x0,
4116                 .global1_addr = 0x1b,
4117                 .global2_addr = 0x1c,
4118                 .age_time_coeff = 15000,
4119                 .g1_irqs = 9,
4120                 .g2_irqs = 10,
4121                 .atu_move_port_mask = 0xf,
4122                 .pvt = true,
4123                 .multi_chip = true,
4124                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4125                 .ops = &mv88e6172_ops,
4126         },
4127
4128         [MV88E6175] = {
4129                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4130                 .family = MV88E6XXX_FAMILY_6351,
4131                 .name = "Marvell 88E6175",
4132                 .num_databases = 4096,
4133                 .num_ports = 7,
4134                 .num_internal_phys = 5,
4135                 .max_vid = 4095,
4136                 .port_base_addr = 0x10,
4137                 .phy_base_addr = 0x0,
4138                 .global1_addr = 0x1b,
4139                 .global2_addr = 0x1c,
4140                 .age_time_coeff = 15000,
4141                 .g1_irqs = 9,
4142                 .g2_irqs = 10,
4143                 .atu_move_port_mask = 0xf,
4144                 .pvt = true,
4145                 .multi_chip = true,
4146                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4147                 .ops = &mv88e6175_ops,
4148         },
4149
4150         [MV88E6176] = {
4151                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4152                 .family = MV88E6XXX_FAMILY_6352,
4153                 .name = "Marvell 88E6176",
4154                 .num_databases = 4096,
4155                 .num_ports = 7,
4156                 .num_internal_phys = 5,
4157                 .num_gpio = 15,
4158                 .max_vid = 4095,
4159                 .port_base_addr = 0x10,
4160                 .phy_base_addr = 0x0,
4161                 .global1_addr = 0x1b,
4162                 .global2_addr = 0x1c,
4163                 .age_time_coeff = 15000,
4164                 .g1_irqs = 9,
4165                 .g2_irqs = 10,
4166                 .atu_move_port_mask = 0xf,
4167                 .pvt = true,
4168                 .multi_chip = true,
4169                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4170                 .ops = &mv88e6176_ops,
4171         },
4172
4173         [MV88E6185] = {
4174                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4175                 .family = MV88E6XXX_FAMILY_6185,
4176                 .name = "Marvell 88E6185",
4177                 .num_databases = 256,
4178                 .num_ports = 10,
4179                 .num_internal_phys = 0,
4180                 .max_vid = 4095,
4181                 .port_base_addr = 0x10,
4182                 .phy_base_addr = 0x0,
4183                 .global1_addr = 0x1b,
4184                 .global2_addr = 0x1c,
4185                 .age_time_coeff = 15000,
4186                 .g1_irqs = 8,
4187                 .atu_move_port_mask = 0xf,
4188                 .multi_chip = true,
4189                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4190                 .ops = &mv88e6185_ops,
4191         },
4192
4193         [MV88E6190] = {
4194                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4195                 .family = MV88E6XXX_FAMILY_6390,
4196                 .name = "Marvell 88E6190",
4197                 .num_databases = 4096,
4198                 .num_ports = 11,        /* 10 + Z80 */
4199                 .num_internal_phys = 9,
4200                 .num_gpio = 16,
4201                 .max_vid = 8191,
4202                 .port_base_addr = 0x0,
4203                 .phy_base_addr = 0x0,
4204                 .global1_addr = 0x1b,
4205                 .global2_addr = 0x1c,
4206                 .tag_protocol = DSA_TAG_PROTO_DSA,
4207                 .age_time_coeff = 3750,
4208                 .g1_irqs = 9,
4209                 .g2_irqs = 14,
4210                 .pvt = true,
4211                 .multi_chip = true,
4212                 .atu_move_port_mask = 0x1f,
4213                 .ops = &mv88e6190_ops,
4214         },
4215
4216         [MV88E6190X] = {
4217                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4218                 .family = MV88E6XXX_FAMILY_6390,
4219                 .name = "Marvell 88E6190X",
4220                 .num_databases = 4096,
4221                 .num_ports = 11,        /* 10 + Z80 */
4222                 .num_internal_phys = 9,
4223                 .num_gpio = 16,
4224                 .max_vid = 8191,
4225                 .port_base_addr = 0x0,
4226                 .phy_base_addr = 0x0,
4227                 .global1_addr = 0x1b,
4228                 .global2_addr = 0x1c,
4229                 .age_time_coeff = 3750,
4230                 .g1_irqs = 9,
4231                 .g2_irqs = 14,
4232                 .atu_move_port_mask = 0x1f,
4233                 .pvt = true,
4234                 .multi_chip = true,
4235                 .tag_protocol = DSA_TAG_PROTO_DSA,
4236                 .ops = &mv88e6190x_ops,
4237         },
4238
4239         [MV88E6191] = {
4240                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4241                 .family = MV88E6XXX_FAMILY_6390,
4242                 .name = "Marvell 88E6191",
4243                 .num_databases = 4096,
4244                 .num_ports = 11,        /* 10 + Z80 */
4245                 .num_internal_phys = 9,
4246                 .max_vid = 8191,
4247                 .port_base_addr = 0x0,
4248                 .phy_base_addr = 0x0,
4249                 .global1_addr = 0x1b,
4250                 .global2_addr = 0x1c,
4251                 .age_time_coeff = 3750,
4252                 .g1_irqs = 9,
4253                 .g2_irqs = 14,
4254                 .atu_move_port_mask = 0x1f,
4255                 .pvt = true,
4256                 .multi_chip = true,
4257                 .tag_protocol = DSA_TAG_PROTO_DSA,
4258                 .ptp_support = true,
4259                 .ops = &mv88e6191_ops,
4260         },
4261
4262         [MV88E6240] = {
4263                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4264                 .family = MV88E6XXX_FAMILY_6352,
4265                 .name = "Marvell 88E6240",
4266                 .num_databases = 4096,
4267                 .num_ports = 7,
4268                 .num_internal_phys = 5,
4269                 .num_gpio = 15,
4270                 .max_vid = 4095,
4271                 .port_base_addr = 0x10,
4272                 .phy_base_addr = 0x0,
4273                 .global1_addr = 0x1b,
4274                 .global2_addr = 0x1c,
4275                 .age_time_coeff = 15000,
4276                 .g1_irqs = 9,
4277                 .g2_irqs = 10,
4278                 .atu_move_port_mask = 0xf,
4279                 .pvt = true,
4280                 .multi_chip = true,
4281                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4282                 .ptp_support = true,
4283                 .ops = &mv88e6240_ops,
4284         },
4285
4286         [MV88E6250] = {
4287                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4288                 .family = MV88E6XXX_FAMILY_6250,
4289                 .name = "Marvell 88E6250",
4290                 .num_databases = 64,
4291                 .num_ports = 7,
4292                 .num_internal_phys = 5,
4293                 .max_vid = 4095,
4294                 .port_base_addr = 0x08,
4295                 .phy_base_addr = 0x00,
4296                 .global1_addr = 0x0f,
4297                 .global2_addr = 0x07,
4298                 .age_time_coeff = 15000,
4299                 .g1_irqs = 9,
4300                 .g2_irqs = 10,
4301                 .atu_move_port_mask = 0xf,
4302                 .dual_chip = true,
4303                 .tag_protocol = DSA_TAG_PROTO_DSA,
4304                 .ops = &mv88e6250_ops,
4305         },
4306
4307         [MV88E6290] = {
4308                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4309                 .family = MV88E6XXX_FAMILY_6390,
4310                 .name = "Marvell 88E6290",
4311                 .num_databases = 4096,
4312                 .num_ports = 11,        /* 10 + Z80 */
4313                 .num_internal_phys = 9,
4314                 .num_gpio = 16,
4315                 .max_vid = 8191,
4316                 .port_base_addr = 0x0,
4317                 .phy_base_addr = 0x0,
4318                 .global1_addr = 0x1b,
4319                 .global2_addr = 0x1c,
4320                 .age_time_coeff = 3750,
4321                 .g1_irqs = 9,
4322                 .g2_irqs = 14,
4323                 .atu_move_port_mask = 0x1f,
4324                 .pvt = true,
4325                 .multi_chip = true,
4326                 .tag_protocol = DSA_TAG_PROTO_DSA,
4327                 .ptp_support = true,
4328                 .ops = &mv88e6290_ops,
4329         },
4330
4331         [MV88E6320] = {
4332                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4333                 .family = MV88E6XXX_FAMILY_6320,
4334                 .name = "Marvell 88E6320",
4335                 .num_databases = 4096,
4336                 .num_ports = 7,
4337                 .num_internal_phys = 5,
4338                 .num_gpio = 15,
4339                 .max_vid = 4095,
4340                 .port_base_addr = 0x10,
4341                 .phy_base_addr = 0x0,
4342                 .global1_addr = 0x1b,
4343                 .global2_addr = 0x1c,
4344                 .age_time_coeff = 15000,
4345                 .g1_irqs = 8,
4346                 .g2_irqs = 10,
4347                 .atu_move_port_mask = 0xf,
4348                 .pvt = true,
4349                 .multi_chip = true,
4350                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4351                 .ptp_support = true,
4352                 .ops = &mv88e6320_ops,
4353         },
4354
4355         [MV88E6321] = {
4356                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4357                 .family = MV88E6XXX_FAMILY_6320,
4358                 .name = "Marvell 88E6321",
4359                 .num_databases = 4096,
4360                 .num_ports = 7,
4361                 .num_internal_phys = 5,
4362                 .num_gpio = 15,
4363                 .max_vid = 4095,
4364                 .port_base_addr = 0x10,
4365                 .phy_base_addr = 0x0,
4366                 .global1_addr = 0x1b,
4367                 .global2_addr = 0x1c,
4368                 .age_time_coeff = 15000,
4369                 .g1_irqs = 8,
4370                 .g2_irqs = 10,
4371                 .atu_move_port_mask = 0xf,
4372                 .multi_chip = true,
4373                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4374                 .ptp_support = true,
4375                 .ops = &mv88e6321_ops,
4376         },
4377
4378         [MV88E6341] = {
4379                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4380                 .family = MV88E6XXX_FAMILY_6341,
4381                 .name = "Marvell 88E6341",
4382                 .num_databases = 4096,
4383                 .num_internal_phys = 5,
4384                 .num_ports = 6,
4385                 .num_gpio = 11,
4386                 .max_vid = 4095,
4387                 .port_base_addr = 0x10,
4388                 .phy_base_addr = 0x10,
4389                 .global1_addr = 0x1b,
4390                 .global2_addr = 0x1c,
4391                 .age_time_coeff = 3750,
4392                 .atu_move_port_mask = 0x1f,
4393                 .g1_irqs = 9,
4394                 .g2_irqs = 10,
4395                 .pvt = true,
4396                 .multi_chip = true,
4397                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4398                 .ptp_support = true,
4399                 .ops = &mv88e6341_ops,
4400         },
4401
4402         [MV88E6350] = {
4403                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4404                 .family = MV88E6XXX_FAMILY_6351,
4405                 .name = "Marvell 88E6350",
4406                 .num_databases = 4096,
4407                 .num_ports = 7,
4408                 .num_internal_phys = 5,
4409                 .max_vid = 4095,
4410                 .port_base_addr = 0x10,
4411                 .phy_base_addr = 0x0,
4412                 .global1_addr = 0x1b,
4413                 .global2_addr = 0x1c,
4414                 .age_time_coeff = 15000,
4415                 .g1_irqs = 9,
4416                 .g2_irqs = 10,
4417                 .atu_move_port_mask = 0xf,
4418                 .pvt = true,
4419                 .multi_chip = true,
4420                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4421                 .ops = &mv88e6350_ops,
4422         },
4423
4424         [MV88E6351] = {
4425                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4426                 .family = MV88E6XXX_FAMILY_6351,
4427                 .name = "Marvell 88E6351",
4428                 .num_databases = 4096,
4429                 .num_ports = 7,
4430                 .num_internal_phys = 5,
4431                 .max_vid = 4095,
4432                 .port_base_addr = 0x10,
4433                 .phy_base_addr = 0x0,
4434                 .global1_addr = 0x1b,
4435                 .global2_addr = 0x1c,
4436                 .age_time_coeff = 15000,
4437                 .g1_irqs = 9,
4438                 .g2_irqs = 10,
4439                 .atu_move_port_mask = 0xf,
4440                 .pvt = true,
4441                 .multi_chip = true,
4442                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4443                 .ops = &mv88e6351_ops,
4444         },
4445
4446         [MV88E6352] = {
4447                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4448                 .family = MV88E6XXX_FAMILY_6352,
4449                 .name = "Marvell 88E6352",
4450                 .num_databases = 4096,
4451                 .num_ports = 7,
4452                 .num_internal_phys = 5,
4453                 .num_gpio = 15,
4454                 .max_vid = 4095,
4455                 .port_base_addr = 0x10,
4456                 .phy_base_addr = 0x0,
4457                 .global1_addr = 0x1b,
4458                 .global2_addr = 0x1c,
4459                 .age_time_coeff = 15000,
4460                 .g1_irqs = 9,
4461                 .g2_irqs = 10,
4462                 .atu_move_port_mask = 0xf,
4463                 .pvt = true,
4464                 .multi_chip = true,
4465                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4466                 .ptp_support = true,
4467                 .ops = &mv88e6352_ops,
4468         },
4469         [MV88E6390] = {
4470                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4471                 .family = MV88E6XXX_FAMILY_6390,
4472                 .name = "Marvell 88E6390",
4473                 .num_databases = 4096,
4474                 .num_ports = 11,        /* 10 + Z80 */
4475                 .num_internal_phys = 9,
4476                 .num_gpio = 16,
4477                 .max_vid = 8191,
4478                 .port_base_addr = 0x0,
4479                 .phy_base_addr = 0x0,
4480                 .global1_addr = 0x1b,
4481                 .global2_addr = 0x1c,
4482                 .age_time_coeff = 3750,
4483                 .g1_irqs = 9,
4484                 .g2_irqs = 14,
4485                 .atu_move_port_mask = 0x1f,
4486                 .pvt = true,
4487                 .multi_chip = true,
4488                 .tag_protocol = DSA_TAG_PROTO_DSA,
4489                 .ptp_support = true,
4490                 .ops = &mv88e6390_ops,
4491         },
4492         [MV88E6390X] = {
4493                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4494                 .family = MV88E6XXX_FAMILY_6390,
4495                 .name = "Marvell 88E6390X",
4496                 .num_databases = 4096,
4497                 .num_ports = 11,        /* 10 + Z80 */
4498                 .num_internal_phys = 9,
4499                 .num_gpio = 16,
4500                 .max_vid = 8191,
4501                 .port_base_addr = 0x0,
4502                 .phy_base_addr = 0x0,
4503                 .global1_addr = 0x1b,
4504                 .global2_addr = 0x1c,
4505                 .age_time_coeff = 3750,
4506                 .g1_irqs = 9,
4507                 .g2_irqs = 14,
4508                 .atu_move_port_mask = 0x1f,
4509                 .pvt = true,
4510                 .multi_chip = true,
4511                 .tag_protocol = DSA_TAG_PROTO_DSA,
4512                 .ptp_support = true,
4513                 .ops = &mv88e6390x_ops,
4514         },
4515 };
4516
4517 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4518 {
4519         int i;
4520
4521         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4522                 if (mv88e6xxx_table[i].prod_num == prod_num)
4523                         return &mv88e6xxx_table[i];
4524
4525         return NULL;
4526 }
4527
4528 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4529 {
4530         const struct mv88e6xxx_info *info;
4531         unsigned int prod_num, rev;
4532         u16 id;
4533         int err;
4534
4535         mv88e6xxx_reg_lock(chip);
4536         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4537         mv88e6xxx_reg_unlock(chip);
4538         if (err)
4539                 return err;
4540
4541         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4542         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4543
4544         info = mv88e6xxx_lookup_info(prod_num);
4545         if (!info)
4546                 return -ENODEV;
4547
4548         /* Update the compatible info with the probed one */
4549         chip->info = info;
4550
4551         err = mv88e6xxx_g2_require(chip);
4552         if (err)
4553                 return err;
4554
4555         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4556                  chip->info->prod_num, chip->info->name, rev);
4557
4558         return 0;
4559 }
4560
4561 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4562 {
4563         struct mv88e6xxx_chip *chip;
4564
4565         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4566         if (!chip)
4567                 return NULL;
4568
4569         chip->dev = dev;
4570
4571         mutex_init(&chip->reg_lock);
4572         INIT_LIST_HEAD(&chip->mdios);
4573
4574         return chip;
4575 }
4576
4577 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4578                                                         int port)
4579 {
4580         struct mv88e6xxx_chip *chip = ds->priv;
4581
4582         return chip->info->tag_protocol;
4583 }
4584
4585 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4586                                       const struct switchdev_obj_port_mdb *mdb)
4587 {
4588         /* We don't need any dynamic resource from the kernel (yet),
4589          * so skip the prepare phase.
4590          */
4591
4592         return 0;
4593 }
4594
4595 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4596                                    const struct switchdev_obj_port_mdb *mdb)
4597 {
4598         struct mv88e6xxx_chip *chip = ds->priv;
4599
4600         mv88e6xxx_reg_lock(chip);
4601         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4602                                          MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4603                 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4604                         port);
4605         mv88e6xxx_reg_unlock(chip);
4606 }
4607
4608 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4609                                   const struct switchdev_obj_port_mdb *mdb)
4610 {
4611         struct mv88e6xxx_chip *chip = ds->priv;
4612         int err;
4613
4614         mv88e6xxx_reg_lock(chip);
4615         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4616                                            MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4617         mv88e6xxx_reg_unlock(chip);
4618
4619         return err;
4620 }
4621
4622 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
4623                                          bool unicast, bool multicast)
4624 {
4625         struct mv88e6xxx_chip *chip = ds->priv;
4626         int err = -EOPNOTSUPP;
4627
4628         mv88e6xxx_reg_lock(chip);
4629         if (chip->info->ops->port_set_egress_floods)
4630                 err = chip->info->ops->port_set_egress_floods(chip, port,
4631                                                               unicast,
4632                                                               multicast);
4633         mv88e6xxx_reg_unlock(chip);
4634
4635         return err;
4636 }
4637
4638 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4639         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
4640         .setup                  = mv88e6xxx_setup,
4641         .adjust_link            = mv88e6xxx_adjust_link,
4642         .phylink_validate       = mv88e6xxx_validate,
4643         .phylink_mac_link_state = mv88e6xxx_link_state,
4644         .phylink_mac_config     = mv88e6xxx_mac_config,
4645         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
4646         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
4647         .get_strings            = mv88e6xxx_get_strings,
4648         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
4649         .get_sset_count         = mv88e6xxx_get_sset_count,
4650         .port_enable            = mv88e6xxx_port_enable,
4651         .port_disable           = mv88e6xxx_port_disable,
4652         .get_mac_eee            = mv88e6xxx_get_mac_eee,
4653         .set_mac_eee            = mv88e6xxx_set_mac_eee,
4654         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
4655         .get_eeprom             = mv88e6xxx_get_eeprom,
4656         .set_eeprom             = mv88e6xxx_set_eeprom,
4657         .get_regs_len           = mv88e6xxx_get_regs_len,
4658         .get_regs               = mv88e6xxx_get_regs,
4659         .set_ageing_time        = mv88e6xxx_set_ageing_time,
4660         .port_bridge_join       = mv88e6xxx_port_bridge_join,
4661         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
4662         .port_egress_floods     = mv88e6xxx_port_egress_floods,
4663         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
4664         .port_fast_age          = mv88e6xxx_port_fast_age,
4665         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
4666         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
4667         .port_vlan_add          = mv88e6xxx_port_vlan_add,
4668         .port_vlan_del          = mv88e6xxx_port_vlan_del,
4669         .port_fdb_add           = mv88e6xxx_port_fdb_add,
4670         .port_fdb_del           = mv88e6xxx_port_fdb_del,
4671         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4672         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
4673         .port_mdb_add           = mv88e6xxx_port_mdb_add,
4674         .port_mdb_del           = mv88e6xxx_port_mdb_del,
4675         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
4676         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4677         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
4678         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
4679         .port_txtstamp          = mv88e6xxx_port_txtstamp,
4680         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
4681         .get_ts_info            = mv88e6xxx_get_ts_info,
4682 };
4683
4684 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4685 {
4686         struct device *dev = chip->dev;
4687         struct dsa_switch *ds;
4688
4689         ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4690         if (!ds)
4691                 return -ENOMEM;
4692
4693         ds->priv = chip;
4694         ds->dev = dev;
4695         ds->ops = &mv88e6xxx_switch_ops;
4696         ds->ageing_time_min = chip->info->age_time_coeff;
4697         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4698
4699         dev_set_drvdata(dev, ds);
4700
4701         return dsa_register_switch(ds);
4702 }
4703
4704 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4705 {
4706         dsa_unregister_switch(chip->ds);
4707 }
4708
4709 static const void *pdata_device_get_match_data(struct device *dev)
4710 {
4711         const struct of_device_id *matches = dev->driver->of_match_table;
4712         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
4713
4714         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
4715              matches++) {
4716                 if (!strcmp(pdata->compatible, matches->compatible))
4717                         return matches->data;
4718         }
4719         return NULL;
4720 }
4721
4722 /* There is no suspend to RAM support at DSA level yet, the switch configuration
4723  * would be lost after a power cycle so prevent it to be suspended.
4724  */
4725 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
4726 {
4727         return -EOPNOTSUPP;
4728 }
4729
4730 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
4731 {
4732         return 0;
4733 }
4734
4735 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
4736
4737 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4738 {
4739         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4740         const struct mv88e6xxx_info *compat_info = NULL;
4741         struct device *dev = &mdiodev->dev;
4742         struct device_node *np = dev->of_node;
4743         struct mv88e6xxx_chip *chip;
4744         int port;
4745         int err;
4746
4747         if (!np && !pdata)
4748                 return -EINVAL;
4749
4750         if (np)
4751                 compat_info = of_device_get_match_data(dev);
4752
4753         if (pdata) {
4754                 compat_info = pdata_device_get_match_data(dev);
4755
4756                 if (!pdata->netdev)
4757                         return -EINVAL;
4758
4759                 for (port = 0; port < DSA_MAX_PORTS; port++) {
4760                         if (!(pdata->enabled_ports & (1 << port)))
4761                                 continue;
4762                         if (strcmp(pdata->cd.port_names[port], "cpu"))
4763                                 continue;
4764                         pdata->cd.netdev[port] = &pdata->netdev->dev;
4765                         break;
4766                 }
4767         }
4768
4769         if (!compat_info)
4770                 return -EINVAL;
4771
4772         chip = mv88e6xxx_alloc_chip(dev);
4773         if (!chip) {
4774                 err = -ENOMEM;
4775                 goto out;
4776         }
4777
4778         chip->info = compat_info;
4779
4780         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4781         if (err)
4782                 goto out;
4783
4784         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4785         if (IS_ERR(chip->reset)) {
4786                 err = PTR_ERR(chip->reset);
4787                 goto out;
4788         }
4789         if (chip->reset)
4790                 usleep_range(1000, 2000);
4791
4792         err = mv88e6xxx_detect(chip);
4793         if (err)
4794                 goto out;
4795
4796         mv88e6xxx_phy_init(chip);
4797
4798         if (chip->info->ops->get_eeprom) {
4799                 if (np)
4800                         of_property_read_u32(np, "eeprom-length",
4801                                              &chip->eeprom_len);
4802                 else
4803                         chip->eeprom_len = pdata->eeprom_len;
4804         }
4805
4806         mv88e6xxx_reg_lock(chip);
4807         err = mv88e6xxx_switch_reset(chip);
4808         mv88e6xxx_reg_unlock(chip);
4809         if (err)
4810                 goto out;
4811
4812         if (np) {
4813                 chip->irq = of_irq_get(np, 0);
4814                 if (chip->irq == -EPROBE_DEFER) {
4815                         err = chip->irq;
4816                         goto out;
4817                 }
4818         }
4819
4820         if (pdata)
4821                 chip->irq = pdata->irq;
4822
4823         /* Has to be performed before the MDIO bus is created, because
4824          * the PHYs will link their interrupts to these interrupt
4825          * controllers
4826          */
4827         mv88e6xxx_reg_lock(chip);
4828         if (chip->irq > 0)
4829                 err = mv88e6xxx_g1_irq_setup(chip);
4830         else
4831                 err = mv88e6xxx_irq_poll_setup(chip);
4832         mv88e6xxx_reg_unlock(chip);
4833
4834         if (err)
4835                 goto out;
4836
4837         if (chip->info->g2_irqs > 0) {
4838                 err = mv88e6xxx_g2_irq_setup(chip);
4839                 if (err)
4840                         goto out_g1_irq;
4841         }
4842
4843         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4844         if (err)
4845                 goto out_g2_irq;
4846
4847         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4848         if (err)
4849                 goto out_g1_atu_prob_irq;
4850
4851         err = mv88e6xxx_mdios_register(chip, np);
4852         if (err)
4853                 goto out_g1_vtu_prob_irq;
4854
4855         err = mv88e6xxx_register_switch(chip);
4856         if (err)
4857                 goto out_mdio;
4858
4859         return 0;
4860
4861 out_mdio:
4862         mv88e6xxx_mdios_unregister(chip);
4863 out_g1_vtu_prob_irq:
4864         mv88e6xxx_g1_vtu_prob_irq_free(chip);
4865 out_g1_atu_prob_irq:
4866         mv88e6xxx_g1_atu_prob_irq_free(chip);
4867 out_g2_irq:
4868         if (chip->info->g2_irqs > 0)
4869                 mv88e6xxx_g2_irq_free(chip);
4870 out_g1_irq:
4871         if (chip->irq > 0)
4872                 mv88e6xxx_g1_irq_free(chip);
4873         else
4874                 mv88e6xxx_irq_poll_free(chip);
4875 out:
4876         if (pdata)
4877                 dev_put(pdata->netdev);
4878
4879         return err;
4880 }
4881
4882 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4883 {
4884         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4885         struct mv88e6xxx_chip *chip = ds->priv;
4886
4887         if (chip->info->ptp_support) {
4888                 mv88e6xxx_hwtstamp_free(chip);
4889                 mv88e6xxx_ptp_free(chip);
4890         }
4891
4892         mv88e6xxx_phy_destroy(chip);
4893         mv88e6xxx_unregister_switch(chip);
4894         mv88e6xxx_mdios_unregister(chip);
4895
4896         mv88e6xxx_g1_vtu_prob_irq_free(chip);
4897         mv88e6xxx_g1_atu_prob_irq_free(chip);
4898
4899         if (chip->info->g2_irqs > 0)
4900                 mv88e6xxx_g2_irq_free(chip);
4901
4902         if (chip->irq > 0)
4903                 mv88e6xxx_g1_irq_free(chip);
4904         else
4905                 mv88e6xxx_irq_poll_free(chip);
4906 }
4907
4908 static const struct of_device_id mv88e6xxx_of_match[] = {
4909         {
4910                 .compatible = "marvell,mv88e6085",
4911                 .data = &mv88e6xxx_table[MV88E6085],
4912         },
4913         {
4914                 .compatible = "marvell,mv88e6190",
4915                 .data = &mv88e6xxx_table[MV88E6190],
4916         },
4917         {
4918                 .compatible = "marvell,mv88e6250",
4919                 .data = &mv88e6xxx_table[MV88E6250],
4920         },
4921         { /* sentinel */ },
4922 };
4923
4924 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4925
4926 static struct mdio_driver mv88e6xxx_driver = {
4927         .probe  = mv88e6xxx_probe,
4928         .remove = mv88e6xxx_remove,
4929         .mdiodrv.driver = {
4930                 .name = "mv88e6085",
4931                 .of_match_table = mv88e6xxx_of_match,
4932                 .pm = &mv88e6xxx_pm_ops,
4933         },
4934 };
4935
4936 mdio_module_driver(mv88e6xxx_driver);
4937
4938 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4939 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4940 MODULE_LICENSE("GPL");