drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_mdio.h>
  28 #include <linux/platform_data/mv88e6xxx.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <linux/phylink.h>
  32 #include <net/dsa.h>
  33
  34 #include "chip.h"
  35 #include "devlink.h"
  36 #include "global1.h"
  37 #include "global2.h"
  38 #include "hwtstamp.h"
  39 #include "phy.h"
  40 #include "port.h"
  41 #include "ptp.h"
  42 #include "serdes.h"
  43 #include "smi.h"
  44
  45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  46 {
  47         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  48                 dev_err(chip->dev, "Switch registers lock not held!\n");
  49                 dump_stack();
  50         }
  51 }
  52
  53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  54 {
  55         int err;
  56
  57         assert_reg_lock(chip);
  58
  59         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  60         if (err)
  61                 return err;
  62
  63         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  64                 addr, reg, *val);
  65
  66         return 0;
  67 }
  68
  69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  70 {
  71         int err;
  72
  73         assert_reg_lock(chip);
  74
  75         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  76         if (err)
  77                 return err;
  78
  79         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  80                 addr, reg, val);
  81
  82         return 0;
  83 }
  84
  85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  86                         u16 mask, u16 val)
  87 {
  88         u16 data;
  89         int err;
  90         int i;
  91
  92         /* There's no bus specific operation to wait for a mask */
  93         for (i = 0; i < 16; i++) {
  94                 err = mv88e6xxx_read(chip, addr, reg, &data);
  95                 if (err)
  96                         return err;
  97
  98                 if ((data & mask) == val)
  99                         return 0;
 100
 101                 usleep_range(1000, 2000);
 102         }
 103
 104         dev_err(chip->dev, "Timeout while waiting for switch\n");
 105         return -ETIMEDOUT;
 106 }
 107
 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 109                        int bit, int val)
 110 {
 111         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 112                                    val ? BIT(bit) : 0x0000);
 113 }
 114
 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 116 {
 117         struct mv88e6xxx_mdio_bus *mdio_bus;
 118
 119         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 120                                     list);
 121         if (!mdio_bus)
 122                 return NULL;
 123
 124         return mdio_bus->bus;
 125 }
 126
 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 128 {
 129         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 130         unsigned int n = d->hwirq;
 131
 132         chip->g1_irq.masked |= (1 << n);
 133 }
 134
 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 136 {
 137         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 138         unsigned int n = d->hwirq;
 139
 140         chip->g1_irq.masked &= ~(1 << n);
 141 }
 142
 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 144 {
 145         unsigned int nhandled = 0;
 146         unsigned int sub_irq;
 147         unsigned int n;
 148         u16 reg;
 149         u16 ctl1;
 150         int err;
 151
 152         mv88e6xxx_reg_lock(chip);
 153         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 154         mv88e6xxx_reg_unlock(chip);
 155
 156         if (err)
 157                 goto out;
 158
 159         do {
 160                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 161                         if (reg & (1 << n)) {
 162                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 163                                                            n);
 164                                 handle_nested_irq(sub_irq);
 165                                 ++nhandled;
 166                         }
 167                 }
 168
 169                 mv88e6xxx_reg_lock(chip);
 170                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 171                 if (err)
 172                         goto unlock;
 173                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 174 unlock:
 175                 mv88e6xxx_reg_unlock(chip);
 176                 if (err)
 177                         goto out;
 178                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 179         } while (reg & ctl1);
 180
 181 out:
 182         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 183 }
 184
 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 186 {
 187         struct mv88e6xxx_chip *chip = dev_id;
 188
 189         return mv88e6xxx_g1_irq_thread_work(chip);
 190 }
 191
 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 193 {
 194         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 195
 196         mv88e6xxx_reg_lock(chip);
 197 }
 198
 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 200 {
 201         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 202         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 203         u16 reg;
 204         int err;
 205
 206         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 207         if (err)
 208                 goto out;
 209
 210         reg &= ~mask;
 211         reg |= (~chip->g1_irq.masked & mask);
 212
 213         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 214         if (err)
 215                 goto out;
 216
 217 out:
 218         mv88e6xxx_reg_unlock(chip);
 219 }
 220
 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 222         .name                   = "mv88e6xxx-g1",
 223         .irq_mask               = mv88e6xxx_g1_irq_mask,
 224         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 225         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 226         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 227 };
 228
 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 230                                        unsigned int irq,
 231                                        irq_hw_number_t hwirq)
 232 {
 233         struct mv88e6xxx_chip *chip = d->host_data;
 234
 235         irq_set_chip_data(irq, d->host_data);
 236         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 237         irq_set_noprobe(irq);
 238
 239         return 0;
 240 }
 241
 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 243         .map    = mv88e6xxx_g1_irq_domain_map,
 244         .xlate  = irq_domain_xlate_twocell,
 245 };
 246
 247 /* To be called with reg_lock held */
 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 249 {
 250         int irq, virq;
 251         u16 mask;
 252
 253         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 254         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 255         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 256
 257         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 258                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 259                 irq_dispose_mapping(virq);
 260         }
 261
 262         irq_domain_remove(chip->g1_irq.domain);
 263 }
 264
 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 266 {
 267         /*
 268          * free_irq must be called without reg_lock taken because the irq
 269          * handler takes this lock, too.
 270          */
 271         free_irq(chip->irq, chip);
 272
 273         mv88e6xxx_reg_lock(chip);
 274         mv88e6xxx_g1_irq_free_common(chip);
 275         mv88e6xxx_reg_unlock(chip);
 276 }
 277
 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 279 {
 280         int err, irq, virq;
 281         u16 reg, mask;
 282
 283         chip->g1_irq.nirqs = chip->info->g1_irqs;
 284         chip->g1_irq.domain = irq_domain_add_simple(
 285                 NULL, chip->g1_irq.nirqs, 0,
 286                 &mv88e6xxx_g1_irq_domain_ops, chip);
 287         if (!chip->g1_irq.domain)
 288                 return -ENOMEM;
 289
 290         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 291                 irq_create_mapping(chip->g1_irq.domain, irq);
 292
 293         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 294         chip->g1_irq.masked = ~0;
 295
 296         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 297         if (err)
 298                 goto out_mapping;
 299
 300         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 301
 302         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 303         if (err)
 304                 goto out_disable;
 305
 306         /* Reading the interrupt status clears (most of) them */
 307         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 308         if (err)
 309                 goto out_disable;
 310
 311         return 0;
 312
 313 out_disable:
 314         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 315         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 316
 317 out_mapping:
 318         for (irq = 0; irq < 16; irq++) {
 319                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 320                 irq_dispose_mapping(virq);
 321         }
 322
 323         irq_domain_remove(chip->g1_irq.domain);
 324
 325         return err;
 326 }
 327
 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 329 {
 330         static struct lock_class_key lock_key;
 331         static struct lock_class_key request_key;
 332         int err;
 333
 334         err = mv88e6xxx_g1_irq_setup_common(chip);
 335         if (err)
 336                 return err;
 337
 338         /* These lock classes tells lockdep that global 1 irqs are in
 339          * a different category than their parent GPIO, so it won't
 340          * report false recursion.
 341          */
 342         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 343
 344         snprintf(chip->irq_name, sizeof(chip->irq_name),
 345                  "mv88e6xxx-%s", dev_name(chip->dev));
 346
 347         mv88e6xxx_reg_unlock(chip);
 348         err = request_threaded_irq(chip->irq, NULL,
 349                                    mv88e6xxx_g1_irq_thread_fn,
 350                                    IRQF_ONESHOT | IRQF_SHARED,
 351                                    chip->irq_name, chip);
 352         mv88e6xxx_reg_lock(chip);
 353         if (err)
 354                 mv88e6xxx_g1_irq_free_common(chip);
 355
 356         return err;
 357 }
 358
 359 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 360 {
 361         struct mv88e6xxx_chip *chip = container_of(work,
 362                                                    struct mv88e6xxx_chip,
 363                                                    irq_poll_work.work);
 364         mv88e6xxx_g1_irq_thread_work(chip);
 365
 366         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 367                                    msecs_to_jiffies(100));
 368 }
 369
 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 371 {
 372         int err;
 373
 374         err = mv88e6xxx_g1_irq_setup_common(chip);
 375         if (err)
 376                 return err;
 377
 378         kthread_init_delayed_work(&chip->irq_poll_work,
 379                                   mv88e6xxx_irq_poll);
 380
 381         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 382         if (IS_ERR(chip->kworker))
 383                 return PTR_ERR(chip->kworker);
 384
 385         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 386                                    msecs_to_jiffies(100));
 387
 388         return 0;
 389 }
 390
 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 392 {
 393         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 394         kthread_destroy_worker(chip->kworker);
 395
 396         mv88e6xxx_reg_lock(chip);
 397         mv88e6xxx_g1_irq_free_common(chip);
 398         mv88e6xxx_reg_unlock(chip);
 399 }
 400
 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 402                                            int port, phy_interface_t interface)
 403 {
 404         int err;
 405
 406         if (chip->info->ops->port_set_rgmii_delay) {
 407                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 408                                                             interface);
 409                 if (err && err != -EOPNOTSUPP)
 410                         return err;
 411         }
 412
 413         if (chip->info->ops->port_set_cmode) {
 414                 err = chip->info->ops->port_set_cmode(chip, port,
 415                                                       interface);
 416                 if (err && err != -EOPNOTSUPP)
 417                         return err;
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 424                                     int link, int speed, int duplex, int pause,
 425                                     phy_interface_t mode)
 426 {
 427         int err;
 428
 429         if (!chip->info->ops->port_set_link)
 430                 return 0;
 431
 432         /* Port's MAC control must not be changed unless the link is down */
 433         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 434         if (err)
 435                 return err;
 436
 437         if (chip->info->ops->port_set_speed_duplex) {
 438                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 439                                                              speed, duplex);
 440                 if (err && err != -EOPNOTSUPP)
 441                         goto restore_link;
 442         }
 443
 444         if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
 445                 mode = chip->info->ops->port_max_speed_mode(port);
 446
 447         if (chip->info->ops->port_set_pause) {
 448                 err = chip->info->ops->port_set_pause(chip, port, pause);
 449                 if (err)
 450                         goto restore_link;
 451         }
 452
 453         err = mv88e6xxx_port_config_interface(chip, port, mode);
 454 restore_link:
 455         if (chip->info->ops->port_set_link(chip, port, link))
 456                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 457
 458         return err;
 459 }
 460
 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 462 {
 463         struct mv88e6xxx_chip *chip = ds->priv;
 464
 465         return port < chip->info->num_internal_phys;
 466 }
 467
 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 469 {
 470         u16 reg;
 471         int err;
 472
 473         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 474         if (err) {
 475                 dev_err(chip->dev,
 476                         "p%d: %s: failed to read port status\n",
 477                         port, __func__);
 478                 return err;
 479         }
 480
 481         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 482 }
 483
 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
 485                                           struct phylink_link_state *state)
 486 {
 487         struct mv88e6xxx_chip *chip = ds->priv;
 488         u8 lane;
 489         int err;
 490
 491         mv88e6xxx_reg_lock(chip);
 492         lane = mv88e6xxx_serdes_get_lane(chip, port);
 493         if (lane && chip->info->ops->serdes_pcs_get_state)
 494                 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
 495                                                             state);
 496         else
 497                 err = -EOPNOTSUPP;
 498         mv88e6xxx_reg_unlock(chip);
 499
 500         return err;
 501 }
 502
 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 504                                        unsigned int mode,
 505                                        phy_interface_t interface,
 506                                        const unsigned long *advertise)
 507 {
 508         const struct mv88e6xxx_ops *ops = chip->info->ops;
 509         u8 lane;
 510
 511         if (ops->serdes_pcs_config) {
 512                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 513                 if (lane)
 514                         return ops->serdes_pcs_config(chip, port, lane, mode,
 515                                                       interface, advertise);
 516         }
 517
 518         return 0;
 519 }
 520
 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
 522 {
 523         struct mv88e6xxx_chip *chip = ds->priv;
 524         const struct mv88e6xxx_ops *ops;
 525         int err = 0;
 526         u8 lane;
 527
 528         ops = chip->info->ops;
 529
 530         if (ops->serdes_pcs_an_restart) {
 531                 mv88e6xxx_reg_lock(chip);
 532                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 533                 if (lane)
 534                         err = ops->serdes_pcs_an_restart(chip, port, lane);
 535                 mv88e6xxx_reg_unlock(chip);
 536
 537                 if (err)
 538                         dev_err(ds->dev, "p%d: failed to restart AN\n", port);
 539         }
 540 }
 541
 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 543                                         unsigned int mode,
 544                                         int speed, int duplex)
 545 {
 546         const struct mv88e6xxx_ops *ops = chip->info->ops;
 547         u8 lane;
 548
 549         if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
 550                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 551                 if (lane)
 552                         return ops->serdes_pcs_link_up(chip, port, lane,
 553                                                        speed, duplex);
 554         }
 555
 556         return 0;
 557 }
 558
 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 560                                        unsigned long *mask,
 561                                        struct phylink_link_state *state)
 562 {
 563         if (!phy_interface_mode_is_8023z(state->interface)) {
 564                 /* 10M and 100M are only supported in non-802.3z mode */
 565                 phylink_set(mask, 10baseT_Half);
 566                 phylink_set(mask, 10baseT_Full);
 567                 phylink_set(mask, 100baseT_Half);
 568                 phylink_set(mask, 100baseT_Full);
 569         }
 570 }
 571
 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 573                                        unsigned long *mask,
 574                                        struct phylink_link_state *state)
 575 {
 576         /* FIXME: if the port is in 1000Base-X mode, then it only supports
 577          * 1000M FD speeds.  In this case, CMODE will indicate 5.
 578          */
 579         phylink_set(mask, 1000baseT_Full);
 580         phylink_set(mask, 1000baseX_Full);
 581
 582         mv88e6065_phylink_validate(chip, port, mask, state);
 583 }
 584
 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 586                                        unsigned long *mask,
 587                                        struct phylink_link_state *state)
 588 {
 589         if (port >= 5)
 590                 phylink_set(mask, 2500baseX_Full);
 591
 592         /* No ethtool bits for 200Mbps */
 593         phylink_set(mask, 1000baseT_Full);
 594         phylink_set(mask, 1000baseX_Full);
 595
 596         mv88e6065_phylink_validate(chip, port, mask, state);
 597 }
 598
 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 600                                        unsigned long *mask,
 601                                        struct phylink_link_state *state)
 602 {
 603         /* No ethtool bits for 200Mbps */
 604         phylink_set(mask, 1000baseT_Full);
 605         phylink_set(mask, 1000baseX_Full);
 606
 607         mv88e6065_phylink_validate(chip, port, mask, state);
 608 }
 609
 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 611                                        unsigned long *mask,
 612                                        struct phylink_link_state *state)
 613 {
 614         if (port >= 9) {
 615                 phylink_set(mask, 2500baseX_Full);
 616                 phylink_set(mask, 2500baseT_Full);
 617         }
 618
 619         /* No ethtool bits for 200Mbps */
 620         phylink_set(mask, 1000baseT_Full);
 621         phylink_set(mask, 1000baseX_Full);
 622
 623         mv88e6065_phylink_validate(chip, port, mask, state);
 624 }
 625
 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 627                                         unsigned long *mask,
 628                                         struct phylink_link_state *state)
 629 {
 630         if (port >= 9) {
 631                 phylink_set(mask, 10000baseT_Full);
 632                 phylink_set(mask, 10000baseKR_Full);
 633         }
 634
 635         mv88e6390_phylink_validate(chip, port, mask, state);
 636 }
 637
 638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
 639                                unsigned long *supported,
 640                                struct phylink_link_state *state)
 641 {
 642         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 643         struct mv88e6xxx_chip *chip = ds->priv;
 644
 645         /* Allow all the expected bits */
 646         phylink_set(mask, Autoneg);
 647         phylink_set(mask, Pause);
 648         phylink_set_port_modes(mask);
 649
 650         if (chip->info->ops->phylink_validate)
 651                 chip->info->ops->phylink_validate(chip, port, mask, state);
 652
 653         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 654         bitmap_and(state->advertising, state->advertising, mask,
 655                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 656
 657         /* We can only operate at 2500BaseX or 1000BaseX.  If requested
 658          * to advertise both, only report advertising at 2500BaseX.
 659          */
 660         phylink_helper_basex_speed(state);
 661 }
 662
 663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 664                                  unsigned int mode,
 665                                  const struct phylink_link_state *state)
 666 {
 667         struct mv88e6xxx_chip *chip = ds->priv;
 668         struct mv88e6xxx_port *p;
 669         int err;
 670
 671         p = &chip->ports[port];
 672
 673         /* FIXME: is this the correct test? If we're in fixed mode on an
 674          * internal port, why should we process this any different from
 675          * PHY mode? On the other hand, the port may be automedia between
 676          * an internal PHY and the serdes...
 677          */
 678         if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
 679                 return;
 680
 681         mv88e6xxx_reg_lock(chip);
 682         /* In inband mode, the link may come up at any time while the link
 683          * is not forced down. Force the link down while we reconfigure the
 684          * interface mode.
 685          */
 686         if (mode == MLO_AN_INBAND && p->interface != state->interface &&
 687             chip->info->ops->port_set_link)
 688                 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 689
 690         err = mv88e6xxx_port_config_interface(chip, port, state->interface);
 691         if (err && err != -EOPNOTSUPP)
 692                 goto err_unlock;
 693
 694         err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
 695                                           state->advertising);
 696         /* FIXME: we should restart negotiation if something changed - which
 697          * is something we get if we convert to using phylinks PCS operations.
 698          */
 699         if (err > 0)
 700                 err = 0;
 701
 702         /* Undo the forced down state above after completing configuration
 703          * irrespective of its state on entry, which allows the link to come up.
 704          */
 705         if (mode == MLO_AN_INBAND && p->interface != state->interface &&
 706             chip->info->ops->port_set_link)
 707                 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 708
 709         p->interface = state->interface;
 710
 711 err_unlock:
 712         mv88e6xxx_reg_unlock(chip);
 713
 714         if (err && err != -EOPNOTSUPP)
 715                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 716 }
 717
 718 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 719                                     unsigned int mode,
 720                                     phy_interface_t interface)
 721 {
 722         struct mv88e6xxx_chip *chip = ds->priv;
 723         const struct mv88e6xxx_ops *ops;
 724         int err = 0;
 725
 726         ops = chip->info->ops;
 727
 728         mv88e6xxx_reg_lock(chip);
 729         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 730              mode == MLO_AN_FIXED) && ops->port_sync_link)
 731                 err = ops->port_sync_link(chip, port, mode, false);
 732         mv88e6xxx_reg_unlock(chip);
 733
 734         if (err)
 735                 dev_err(chip->dev,
 736                         "p%d: failed to force MAC link down\n", port);
 737 }
 738
 739 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 740                                   unsigned int mode, phy_interface_t interface,
 741                                   struct phy_device *phydev,
 742                                   int speed, int duplex,
 743                                   bool tx_pause, bool rx_pause)
 744 {
 745         struct mv88e6xxx_chip *chip = ds->priv;
 746         const struct mv88e6xxx_ops *ops;
 747         int err = 0;
 748
 749         ops = chip->info->ops;
 750
 751         mv88e6xxx_reg_lock(chip);
 752         if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
 753                 /* FIXME: for an automedia port, should we force the link
 754                  * down here - what if the link comes up due to "other" media
 755                  * while we're bringing the port up, how is the exclusivity
 756                  * handled in the Marvell hardware? E.g. port 2 on 88E6390
 757                  * shared between internal PHY and Serdes.
 758                  */
 759                 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
 760                                                    duplex);
 761                 if (err)
 762                         goto error;
 763
 764                 if (ops->port_set_speed_duplex) {
 765                         err = ops->port_set_speed_duplex(chip, port,
 766                                                          speed, duplex);
 767                         if (err && err != -EOPNOTSUPP)
 768                                 goto error;
 769                 }
 770
 771                 if (ops->port_sync_link)
 772                         err = ops->port_sync_link(chip, port, mode, true);
 773         }
 774 error:
 775         mv88e6xxx_reg_unlock(chip);
 776
 777         if (err && err != -EOPNOTSUPP)
 778                 dev_err(ds->dev,
 779                         "p%d: failed to configure MAC link up\n", port);
 780 }
 781
 782 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 783 {
 784         if (!chip->info->ops->stats_snapshot)
 785                 return -EOPNOTSUPP;
 786
 787         return chip->info->ops->stats_snapshot(chip, port);
 788 }
 789
 790 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 791         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 792         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 793         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 794         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 795         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 796         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 797         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 798         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 799         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 800         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 801         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 802         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 803         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 804         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 805         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 806         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 807         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 808         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 809         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 810         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 811         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 812         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 813         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 814         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 815         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 816         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 817         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 818         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 819         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 820         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 821         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 822         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 823         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 824         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 825         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 826         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 827         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 828         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 829         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 830         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 831         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 832         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 833         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 834         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 835         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 836         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 837         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 838         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 839         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 840         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 841         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 842         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 843         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 844         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 845         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 846         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 847         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 848         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 849         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
 850 };
 851
 852 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 853                                             struct mv88e6xxx_hw_stat *s,
 854                                             int port, u16 bank1_select,
 855                                             u16 histogram)
 856 {
 857         u32 low;
 858         u32 high = 0;
 859         u16 reg = 0;
 860         int err;
 861         u64 value;
 862
 863         switch (s->type) {
 864         case STATS_TYPE_PORT:
 865                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 866                 if (err)
 867                         return U64_MAX;
 868
 869                 low = reg;
 870                 if (s->size == 4) {
 871                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 872                         if (err)
 873                                 return U64_MAX;
 874                         low |= ((u32)reg) << 16;
 875                 }
 876                 break;
 877         case STATS_TYPE_BANK1:
 878                 reg = bank1_select;
 879                 fallthrough;
 880         case STATS_TYPE_BANK0:
 881                 reg |= s->reg | histogram;
 882                 mv88e6xxx_g1_stats_read(chip, reg, &low);
 883                 if (s->size == 8)
 884                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
 885                 break;
 886         default:
 887                 return U64_MAX;
 888         }
 889         value = (((u64)high) << 32) | low;
 890         return value;
 891 }
 892
 893 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
 894                                        uint8_t *data, int types)
 895 {
 896         struct mv88e6xxx_hw_stat *stat;
 897         int i, j;
 898
 899         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 900                 stat = &mv88e6xxx_hw_stats[i];
 901                 if (stat->type & types) {
 902                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 903                                ETH_GSTRING_LEN);
 904                         j++;
 905                 }
 906         }
 907
 908         return j;
 909 }
 910
 911 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
 912                                        uint8_t *data)
 913 {
 914         return mv88e6xxx_stats_get_strings(chip, data,
 915                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
 916 }
 917
 918 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
 919                                        uint8_t *data)
 920 {
 921         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
 922 }
 923
 924 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
 925                                        uint8_t *data)
 926 {
 927         return mv88e6xxx_stats_get_strings(chip, data,
 928                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
 929 }
 930
 931 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
 932         "atu_member_violation",
 933         "atu_miss_violation",
 934         "atu_full_violation",
 935         "vtu_member_violation",
 936         "vtu_miss_violation",
 937 };
 938
 939 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
 940 {
 941         unsigned int i;
 942
 943         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
 944                 strlcpy(data + i * ETH_GSTRING_LEN,
 945                         mv88e6xxx_atu_vtu_stats_strings[i],
 946                         ETH_GSTRING_LEN);
 947 }
 948
 949 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 950                                   u32 stringset, uint8_t *data)
 951 {
 952         struct mv88e6xxx_chip *chip = ds->priv;
 953         int count = 0;
 954
 955         if (stringset != ETH_SS_STATS)
 956                 return;
 957
 958         mv88e6xxx_reg_lock(chip);
 959
 960         if (chip->info->ops->stats_get_strings)
 961                 count = chip->info->ops->stats_get_strings(chip, data);
 962
 963         if (chip->info->ops->serdes_get_strings) {
 964                 data += count * ETH_GSTRING_LEN;
 965                 count = chip->info->ops->serdes_get_strings(chip, port, data);
 966         }
 967
 968         data += count * ETH_GSTRING_LEN;
 969         mv88e6xxx_atu_vtu_get_strings(data);
 970
 971         mv88e6xxx_reg_unlock(chip);
 972 }
 973
 974 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
 975                                           int types)
 976 {
 977         struct mv88e6xxx_hw_stat *stat;
 978         int i, j;
 979
 980         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 981                 stat = &mv88e6xxx_hw_stats[i];
 982                 if (stat->type & types)
 983                         j++;
 984         }
 985         return j;
 986 }
 987
 988 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 989 {
 990         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 991                                               STATS_TYPE_PORT);
 992 }
 993
 994 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 995 {
 996         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
 997 }
 998
 999 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1000 {
1001         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1002                                               STATS_TYPE_BANK1);
1003 }
1004
1005 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1006 {
1007         struct mv88e6xxx_chip *chip = ds->priv;
1008         int serdes_count = 0;
1009         int count = 0;
1010
1011         if (sset != ETH_SS_STATS)
1012                 return 0;
1013
1014         mv88e6xxx_reg_lock(chip);
1015         if (chip->info->ops->stats_get_sset_count)
1016                 count = chip->info->ops->stats_get_sset_count(chip);
1017         if (count < 0)
1018                 goto out;
1019
1020         if (chip->info->ops->serdes_get_sset_count)
1021                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1022                                                                       port);
1023         if (serdes_count < 0) {
1024                 count = serdes_count;
1025                 goto out;
1026         }
1027         count += serdes_count;
1028         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1029
1030 out:
1031         mv88e6xxx_reg_unlock(chip);
1032
1033         return count;
1034 }
1035
1036 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1037                                      uint64_t *data, int types,
1038                                      u16 bank1_select, u16 histogram)
1039 {
1040         struct mv88e6xxx_hw_stat *stat;
1041         int i, j;
1042
1043         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1044                 stat = &mv88e6xxx_hw_stats[i];
1045                 if (stat->type & types) {
1046                         mv88e6xxx_reg_lock(chip);
1047                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1048                                                               bank1_select,
1049                                                               histogram);
1050                         mv88e6xxx_reg_unlock(chip);
1051
1052                         j++;
1053                 }
1054         }
1055         return j;
1056 }
1057
1058 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1059                                      uint64_t *data)
1060 {
1061         return mv88e6xxx_stats_get_stats(chip, port, data,
1062                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1063                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1064 }
1065
1066 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1067                                      uint64_t *data)
1068 {
1069         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1070                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1071 }
1072
1073 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1074                                      uint64_t *data)
1075 {
1076         return mv88e6xxx_stats_get_stats(chip, port, data,
1077                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1078                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1079                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1080 }
1081
1082 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1083                                      uint64_t *data)
1084 {
1085         return mv88e6xxx_stats_get_stats(chip, port, data,
1086                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1087                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1088                                          0);
1089 }
1090
1091 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1092                                         uint64_t *data)
1093 {
1094         *data++ = chip->ports[port].atu_member_violation;
1095         *data++ = chip->ports[port].atu_miss_violation;
1096         *data++ = chip->ports[port].atu_full_violation;
1097         *data++ = chip->ports[port].vtu_member_violation;
1098         *data++ = chip->ports[port].vtu_miss_violation;
1099 }
1100
1101 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1102                                 uint64_t *data)
1103 {
1104         int count = 0;
1105
1106         if (chip->info->ops->stats_get_stats)
1107                 count = chip->info->ops->stats_get_stats(chip, port, data);
1108
1109         mv88e6xxx_reg_lock(chip);
1110         if (chip->info->ops->serdes_get_stats) {
1111                 data += count;
1112                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1113         }
1114         data += count;
1115         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1116         mv88e6xxx_reg_unlock(chip);
1117 }
1118
1119 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1120                                         uint64_t *data)
1121 {
1122         struct mv88e6xxx_chip *chip = ds->priv;
1123         int ret;
1124
1125         mv88e6xxx_reg_lock(chip);
1126
1127         ret = mv88e6xxx_stats_snapshot(chip, port);
1128         mv88e6xxx_reg_unlock(chip);
1129
1130         if (ret < 0)
1131                 return;
1132
1133         mv88e6xxx_get_stats(chip, port, data);
1134
1135 }
1136
1137 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1138 {
1139         struct mv88e6xxx_chip *chip = ds->priv;
1140         int len;
1141
1142         len = 32 * sizeof(u16);
1143         if (chip->info->ops->serdes_get_regs_len)
1144                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1145
1146         return len;
1147 }
1148
1149 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1150                                struct ethtool_regs *regs, void *_p)
1151 {
1152         struct mv88e6xxx_chip *chip = ds->priv;
1153         int err;
1154         u16 reg;
1155         u16 *p = _p;
1156         int i;
1157
1158         regs->version = chip->info->prod_num;
1159
1160         memset(p, 0xff, 32 * sizeof(u16));
1161
1162         mv88e6xxx_reg_lock(chip);
1163
1164         for (i = 0; i < 32; i++) {
1165
1166                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1167                 if (!err)
1168                         p[i] = reg;
1169         }
1170
1171         if (chip->info->ops->serdes_get_regs)
1172                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1173
1174         mv88e6xxx_reg_unlock(chip);
1175 }
1176
1177 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1178                                  struct ethtool_eee *e)
1179 {
1180         /* Nothing to do on the port's MAC */
1181         return 0;
1182 }
1183
1184 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1185                                  struct ethtool_eee *e)
1186 {
1187         /* Nothing to do on the port's MAC */
1188         return 0;
1189 }
1190
1191 /* Mask of the local ports allowed to receive frames from a given fabric port */
1192 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1193 {
1194         struct dsa_switch *ds = chip->ds;
1195         struct dsa_switch_tree *dst = ds->dst;
1196         struct net_device *br;
1197         struct dsa_port *dp;
1198         bool found = false;
1199         u16 pvlan;
1200
1201         list_for_each_entry(dp, &dst->ports, list) {
1202                 if (dp->ds->index == dev && dp->index == port) {
1203                         found = true;
1204                         break;
1205                 }
1206         }
1207
1208         /* Prevent frames from unknown switch or port */
1209         if (!found)
1210                 return 0;
1211
1212         /* Frames from DSA links and CPU ports can egress any local port */
1213         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1214                 return mv88e6xxx_port_mask(chip);
1215
1216         br = dp->bridge_dev;
1217         pvlan = 0;
1218
1219         /* Frames from user ports can egress any local DSA links and CPU ports,
1220          * as well as any local member of their bridge group.
1221          */
1222         list_for_each_entry(dp, &dst->ports, list)
1223                 if (dp->ds == ds &&
1224                     (dp->type == DSA_PORT_TYPE_CPU ||
1225                      dp->type == DSA_PORT_TYPE_DSA ||
1226                      (br && dp->bridge_dev == br)))
1227                         pvlan |= BIT(dp->index);
1228
1229         return pvlan;
1230 }
1231
1232 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1233 {
1234         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1235
1236         /* prevent frames from going back out of the port they came in on */
1237         output_ports &= ~BIT(port);
1238
1239         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1240 }
1241
1242 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1243                                          u8 state)
1244 {
1245         struct mv88e6xxx_chip *chip = ds->priv;
1246         int err;
1247
1248         mv88e6xxx_reg_lock(chip);
1249         err = mv88e6xxx_port_set_state(chip, port, state);
1250         mv88e6xxx_reg_unlock(chip);
1251
1252         if (err)
1253                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1254 }
1255
1256 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1257 {
1258         int err;
1259
1260         if (chip->info->ops->ieee_pri_map) {
1261                 err = chip->info->ops->ieee_pri_map(chip);
1262                 if (err)
1263                         return err;
1264         }
1265
1266         if (chip->info->ops->ip_pri_map) {
1267                 err = chip->info->ops->ip_pri_map(chip);
1268                 if (err)
1269                         return err;
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1276 {
1277         struct dsa_switch *ds = chip->ds;
1278         int target, port;
1279         int err;
1280
1281         if (!chip->info->global2_addr)
1282                 return 0;
1283
1284         /* Initialize the routing port to the 32 possible target devices */
1285         for (target = 0; target < 32; target++) {
1286                 port = dsa_routing_port(ds, target);
1287                 if (port == ds->num_ports)
1288                         port = 0x1f;
1289
1290                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1291                 if (err)
1292                         return err;
1293         }
1294
1295         if (chip->info->ops->set_cascade_port) {
1296                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1297                 err = chip->info->ops->set_cascade_port(chip, port);
1298                 if (err)
1299                         return err;
1300         }
1301
1302         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1303         if (err)
1304                 return err;
1305
1306         return 0;
1307 }
1308
1309 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1310 {
1311         /* Clear all trunk masks and mapping */
1312         if (chip->info->global2_addr)
1313                 return mv88e6xxx_g2_trunk_clear(chip);
1314
1315         return 0;
1316 }
1317
1318 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1319 {
1320         if (chip->info->ops->rmu_disable)
1321                 return chip->info->ops->rmu_disable(chip);
1322
1323         return 0;
1324 }
1325
1326 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1327 {
1328         if (chip->info->ops->pot_clear)
1329                 return chip->info->ops->pot_clear(chip);
1330
1331         return 0;
1332 }
1333
1334 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1335 {
1336         if (chip->info->ops->mgmt_rsvd2cpu)
1337                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1338
1339         return 0;
1340 }
1341
1342 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1343 {
1344         int err;
1345
1346         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1347         if (err)
1348                 return err;
1349
1350         /* The chips that have a "learn2all" bit in Global1, ATU
1351          * Control are precisely those whose port registers have a
1352          * Message Port bit in Port Control 1 and hence implement
1353          * ->port_setup_message_port.
1354          */
1355         if (chip->info->ops->port_setup_message_port) {
1356                 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1357                 if (err)
1358                         return err;
1359         }
1360
1361         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1362 }
1363
1364 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1365 {
1366         int port;
1367         int err;
1368
1369         if (!chip->info->ops->irl_init_all)
1370                 return 0;
1371
1372         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1373                 /* Disable ingress rate limiting by resetting all per port
1374                  * ingress rate limit resources to their initial state.
1375                  */
1376                 err = chip->info->ops->irl_init_all(chip, port);
1377                 if (err)
1378                         return err;
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1385 {
1386         if (chip->info->ops->set_switch_mac) {
1387                 u8 addr[ETH_ALEN];
1388
1389                 eth_random_addr(addr);
1390
1391                 return chip->info->ops->set_switch_mac(chip, addr);
1392         }
1393
1394         return 0;
1395 }
1396
1397 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1398 {
1399         u16 pvlan = 0;
1400
1401         if (!mv88e6xxx_has_pvt(chip))
1402                 return 0;
1403
1404         /* Skip the local source device, which uses in-chip port VLAN */
1405         if (dev != chip->ds->index)
1406                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1407
1408         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1409 }
1410
1411 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1412 {
1413         int dev, port;
1414         int err;
1415
1416         if (!mv88e6xxx_has_pvt(chip))
1417                 return 0;
1418
1419         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1420          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1421          */
1422         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1423         if (err)
1424                 return err;
1425
1426         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1427                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1428                         err = mv88e6xxx_pvt_map(chip, dev, port);
1429                         if (err)
1430                                 return err;
1431                 }
1432         }
1433
1434         return 0;
1435 }
1436
1437 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1438 {
1439         struct mv88e6xxx_chip *chip = ds->priv;
1440         int err;
1441
1442         mv88e6xxx_reg_lock(chip);
1443         err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1444         mv88e6xxx_reg_unlock(chip);
1445
1446         if (err)
1447                 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1448 }
1449
1450 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1451 {
1452         if (!mv88e6xxx_max_vid(chip))
1453                 return 0;
1454
1455         return mv88e6xxx_g1_vtu_flush(chip);
1456 }
1457
1458 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1459                                  struct mv88e6xxx_vtu_entry *entry)
1460 {
1461         if (!chip->info->ops->vtu_getnext)
1462                 return -EOPNOTSUPP;
1463
1464         return chip->info->ops->vtu_getnext(chip, entry);
1465 }
1466
1467 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1468                                    struct mv88e6xxx_vtu_entry *entry)
1469 {
1470         if (!chip->info->ops->vtu_loadpurge)
1471                 return -EOPNOTSUPP;
1472
1473         return chip->info->ops->vtu_loadpurge(chip, entry);
1474 }
1475
1476 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1477 {
1478         struct mv88e6xxx_vtu_entry vlan;
1479         int i, err;
1480         u16 fid;
1481
1482         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1483
1484         /* Set every FID bit used by the (un)bridged ports */
1485         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1486                 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1487                 if (err)
1488                         return err;
1489
1490                 set_bit(fid, fid_bitmap);
1491         }
1492
1493         /* Set every FID bit used by the VLAN entries */
1494         vlan.vid = mv88e6xxx_max_vid(chip);
1495         vlan.valid = false;
1496
1497         do {
1498                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1499                 if (err)
1500                         return err;
1501
1502                 if (!vlan.valid)
1503                         break;
1504
1505                 set_bit(vlan.fid, fid_bitmap);
1506         } while (vlan.vid < mv88e6xxx_max_vid(chip));
1507
1508         return 0;
1509 }
1510
1511 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1512 {
1513         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1514         int err;
1515
1516         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1517         if (err)
1518                 return err;
1519
1520         /* The reset value 0x000 is used to indicate that multiple address
1521          * databases are not needed. Return the next positive available.
1522          */
1523         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1524         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1525                 return -ENOSPC;
1526
1527         /* Clear the database */
1528         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1529 }
1530
1531 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1532                                         u16 vid_begin, u16 vid_end)
1533 {
1534         struct mv88e6xxx_chip *chip = ds->priv;
1535         struct mv88e6xxx_vtu_entry vlan;
1536         int i, err;
1537
1538         /* DSA and CPU ports have to be members of multiple vlans */
1539         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1540                 return 0;
1541
1542         if (!vid_begin)
1543                 return -EOPNOTSUPP;
1544
1545         vlan.vid = vid_begin - 1;
1546         vlan.valid = false;
1547
1548         do {
1549                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1550                 if (err)
1551                         return err;
1552
1553                 if (!vlan.valid)
1554                         break;
1555
1556                 if (vlan.vid > vid_end)
1557                         break;
1558
1559                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1560                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1561                                 continue;
1562
1563                         if (!dsa_to_port(ds, i)->slave)
1564                                 continue;
1565
1566                         if (vlan.member[i] ==
1567                             MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1568                                 continue;
1569
1570                         if (dsa_to_port(ds, i)->bridge_dev ==
1571                             dsa_to_port(ds, port)->bridge_dev)
1572                                 break; /* same bridge, check next VLAN */
1573
1574                         if (!dsa_to_port(ds, i)->bridge_dev)
1575                                 continue;
1576
1577                         dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1578                                 port, vlan.vid, i,
1579                                 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1580                         return -EOPNOTSUPP;
1581                 }
1582         } while (vlan.vid < vid_end);
1583
1584         return 0;
1585 }
1586
1587 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1588                                          bool vlan_filtering,
1589                                          struct switchdev_trans *trans)
1590 {
1591         struct mv88e6xxx_chip *chip = ds->priv;
1592         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1593                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1594         int err;
1595
1596         if (switchdev_trans_ph_prepare(trans))
1597                 return mv88e6xxx_max_vid(chip) ? 0 : -EOPNOTSUPP;
1598
1599         mv88e6xxx_reg_lock(chip);
1600         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1601         mv88e6xxx_reg_unlock(chip);
1602
1603         return err;
1604 }
1605
1606 static int
1607 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1608                             const struct switchdev_obj_port_vlan *vlan)
1609 {
1610         struct mv88e6xxx_chip *chip = ds->priv;
1611         int err;
1612
1613         if (!mv88e6xxx_max_vid(chip))
1614                 return -EOPNOTSUPP;
1615
1616         /* If the requested port doesn't belong to the same bridge as the VLAN
1617          * members, do not support it (yet) and fallback to software VLAN.
1618          */
1619         mv88e6xxx_reg_lock(chip);
1620         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1621                                            vlan->vid_end);
1622         mv88e6xxx_reg_unlock(chip);
1623
1624         /* We don't need any dynamic resource from the kernel (yet),
1625          * so skip the prepare phase.
1626          */
1627         return err;
1628 }
1629
1630 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1631                                         const unsigned char *addr, u16 vid,
1632                                         u8 state)
1633 {
1634         struct mv88e6xxx_atu_entry entry;
1635         struct mv88e6xxx_vtu_entry vlan;
1636         u16 fid;
1637         int err;
1638
1639         /* Null VLAN ID corresponds to the port private database */
1640         if (vid == 0) {
1641                 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1642                 if (err)
1643                         return err;
1644         } else {
1645                 vlan.vid = vid - 1;
1646                 vlan.valid = false;
1647
1648                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1649                 if (err)
1650                         return err;
1651
1652                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1653                 if (vlan.vid != vid || !vlan.valid)
1654                         return -EOPNOTSUPP;
1655
1656                 fid = vlan.fid;
1657         }
1658
1659         entry.state = 0;
1660         ether_addr_copy(entry.mac, addr);
1661         eth_addr_dec(entry.mac);
1662
1663         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1664         if (err)
1665                 return err;
1666
1667         /* Initialize a fresh ATU entry if it isn't found */
1668         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1669                 memset(&entry, 0, sizeof(entry));
1670                 ether_addr_copy(entry.mac, addr);
1671         }
1672
1673         /* Purge the ATU entry only if no port is using it anymore */
1674         if (!state) {
1675                 entry.portvec &= ~BIT(port);
1676                 if (!entry.portvec)
1677                         entry.state = 0;
1678         } else {
1679                 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1680                         entry.portvec = BIT(port);
1681                 else
1682                         entry.portvec |= BIT(port);
1683
1684                 entry.state = state;
1685         }
1686
1687         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1688 }
1689
1690 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1691                                   const struct mv88e6xxx_policy *policy)
1692 {
1693         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1694         enum mv88e6xxx_policy_action action = policy->action;
1695         const u8 *addr = policy->addr;
1696         u16 vid = policy->vid;
1697         u8 state;
1698         int err;
1699         int id;
1700
1701         if (!chip->info->ops->port_set_policy)
1702                 return -EOPNOTSUPP;
1703
1704         switch (mapping) {
1705         case MV88E6XXX_POLICY_MAPPING_DA:
1706         case MV88E6XXX_POLICY_MAPPING_SA:
1707                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1708                         state = 0; /* Dissociate the port and address */
1709                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1710                          is_multicast_ether_addr(addr))
1711                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1712                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1713                          is_unicast_ether_addr(addr))
1714                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1715                 else
1716                         return -EOPNOTSUPP;
1717
1718                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1719                                                    state);
1720                 if (err)
1721                         return err;
1722                 break;
1723         default:
1724                 return -EOPNOTSUPP;
1725         }
1726
1727         /* Skip the port's policy clearing if the mapping is still in use */
1728         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1729                 idr_for_each_entry(&chip->policies, policy, id)
1730                         if (policy->port == port &&
1731                             policy->mapping == mapping &&
1732                             policy->action != action)
1733                                 return 0;
1734
1735         return chip->info->ops->port_set_policy(chip, port, mapping, action);
1736 }
1737
1738 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1739                                    struct ethtool_rx_flow_spec *fs)
1740 {
1741         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1742         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1743         enum mv88e6xxx_policy_mapping mapping;
1744         enum mv88e6xxx_policy_action action;
1745         struct mv88e6xxx_policy *policy;
1746         u16 vid = 0;
1747         u8 *addr;
1748         int err;
1749         int id;
1750
1751         if (fs->location != RX_CLS_LOC_ANY)
1752                 return -EINVAL;
1753
1754         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1755                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1756         else
1757                 return -EOPNOTSUPP;
1758
1759         switch (fs->flow_type & ~FLOW_EXT) {
1760         case ETHER_FLOW:
1761                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1762                     is_zero_ether_addr(mac_mask->h_source)) {
1763                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
1764                         addr = mac_entry->h_dest;
1765                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1766                     !is_zero_ether_addr(mac_mask->h_source)) {
1767                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
1768                         addr = mac_entry->h_source;
1769                 } else {
1770                         /* Cannot support DA and SA mapping in the same rule */
1771                         return -EOPNOTSUPP;
1772                 }
1773                 break;
1774         default:
1775                 return -EOPNOTSUPP;
1776         }
1777
1778         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1779                 if (fs->m_ext.vlan_tci != htons(0xffff))
1780                         return -EOPNOTSUPP;
1781                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1782         }
1783
1784         idr_for_each_entry(&chip->policies, policy, id) {
1785                 if (policy->port == port && policy->mapping == mapping &&
1786                     policy->action == action && policy->vid == vid &&
1787                     ether_addr_equal(policy->addr, addr))
1788                         return -EEXIST;
1789         }
1790
1791         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1792         if (!policy)
1793                 return -ENOMEM;
1794
1795         fs->location = 0;
1796         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1797                             GFP_KERNEL);
1798         if (err) {
1799                 devm_kfree(chip->dev, policy);
1800                 return err;
1801         }
1802
1803         memcpy(&policy->fs, fs, sizeof(*fs));
1804         ether_addr_copy(policy->addr, addr);
1805         policy->mapping = mapping;
1806         policy->action = action;
1807         policy->port = port;
1808         policy->vid = vid;
1809
1810         err = mv88e6xxx_policy_apply(chip, port, policy);
1811         if (err) {
1812                 idr_remove(&chip->policies, fs->location);
1813                 devm_kfree(chip->dev, policy);
1814                 return err;
1815         }
1816
1817         return 0;
1818 }
1819
1820 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1821                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1822 {
1823         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1824         struct mv88e6xxx_chip *chip = ds->priv;
1825         struct mv88e6xxx_policy *policy;
1826         int err;
1827         int id;
1828
1829         mv88e6xxx_reg_lock(chip);
1830
1831         switch (rxnfc->cmd) {
1832         case ETHTOOL_GRXCLSRLCNT:
1833                 rxnfc->data = 0;
1834                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1835                 rxnfc->rule_cnt = 0;
1836                 idr_for_each_entry(&chip->policies, policy, id)
1837                         if (policy->port == port)
1838                                 rxnfc->rule_cnt++;
1839                 err = 0;
1840                 break;
1841         case ETHTOOL_GRXCLSRULE:
1842                 err = -ENOENT;
1843                 policy = idr_find(&chip->policies, fs->location);
1844                 if (policy) {
1845                         memcpy(fs, &policy->fs, sizeof(*fs));
1846                         err = 0;
1847                 }
1848                 break;
1849         case ETHTOOL_GRXCLSRLALL:
1850                 rxnfc->data = 0;
1851                 rxnfc->rule_cnt = 0;
1852                 idr_for_each_entry(&chip->policies, policy, id)
1853                         if (policy->port == port)
1854                                 rule_locs[rxnfc->rule_cnt++] = id;
1855                 err = 0;
1856                 break;
1857         default:
1858                 err = -EOPNOTSUPP;
1859                 break;
1860         }
1861
1862         mv88e6xxx_reg_unlock(chip);
1863
1864         return err;
1865 }
1866
1867 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1868                                struct ethtool_rxnfc *rxnfc)
1869 {
1870         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1871         struct mv88e6xxx_chip *chip = ds->priv;
1872         struct mv88e6xxx_policy *policy;
1873         int err;
1874
1875         mv88e6xxx_reg_lock(chip);
1876
1877         switch (rxnfc->cmd) {
1878         case ETHTOOL_SRXCLSRLINS:
1879                 err = mv88e6xxx_policy_insert(chip, port, fs);
1880                 break;
1881         case ETHTOOL_SRXCLSRLDEL:
1882                 err = -ENOENT;
1883                 policy = idr_remove(&chip->policies, fs->location);
1884                 if (policy) {
1885                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1886                         err = mv88e6xxx_policy_apply(chip, port, policy);
1887                         devm_kfree(chip->dev, policy);
1888                 }
1889                 break;
1890         default:
1891                 err = -EOPNOTSUPP;
1892                 break;
1893         }
1894
1895         mv88e6xxx_reg_unlock(chip);
1896
1897         return err;
1898 }
1899
1900 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1901                                         u16 vid)
1902 {
1903         const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1904         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1905
1906         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1907 }
1908
1909 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1910 {
1911         int port;
1912         int err;
1913
1914         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1915                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1916                 if (err)
1917                         return err;
1918         }
1919
1920         return 0;
1921 }
1922
1923 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1924                                     u16 vid, u8 member, bool warn)
1925 {
1926         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1927         struct mv88e6xxx_vtu_entry vlan;
1928         int i, err;
1929
1930         if (!vid)
1931                 return -EOPNOTSUPP;
1932
1933         vlan.vid = vid - 1;
1934         vlan.valid = false;
1935
1936         err = mv88e6xxx_vtu_getnext(chip, &vlan);
1937         if (err)
1938                 return err;
1939
1940         if (vlan.vid != vid || !vlan.valid) {
1941                 memset(&vlan, 0, sizeof(vlan));
1942
1943                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1944                 if (err)
1945                         return err;
1946
1947                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1948                         if (i == port)
1949                                 vlan.member[i] = member;
1950                         else
1951                                 vlan.member[i] = non_member;
1952
1953                 vlan.vid = vid;
1954                 vlan.valid = true;
1955
1956                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1957                 if (err)
1958                         return err;
1959
1960                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1961                 if (err)
1962                         return err;
1963         } else if (vlan.member[port] != member) {
1964                 vlan.member[port] = member;
1965
1966                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1967                 if (err)
1968                         return err;
1969         } else if (warn) {
1970                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1971                          port, vid);
1972         }
1973
1974         return 0;
1975 }
1976
1977 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1978                                     const struct switchdev_obj_port_vlan *vlan)
1979 {
1980         struct mv88e6xxx_chip *chip = ds->priv;
1981         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1982         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1983         bool warn;
1984         u8 member;
1985         u16 vid;
1986
1987         if (!mv88e6xxx_max_vid(chip))
1988                 return;
1989
1990         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1991                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1992         else if (untagged)
1993                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1994         else
1995                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1996
1997         /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
1998          * and then the CPU port. Do not warn for duplicates for the CPU port.
1999          */
2000         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2001
2002         mv88e6xxx_reg_lock(chip);
2003
2004         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2005                 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
2006                         dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2007                                 vid, untagged ? 'u' : 't');
2008
2009         if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
2010                 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
2011                         vlan->vid_end);
2012
2013         mv88e6xxx_reg_unlock(chip);
2014 }
2015
2016 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2017                                      int port, u16 vid)
2018 {
2019         struct mv88e6xxx_vtu_entry vlan;
2020         int i, err;
2021
2022         if (!vid)
2023                 return -EOPNOTSUPP;
2024
2025         vlan.vid = vid - 1;
2026         vlan.valid = false;
2027
2028         err = mv88e6xxx_vtu_getnext(chip, &vlan);
2029         if (err)
2030                 return err;
2031
2032         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2033          * tell switchdev that this VLAN is likely handled in software.
2034          */
2035         if (vlan.vid != vid || !vlan.valid ||
2036             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2037                 return -EOPNOTSUPP;
2038
2039         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2040
2041         /* keep the VLAN unless all ports are excluded */
2042         vlan.valid = false;
2043         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2044                 if (vlan.member[i] !=
2045                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2046                         vlan.valid = true;
2047                         break;
2048                 }
2049         }
2050
2051         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2052         if (err)
2053                 return err;
2054
2055         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2056 }
2057
2058 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2059                                    const struct switchdev_obj_port_vlan *vlan)
2060 {
2061         struct mv88e6xxx_chip *chip = ds->priv;
2062         u16 pvid, vid;
2063         int err = 0;
2064
2065         if (!mv88e6xxx_max_vid(chip))
2066                 return -EOPNOTSUPP;
2067
2068         mv88e6xxx_reg_lock(chip);
2069
2070         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2071         if (err)
2072                 goto unlock;
2073
2074         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2075                 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
2076                 if (err)
2077                         goto unlock;
2078
2079                 if (vid == pvid) {
2080                         err = mv88e6xxx_port_set_pvid(chip, port, 0);
2081                         if (err)
2082                                 goto unlock;
2083                 }
2084         }
2085
2086 unlock:
2087         mv88e6xxx_reg_unlock(chip);
2088
2089         return err;
2090 }
2091
2092 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2093                                   const unsigned char *addr, u16 vid)
2094 {
2095         struct mv88e6xxx_chip *chip = ds->priv;
2096         int err;
2097
2098         mv88e6xxx_reg_lock(chip);
2099         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2100                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2101         mv88e6xxx_reg_unlock(chip);
2102
2103         return err;
2104 }
2105
2106 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2107                                   const unsigned char *addr, u16 vid)
2108 {
2109         struct mv88e6xxx_chip *chip = ds->priv;
2110         int err;
2111
2112         mv88e6xxx_reg_lock(chip);
2113         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2114         mv88e6xxx_reg_unlock(chip);
2115
2116         return err;
2117 }
2118
2119 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2120                                       u16 fid, u16 vid, int port,
2121                                       dsa_fdb_dump_cb_t *cb, void *data)
2122 {
2123         struct mv88e6xxx_atu_entry addr;
2124         bool is_static;
2125         int err;
2126
2127         addr.state = 0;
2128         eth_broadcast_addr(addr.mac);
2129
2130         do {
2131                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2132                 if (err)
2133                         return err;
2134
2135                 if (!addr.state)
2136                         break;
2137
2138                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2139                         continue;
2140
2141                 if (!is_unicast_ether_addr(addr.mac))
2142                         continue;
2143
2144                 is_static = (addr.state ==
2145                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2146                 err = cb(addr.mac, vid, is_static, data);
2147                 if (err)
2148                         return err;
2149         } while (!is_broadcast_ether_addr(addr.mac));
2150
2151         return err;
2152 }
2153
2154 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2155                                   dsa_fdb_dump_cb_t *cb, void *data)
2156 {
2157         struct mv88e6xxx_vtu_entry vlan;
2158         u16 fid;
2159         int err;
2160
2161         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2162         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2163         if (err)
2164                 return err;
2165
2166         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2167         if (err)
2168                 return err;
2169
2170         /* Dump VLANs' Filtering Information Databases */
2171         vlan.vid = mv88e6xxx_max_vid(chip);
2172         vlan.valid = false;
2173
2174         do {
2175                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2176                 if (err)
2177                         return err;
2178
2179                 if (!vlan.valid)
2180                         break;
2181
2182                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2183                                                  cb, data);
2184                 if (err)
2185                         return err;
2186         } while (vlan.vid < mv88e6xxx_max_vid(chip));
2187
2188         return err;
2189 }
2190
2191 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2192                                    dsa_fdb_dump_cb_t *cb, void *data)
2193 {
2194         struct mv88e6xxx_chip *chip = ds->priv;
2195         int err;
2196
2197         mv88e6xxx_reg_lock(chip);
2198         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2199         mv88e6xxx_reg_unlock(chip);
2200
2201         return err;
2202 }
2203
2204 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2205                                 struct net_device *br)
2206 {
2207         struct dsa_switch *ds = chip->ds;
2208         struct dsa_switch_tree *dst = ds->dst;
2209         struct dsa_port *dp;
2210         int err;
2211
2212         list_for_each_entry(dp, &dst->ports, list) {
2213                 if (dp->bridge_dev == br) {
2214                         if (dp->ds == ds) {
2215                                 /* This is a local bridge group member,
2216                                  * remap its Port VLAN Map.
2217                                  */
2218                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2219                                 if (err)
2220                                         return err;
2221                         } else {
2222                                 /* This is an external bridge group member,
2223                                  * remap its cross-chip Port VLAN Table entry.
2224                                  */
2225                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2226                                                         dp->index);
2227                                 if (err)
2228                                         return err;
2229                         }
2230                 }
2231         }
2232
2233         return 0;
2234 }
2235
2236 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2237                                       struct net_device *br)
2238 {
2239         struct mv88e6xxx_chip *chip = ds->priv;
2240         int err;
2241
2242         mv88e6xxx_reg_lock(chip);
2243         err = mv88e6xxx_bridge_map(chip, br);
2244         mv88e6xxx_reg_unlock(chip);
2245
2246         return err;
2247 }
2248
2249 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2250                                         struct net_device *br)
2251 {
2252         struct mv88e6xxx_chip *chip = ds->priv;
2253
2254         mv88e6xxx_reg_lock(chip);
2255         if (mv88e6xxx_bridge_map(chip, br) ||
2256             mv88e6xxx_port_vlan_map(chip, port))
2257                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2258         mv88e6xxx_reg_unlock(chip);
2259 }
2260
2261 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2262                                            int tree_index, int sw_index,
2263                                            int port, struct net_device *br)
2264 {
2265         struct mv88e6xxx_chip *chip = ds->priv;
2266         int err;
2267
2268         if (tree_index != ds->dst->index)
2269                 return 0;
2270
2271         mv88e6xxx_reg_lock(chip);
2272         err = mv88e6xxx_pvt_map(chip, sw_index, port);
2273         mv88e6xxx_reg_unlock(chip);
2274
2275         return err;
2276 }
2277
2278 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2279                                              int tree_index, int sw_index,
2280                                              int port, struct net_device *br)
2281 {
2282         struct mv88e6xxx_chip *chip = ds->priv;
2283
2284         if (tree_index != ds->dst->index)
2285                 return;
2286
2287         mv88e6xxx_reg_lock(chip);
2288         if (mv88e6xxx_pvt_map(chip, sw_index, port))
2289                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2290         mv88e6xxx_reg_unlock(chip);
2291 }
2292
2293 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2294 {
2295         if (chip->info->ops->reset)
2296                 return chip->info->ops->reset(chip);
2297
2298         return 0;
2299 }
2300
2301 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2302 {
2303         struct gpio_desc *gpiod = chip->reset;
2304
2305         /* If there is a GPIO connected to the reset pin, toggle it */
2306         if (gpiod) {
2307                 gpiod_set_value_cansleep(gpiod, 1);
2308                 usleep_range(10000, 20000);
2309                 gpiod_set_value_cansleep(gpiod, 0);
2310                 usleep_range(10000, 20000);
2311
2312                 mv88e6xxx_g1_wait_eeprom_done(chip);
2313         }
2314 }
2315
2316 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2317 {
2318         int i, err;
2319
2320         /* Set all ports to the Disabled state */
2321         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2322                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2323                 if (err)
2324                         return err;
2325         }
2326
2327         /* Wait for transmit queues to drain,
2328          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2329          */
2330         usleep_range(2000, 4000);
2331
2332         return 0;
2333 }
2334
2335 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2336 {
2337         int err;
2338
2339         err = mv88e6xxx_disable_ports(chip);
2340         if (err)
2341                 return err;
2342
2343         mv88e6xxx_hardware_reset(chip);
2344
2345         return mv88e6xxx_software_reset(chip);
2346 }
2347
2348 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2349                                    enum mv88e6xxx_frame_mode frame,
2350                                    enum mv88e6xxx_egress_mode egress, u16 etype)
2351 {
2352         int err;
2353
2354         if (!chip->info->ops->port_set_frame_mode)
2355                 return -EOPNOTSUPP;
2356
2357         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2358         if (err)
2359                 return err;
2360
2361         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2362         if (err)
2363                 return err;
2364
2365         if (chip->info->ops->port_set_ether_type)
2366                 return chip->info->ops->port_set_ether_type(chip, port, etype);
2367
2368         return 0;
2369 }
2370
2371 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2372 {
2373         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2374                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2375                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2376 }
2377
2378 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2379 {
2380         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2381                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2382                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2383 }
2384
2385 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2386 {
2387         return mv88e6xxx_set_port_mode(chip, port,
2388                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
2389                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2390                                        ETH_P_EDSA);
2391 }
2392
2393 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2394 {
2395         if (dsa_is_dsa_port(chip->ds, port))
2396                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2397
2398         if (dsa_is_user_port(chip->ds, port))
2399                 return mv88e6xxx_set_port_mode_normal(chip, port);
2400
2401         /* Setup CPU port mode depending on its supported tag format */
2402         if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2403                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2404
2405         if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2406                 return mv88e6xxx_set_port_mode_edsa(chip, port);
2407
2408         return -EINVAL;
2409 }
2410
2411 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2412 {
2413         bool message = dsa_is_dsa_port(chip->ds, port);
2414
2415         return mv88e6xxx_port_set_message_port(chip, port, message);
2416 }
2417
2418 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2419 {
2420         struct dsa_switch *ds = chip->ds;
2421         bool flood;
2422
2423         /* Upstream ports flood frames with unknown unicast or multicast DA */
2424         flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2425         if (chip->info->ops->port_set_egress_floods)
2426                 return chip->info->ops->port_set_egress_floods(chip, port,
2427                                                                flood, flood);
2428
2429         return 0;
2430 }
2431
2432 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2433 {
2434         struct mv88e6xxx_port *mvp = dev_id;
2435         struct mv88e6xxx_chip *chip = mvp->chip;
2436         irqreturn_t ret = IRQ_NONE;
2437         int port = mvp->port;
2438         u8 lane;
2439
2440         mv88e6xxx_reg_lock(chip);
2441         lane = mv88e6xxx_serdes_get_lane(chip, port);
2442         if (lane)
2443                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2444         mv88e6xxx_reg_unlock(chip);
2445
2446         return ret;
2447 }
2448
2449 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2450                                         u8 lane)
2451 {
2452         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2453         unsigned int irq;
2454         int err;
2455
2456         /* Nothing to request if this SERDES port has no IRQ */
2457         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2458         if (!irq)
2459                 return 0;
2460
2461         snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2462                  "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2463
2464         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2465         mv88e6xxx_reg_unlock(chip);
2466         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2467                                    IRQF_ONESHOT, dev_id->serdes_irq_name,
2468                                    dev_id);
2469         mv88e6xxx_reg_lock(chip);
2470         if (err)
2471                 return err;
2472
2473         dev_id->serdes_irq = irq;
2474
2475         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2476 }
2477
2478 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2479                                      u8 lane)
2480 {
2481         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2482         unsigned int irq = dev_id->serdes_irq;
2483         int err;
2484
2485         /* Nothing to free if no IRQ has been requested */
2486         if (!irq)
2487                 return 0;
2488
2489         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2490
2491         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2492         mv88e6xxx_reg_unlock(chip);
2493         free_irq(irq, dev_id);
2494         mv88e6xxx_reg_lock(chip);
2495
2496         dev_id->serdes_irq = 0;
2497
2498         return err;
2499 }
2500
2501 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2502                                   bool on)
2503 {
2504         u8 lane;
2505         int err;
2506
2507         lane = mv88e6xxx_serdes_get_lane(chip, port);
2508         if (!lane)
2509                 return 0;
2510
2511         if (on) {
2512                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2513                 if (err)
2514                         return err;
2515
2516                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2517         } else {
2518                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2519                 if (err)
2520                         return err;
2521
2522                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2523         }
2524
2525         return err;
2526 }
2527
2528 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2529 {
2530         struct dsa_switch *ds = chip->ds;
2531         int upstream_port;
2532         int err;
2533
2534         upstream_port = dsa_upstream_port(ds, port);
2535         if (chip->info->ops->port_set_upstream_port) {
2536                 err = chip->info->ops->port_set_upstream_port(chip, port,
2537                                                               upstream_port);
2538                 if (err)
2539                         return err;
2540         }
2541
2542         if (port == upstream_port) {
2543                 if (chip->info->ops->set_cpu_port) {
2544                         err = chip->info->ops->set_cpu_port(chip,
2545                                                             upstream_port);
2546                         if (err)
2547                                 return err;
2548                 }
2549
2550                 if (chip->info->ops->set_egress_port) {
2551                         err = chip->info->ops->set_egress_port(chip,
2552                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
2553                                                 upstream_port);
2554                         if (err)
2555                                 return err;
2556
2557                         err = chip->info->ops->set_egress_port(chip,
2558                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
2559                                                 upstream_port);
2560                         if (err)
2561                                 return err;
2562                 }
2563         }
2564
2565         return 0;
2566 }
2567
2568 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2569 {
2570         struct dsa_switch *ds = chip->ds;
2571         int err;
2572         u16 reg;
2573
2574         chip->ports[port].chip = chip;
2575         chip->ports[port].port = port;
2576
2577         /* MAC Forcing register: don't force link, speed, duplex or flow control
2578          * state to any particular values on physical ports, but force the CPU
2579          * port and all DSA ports to their maximum bandwidth and full duplex.
2580          */
2581         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2582                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2583                                                SPEED_MAX, DUPLEX_FULL,
2584                                                PAUSE_OFF,
2585                                                PHY_INTERFACE_MODE_NA);
2586         else
2587                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2588                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2589                                                PAUSE_ON,
2590                                                PHY_INTERFACE_MODE_NA);
2591         if (err)
2592                 return err;
2593
2594         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2595          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2596          * tunneling, determine priority by looking at 802.1p and IP
2597          * priority fields (IP prio has precedence), and set STP state
2598          * to Forwarding.
2599          *
2600          * If this is the CPU link, use DSA or EDSA tagging depending
2601          * on which tagging mode was configured.
2602          *
2603          * If this is a link to another switch, use DSA tagging mode.
2604          *
2605          * If this is the upstream port for this switch, enable
2606          * forwarding of unknown unicasts and multicasts.
2607          */
2608         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2609                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2610                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2611         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2612         if (err)
2613                 return err;
2614
2615         err = mv88e6xxx_setup_port_mode(chip, port);
2616         if (err)
2617                 return err;
2618
2619         err = mv88e6xxx_setup_egress_floods(chip, port);
2620         if (err)
2621                 return err;
2622
2623         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2624          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2625          * untagged frames on this port, do a destination address lookup on all
2626          * received packets as usual, disable ARP mirroring and don't send a
2627          * copy of all transmitted/received frames on this port to the CPU.
2628          */
2629         err = mv88e6xxx_port_set_map_da(chip, port);
2630         if (err)
2631                 return err;
2632
2633         err = mv88e6xxx_setup_upstream_port(chip, port);
2634         if (err)
2635                 return err;
2636
2637         err = mv88e6xxx_port_set_8021q_mode(chip, port,
2638                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2639         if (err)
2640                 return err;
2641
2642         if (chip->info->ops->port_set_jumbo_size) {
2643                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2644                 if (err)
2645                         return err;
2646         }
2647
2648         /* Port Association Vector: when learning source addresses
2649          * of packets, add the address to the address database using
2650          * a port bitmap that has only the bit for this port set and
2651          * the other bits clear.
2652          */
2653         reg = 1 << port;
2654         /* Disable learning for CPU port */
2655         if (dsa_is_cpu_port(ds, port))
2656                 reg = 0;
2657
2658         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2659                                    reg);
2660         if (err)
2661                 return err;
2662
2663         /* Egress rate control 2: disable egress rate control. */
2664         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2665                                    0x0000);
2666         if (err)
2667                 return err;
2668
2669         if (chip->info->ops->port_pause_limit) {
2670                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2671                 if (err)
2672                         return err;
2673         }
2674
2675         if (chip->info->ops->port_disable_learn_limit) {
2676                 err = chip->info->ops->port_disable_learn_limit(chip, port);
2677                 if (err)
2678                         return err;
2679         }
2680
2681         if (chip->info->ops->port_disable_pri_override) {
2682                 err = chip->info->ops->port_disable_pri_override(chip, port);
2683                 if (err)
2684                         return err;
2685         }
2686
2687         if (chip->info->ops->port_tag_remap) {
2688                 err = chip->info->ops->port_tag_remap(chip, port);
2689                 if (err)
2690                         return err;
2691         }
2692
2693         if (chip->info->ops->port_egress_rate_limiting) {
2694                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2695                 if (err)
2696                         return err;
2697         }
2698
2699         if (chip->info->ops->port_setup_message_port) {
2700                 err = chip->info->ops->port_setup_message_port(chip, port);
2701                 if (err)
2702                         return err;
2703         }
2704
2705         /* Port based VLAN map: give each port the same default address
2706          * database, and allow bidirectional communication between the
2707          * CPU and DSA port(s), and the other ports.
2708          */
2709         err = mv88e6xxx_port_set_fid(chip, port, 0);
2710         if (err)
2711                 return err;
2712
2713         err = mv88e6xxx_port_vlan_map(chip, port);
2714         if (err)
2715                 return err;
2716
2717         /* Default VLAN ID and priority: don't set a default VLAN
2718          * ID, and set the default packet priority to zero.
2719          */
2720         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2721 }
2722
2723 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2724 {
2725         struct mv88e6xxx_chip *chip = ds->priv;
2726
2727         if (chip->info->ops->port_set_jumbo_size)
2728                 return 10240;
2729         else if (chip->info->ops->set_max_frame_size)
2730                 return 1632;
2731         return 1522;
2732 }
2733
2734 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2735 {
2736         struct mv88e6xxx_chip *chip = ds->priv;
2737         int ret = 0;
2738
2739         mv88e6xxx_reg_lock(chip);
2740         if (chip->info->ops->port_set_jumbo_size)
2741                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2742         else if (chip->info->ops->set_max_frame_size)
2743                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2744         else
2745                 if (new_mtu > 1522)
2746                         ret = -EINVAL;
2747         mv88e6xxx_reg_unlock(chip);
2748
2749         return ret;
2750 }
2751
2752 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2753                                  struct phy_device *phydev)
2754 {
2755         struct mv88e6xxx_chip *chip = ds->priv;
2756         int err;
2757
2758         mv88e6xxx_reg_lock(chip);
2759         err = mv88e6xxx_serdes_power(chip, port, true);
2760         mv88e6xxx_reg_unlock(chip);
2761
2762         return err;
2763 }
2764
2765 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2766 {
2767         struct mv88e6xxx_chip *chip = ds->priv;
2768
2769         mv88e6xxx_reg_lock(chip);
2770         if (mv88e6xxx_serdes_power(chip, port, false))
2771                 dev_err(chip->dev, "failed to power off SERDES\n");
2772         mv88e6xxx_reg_unlock(chip);
2773 }
2774
2775 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2776                                      unsigned int ageing_time)
2777 {
2778         struct mv88e6xxx_chip *chip = ds->priv;
2779         int err;
2780
2781         mv88e6xxx_reg_lock(chip);
2782         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2783         mv88e6xxx_reg_unlock(chip);
2784
2785         return err;
2786 }
2787
2788 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2789 {
2790         int err;
2791
2792         /* Initialize the statistics unit */
2793         if (chip->info->ops->stats_set_histogram) {
2794                 err = chip->info->ops->stats_set_histogram(chip);
2795                 if (err)
2796                         return err;
2797         }
2798
2799         return mv88e6xxx_g1_stats_clear(chip);
2800 }
2801
2802 /* Check if the errata has already been applied. */
2803 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2804 {
2805         int port;
2806         int err;
2807         u16 val;
2808
2809         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2810                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2811                 if (err) {
2812                         dev_err(chip->dev,
2813                                 "Error reading hidden register: %d\n", err);
2814                         return false;
2815                 }
2816                 if (val != 0x01c0)
2817                         return false;
2818         }
2819
2820         return true;
2821 }
2822
2823 /* The 6390 copper ports have an errata which require poking magic
2824  * values into undocumented hidden registers and then performing a
2825  * software reset.
2826  */
2827 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2828 {
2829         int port;
2830         int err;
2831
2832         if (mv88e6390_setup_errata_applied(chip))
2833                 return 0;
2834
2835         /* Set the ports into blocking mode */
2836         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2837                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2838                 if (err)
2839                         return err;
2840         }
2841
2842         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2843                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2844                 if (err)
2845                         return err;
2846         }
2847
2848         return mv88e6xxx_software_reset(chip);
2849 }
2850
2851 static void mv88e6xxx_teardown(struct dsa_switch *ds)
2852 {
2853         mv88e6xxx_teardown_devlink_params(ds);
2854         dsa_devlink_resources_unregister(ds);
2855         mv88e6xxx_teardown_devlink_regions(ds);
2856 }
2857
2858 static int mv88e6xxx_setup(struct dsa_switch *ds)
2859 {
2860         struct mv88e6xxx_chip *chip = ds->priv;
2861         u8 cmode;
2862         int err;
2863         int i;
2864
2865         chip->ds = ds;
2866         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2867         ds->configure_vlan_while_not_filtering = true;
2868
2869         mv88e6xxx_reg_lock(chip);
2870
2871         if (chip->info->ops->setup_errata) {
2872                 err = chip->info->ops->setup_errata(chip);
2873                 if (err)
2874                         goto unlock;
2875         }
2876
2877         /* Cache the cmode of each port. */
2878         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2879                 if (chip->info->ops->port_get_cmode) {
2880                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2881                         if (err)
2882                                 goto unlock;
2883
2884                         chip->ports[i].cmode = cmode;
2885                 }
2886         }
2887
2888         /* Setup Switch Port Registers */
2889         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2890                 if (dsa_is_unused_port(ds, i))
2891                         continue;
2892
2893                 /* Prevent the use of an invalid port. */
2894                 if (mv88e6xxx_is_invalid_port(chip, i)) {
2895                         dev_err(chip->dev, "port %d is invalid\n", i);
2896                         err = -EINVAL;
2897                         goto unlock;
2898                 }
2899
2900                 err = mv88e6xxx_setup_port(chip, i);
2901                 if (err)
2902                         goto unlock;
2903         }
2904
2905         err = mv88e6xxx_irl_setup(chip);
2906         if (err)
2907                 goto unlock;
2908
2909         err = mv88e6xxx_mac_setup(chip);
2910         if (err)
2911                 goto unlock;
2912
2913         err = mv88e6xxx_phy_setup(chip);
2914         if (err)
2915                 goto unlock;
2916
2917         err = mv88e6xxx_vtu_setup(chip);
2918         if (err)
2919                 goto unlock;
2920
2921         err = mv88e6xxx_pvt_setup(chip);
2922         if (err)
2923                 goto unlock;
2924
2925         err = mv88e6xxx_atu_setup(chip);
2926         if (err)
2927                 goto unlock;
2928
2929         err = mv88e6xxx_broadcast_setup(chip, 0);
2930         if (err)
2931                 goto unlock;
2932
2933         err = mv88e6xxx_pot_setup(chip);
2934         if (err)
2935                 goto unlock;
2936
2937         err = mv88e6xxx_rmu_setup(chip);
2938         if (err)
2939                 goto unlock;
2940
2941         err = mv88e6xxx_rsvd2cpu_setup(chip);
2942         if (err)
2943                 goto unlock;
2944
2945         err = mv88e6xxx_trunk_setup(chip);
2946         if (err)
2947                 goto unlock;
2948
2949         err = mv88e6xxx_devmap_setup(chip);
2950         if (err)
2951                 goto unlock;
2952
2953         err = mv88e6xxx_pri_setup(chip);
2954         if (err)
2955                 goto unlock;
2956
2957         /* Setup PTP Hardware Clock and timestamping */
2958         if (chip->info->ptp_support) {
2959                 err = mv88e6xxx_ptp_setup(chip);
2960                 if (err)
2961                         goto unlock;
2962
2963                 err = mv88e6xxx_hwtstamp_setup(chip);
2964                 if (err)
2965                         goto unlock;
2966         }
2967
2968         err = mv88e6xxx_stats_setup(chip);
2969         if (err)
2970                 goto unlock;
2971
2972 unlock:
2973         mv88e6xxx_reg_unlock(chip);
2974
2975         if (err)
2976                 return err;
2977
2978         /* Have to be called without holding the register lock, since
2979          * they take the devlink lock, and we later take the locks in
2980          * the reverse order when getting/setting parameters or
2981          * resource occupancy.
2982          */
2983         err = mv88e6xxx_setup_devlink_resources(ds);
2984         if (err)
2985                 return err;
2986
2987         err = mv88e6xxx_setup_devlink_params(ds);
2988         if (err)
2989                 goto out_resources;
2990
2991         err = mv88e6xxx_setup_devlink_regions(ds);
2992         if (err)
2993                 goto out_params;
2994
2995         return 0;
2996
2997 out_params:
2998         mv88e6xxx_teardown_devlink_params(ds);
2999 out_resources:
3000         dsa_devlink_resources_unregister(ds);
3001
3002         return err;
3003 }
3004
3005 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3006 {
3007         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3008         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3009         u16 val;
3010         int err;
3011
3012         if (!chip->info->ops->phy_read)
3013                 return -EOPNOTSUPP;
3014
3015         mv88e6xxx_reg_lock(chip);
3016         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3017         mv88e6xxx_reg_unlock(chip);
3018
3019         if (reg == MII_PHYSID2) {
3020                 /* Some internal PHYs don't have a model number. */
3021                 if (chip->info->family != MV88E6XXX_FAMILY_6165)
3022                         /* Then there is the 6165 family. It gets is
3023                          * PHYs correct. But it can also have two
3024                          * SERDES interfaces in the PHY address
3025                          * space. And these don't have a model
3026                          * number. But they are not PHYs, so we don't
3027                          * want to give them something a PHY driver
3028                          * will recognise.
3029                          *
3030                          * Use the mv88e6390 family model number
3031                          * instead, for anything which really could be
3032                          * a PHY,
3033                          */
3034                         if (!(val & 0x3f0))
3035                                 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
3036         }
3037
3038         return err ? err : val;
3039 }
3040
3041 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3042 {
3043         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3044         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3045         int err;
3046
3047         if (!chip->info->ops->phy_write)
3048                 return -EOPNOTSUPP;
3049
3050         mv88e6xxx_reg_lock(chip);
3051         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3052         mv88e6xxx_reg_unlock(chip);
3053
3054         return err;
3055 }
3056
3057 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3058                                    struct device_node *np,
3059                                    bool external)
3060 {
3061         static int index;
3062         struct mv88e6xxx_mdio_bus *mdio_bus;
3063         struct mii_bus *bus;
3064         int err;
3065
3066         if (external) {
3067                 mv88e6xxx_reg_lock(chip);
3068                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3069                 mv88e6xxx_reg_unlock(chip);
3070
3071                 if (err)
3072                         return err;
3073         }
3074
3075         bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3076         if (!bus)
3077                 return -ENOMEM;
3078
3079         mdio_bus = bus->priv;
3080         mdio_bus->bus = bus;
3081         mdio_bus->chip = chip;
3082         INIT_LIST_HEAD(&mdio_bus->list);
3083         mdio_bus->external = external;
3084
3085         if (np) {
3086                 bus->name = np->full_name;
3087                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3088         } else {
3089                 bus->name = "mv88e6xxx SMI";
3090                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3091         }
3092
3093         bus->read = mv88e6xxx_mdio_read;
3094         bus->write = mv88e6xxx_mdio_write;
3095         bus->parent = chip->dev;
3096
3097         if (!external) {
3098                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3099                 if (err)
3100                         return err;
3101         }
3102
3103         err = of_mdiobus_register(bus, np);
3104         if (err) {
3105                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3106                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3107                 return err;
3108         }
3109
3110         if (external)
3111                 list_add_tail(&mdio_bus->list, &chip->mdios);
3112         else
3113                 list_add(&mdio_bus->list, &chip->mdios);
3114
3115         return 0;
3116 }
3117
3118 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3119
3120 {
3121         struct mv88e6xxx_mdio_bus *mdio_bus;
3122         struct mii_bus *bus;
3123
3124         list_for_each_entry(mdio_bus, &chip->mdios, list) {
3125                 bus = mdio_bus->bus;
3126
3127                 if (!mdio_bus->external)
3128                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3129
3130                 mdiobus_unregister(bus);
3131         }
3132 }
3133
3134 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3135                                     struct device_node *np)
3136 {
3137         struct device_node *child;
3138         int err;
3139
3140         /* Always register one mdio bus for the internal/default mdio
3141          * bus. This maybe represented in the device tree, but is
3142          * optional.
3143          */
3144         child = of_get_child_by_name(np, "mdio");
3145         err = mv88e6xxx_mdio_register(chip, child, false);
3146         if (err)
3147                 return err;
3148
3149         /* Walk the device tree, and see if there are any other nodes
3150          * which say they are compatible with the external mdio
3151          * bus.
3152          */
3153         for_each_available_child_of_node(np, child) {
3154                 if (of_device_is_compatible(
3155                             child, "marvell,mv88e6xxx-mdio-external")) {
3156                         err = mv88e6xxx_mdio_register(chip, child, true);
3157                         if (err) {
3158                                 mv88e6xxx_mdios_unregister(chip);
3159                                 of_node_put(child);
3160                                 return err;
3161                         }
3162                 }
3163         }
3164
3165         return 0;
3166 }
3167
3168 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3169 {
3170         struct mv88e6xxx_chip *chip = ds->priv;
3171
3172         return chip->eeprom_len;
3173 }
3174
3175 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3176                                 struct ethtool_eeprom *eeprom, u8 *data)
3177 {
3178         struct mv88e6xxx_chip *chip = ds->priv;
3179         int err;
3180
3181         if (!chip->info->ops->get_eeprom)
3182                 return -EOPNOTSUPP;
3183
3184         mv88e6xxx_reg_lock(chip);
3185         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3186         mv88e6xxx_reg_unlock(chip);
3187
3188         if (err)
3189                 return err;
3190
3191         eeprom->magic = 0xc3ec4951;
3192
3193         return 0;
3194 }
3195
3196 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3197                                 struct ethtool_eeprom *eeprom, u8 *data)
3198 {
3199         struct mv88e6xxx_chip *chip = ds->priv;
3200         int err;
3201
3202         if (!chip->info->ops->set_eeprom)
3203                 return -EOPNOTSUPP;
3204
3205         if (eeprom->magic != 0xc3ec4951)
3206                 return -EINVAL;
3207
3208         mv88e6xxx_reg_lock(chip);
3209         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3210         mv88e6xxx_reg_unlock(chip);
3211
3212         return err;
3213 }
3214
3215 static const struct mv88e6xxx_ops mv88e6085_ops = {
3216         /* MV88E6XXX_FAMILY_6097 */
3217         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3218         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3219         .irl_init_all = mv88e6352_g2_irl_init_all,
3220         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3221         .phy_read = mv88e6185_phy_ppu_read,
3222         .phy_write = mv88e6185_phy_ppu_write,
3223         .port_set_link = mv88e6xxx_port_set_link,
3224         .port_sync_link = mv88e6xxx_port_sync_link,
3225         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3226         .port_tag_remap = mv88e6095_port_tag_remap,
3227         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3228         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3229         .port_set_ether_type = mv88e6351_port_set_ether_type,
3230         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3231         .port_pause_limit = mv88e6097_port_pause_limit,
3232         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3233         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3234         .port_get_cmode = mv88e6185_port_get_cmode,
3235         .port_setup_message_port = mv88e6xxx_setup_message_port,
3236         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3237         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3238         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3239         .stats_get_strings = mv88e6095_stats_get_strings,
3240         .stats_get_stats = mv88e6095_stats_get_stats,
3241         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3242         .set_egress_port = mv88e6095_g1_set_egress_port,
3243         .watchdog_ops = &mv88e6097_watchdog_ops,
3244         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3245         .pot_clear = mv88e6xxx_g2_pot_clear,
3246         .ppu_enable = mv88e6185_g1_ppu_enable,
3247         .ppu_disable = mv88e6185_g1_ppu_disable,
3248         .reset = mv88e6185_g1_reset,
3249         .rmu_disable = mv88e6085_g1_rmu_disable,
3250         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3251         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3252         .phylink_validate = mv88e6185_phylink_validate,
3253         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3254 };
3255
3256 static const struct mv88e6xxx_ops mv88e6095_ops = {
3257         /* MV88E6XXX_FAMILY_6095 */
3258         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3259         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3260         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3261         .phy_read = mv88e6185_phy_ppu_read,
3262         .phy_write = mv88e6185_phy_ppu_write,
3263         .port_set_link = mv88e6xxx_port_set_link,
3264         .port_sync_link = mv88e6185_port_sync_link,
3265         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3266         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3267         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3268         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3269         .port_get_cmode = mv88e6185_port_get_cmode,
3270         .port_setup_message_port = mv88e6xxx_setup_message_port,
3271         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3272         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3273         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3274         .stats_get_strings = mv88e6095_stats_get_strings,
3275         .stats_get_stats = mv88e6095_stats_get_stats,
3276         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3277         .serdes_power = mv88e6185_serdes_power,
3278         .serdes_get_lane = mv88e6185_serdes_get_lane,
3279         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3280         .ppu_enable = mv88e6185_g1_ppu_enable,
3281         .ppu_disable = mv88e6185_g1_ppu_disable,
3282         .reset = mv88e6185_g1_reset,
3283         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3284         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3285         .phylink_validate = mv88e6185_phylink_validate,
3286         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3287 };
3288
3289 static const struct mv88e6xxx_ops mv88e6097_ops = {
3290         /* MV88E6XXX_FAMILY_6097 */
3291         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3292         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3293         .irl_init_all = mv88e6352_g2_irl_init_all,
3294         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3295         .phy_read = mv88e6xxx_g2_smi_phy_read,
3296         .phy_write = mv88e6xxx_g2_smi_phy_write,
3297         .port_set_link = mv88e6xxx_port_set_link,
3298         .port_sync_link = mv88e6185_port_sync_link,
3299         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3300         .port_tag_remap = mv88e6095_port_tag_remap,
3301         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3302         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3303         .port_set_ether_type = mv88e6351_port_set_ether_type,
3304         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3305         .port_pause_limit = mv88e6097_port_pause_limit,
3306         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3307         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3308         .port_get_cmode = mv88e6185_port_get_cmode,
3309         .port_setup_message_port = mv88e6xxx_setup_message_port,
3310         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3311         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3312         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3313         .stats_get_strings = mv88e6095_stats_get_strings,
3314         .stats_get_stats = mv88e6095_stats_get_stats,
3315         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3316         .set_egress_port = mv88e6095_g1_set_egress_port,
3317         .watchdog_ops = &mv88e6097_watchdog_ops,
3318         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3319         .serdes_power = mv88e6185_serdes_power,
3320         .serdes_get_lane = mv88e6185_serdes_get_lane,
3321         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3322         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3323         .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3324         .serdes_irq_status = mv88e6097_serdes_irq_status,
3325         .pot_clear = mv88e6xxx_g2_pot_clear,
3326         .reset = mv88e6352_g1_reset,
3327         .rmu_disable = mv88e6085_g1_rmu_disable,
3328         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3329         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3330         .phylink_validate = mv88e6185_phylink_validate,
3331         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3332 };
3333
3334 static const struct mv88e6xxx_ops mv88e6123_ops = {
3335         /* MV88E6XXX_FAMILY_6165 */
3336         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3337         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3338         .irl_init_all = mv88e6352_g2_irl_init_all,
3339         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3340         .phy_read = mv88e6xxx_g2_smi_phy_read,
3341         .phy_write = mv88e6xxx_g2_smi_phy_write,
3342         .port_set_link = mv88e6xxx_port_set_link,
3343         .port_sync_link = mv88e6xxx_port_sync_link,
3344         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3345         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3346         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3347         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3348         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3349         .port_get_cmode = mv88e6185_port_get_cmode,
3350         .port_setup_message_port = mv88e6xxx_setup_message_port,
3351         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3352         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3353         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3354         .stats_get_strings = mv88e6095_stats_get_strings,
3355         .stats_get_stats = mv88e6095_stats_get_stats,
3356         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3357         .set_egress_port = mv88e6095_g1_set_egress_port,
3358         .watchdog_ops = &mv88e6097_watchdog_ops,
3359         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3360         .pot_clear = mv88e6xxx_g2_pot_clear,
3361         .reset = mv88e6352_g1_reset,
3362         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3363         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3364         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3365         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3366         .phylink_validate = mv88e6185_phylink_validate,
3367         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3368 };
3369
3370 static const struct mv88e6xxx_ops mv88e6131_ops = {
3371         /* MV88E6XXX_FAMILY_6185 */
3372         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3373         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3374         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3375         .phy_read = mv88e6185_phy_ppu_read,
3376         .phy_write = mv88e6185_phy_ppu_write,
3377         .port_set_link = mv88e6xxx_port_set_link,
3378         .port_sync_link = mv88e6xxx_port_sync_link,
3379         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3380         .port_tag_remap = mv88e6095_port_tag_remap,
3381         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3382         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3383         .port_set_ether_type = mv88e6351_port_set_ether_type,
3384         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3385         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3386         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3387         .port_pause_limit = mv88e6097_port_pause_limit,
3388         .port_set_pause = mv88e6185_port_set_pause,
3389         .port_get_cmode = mv88e6185_port_get_cmode,
3390         .port_setup_message_port = mv88e6xxx_setup_message_port,
3391         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3392         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3393         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3394         .stats_get_strings = mv88e6095_stats_get_strings,
3395         .stats_get_stats = mv88e6095_stats_get_stats,
3396         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3397         .set_egress_port = mv88e6095_g1_set_egress_port,
3398         .watchdog_ops = &mv88e6097_watchdog_ops,
3399         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3400         .ppu_enable = mv88e6185_g1_ppu_enable,
3401         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3402         .ppu_disable = mv88e6185_g1_ppu_disable,
3403         .reset = mv88e6185_g1_reset,
3404         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3405         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3406         .phylink_validate = mv88e6185_phylink_validate,
3407 };
3408
3409 static const struct mv88e6xxx_ops mv88e6141_ops = {
3410         /* MV88E6XXX_FAMILY_6341 */
3411         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3412         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3413         .irl_init_all = mv88e6352_g2_irl_init_all,
3414         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3415         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3416         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3417         .phy_read = mv88e6xxx_g2_smi_phy_read,
3418         .phy_write = mv88e6xxx_g2_smi_phy_write,
3419         .port_set_link = mv88e6xxx_port_set_link,
3420         .port_sync_link = mv88e6xxx_port_sync_link,
3421         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3422         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3423         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3424         .port_tag_remap = mv88e6095_port_tag_remap,
3425         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3426         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3427         .port_set_ether_type = mv88e6351_port_set_ether_type,
3428         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3429         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3430         .port_pause_limit = mv88e6097_port_pause_limit,
3431         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3432         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3433         .port_get_cmode = mv88e6352_port_get_cmode,
3434         .port_set_cmode = mv88e6341_port_set_cmode,
3435         .port_setup_message_port = mv88e6xxx_setup_message_port,
3436         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3437         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3438         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3439         .stats_get_strings = mv88e6320_stats_get_strings,
3440         .stats_get_stats = mv88e6390_stats_get_stats,
3441         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3442         .set_egress_port = mv88e6390_g1_set_egress_port,
3443         .watchdog_ops = &mv88e6390_watchdog_ops,
3444         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3445         .pot_clear = mv88e6xxx_g2_pot_clear,
3446         .reset = mv88e6352_g1_reset,
3447         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3448         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3449         .serdes_power = mv88e6390_serdes_power,
3450         .serdes_get_lane = mv88e6341_serdes_get_lane,
3451         /* Check status register pause & lpa register */
3452         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3453         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3454         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3455         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3456         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3457         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3458         .serdes_irq_status = mv88e6390_serdes_irq_status,
3459         .gpio_ops = &mv88e6352_gpio_ops,
3460         .phylink_validate = mv88e6341_phylink_validate,
3461 };
3462
3463 static const struct mv88e6xxx_ops mv88e6161_ops = {
3464         /* MV88E6XXX_FAMILY_6165 */
3465         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3466         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3467         .irl_init_all = mv88e6352_g2_irl_init_all,
3468         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3469         .phy_read = mv88e6xxx_g2_smi_phy_read,
3470         .phy_write = mv88e6xxx_g2_smi_phy_write,
3471         .port_set_link = mv88e6xxx_port_set_link,
3472         .port_sync_link = mv88e6xxx_port_sync_link,
3473         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3474         .port_tag_remap = mv88e6095_port_tag_remap,
3475         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3476         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3477         .port_set_ether_type = mv88e6351_port_set_ether_type,
3478         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3479         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3480         .port_pause_limit = mv88e6097_port_pause_limit,
3481         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3482         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3483         .port_get_cmode = mv88e6185_port_get_cmode,
3484         .port_setup_message_port = mv88e6xxx_setup_message_port,
3485         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3486         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3487         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3488         .stats_get_strings = mv88e6095_stats_get_strings,
3489         .stats_get_stats = mv88e6095_stats_get_stats,
3490         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3491         .set_egress_port = mv88e6095_g1_set_egress_port,
3492         .watchdog_ops = &mv88e6097_watchdog_ops,
3493         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3494         .pot_clear = mv88e6xxx_g2_pot_clear,
3495         .reset = mv88e6352_g1_reset,
3496         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3497         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3498         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3499         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3500         .avb_ops = &mv88e6165_avb_ops,
3501         .ptp_ops = &mv88e6165_ptp_ops,
3502         .phylink_validate = mv88e6185_phylink_validate,
3503 };
3504
3505 static const struct mv88e6xxx_ops mv88e6165_ops = {
3506         /* MV88E6XXX_FAMILY_6165 */
3507         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3508         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3509         .irl_init_all = mv88e6352_g2_irl_init_all,
3510         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3511         .phy_read = mv88e6165_phy_read,
3512         .phy_write = mv88e6165_phy_write,
3513         .port_set_link = mv88e6xxx_port_set_link,
3514         .port_sync_link = mv88e6xxx_port_sync_link,
3515         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3516         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3517         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3518         .port_get_cmode = mv88e6185_port_get_cmode,
3519         .port_setup_message_port = mv88e6xxx_setup_message_port,
3520         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3521         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3522         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3523         .stats_get_strings = mv88e6095_stats_get_strings,
3524         .stats_get_stats = mv88e6095_stats_get_stats,
3525         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3526         .set_egress_port = mv88e6095_g1_set_egress_port,
3527         .watchdog_ops = &mv88e6097_watchdog_ops,
3528         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3529         .pot_clear = mv88e6xxx_g2_pot_clear,
3530         .reset = mv88e6352_g1_reset,
3531         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3532         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3533         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3534         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3535         .avb_ops = &mv88e6165_avb_ops,
3536         .ptp_ops = &mv88e6165_ptp_ops,
3537         .phylink_validate = mv88e6185_phylink_validate,
3538 };
3539
3540 static const struct mv88e6xxx_ops mv88e6171_ops = {
3541         /* MV88E6XXX_FAMILY_6351 */
3542         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3543         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3544         .irl_init_all = mv88e6352_g2_irl_init_all,
3545         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3546         .phy_read = mv88e6xxx_g2_smi_phy_read,
3547         .phy_write = mv88e6xxx_g2_smi_phy_write,
3548         .port_set_link = mv88e6xxx_port_set_link,
3549         .port_sync_link = mv88e6xxx_port_sync_link,
3550         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3551         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3552         .port_tag_remap = mv88e6095_port_tag_remap,
3553         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3554         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3555         .port_set_ether_type = mv88e6351_port_set_ether_type,
3556         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3557         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3558         .port_pause_limit = mv88e6097_port_pause_limit,
3559         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3560         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3561         .port_get_cmode = mv88e6352_port_get_cmode,
3562         .port_setup_message_port = mv88e6xxx_setup_message_port,
3563         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3564         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3565         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3566         .stats_get_strings = mv88e6095_stats_get_strings,
3567         .stats_get_stats = mv88e6095_stats_get_stats,
3568         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3569         .set_egress_port = mv88e6095_g1_set_egress_port,
3570         .watchdog_ops = &mv88e6097_watchdog_ops,
3571         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3572         .pot_clear = mv88e6xxx_g2_pot_clear,
3573         .reset = mv88e6352_g1_reset,
3574         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3575         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3576         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3577         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3578         .phylink_validate = mv88e6185_phylink_validate,
3579 };
3580
3581 static const struct mv88e6xxx_ops mv88e6172_ops = {
3582         /* MV88E6XXX_FAMILY_6352 */
3583         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3584         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3585         .irl_init_all = mv88e6352_g2_irl_init_all,
3586         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3587         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3588         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3589         .phy_read = mv88e6xxx_g2_smi_phy_read,
3590         .phy_write = mv88e6xxx_g2_smi_phy_write,
3591         .port_set_link = mv88e6xxx_port_set_link,
3592         .port_sync_link = mv88e6xxx_port_sync_link,
3593         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3594         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3595         .port_tag_remap = mv88e6095_port_tag_remap,
3596         .port_set_policy = mv88e6352_port_set_policy,
3597         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3598         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3599         .port_set_ether_type = mv88e6351_port_set_ether_type,
3600         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3601         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3602         .port_pause_limit = mv88e6097_port_pause_limit,
3603         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3604         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3605         .port_get_cmode = mv88e6352_port_get_cmode,
3606         .port_setup_message_port = mv88e6xxx_setup_message_port,
3607         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3608         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3609         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3610         .stats_get_strings = mv88e6095_stats_get_strings,
3611         .stats_get_stats = mv88e6095_stats_get_stats,
3612         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3613         .set_egress_port = mv88e6095_g1_set_egress_port,
3614         .watchdog_ops = &mv88e6097_watchdog_ops,
3615         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3616         .pot_clear = mv88e6xxx_g2_pot_clear,
3617         .reset = mv88e6352_g1_reset,
3618         .rmu_disable = mv88e6352_g1_rmu_disable,
3619         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3620         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3621         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3622         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3623         .serdes_get_lane = mv88e6352_serdes_get_lane,
3624         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3625         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3626         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3627         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3628         .serdes_power = mv88e6352_serdes_power,
3629         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3630         .serdes_get_regs = mv88e6352_serdes_get_regs,
3631         .gpio_ops = &mv88e6352_gpio_ops,
3632         .phylink_validate = mv88e6352_phylink_validate,
3633 };
3634
3635 static const struct mv88e6xxx_ops mv88e6175_ops = {
3636         /* MV88E6XXX_FAMILY_6351 */
3637         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3638         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3639         .irl_init_all = mv88e6352_g2_irl_init_all,
3640         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3641         .phy_read = mv88e6xxx_g2_smi_phy_read,
3642         .phy_write = mv88e6xxx_g2_smi_phy_write,
3643         .port_set_link = mv88e6xxx_port_set_link,
3644         .port_sync_link = mv88e6xxx_port_sync_link,
3645         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3646         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3647         .port_tag_remap = mv88e6095_port_tag_remap,
3648         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3649         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3650         .port_set_ether_type = mv88e6351_port_set_ether_type,
3651         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3652         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3653         .port_pause_limit = mv88e6097_port_pause_limit,
3654         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3655         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3656         .port_get_cmode = mv88e6352_port_get_cmode,
3657         .port_setup_message_port = mv88e6xxx_setup_message_port,
3658         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3659         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3660         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3661         .stats_get_strings = mv88e6095_stats_get_strings,
3662         .stats_get_stats = mv88e6095_stats_get_stats,
3663         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3664         .set_egress_port = mv88e6095_g1_set_egress_port,
3665         .watchdog_ops = &mv88e6097_watchdog_ops,
3666         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3667         .pot_clear = mv88e6xxx_g2_pot_clear,
3668         .reset = mv88e6352_g1_reset,
3669         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3670         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3671         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3672         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3673         .phylink_validate = mv88e6185_phylink_validate,
3674 };
3675
3676 static const struct mv88e6xxx_ops mv88e6176_ops = {
3677         /* MV88E6XXX_FAMILY_6352 */
3678         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3679         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3680         .irl_init_all = mv88e6352_g2_irl_init_all,
3681         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3682         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3683         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3684         .phy_read = mv88e6xxx_g2_smi_phy_read,
3685         .phy_write = mv88e6xxx_g2_smi_phy_write,
3686         .port_set_link = mv88e6xxx_port_set_link,
3687         .port_sync_link = mv88e6xxx_port_sync_link,
3688         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3689         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3690         .port_tag_remap = mv88e6095_port_tag_remap,
3691         .port_set_policy = mv88e6352_port_set_policy,
3692         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3693         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3694         .port_set_ether_type = mv88e6351_port_set_ether_type,
3695         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3696         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3697         .port_pause_limit = mv88e6097_port_pause_limit,
3698         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3699         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3700         .port_get_cmode = mv88e6352_port_get_cmode,
3701         .port_setup_message_port = mv88e6xxx_setup_message_port,
3702         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3703         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3704         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3705         .stats_get_strings = mv88e6095_stats_get_strings,
3706         .stats_get_stats = mv88e6095_stats_get_stats,
3707         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3708         .set_egress_port = mv88e6095_g1_set_egress_port,
3709         .watchdog_ops = &mv88e6097_watchdog_ops,
3710         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3711         .pot_clear = mv88e6xxx_g2_pot_clear,
3712         .reset = mv88e6352_g1_reset,
3713         .rmu_disable = mv88e6352_g1_rmu_disable,
3714         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3715         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3716         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3717         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3718         .serdes_get_lane = mv88e6352_serdes_get_lane,
3719         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3720         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3721         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3722         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3723         .serdes_power = mv88e6352_serdes_power,
3724         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3725         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3726         .serdes_irq_status = mv88e6352_serdes_irq_status,
3727         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3728         .serdes_get_regs = mv88e6352_serdes_get_regs,
3729         .gpio_ops = &mv88e6352_gpio_ops,
3730         .phylink_validate = mv88e6352_phylink_validate,
3731 };
3732
3733 static const struct mv88e6xxx_ops mv88e6185_ops = {
3734         /* MV88E6XXX_FAMILY_6185 */
3735         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3736         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3737         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3738         .phy_read = mv88e6185_phy_ppu_read,
3739         .phy_write = mv88e6185_phy_ppu_write,
3740         .port_set_link = mv88e6xxx_port_set_link,
3741         .port_sync_link = mv88e6185_port_sync_link,
3742         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3743         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3744         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3745         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3746         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3747         .port_set_pause = mv88e6185_port_set_pause,
3748         .port_get_cmode = mv88e6185_port_get_cmode,
3749         .port_setup_message_port = mv88e6xxx_setup_message_port,
3750         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3751         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3752         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3753         .stats_get_strings = mv88e6095_stats_get_strings,
3754         .stats_get_stats = mv88e6095_stats_get_stats,
3755         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3756         .set_egress_port = mv88e6095_g1_set_egress_port,
3757         .watchdog_ops = &mv88e6097_watchdog_ops,
3758         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3759         .serdes_power = mv88e6185_serdes_power,
3760         .serdes_get_lane = mv88e6185_serdes_get_lane,
3761         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3762         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3763         .ppu_enable = mv88e6185_g1_ppu_enable,
3764         .ppu_disable = mv88e6185_g1_ppu_disable,
3765         .reset = mv88e6185_g1_reset,
3766         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3767         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3768         .phylink_validate = mv88e6185_phylink_validate,
3769         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3770 };
3771
3772 static const struct mv88e6xxx_ops mv88e6190_ops = {
3773         /* MV88E6XXX_FAMILY_6390 */
3774         .setup_errata = mv88e6390_setup_errata,
3775         .irl_init_all = mv88e6390_g2_irl_init_all,
3776         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3777         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3778         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3779         .phy_read = mv88e6xxx_g2_smi_phy_read,
3780         .phy_write = mv88e6xxx_g2_smi_phy_write,
3781         .port_set_link = mv88e6xxx_port_set_link,
3782         .port_sync_link = mv88e6xxx_port_sync_link,
3783         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3784         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3785         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3786         .port_tag_remap = mv88e6390_port_tag_remap,
3787         .port_set_policy = mv88e6352_port_set_policy,
3788         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3789         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3790         .port_set_ether_type = mv88e6351_port_set_ether_type,
3791         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3792         .port_pause_limit = mv88e6390_port_pause_limit,
3793         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3794         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3795         .port_get_cmode = mv88e6352_port_get_cmode,
3796         .port_set_cmode = mv88e6390_port_set_cmode,
3797         .port_setup_message_port = mv88e6xxx_setup_message_port,
3798         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3799         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3800         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3801         .stats_get_strings = mv88e6320_stats_get_strings,
3802         .stats_get_stats = mv88e6390_stats_get_stats,
3803         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3804         .set_egress_port = mv88e6390_g1_set_egress_port,
3805         .watchdog_ops = &mv88e6390_watchdog_ops,
3806         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3807         .pot_clear = mv88e6xxx_g2_pot_clear,
3808         .reset = mv88e6352_g1_reset,
3809         .rmu_disable = mv88e6390_g1_rmu_disable,
3810         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3811         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3812         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3813         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3814         .serdes_power = mv88e6390_serdes_power,
3815         .serdes_get_lane = mv88e6390_serdes_get_lane,
3816         /* Check status register pause & lpa register */
3817         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3818         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3819         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3820         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3821         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3822         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3823         .serdes_irq_status = mv88e6390_serdes_irq_status,
3824         .serdes_get_strings = mv88e6390_serdes_get_strings,
3825         .serdes_get_stats = mv88e6390_serdes_get_stats,
3826         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3827         .serdes_get_regs = mv88e6390_serdes_get_regs,
3828         .gpio_ops = &mv88e6352_gpio_ops,
3829         .phylink_validate = mv88e6390_phylink_validate,
3830 };
3831
3832 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3833         /* MV88E6XXX_FAMILY_6390 */
3834         .setup_errata = mv88e6390_setup_errata,
3835         .irl_init_all = mv88e6390_g2_irl_init_all,
3836         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3837         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3838         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3839         .phy_read = mv88e6xxx_g2_smi_phy_read,
3840         .phy_write = mv88e6xxx_g2_smi_phy_write,
3841         .port_set_link = mv88e6xxx_port_set_link,
3842         .port_sync_link = mv88e6xxx_port_sync_link,
3843         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3844         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
3845         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3846         .port_tag_remap = mv88e6390_port_tag_remap,
3847         .port_set_policy = mv88e6352_port_set_policy,
3848         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3849         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3850         .port_set_ether_type = mv88e6351_port_set_ether_type,
3851         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3852         .port_pause_limit = mv88e6390_port_pause_limit,
3853         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3854         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3855         .port_get_cmode = mv88e6352_port_get_cmode,
3856         .port_set_cmode = mv88e6390x_port_set_cmode,
3857         .port_setup_message_port = mv88e6xxx_setup_message_port,
3858         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3859         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3860         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3861         .stats_get_strings = mv88e6320_stats_get_strings,
3862         .stats_get_stats = mv88e6390_stats_get_stats,
3863         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3864         .set_egress_port = mv88e6390_g1_set_egress_port,
3865         .watchdog_ops = &mv88e6390_watchdog_ops,
3866         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3867         .pot_clear = mv88e6xxx_g2_pot_clear,
3868         .reset = mv88e6352_g1_reset,
3869         .rmu_disable = mv88e6390_g1_rmu_disable,
3870         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3871         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3872         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3873         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3874         .serdes_power = mv88e6390_serdes_power,
3875         .serdes_get_lane = mv88e6390x_serdes_get_lane,
3876         /* Check status register pause & lpa register */
3877         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3878         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3879         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3880         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3881         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3882         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3883         .serdes_irq_status = mv88e6390_serdes_irq_status,
3884         .serdes_get_strings = mv88e6390_serdes_get_strings,
3885         .serdes_get_stats = mv88e6390_serdes_get_stats,
3886         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3887         .serdes_get_regs = mv88e6390_serdes_get_regs,
3888         .gpio_ops = &mv88e6352_gpio_ops,
3889         .phylink_validate = mv88e6390x_phylink_validate,
3890 };
3891
3892 static const struct mv88e6xxx_ops mv88e6191_ops = {
3893         /* MV88E6XXX_FAMILY_6390 */
3894         .setup_errata = mv88e6390_setup_errata,
3895         .irl_init_all = mv88e6390_g2_irl_init_all,
3896         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3897         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3898         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3899         .phy_read = mv88e6xxx_g2_smi_phy_read,
3900         .phy_write = mv88e6xxx_g2_smi_phy_write,
3901         .port_set_link = mv88e6xxx_port_set_link,
3902         .port_sync_link = mv88e6xxx_port_sync_link,
3903         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3904         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3905         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3906         .port_tag_remap = mv88e6390_port_tag_remap,
3907         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3908         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3909         .port_set_ether_type = mv88e6351_port_set_ether_type,
3910         .port_pause_limit = mv88e6390_port_pause_limit,
3911         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3912         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3913         .port_get_cmode = mv88e6352_port_get_cmode,
3914         .port_set_cmode = mv88e6390_port_set_cmode,
3915         .port_setup_message_port = mv88e6xxx_setup_message_port,
3916         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3917         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3918         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3919         .stats_get_strings = mv88e6320_stats_get_strings,
3920         .stats_get_stats = mv88e6390_stats_get_stats,
3921         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3922         .set_egress_port = mv88e6390_g1_set_egress_port,
3923         .watchdog_ops = &mv88e6390_watchdog_ops,
3924         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3925         .pot_clear = mv88e6xxx_g2_pot_clear,
3926         .reset = mv88e6352_g1_reset,
3927         .rmu_disable = mv88e6390_g1_rmu_disable,
3928         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3929         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3930         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3931         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3932         .serdes_power = mv88e6390_serdes_power,
3933         .serdes_get_lane = mv88e6390_serdes_get_lane,
3934         /* Check status register pause & lpa register */
3935         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3936         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3937         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3938         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3939         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3940         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3941         .serdes_irq_status = mv88e6390_serdes_irq_status,
3942         .serdes_get_strings = mv88e6390_serdes_get_strings,
3943         .serdes_get_stats = mv88e6390_serdes_get_stats,
3944         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3945         .serdes_get_regs = mv88e6390_serdes_get_regs,
3946         .avb_ops = &mv88e6390_avb_ops,
3947         .ptp_ops = &mv88e6352_ptp_ops,
3948         .phylink_validate = mv88e6390_phylink_validate,
3949 };
3950
3951 static const struct mv88e6xxx_ops mv88e6240_ops = {
3952         /* MV88E6XXX_FAMILY_6352 */
3953         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3954         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3955         .irl_init_all = mv88e6352_g2_irl_init_all,
3956         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3957         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3958         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3959         .phy_read = mv88e6xxx_g2_smi_phy_read,
3960         .phy_write = mv88e6xxx_g2_smi_phy_write,
3961         .port_set_link = mv88e6xxx_port_set_link,
3962         .port_sync_link = mv88e6xxx_port_sync_link,
3963         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3964         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3965         .port_tag_remap = mv88e6095_port_tag_remap,
3966         .port_set_policy = mv88e6352_port_set_policy,
3967         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3968         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3969         .port_set_ether_type = mv88e6351_port_set_ether_type,
3970         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3971         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3972         .port_pause_limit = mv88e6097_port_pause_limit,
3973         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3974         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3975         .port_get_cmode = mv88e6352_port_get_cmode,
3976         .port_setup_message_port = mv88e6xxx_setup_message_port,
3977         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3978         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3979         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3980         .stats_get_strings = mv88e6095_stats_get_strings,
3981         .stats_get_stats = mv88e6095_stats_get_stats,
3982         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3983         .set_egress_port = mv88e6095_g1_set_egress_port,
3984         .watchdog_ops = &mv88e6097_watchdog_ops,
3985         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3986         .pot_clear = mv88e6xxx_g2_pot_clear,
3987         .reset = mv88e6352_g1_reset,
3988         .rmu_disable = mv88e6352_g1_rmu_disable,
3989         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3990         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3991         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3992         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3993         .serdes_get_lane = mv88e6352_serdes_get_lane,
3994         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3995         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3996         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3997         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3998         .serdes_power = mv88e6352_serdes_power,
3999         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4000         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4001         .serdes_irq_status = mv88e6352_serdes_irq_status,
4002         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4003         .serdes_get_regs = mv88e6352_serdes_get_regs,
4004         .gpio_ops = &mv88e6352_gpio_ops,
4005         .avb_ops = &mv88e6352_avb_ops,
4006         .ptp_ops = &mv88e6352_ptp_ops,
4007         .phylink_validate = mv88e6352_phylink_validate,
4008 };
4009
4010 static const struct mv88e6xxx_ops mv88e6250_ops = {
4011         /* MV88E6XXX_FAMILY_6250 */
4012         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4013         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4014         .irl_init_all = mv88e6352_g2_irl_init_all,
4015         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4016         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4017         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4018         .phy_read = mv88e6xxx_g2_smi_phy_read,
4019         .phy_write = mv88e6xxx_g2_smi_phy_write,
4020         .port_set_link = mv88e6xxx_port_set_link,
4021         .port_sync_link = mv88e6xxx_port_sync_link,
4022         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4023         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4024         .port_tag_remap = mv88e6095_port_tag_remap,
4025         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4026         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4027         .port_set_ether_type = mv88e6351_port_set_ether_type,
4028         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4029         .port_pause_limit = mv88e6097_port_pause_limit,
4030         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4031         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4032         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4033         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4034         .stats_get_strings = mv88e6250_stats_get_strings,
4035         .stats_get_stats = mv88e6250_stats_get_stats,
4036         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4037         .set_egress_port = mv88e6095_g1_set_egress_port,
4038         .watchdog_ops = &mv88e6250_watchdog_ops,
4039         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4040         .pot_clear = mv88e6xxx_g2_pot_clear,
4041         .reset = mv88e6250_g1_reset,
4042         .vtu_getnext = mv88e6250_g1_vtu_getnext,
4043         .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4044         .avb_ops = &mv88e6352_avb_ops,
4045         .ptp_ops = &mv88e6250_ptp_ops,
4046         .phylink_validate = mv88e6065_phylink_validate,
4047 };
4048
4049 static const struct mv88e6xxx_ops mv88e6290_ops = {
4050         /* MV88E6XXX_FAMILY_6390 */
4051         .setup_errata = mv88e6390_setup_errata,
4052         .irl_init_all = mv88e6390_g2_irl_init_all,
4053         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4054         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4055         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4056         .phy_read = mv88e6xxx_g2_smi_phy_read,
4057         .phy_write = mv88e6xxx_g2_smi_phy_write,
4058         .port_set_link = mv88e6xxx_port_set_link,
4059         .port_sync_link = mv88e6xxx_port_sync_link,
4060         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4061         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4062         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4063         .port_tag_remap = mv88e6390_port_tag_remap,
4064         .port_set_policy = mv88e6352_port_set_policy,
4065         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4066         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4067         .port_set_ether_type = mv88e6351_port_set_ether_type,
4068         .port_pause_limit = mv88e6390_port_pause_limit,
4069         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4070         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4071         .port_get_cmode = mv88e6352_port_get_cmode,
4072         .port_set_cmode = mv88e6390_port_set_cmode,
4073         .port_setup_message_port = mv88e6xxx_setup_message_port,
4074         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4075         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4076         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4077         .stats_get_strings = mv88e6320_stats_get_strings,
4078         .stats_get_stats = mv88e6390_stats_get_stats,
4079         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4080         .set_egress_port = mv88e6390_g1_set_egress_port,
4081         .watchdog_ops = &mv88e6390_watchdog_ops,
4082         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4083         .pot_clear = mv88e6xxx_g2_pot_clear,
4084         .reset = mv88e6352_g1_reset,
4085         .rmu_disable = mv88e6390_g1_rmu_disable,
4086         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4087         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4088         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4089         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4090         .serdes_power = mv88e6390_serdes_power,
4091         .serdes_get_lane = mv88e6390_serdes_get_lane,
4092         /* Check status register pause & lpa register */
4093         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4094         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4095         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4096         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4097         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4098         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4099         .serdes_irq_status = mv88e6390_serdes_irq_status,
4100         .serdes_get_strings = mv88e6390_serdes_get_strings,
4101         .serdes_get_stats = mv88e6390_serdes_get_stats,
4102         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4103         .serdes_get_regs = mv88e6390_serdes_get_regs,
4104         .gpio_ops = &mv88e6352_gpio_ops,
4105         .avb_ops = &mv88e6390_avb_ops,
4106         .ptp_ops = &mv88e6352_ptp_ops,
4107         .phylink_validate = mv88e6390_phylink_validate,
4108 };
4109
4110 static const struct mv88e6xxx_ops mv88e6320_ops = {
4111         /* MV88E6XXX_FAMILY_6320 */
4112         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4113         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4114         .irl_init_all = mv88e6352_g2_irl_init_all,
4115         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4116         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4117         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4118         .phy_read = mv88e6xxx_g2_smi_phy_read,
4119         .phy_write = mv88e6xxx_g2_smi_phy_write,
4120         .port_set_link = mv88e6xxx_port_set_link,
4121         .port_sync_link = mv88e6xxx_port_sync_link,
4122         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4123         .port_tag_remap = mv88e6095_port_tag_remap,
4124         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4125         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4126         .port_set_ether_type = mv88e6351_port_set_ether_type,
4127         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4128         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4129         .port_pause_limit = mv88e6097_port_pause_limit,
4130         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4131         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4132         .port_get_cmode = mv88e6352_port_get_cmode,
4133         .port_setup_message_port = mv88e6xxx_setup_message_port,
4134         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4135         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4136         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4137         .stats_get_strings = mv88e6320_stats_get_strings,
4138         .stats_get_stats = mv88e6320_stats_get_stats,
4139         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4140         .set_egress_port = mv88e6095_g1_set_egress_port,
4141         .watchdog_ops = &mv88e6390_watchdog_ops,
4142         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4143         .pot_clear = mv88e6xxx_g2_pot_clear,
4144         .reset = mv88e6352_g1_reset,
4145         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4146         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4147         .gpio_ops = &mv88e6352_gpio_ops,
4148         .avb_ops = &mv88e6352_avb_ops,
4149         .ptp_ops = &mv88e6352_ptp_ops,
4150         .phylink_validate = mv88e6185_phylink_validate,
4151 };
4152
4153 static const struct mv88e6xxx_ops mv88e6321_ops = {
4154         /* MV88E6XXX_FAMILY_6320 */
4155         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4156         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4157         .irl_init_all = mv88e6352_g2_irl_init_all,
4158         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4159         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4160         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4161         .phy_read = mv88e6xxx_g2_smi_phy_read,
4162         .phy_write = mv88e6xxx_g2_smi_phy_write,
4163         .port_set_link = mv88e6xxx_port_set_link,
4164         .port_sync_link = mv88e6xxx_port_sync_link,
4165         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4166         .port_tag_remap = mv88e6095_port_tag_remap,
4167         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4168         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4169         .port_set_ether_type = mv88e6351_port_set_ether_type,
4170         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4171         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4172         .port_pause_limit = mv88e6097_port_pause_limit,
4173         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4174         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4175         .port_get_cmode = mv88e6352_port_get_cmode,
4176         .port_setup_message_port = mv88e6xxx_setup_message_port,
4177         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4178         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4179         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4180         .stats_get_strings = mv88e6320_stats_get_strings,
4181         .stats_get_stats = mv88e6320_stats_get_stats,
4182         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4183         .set_egress_port = mv88e6095_g1_set_egress_port,
4184         .watchdog_ops = &mv88e6390_watchdog_ops,
4185         .reset = mv88e6352_g1_reset,
4186         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4187         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4188         .gpio_ops = &mv88e6352_gpio_ops,
4189         .avb_ops = &mv88e6352_avb_ops,
4190         .ptp_ops = &mv88e6352_ptp_ops,
4191         .phylink_validate = mv88e6185_phylink_validate,
4192 };
4193
4194 static const struct mv88e6xxx_ops mv88e6341_ops = {
4195         /* MV88E6XXX_FAMILY_6341 */
4196         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4197         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4198         .irl_init_all = mv88e6352_g2_irl_init_all,
4199         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4200         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4201         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4202         .phy_read = mv88e6xxx_g2_smi_phy_read,
4203         .phy_write = mv88e6xxx_g2_smi_phy_write,
4204         .port_set_link = mv88e6xxx_port_set_link,
4205         .port_sync_link = mv88e6xxx_port_sync_link,
4206         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4207         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4208         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4209         .port_tag_remap = mv88e6095_port_tag_remap,
4210         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4211         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4212         .port_set_ether_type = mv88e6351_port_set_ether_type,
4213         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4214         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4215         .port_pause_limit = mv88e6097_port_pause_limit,
4216         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4217         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4218         .port_get_cmode = mv88e6352_port_get_cmode,
4219         .port_set_cmode = mv88e6341_port_set_cmode,
4220         .port_setup_message_port = mv88e6xxx_setup_message_port,
4221         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4222         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4223         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4224         .stats_get_strings = mv88e6320_stats_get_strings,
4225         .stats_get_stats = mv88e6390_stats_get_stats,
4226         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4227         .set_egress_port = mv88e6390_g1_set_egress_port,
4228         .watchdog_ops = &mv88e6390_watchdog_ops,
4229         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4230         .pot_clear = mv88e6xxx_g2_pot_clear,
4231         .reset = mv88e6352_g1_reset,
4232         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4233         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4234         .serdes_power = mv88e6390_serdes_power,
4235         .serdes_get_lane = mv88e6341_serdes_get_lane,
4236         /* Check status register pause & lpa register */
4237         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4238         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4239         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4240         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4242         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4243         .serdes_irq_status = mv88e6390_serdes_irq_status,
4244         .gpio_ops = &mv88e6352_gpio_ops,
4245         .avb_ops = &mv88e6390_avb_ops,
4246         .ptp_ops = &mv88e6352_ptp_ops,
4247         .phylink_validate = mv88e6341_phylink_validate,
4248 };
4249
4250 static const struct mv88e6xxx_ops mv88e6350_ops = {
4251         /* MV88E6XXX_FAMILY_6351 */
4252         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4253         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4254         .irl_init_all = mv88e6352_g2_irl_init_all,
4255         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4256         .phy_read = mv88e6xxx_g2_smi_phy_read,
4257         .phy_write = mv88e6xxx_g2_smi_phy_write,
4258         .port_set_link = mv88e6xxx_port_set_link,
4259         .port_sync_link = mv88e6xxx_port_sync_link,
4260         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4261         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4262         .port_tag_remap = mv88e6095_port_tag_remap,
4263         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4264         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4265         .port_set_ether_type = mv88e6351_port_set_ether_type,
4266         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4267         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4268         .port_pause_limit = mv88e6097_port_pause_limit,
4269         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4270         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4271         .port_get_cmode = mv88e6352_port_get_cmode,
4272         .port_setup_message_port = mv88e6xxx_setup_message_port,
4273         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4274         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4275         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4276         .stats_get_strings = mv88e6095_stats_get_strings,
4277         .stats_get_stats = mv88e6095_stats_get_stats,
4278         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4279         .set_egress_port = mv88e6095_g1_set_egress_port,
4280         .watchdog_ops = &mv88e6097_watchdog_ops,
4281         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4282         .pot_clear = mv88e6xxx_g2_pot_clear,
4283         .reset = mv88e6352_g1_reset,
4284         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4285         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4286         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4287         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4288         .phylink_validate = mv88e6185_phylink_validate,
4289 };
4290
4291 static const struct mv88e6xxx_ops mv88e6351_ops = {
4292         /* MV88E6XXX_FAMILY_6351 */
4293         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4294         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4295         .irl_init_all = mv88e6352_g2_irl_init_all,
4296         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4297         .phy_read = mv88e6xxx_g2_smi_phy_read,
4298         .phy_write = mv88e6xxx_g2_smi_phy_write,
4299         .port_set_link = mv88e6xxx_port_set_link,
4300         .port_sync_link = mv88e6xxx_port_sync_link,
4301         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4302         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4303         .port_tag_remap = mv88e6095_port_tag_remap,
4304         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4305         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4306         .port_set_ether_type = mv88e6351_port_set_ether_type,
4307         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4308         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4309         .port_pause_limit = mv88e6097_port_pause_limit,
4310         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4311         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4312         .port_get_cmode = mv88e6352_port_get_cmode,
4313         .port_setup_message_port = mv88e6xxx_setup_message_port,
4314         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4315         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4316         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4317         .stats_get_strings = mv88e6095_stats_get_strings,
4318         .stats_get_stats = mv88e6095_stats_get_stats,
4319         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4320         .set_egress_port = mv88e6095_g1_set_egress_port,
4321         .watchdog_ops = &mv88e6097_watchdog_ops,
4322         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4323         .pot_clear = mv88e6xxx_g2_pot_clear,
4324         .reset = mv88e6352_g1_reset,
4325         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4326         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4327         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4328         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4329         .avb_ops = &mv88e6352_avb_ops,
4330         .ptp_ops = &mv88e6352_ptp_ops,
4331         .phylink_validate = mv88e6185_phylink_validate,
4332 };
4333
4334 static const struct mv88e6xxx_ops mv88e6352_ops = {
4335         /* MV88E6XXX_FAMILY_6352 */
4336         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4337         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4338         .irl_init_all = mv88e6352_g2_irl_init_all,
4339         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4340         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4341         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4342         .phy_read = mv88e6xxx_g2_smi_phy_read,
4343         .phy_write = mv88e6xxx_g2_smi_phy_write,
4344         .port_set_link = mv88e6xxx_port_set_link,
4345         .port_sync_link = mv88e6xxx_port_sync_link,
4346         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4347         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4348         .port_tag_remap = mv88e6095_port_tag_remap,
4349         .port_set_policy = mv88e6352_port_set_policy,
4350         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4351         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4352         .port_set_ether_type = mv88e6351_port_set_ether_type,
4353         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4354         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4355         .port_pause_limit = mv88e6097_port_pause_limit,
4356         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4357         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4358         .port_get_cmode = mv88e6352_port_get_cmode,
4359         .port_setup_message_port = mv88e6xxx_setup_message_port,
4360         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4361         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4362         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4363         .stats_get_strings = mv88e6095_stats_get_strings,
4364         .stats_get_stats = mv88e6095_stats_get_stats,
4365         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4366         .set_egress_port = mv88e6095_g1_set_egress_port,
4367         .watchdog_ops = &mv88e6097_watchdog_ops,
4368         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4369         .pot_clear = mv88e6xxx_g2_pot_clear,
4370         .reset = mv88e6352_g1_reset,
4371         .rmu_disable = mv88e6352_g1_rmu_disable,
4372         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4373         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4374         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4375         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4376         .serdes_get_lane = mv88e6352_serdes_get_lane,
4377         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4378         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4379         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4380         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4381         .serdes_power = mv88e6352_serdes_power,
4382         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4383         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4384         .serdes_irq_status = mv88e6352_serdes_irq_status,
4385         .gpio_ops = &mv88e6352_gpio_ops,
4386         .avb_ops = &mv88e6352_avb_ops,
4387         .ptp_ops = &mv88e6352_ptp_ops,
4388         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4389         .serdes_get_strings = mv88e6352_serdes_get_strings,
4390         .serdes_get_stats = mv88e6352_serdes_get_stats,
4391         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4392         .serdes_get_regs = mv88e6352_serdes_get_regs,
4393         .phylink_validate = mv88e6352_phylink_validate,
4394 };
4395
4396 static const struct mv88e6xxx_ops mv88e6390_ops = {
4397         /* MV88E6XXX_FAMILY_6390 */
4398         .setup_errata = mv88e6390_setup_errata,
4399         .irl_init_all = mv88e6390_g2_irl_init_all,
4400         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4401         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4402         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4403         .phy_read = mv88e6xxx_g2_smi_phy_read,
4404         .phy_write = mv88e6xxx_g2_smi_phy_write,
4405         .port_set_link = mv88e6xxx_port_set_link,
4406         .port_sync_link = mv88e6xxx_port_sync_link,
4407         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4408         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4409         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4410         .port_tag_remap = mv88e6390_port_tag_remap,
4411         .port_set_policy = mv88e6352_port_set_policy,
4412         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4413         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4414         .port_set_ether_type = mv88e6351_port_set_ether_type,
4415         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4416         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4417         .port_pause_limit = mv88e6390_port_pause_limit,
4418         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4419         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4420         .port_get_cmode = mv88e6352_port_get_cmode,
4421         .port_set_cmode = mv88e6390_port_set_cmode,
4422         .port_setup_message_port = mv88e6xxx_setup_message_port,
4423         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4424         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4425         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4426         .stats_get_strings = mv88e6320_stats_get_strings,
4427         .stats_get_stats = mv88e6390_stats_get_stats,
4428         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4429         .set_egress_port = mv88e6390_g1_set_egress_port,
4430         .watchdog_ops = &mv88e6390_watchdog_ops,
4431         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4432         .pot_clear = mv88e6xxx_g2_pot_clear,
4433         .reset = mv88e6352_g1_reset,
4434         .rmu_disable = mv88e6390_g1_rmu_disable,
4435         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4436         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4437         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4438         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4439         .serdes_power = mv88e6390_serdes_power,
4440         .serdes_get_lane = mv88e6390_serdes_get_lane,
4441         /* Check status register pause & lpa register */
4442         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4443         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4444         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4445         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4446         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4447         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4448         .serdes_irq_status = mv88e6390_serdes_irq_status,
4449         .gpio_ops = &mv88e6352_gpio_ops,
4450         .avb_ops = &mv88e6390_avb_ops,
4451         .ptp_ops = &mv88e6352_ptp_ops,
4452         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4453         .serdes_get_strings = mv88e6390_serdes_get_strings,
4454         .serdes_get_stats = mv88e6390_serdes_get_stats,
4455         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4456         .serdes_get_regs = mv88e6390_serdes_get_regs,
4457         .phylink_validate = mv88e6390_phylink_validate,
4458 };
4459
4460 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4461         /* MV88E6XXX_FAMILY_6390 */
4462         .setup_errata = mv88e6390_setup_errata,
4463         .irl_init_all = mv88e6390_g2_irl_init_all,
4464         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4465         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4466         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4467         .phy_read = mv88e6xxx_g2_smi_phy_read,
4468         .phy_write = mv88e6xxx_g2_smi_phy_write,
4469         .port_set_link = mv88e6xxx_port_set_link,
4470         .port_sync_link = mv88e6xxx_port_sync_link,
4471         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4472         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4473         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4474         .port_tag_remap = mv88e6390_port_tag_remap,
4475         .port_set_policy = mv88e6352_port_set_policy,
4476         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4477         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4478         .port_set_ether_type = mv88e6351_port_set_ether_type,
4479         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4480         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4481         .port_pause_limit = mv88e6390_port_pause_limit,
4482         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4483         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4484         .port_get_cmode = mv88e6352_port_get_cmode,
4485         .port_set_cmode = mv88e6390x_port_set_cmode,
4486         .port_setup_message_port = mv88e6xxx_setup_message_port,
4487         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4488         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4489         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4490         .stats_get_strings = mv88e6320_stats_get_strings,
4491         .stats_get_stats = mv88e6390_stats_get_stats,
4492         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4493         .set_egress_port = mv88e6390_g1_set_egress_port,
4494         .watchdog_ops = &mv88e6390_watchdog_ops,
4495         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4496         .pot_clear = mv88e6xxx_g2_pot_clear,
4497         .reset = mv88e6352_g1_reset,
4498         .rmu_disable = mv88e6390_g1_rmu_disable,
4499         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4500         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4501         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4502         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4503         .serdes_power = mv88e6390_serdes_power,
4504         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4505         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4506         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4507         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4508         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4509         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4510         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4511         .serdes_irq_status = mv88e6390_serdes_irq_status,
4512         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4513         .serdes_get_strings = mv88e6390_serdes_get_strings,
4514         .serdes_get_stats = mv88e6390_serdes_get_stats,
4515         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4516         .serdes_get_regs = mv88e6390_serdes_get_regs,
4517         .gpio_ops = &mv88e6352_gpio_ops,
4518         .avb_ops = &mv88e6390_avb_ops,
4519         .ptp_ops = &mv88e6352_ptp_ops,
4520         .phylink_validate = mv88e6390x_phylink_validate,
4521 };
4522
4523 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4524         [MV88E6085] = {
4525                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4526                 .family = MV88E6XXX_FAMILY_6097,
4527                 .name = "Marvell 88E6085",
4528                 .num_databases = 4096,
4529                 .num_macs = 8192,
4530                 .num_ports = 10,
4531                 .num_internal_phys = 5,
4532                 .max_vid = 4095,
4533                 .port_base_addr = 0x10,
4534                 .phy_base_addr = 0x0,
4535                 .global1_addr = 0x1b,
4536                 .global2_addr = 0x1c,
4537                 .age_time_coeff = 15000,
4538                 .g1_irqs = 8,
4539                 .g2_irqs = 10,
4540                 .atu_move_port_mask = 0xf,
4541                 .pvt = true,
4542                 .multi_chip = true,
4543                 .tag_protocol = DSA_TAG_PROTO_DSA,
4544                 .ops = &mv88e6085_ops,
4545         },
4546
4547         [MV88E6095] = {
4548                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4549                 .family = MV88E6XXX_FAMILY_6095,
4550                 .name = "Marvell 88E6095/88E6095F",
4551                 .num_databases = 256,
4552                 .num_macs = 8192,
4553                 .num_ports = 11,
4554                 .num_internal_phys = 0,
4555                 .max_vid = 4095,
4556                 .port_base_addr = 0x10,
4557                 .phy_base_addr = 0x0,
4558                 .global1_addr = 0x1b,
4559                 .global2_addr = 0x1c,
4560                 .age_time_coeff = 15000,
4561                 .g1_irqs = 8,
4562                 .atu_move_port_mask = 0xf,
4563                 .multi_chip = true,
4564                 .tag_protocol = DSA_TAG_PROTO_DSA,
4565                 .ops = &mv88e6095_ops,
4566         },
4567
4568         [MV88E6097] = {
4569                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4570                 .family = MV88E6XXX_FAMILY_6097,
4571                 .name = "Marvell 88E6097/88E6097F",
4572                 .num_databases = 4096,
4573                 .num_macs = 8192,
4574                 .num_ports = 11,
4575                 .num_internal_phys = 8,
4576                 .max_vid = 4095,
4577                 .port_base_addr = 0x10,
4578                 .phy_base_addr = 0x0,
4579                 .global1_addr = 0x1b,
4580                 .global2_addr = 0x1c,
4581                 .age_time_coeff = 15000,
4582                 .g1_irqs = 8,
4583                 .g2_irqs = 10,
4584                 .atu_move_port_mask = 0xf,
4585                 .pvt = true,
4586                 .multi_chip = true,
4587                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4588                 .ops = &mv88e6097_ops,
4589         },
4590
4591         [MV88E6123] = {
4592                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4593                 .family = MV88E6XXX_FAMILY_6165,
4594                 .name = "Marvell 88E6123",
4595                 .num_databases = 4096,
4596                 .num_macs = 1024,
4597                 .num_ports = 3,
4598                 .num_internal_phys = 5,
4599                 .max_vid = 4095,
4600                 .port_base_addr = 0x10,
4601                 .phy_base_addr = 0x0,
4602                 .global1_addr = 0x1b,
4603                 .global2_addr = 0x1c,
4604                 .age_time_coeff = 15000,
4605                 .g1_irqs = 9,
4606                 .g2_irqs = 10,
4607                 .atu_move_port_mask = 0xf,
4608                 .pvt = true,
4609                 .multi_chip = true,
4610                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4611                 .ops = &mv88e6123_ops,
4612         },
4613
4614         [MV88E6131] = {
4615                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4616                 .family = MV88E6XXX_FAMILY_6185,
4617                 .name = "Marvell 88E6131",
4618                 .num_databases = 256,
4619                 .num_macs = 8192,
4620                 .num_ports = 8,
4621                 .num_internal_phys = 0,
4622                 .max_vid = 4095,
4623                 .port_base_addr = 0x10,
4624                 .phy_base_addr = 0x0,
4625                 .global1_addr = 0x1b,
4626                 .global2_addr = 0x1c,
4627                 .age_time_coeff = 15000,
4628                 .g1_irqs = 9,
4629                 .atu_move_port_mask = 0xf,
4630                 .multi_chip = true,
4631                 .tag_protocol = DSA_TAG_PROTO_DSA,
4632                 .ops = &mv88e6131_ops,
4633         },
4634
4635         [MV88E6141] = {
4636                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4637                 .family = MV88E6XXX_FAMILY_6341,
4638                 .name = "Marvell 88E6141",
4639                 .num_databases = 4096,
4640                 .num_macs = 2048,
4641                 .num_ports = 6,
4642                 .num_internal_phys = 5,
4643                 .num_gpio = 11,
4644                 .max_vid = 4095,
4645                 .port_base_addr = 0x10,
4646                 .phy_base_addr = 0x10,
4647                 .global1_addr = 0x1b,
4648                 .global2_addr = 0x1c,
4649                 .age_time_coeff = 3750,
4650                 .atu_move_port_mask = 0x1f,
4651                 .g1_irqs = 9,
4652                 .g2_irqs = 10,
4653                 .pvt = true,
4654                 .multi_chip = true,
4655                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4656                 .ops = &mv88e6141_ops,
4657         },
4658
4659         [MV88E6161] = {
4660                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4661                 .family = MV88E6XXX_FAMILY_6165,
4662                 .name = "Marvell 88E6161",
4663                 .num_databases = 4096,
4664                 .num_macs = 1024,
4665                 .num_ports = 6,
4666                 .num_internal_phys = 5,
4667                 .max_vid = 4095,
4668                 .port_base_addr = 0x10,
4669                 .phy_base_addr = 0x0,
4670                 .global1_addr = 0x1b,
4671                 .global2_addr = 0x1c,
4672                 .age_time_coeff = 15000,
4673                 .g1_irqs = 9,
4674                 .g2_irqs = 10,
4675                 .atu_move_port_mask = 0xf,
4676                 .pvt = true,
4677                 .multi_chip = true,
4678                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4679                 .ptp_support = true,
4680                 .ops = &mv88e6161_ops,
4681         },
4682
4683         [MV88E6165] = {
4684                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4685                 .family = MV88E6XXX_FAMILY_6165,
4686                 .name = "Marvell 88E6165",
4687                 .num_databases = 4096,
4688                 .num_macs = 8192,
4689                 .num_ports = 6,
4690                 .num_internal_phys = 0,
4691                 .max_vid = 4095,
4692                 .port_base_addr = 0x10,
4693                 .phy_base_addr = 0x0,
4694                 .global1_addr = 0x1b,
4695                 .global2_addr = 0x1c,
4696                 .age_time_coeff = 15000,
4697                 .g1_irqs = 9,
4698                 .g2_irqs = 10,
4699                 .atu_move_port_mask = 0xf,
4700                 .pvt = true,
4701                 .multi_chip = true,
4702                 .tag_protocol = DSA_TAG_PROTO_DSA,
4703                 .ptp_support = true,
4704                 .ops = &mv88e6165_ops,
4705         },
4706
4707         [MV88E6171] = {
4708                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4709                 .family = MV88E6XXX_FAMILY_6351,
4710                 .name = "Marvell 88E6171",
4711                 .num_databases = 4096,
4712                 .num_macs = 8192,
4713                 .num_ports = 7,
4714                 .num_internal_phys = 5,
4715                 .max_vid = 4095,
4716                 .port_base_addr = 0x10,
4717                 .phy_base_addr = 0x0,
4718                 .global1_addr = 0x1b,
4719                 .global2_addr = 0x1c,
4720                 .age_time_coeff = 15000,
4721                 .g1_irqs = 9,
4722                 .g2_irqs = 10,
4723                 .atu_move_port_mask = 0xf,
4724                 .pvt = true,
4725                 .multi_chip = true,
4726                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4727                 .ops = &mv88e6171_ops,
4728         },
4729
4730         [MV88E6172] = {
4731                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4732                 .family = MV88E6XXX_FAMILY_6352,
4733                 .name = "Marvell 88E6172",
4734                 .num_databases = 4096,
4735                 .num_macs = 8192,
4736                 .num_ports = 7,
4737                 .num_internal_phys = 5,
4738                 .num_gpio = 15,
4739                 .max_vid = 4095,
4740                 .port_base_addr = 0x10,
4741                 .phy_base_addr = 0x0,
4742                 .global1_addr = 0x1b,
4743                 .global2_addr = 0x1c,
4744                 .age_time_coeff = 15000,
4745                 .g1_irqs = 9,
4746                 .g2_irqs = 10,
4747                 .atu_move_port_mask = 0xf,
4748                 .pvt = true,
4749                 .multi_chip = true,
4750                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4751                 .ops = &mv88e6172_ops,
4752         },
4753
4754         [MV88E6175] = {
4755                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4756                 .family = MV88E6XXX_FAMILY_6351,
4757                 .name = "Marvell 88E6175",
4758                 .num_databases = 4096,
4759                 .num_macs = 8192,
4760                 .num_ports = 7,
4761                 .num_internal_phys = 5,
4762                 .max_vid = 4095,
4763                 .port_base_addr = 0x10,
4764                 .phy_base_addr = 0x0,
4765                 .global1_addr = 0x1b,
4766                 .global2_addr = 0x1c,
4767                 .age_time_coeff = 15000,
4768                 .g1_irqs = 9,
4769                 .g2_irqs = 10,
4770                 .atu_move_port_mask = 0xf,
4771                 .pvt = true,
4772                 .multi_chip = true,
4773                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4774                 .ops = &mv88e6175_ops,
4775         },
4776
4777         [MV88E6176] = {
4778                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4779                 .family = MV88E6XXX_FAMILY_6352,
4780                 .name = "Marvell 88E6176",
4781                 .num_databases = 4096,
4782                 .num_macs = 8192,
4783                 .num_ports = 7,
4784                 .num_internal_phys = 5,
4785                 .num_gpio = 15,
4786                 .max_vid = 4095,
4787                 .port_base_addr = 0x10,
4788                 .phy_base_addr = 0x0,
4789                 .global1_addr = 0x1b,
4790                 .global2_addr = 0x1c,
4791                 .age_time_coeff = 15000,
4792                 .g1_irqs = 9,
4793                 .g2_irqs = 10,
4794                 .atu_move_port_mask = 0xf,
4795                 .pvt = true,
4796                 .multi_chip = true,
4797                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4798                 .ops = &mv88e6176_ops,
4799         },
4800
4801         [MV88E6185] = {
4802                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4803                 .family = MV88E6XXX_FAMILY_6185,
4804                 .name = "Marvell 88E6185",
4805                 .num_databases = 256,
4806                 .num_macs = 8192,
4807                 .num_ports = 10,
4808                 .num_internal_phys = 0,
4809                 .max_vid = 4095,
4810                 .port_base_addr = 0x10,
4811                 .phy_base_addr = 0x0,
4812                 .global1_addr = 0x1b,
4813                 .global2_addr = 0x1c,
4814                 .age_time_coeff = 15000,
4815                 .g1_irqs = 8,
4816                 .atu_move_port_mask = 0xf,
4817                 .multi_chip = true,
4818                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4819                 .ops = &mv88e6185_ops,
4820         },
4821
4822         [MV88E6190] = {
4823                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4824                 .family = MV88E6XXX_FAMILY_6390,
4825                 .name = "Marvell 88E6190",
4826                 .num_databases = 4096,
4827                 .num_macs = 16384,
4828                 .num_ports = 11,        /* 10 + Z80 */
4829                 .num_internal_phys = 9,
4830                 .num_gpio = 16,
4831                 .max_vid = 8191,
4832                 .port_base_addr = 0x0,
4833                 .phy_base_addr = 0x0,
4834                 .global1_addr = 0x1b,
4835                 .global2_addr = 0x1c,
4836                 .tag_protocol = DSA_TAG_PROTO_DSA,
4837                 .age_time_coeff = 3750,
4838                 .g1_irqs = 9,
4839                 .g2_irqs = 14,
4840                 .pvt = true,
4841                 .multi_chip = true,
4842                 .atu_move_port_mask = 0x1f,
4843                 .ops = &mv88e6190_ops,
4844         },
4845
4846         [MV88E6190X] = {
4847                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4848                 .family = MV88E6XXX_FAMILY_6390,
4849                 .name = "Marvell 88E6190X",
4850                 .num_databases = 4096,
4851                 .num_macs = 16384,
4852                 .num_ports = 11,        /* 10 + Z80 */
4853                 .num_internal_phys = 9,
4854                 .num_gpio = 16,
4855                 .max_vid = 8191,
4856                 .port_base_addr = 0x0,
4857                 .phy_base_addr = 0x0,
4858                 .global1_addr = 0x1b,
4859                 .global2_addr = 0x1c,
4860                 .age_time_coeff = 3750,
4861                 .g1_irqs = 9,
4862                 .g2_irqs = 14,
4863                 .atu_move_port_mask = 0x1f,
4864                 .pvt = true,
4865                 .multi_chip = true,
4866                 .tag_protocol = DSA_TAG_PROTO_DSA,
4867                 .ops = &mv88e6190x_ops,
4868         },
4869
4870         [MV88E6191] = {
4871                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4872                 .family = MV88E6XXX_FAMILY_6390,
4873                 .name = "Marvell 88E6191",
4874                 .num_databases = 4096,
4875                 .num_macs = 16384,
4876                 .num_ports = 11,        /* 10 + Z80 */
4877                 .num_internal_phys = 9,
4878                 .max_vid = 8191,
4879                 .port_base_addr = 0x0,
4880                 .phy_base_addr = 0x0,
4881                 .global1_addr = 0x1b,
4882                 .global2_addr = 0x1c,
4883                 .age_time_coeff = 3750,
4884                 .g1_irqs = 9,
4885                 .g2_irqs = 14,
4886                 .atu_move_port_mask = 0x1f,
4887                 .pvt = true,
4888                 .multi_chip = true,
4889                 .tag_protocol = DSA_TAG_PROTO_DSA,
4890                 .ptp_support = true,
4891                 .ops = &mv88e6191_ops,
4892         },
4893
4894         [MV88E6220] = {
4895                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4896                 .family = MV88E6XXX_FAMILY_6250,
4897                 .name = "Marvell 88E6220",
4898                 .num_databases = 64,
4899
4900                 /* Ports 2-4 are not routed to pins
4901                  * => usable ports 0, 1, 5, 6
4902                  */
4903                 .num_ports = 7,
4904                 .num_internal_phys = 2,
4905                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
4906                 .max_vid = 4095,
4907                 .port_base_addr = 0x08,
4908                 .phy_base_addr = 0x00,
4909                 .global1_addr = 0x0f,
4910                 .global2_addr = 0x07,
4911                 .age_time_coeff = 15000,
4912                 .g1_irqs = 9,
4913                 .g2_irqs = 10,
4914                 .atu_move_port_mask = 0xf,
4915                 .dual_chip = true,
4916                 .tag_protocol = DSA_TAG_PROTO_DSA,
4917                 .ptp_support = true,
4918                 .ops = &mv88e6250_ops,
4919         },
4920
4921         [MV88E6240] = {
4922                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4923                 .family = MV88E6XXX_FAMILY_6352,
4924                 .name = "Marvell 88E6240",
4925                 .num_databases = 4096,
4926                 .num_macs = 8192,
4927                 .num_ports = 7,
4928                 .num_internal_phys = 5,
4929                 .num_gpio = 15,
4930                 .max_vid = 4095,
4931                 .port_base_addr = 0x10,
4932                 .phy_base_addr = 0x0,
4933                 .global1_addr = 0x1b,
4934                 .global2_addr = 0x1c,
4935                 .age_time_coeff = 15000,
4936                 .g1_irqs = 9,
4937                 .g2_irqs = 10,
4938                 .atu_move_port_mask = 0xf,
4939                 .pvt = true,
4940                 .multi_chip = true,
4941                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4942                 .ptp_support = true,
4943                 .ops = &mv88e6240_ops,
4944         },
4945
4946         [MV88E6250] = {
4947                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4948                 .family = MV88E6XXX_FAMILY_6250,
4949                 .name = "Marvell 88E6250",
4950                 .num_databases = 64,
4951                 .num_ports = 7,
4952                 .num_internal_phys = 5,
4953                 .max_vid = 4095,
4954                 .port_base_addr = 0x08,
4955                 .phy_base_addr = 0x00,
4956                 .global1_addr = 0x0f,
4957                 .global2_addr = 0x07,
4958                 .age_time_coeff = 15000,
4959                 .g1_irqs = 9,
4960                 .g2_irqs = 10,
4961                 .atu_move_port_mask = 0xf,
4962                 .dual_chip = true,
4963                 .tag_protocol = DSA_TAG_PROTO_DSA,
4964                 .ptp_support = true,
4965                 .ops = &mv88e6250_ops,
4966         },
4967
4968         [MV88E6290] = {
4969                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4970                 .family = MV88E6XXX_FAMILY_6390,
4971                 .name = "Marvell 88E6290",
4972                 .num_databases = 4096,
4973                 .num_ports = 11,        /* 10 + Z80 */
4974                 .num_internal_phys = 9,
4975                 .num_gpio = 16,
4976                 .max_vid = 8191,
4977                 .port_base_addr = 0x0,
4978                 .phy_base_addr = 0x0,
4979                 .global1_addr = 0x1b,
4980                 .global2_addr = 0x1c,
4981                 .age_time_coeff = 3750,
4982                 .g1_irqs = 9,
4983                 .g2_irqs = 14,
4984                 .atu_move_port_mask = 0x1f,
4985                 .pvt = true,
4986                 .multi_chip = true,
4987                 .tag_protocol = DSA_TAG_PROTO_DSA,
4988                 .ptp_support = true,
4989                 .ops = &mv88e6290_ops,
4990         },
4991
4992         [MV88E6320] = {
4993                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4994                 .family = MV88E6XXX_FAMILY_6320,
4995                 .name = "Marvell 88E6320",
4996                 .num_databases = 4096,
4997                 .num_macs = 8192,
4998                 .num_ports = 7,
4999                 .num_internal_phys = 5,
5000                 .num_gpio = 15,
5001                 .max_vid = 4095,
5002                 .port_base_addr = 0x10,
5003                 .phy_base_addr = 0x0,
5004                 .global1_addr = 0x1b,
5005                 .global2_addr = 0x1c,
5006                 .age_time_coeff = 15000,
5007                 .g1_irqs = 8,
5008                 .g2_irqs = 10,
5009                 .atu_move_port_mask = 0xf,
5010                 .pvt = true,
5011                 .multi_chip = true,
5012                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5013                 .ptp_support = true,
5014                 .ops = &mv88e6320_ops,
5015         },
5016
5017         [MV88E6321] = {
5018                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5019                 .family = MV88E6XXX_FAMILY_6320,
5020                 .name = "Marvell 88E6321",
5021                 .num_databases = 4096,
5022                 .num_macs = 8192,
5023                 .num_ports = 7,
5024                 .num_internal_phys = 5,
5025                 .num_gpio = 15,
5026                 .max_vid = 4095,
5027                 .port_base_addr = 0x10,
5028                 .phy_base_addr = 0x0,
5029                 .global1_addr = 0x1b,
5030                 .global2_addr = 0x1c,
5031                 .age_time_coeff = 15000,
5032                 .g1_irqs = 8,
5033                 .g2_irqs = 10,
5034                 .atu_move_port_mask = 0xf,
5035                 .multi_chip = true,
5036                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5037                 .ptp_support = true,
5038                 .ops = &mv88e6321_ops,
5039         },
5040
5041         [MV88E6341] = {
5042                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5043                 .family = MV88E6XXX_FAMILY_6341,
5044                 .name = "Marvell 88E6341",
5045                 .num_databases = 4096,
5046                 .num_macs = 2048,
5047                 .num_internal_phys = 5,
5048                 .num_ports = 6,
5049                 .num_gpio = 11,
5050                 .max_vid = 4095,
5051                 .port_base_addr = 0x10,
5052                 .phy_base_addr = 0x10,
5053                 .global1_addr = 0x1b,
5054                 .global2_addr = 0x1c,
5055                 .age_time_coeff = 3750,
5056                 .atu_move_port_mask = 0x1f,
5057                 .g1_irqs = 9,
5058                 .g2_irqs = 10,
5059                 .pvt = true,
5060                 .multi_chip = true,
5061                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5062                 .ptp_support = true,
5063                 .ops = &mv88e6341_ops,
5064         },
5065
5066         [MV88E6350] = {
5067                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5068                 .family = MV88E6XXX_FAMILY_6351,
5069                 .name = "Marvell 88E6350",
5070                 .num_databases = 4096,
5071                 .num_macs = 8192,
5072                 .num_ports = 7,
5073                 .num_internal_phys = 5,
5074                 .max_vid = 4095,
5075                 .port_base_addr = 0x10,
5076                 .phy_base_addr = 0x0,
5077                 .global1_addr = 0x1b,
5078                 .global2_addr = 0x1c,
5079                 .age_time_coeff = 15000,
5080                 .g1_irqs = 9,
5081                 .g2_irqs = 10,
5082                 .atu_move_port_mask = 0xf,
5083                 .pvt = true,
5084                 .multi_chip = true,
5085                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5086                 .ops = &mv88e6350_ops,
5087         },
5088
5089         [MV88E6351] = {
5090                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5091                 .family = MV88E6XXX_FAMILY_6351,
5092                 .name = "Marvell 88E6351",
5093                 .num_databases = 4096,
5094                 .num_macs = 8192,
5095                 .num_ports = 7,
5096                 .num_internal_phys = 5,
5097                 .max_vid = 4095,
5098                 .port_base_addr = 0x10,
5099                 .phy_base_addr = 0x0,
5100                 .global1_addr = 0x1b,
5101                 .global2_addr = 0x1c,
5102                 .age_time_coeff = 15000,
5103                 .g1_irqs = 9,
5104                 .g2_irqs = 10,
5105                 .atu_move_port_mask = 0xf,
5106                 .pvt = true,
5107                 .multi_chip = true,
5108                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5109                 .ops = &mv88e6351_ops,
5110         },
5111
5112         [MV88E6352] = {
5113                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5114                 .family = MV88E6XXX_FAMILY_6352,
5115                 .name = "Marvell 88E6352",
5116                 .num_databases = 4096,
5117                 .num_macs = 8192,
5118                 .num_ports = 7,
5119                 .num_internal_phys = 5,
5120                 .num_gpio = 15,
5121                 .max_vid = 4095,
5122                 .port_base_addr = 0x10,
5123                 .phy_base_addr = 0x0,
5124                 .global1_addr = 0x1b,
5125                 .global2_addr = 0x1c,
5126                 .age_time_coeff = 15000,
5127                 .g1_irqs = 9,
5128                 .g2_irqs = 10,
5129                 .atu_move_port_mask = 0xf,
5130                 .pvt = true,
5131                 .multi_chip = true,
5132                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5133                 .ptp_support = true,
5134                 .ops = &mv88e6352_ops,
5135         },
5136         [MV88E6390] = {
5137                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5138                 .family = MV88E6XXX_FAMILY_6390,
5139                 .name = "Marvell 88E6390",
5140                 .num_databases = 4096,
5141                 .num_macs = 16384,
5142                 .num_ports = 11,        /* 10 + Z80 */
5143                 .num_internal_phys = 9,
5144                 .num_gpio = 16,
5145                 .max_vid = 8191,
5146                 .port_base_addr = 0x0,
5147                 .phy_base_addr = 0x0,
5148                 .global1_addr = 0x1b,
5149                 .global2_addr = 0x1c,
5150                 .age_time_coeff = 3750,
5151                 .g1_irqs = 9,
5152                 .g2_irqs = 14,
5153                 .atu_move_port_mask = 0x1f,
5154                 .pvt = true,
5155                 .multi_chip = true,
5156                 .tag_protocol = DSA_TAG_PROTO_DSA,
5157                 .ptp_support = true,
5158                 .ops = &mv88e6390_ops,
5159         },
5160         [MV88E6390X] = {
5161                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5162                 .family = MV88E6XXX_FAMILY_6390,
5163                 .name = "Marvell 88E6390X",
5164                 .num_databases = 4096,
5165                 .num_macs = 16384,
5166                 .num_ports = 11,        /* 10 + Z80 */
5167                 .num_internal_phys = 9,
5168                 .num_gpio = 16,
5169                 .max_vid = 8191,
5170                 .port_base_addr = 0x0,
5171                 .phy_base_addr = 0x0,
5172                 .global1_addr = 0x1b,
5173                 .global2_addr = 0x1c,
5174                 .age_time_coeff = 3750,
5175                 .g1_irqs = 9,
5176                 .g2_irqs = 14,
5177                 .atu_move_port_mask = 0x1f,
5178                 .pvt = true,
5179                 .multi_chip = true,
5180                 .tag_protocol = DSA_TAG_PROTO_DSA,
5181                 .ptp_support = true,
5182                 .ops = &mv88e6390x_ops,
5183         },
5184 };
5185
5186 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5187 {
5188         int i;
5189
5190         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5191                 if (mv88e6xxx_table[i].prod_num == prod_num)
5192                         return &mv88e6xxx_table[i];
5193
5194         return NULL;
5195 }
5196
5197 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5198 {
5199         const struct mv88e6xxx_info *info;
5200         unsigned int prod_num, rev;
5201         u16 id;
5202         int err;
5203
5204         mv88e6xxx_reg_lock(chip);
5205         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5206         mv88e6xxx_reg_unlock(chip);
5207         if (err)
5208                 return err;
5209
5210         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5211         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5212
5213         info = mv88e6xxx_lookup_info(prod_num);
5214         if (!info)
5215                 return -ENODEV;
5216
5217         /* Update the compatible info with the probed one */
5218         chip->info = info;
5219
5220         err = mv88e6xxx_g2_require(chip);
5221         if (err)
5222                 return err;
5223
5224         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5225                  chip->info->prod_num, chip->info->name, rev);
5226
5227         return 0;
5228 }
5229
5230 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5231 {
5232         struct mv88e6xxx_chip *chip;
5233
5234         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5235         if (!chip)
5236                 return NULL;
5237
5238         chip->dev = dev;
5239
5240         mutex_init(&chip->reg_lock);
5241         INIT_LIST_HEAD(&chip->mdios);
5242         idr_init(&chip->policies);
5243
5244         return chip;
5245 }
5246
5247 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5248                                                         int port,
5249                                                         enum dsa_tag_protocol m)
5250 {
5251         struct mv88e6xxx_chip *chip = ds->priv;
5252
5253         return chip->info->tag_protocol;
5254 }
5255
5256 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5257                                       const struct switchdev_obj_port_mdb *mdb)
5258 {
5259         /* We don't need any dynamic resource from the kernel (yet),
5260          * so skip the prepare phase.
5261          */
5262
5263         return 0;
5264 }
5265
5266 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5267                                    const struct switchdev_obj_port_mdb *mdb)
5268 {
5269         struct mv88e6xxx_chip *chip = ds->priv;
5270
5271         mv88e6xxx_reg_lock(chip);
5272         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5273                                          MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5274                 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5275                         port);
5276         mv88e6xxx_reg_unlock(chip);
5277 }
5278
5279 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5280                                   const struct switchdev_obj_port_mdb *mdb)
5281 {
5282         struct mv88e6xxx_chip *chip = ds->priv;
5283         int err;
5284
5285         mv88e6xxx_reg_lock(chip);
5286         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5287         mv88e6xxx_reg_unlock(chip);
5288
5289         return err;
5290 }
5291
5292 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5293                                      struct dsa_mall_mirror_tc_entry *mirror,
5294                                      bool ingress)
5295 {
5296         enum mv88e6xxx_egress_direction direction = ingress ?
5297                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5298                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5299         struct mv88e6xxx_chip *chip = ds->priv;
5300         bool other_mirrors = false;
5301         int i;
5302         int err;
5303
5304         if (!chip->info->ops->set_egress_port)
5305                 return -EOPNOTSUPP;
5306
5307         mutex_lock(&chip->reg_lock);
5308         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5309             mirror->to_local_port) {
5310                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5311                         other_mirrors |= ingress ?
5312                                          chip->ports[i].mirror_ingress :
5313                                          chip->ports[i].mirror_egress;
5314
5315                 /* Can't change egress port when other mirror is active */
5316                 if (other_mirrors) {
5317                         err = -EBUSY;
5318                         goto out;
5319                 }
5320
5321                 err = chip->info->ops->set_egress_port(chip,
5322                                                        direction,
5323                                                        mirror->to_local_port);
5324                 if (err)
5325                         goto out;
5326         }
5327
5328         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5329 out:
5330         mutex_unlock(&chip->reg_lock);
5331
5332         return err;
5333 }
5334
5335 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5336                                       struct dsa_mall_mirror_tc_entry *mirror)
5337 {
5338         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5339                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5340                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5341         struct mv88e6xxx_chip *chip = ds->priv;
5342         bool other_mirrors = false;
5343         int i;
5344
5345         mutex_lock(&chip->reg_lock);
5346         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5347                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5348
5349         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5350                 other_mirrors |= mirror->ingress ?
5351                                  chip->ports[i].mirror_ingress :
5352                                  chip->ports[i].mirror_egress;
5353
5354         /* Reset egress port when no other mirror is active */
5355         if (!other_mirrors) {
5356                 if (chip->info->ops->set_egress_port(chip,
5357                                                      direction,
5358                                                      dsa_upstream_port(ds,
5359                                                                        port)))
5360                         dev_err(ds->dev, "failed to set egress port\n");
5361         }
5362
5363         mutex_unlock(&chip->reg_lock);
5364 }
5365
5366 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5367                                          bool unicast, bool multicast)
5368 {
5369         struct mv88e6xxx_chip *chip = ds->priv;
5370         int err = -EOPNOTSUPP;
5371
5372         mv88e6xxx_reg_lock(chip);
5373         if (chip->info->ops->port_set_egress_floods)
5374                 err = chip->info->ops->port_set_egress_floods(chip, port,
5375                                                               unicast,
5376                                                               multicast);
5377         mv88e6xxx_reg_unlock(chip);
5378
5379         return err;
5380 }
5381
5382 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5383         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
5384         .setup                  = mv88e6xxx_setup,
5385         .teardown               = mv88e6xxx_teardown,
5386         .phylink_validate       = mv88e6xxx_validate,
5387         .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
5388         .phylink_mac_config     = mv88e6xxx_mac_config,
5389         .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
5390         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
5391         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
5392         .get_strings            = mv88e6xxx_get_strings,
5393         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
5394         .get_sset_count         = mv88e6xxx_get_sset_count,
5395         .port_enable            = mv88e6xxx_port_enable,
5396         .port_disable           = mv88e6xxx_port_disable,
5397         .port_max_mtu           = mv88e6xxx_get_max_mtu,
5398         .port_change_mtu        = mv88e6xxx_change_mtu,
5399         .get_mac_eee            = mv88e6xxx_get_mac_eee,
5400         .set_mac_eee            = mv88e6xxx_set_mac_eee,
5401         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
5402         .get_eeprom             = mv88e6xxx_get_eeprom,
5403         .set_eeprom             = mv88e6xxx_set_eeprom,
5404         .get_regs_len           = mv88e6xxx_get_regs_len,
5405         .get_regs               = mv88e6xxx_get_regs,
5406         .get_rxnfc              = mv88e6xxx_get_rxnfc,
5407         .set_rxnfc              = mv88e6xxx_set_rxnfc,
5408         .set_ageing_time        = mv88e6xxx_set_ageing_time,
5409         .port_bridge_join       = mv88e6xxx_port_bridge_join,
5410         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
5411         .port_egress_floods     = mv88e6xxx_port_egress_floods,
5412         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
5413         .port_fast_age          = mv88e6xxx_port_fast_age,
5414         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
5415         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
5416         .port_vlan_add          = mv88e6xxx_port_vlan_add,
5417         .port_vlan_del          = mv88e6xxx_port_vlan_del,
5418         .port_fdb_add           = mv88e6xxx_port_fdb_add,
5419         .port_fdb_del           = mv88e6xxx_port_fdb_del,
5420         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
5421         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
5422         .port_mdb_add           = mv88e6xxx_port_mdb_add,
5423         .port_mdb_del           = mv88e6xxx_port_mdb_del,
5424         .port_mirror_add        = mv88e6xxx_port_mirror_add,
5425         .port_mirror_del        = mv88e6xxx_port_mirror_del,
5426         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
5427         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5428         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
5429         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
5430         .port_txtstamp          = mv88e6xxx_port_txtstamp,
5431         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
5432         .get_ts_info            = mv88e6xxx_get_ts_info,
5433         .devlink_param_get      = mv88e6xxx_devlink_param_get,
5434         .devlink_param_set      = mv88e6xxx_devlink_param_set,
5435         .devlink_info_get       = mv88e6xxx_devlink_info_get,
5436 };
5437
5438 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5439 {
5440         struct device *dev = chip->dev;
5441         struct dsa_switch *ds;
5442
5443         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5444         if (!ds)
5445                 return -ENOMEM;
5446
5447         ds->dev = dev;
5448         ds->num_ports = mv88e6xxx_num_ports(chip);
5449         ds->priv = chip;
5450         ds->dev = dev;
5451         ds->ops = &mv88e6xxx_switch_ops;
5452         ds->ageing_time_min = chip->info->age_time_coeff;
5453         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5454
5455         dev_set_drvdata(dev, ds);
5456
5457         return dsa_register_switch(ds);
5458 }
5459
5460 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5461 {
5462         dsa_unregister_switch(chip->ds);
5463 }
5464
5465 static const void *pdata_device_get_match_data(struct device *dev)
5466 {
5467         const struct of_device_id *matches = dev->driver->of_match_table;
5468         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5469
5470         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5471              matches++) {
5472                 if (!strcmp(pdata->compatible, matches->compatible))
5473                         return matches->data;
5474         }
5475         return NULL;
5476 }
5477
5478 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5479  * would be lost after a power cycle so prevent it to be suspended.
5480  */
5481 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5482 {
5483         return -EOPNOTSUPP;
5484 }
5485
5486 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5487 {
5488         return 0;
5489 }
5490
5491 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5492
5493 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5494 {
5495         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5496         const struct mv88e6xxx_info *compat_info = NULL;
5497         struct device *dev = &mdiodev->dev;
5498         struct device_node *np = dev->of_node;
5499         struct mv88e6xxx_chip *chip;
5500         int port;
5501         int err;
5502
5503         if (!np && !pdata)
5504                 return -EINVAL;
5505
5506         if (np)
5507                 compat_info = of_device_get_match_data(dev);
5508
5509         if (pdata) {
5510                 compat_info = pdata_device_get_match_data(dev);
5511
5512                 if (!pdata->netdev)
5513                         return -EINVAL;
5514
5515                 for (port = 0; port < DSA_MAX_PORTS; port++) {
5516                         if (!(pdata->enabled_ports & (1 << port)))
5517                                 continue;
5518                         if (strcmp(pdata->cd.port_names[port], "cpu"))
5519                                 continue;
5520                         pdata->cd.netdev[port] = &pdata->netdev->dev;
5521                         break;
5522                 }
5523         }
5524
5525         if (!compat_info)
5526                 return -EINVAL;
5527
5528         chip = mv88e6xxx_alloc_chip(dev);
5529         if (!chip) {
5530                 err = -ENOMEM;
5531                 goto out;
5532         }
5533
5534         chip->info = compat_info;
5535
5536         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5537         if (err)
5538                 goto out;
5539
5540         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5541         if (IS_ERR(chip->reset)) {
5542                 err = PTR_ERR(chip->reset);
5543                 goto out;
5544         }
5545         if (chip->reset)
5546                 usleep_range(1000, 2000);
5547
5548         err = mv88e6xxx_detect(chip);
5549         if (err)
5550                 goto out;
5551
5552         mv88e6xxx_phy_init(chip);
5553
5554         if (chip->info->ops->get_eeprom) {
5555                 if (np)
5556                         of_property_read_u32(np, "eeprom-length",
5557                                              &chip->eeprom_len);
5558                 else
5559                         chip->eeprom_len = pdata->eeprom_len;
5560         }
5561
5562         mv88e6xxx_reg_lock(chip);
5563         err = mv88e6xxx_switch_reset(chip);
5564         mv88e6xxx_reg_unlock(chip);
5565         if (err)
5566                 goto out;
5567
5568         if (np) {
5569                 chip->irq = of_irq_get(np, 0);
5570                 if (chip->irq == -EPROBE_DEFER) {
5571                         err = chip->irq;
5572                         goto out;
5573                 }
5574         }
5575
5576         if (pdata)
5577                 chip->irq = pdata->irq;
5578
5579         /* Has to be performed before the MDIO bus is created, because
5580          * the PHYs will link their interrupts to these interrupt
5581          * controllers
5582          */
5583         mv88e6xxx_reg_lock(chip);
5584         if (chip->irq > 0)
5585                 err = mv88e6xxx_g1_irq_setup(chip);
5586         else
5587                 err = mv88e6xxx_irq_poll_setup(chip);
5588         mv88e6xxx_reg_unlock(chip);
5589
5590         if (err)
5591                 goto out;
5592
5593         if (chip->info->g2_irqs > 0) {
5594                 err = mv88e6xxx_g2_irq_setup(chip);
5595                 if (err)
5596                         goto out_g1_irq;
5597         }
5598
5599         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5600         if (err)
5601                 goto out_g2_irq;
5602
5603         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5604         if (err)
5605                 goto out_g1_atu_prob_irq;
5606
5607         err = mv88e6xxx_mdios_register(chip, np);
5608         if (err)
5609                 goto out_g1_vtu_prob_irq;
5610
5611         err = mv88e6xxx_register_switch(chip);
5612         if (err)
5613                 goto out_mdio;
5614
5615         return 0;
5616
5617 out_mdio:
5618         mv88e6xxx_mdios_unregister(chip);
5619 out_g1_vtu_prob_irq:
5620         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5621 out_g1_atu_prob_irq:
5622         mv88e6xxx_g1_atu_prob_irq_free(chip);
5623 out_g2_irq:
5624         if (chip->info->g2_irqs > 0)
5625                 mv88e6xxx_g2_irq_free(chip);
5626 out_g1_irq:
5627         if (chip->irq > 0)
5628                 mv88e6xxx_g1_irq_free(chip);
5629         else
5630                 mv88e6xxx_irq_poll_free(chip);
5631 out:
5632         if (pdata)
5633                 dev_put(pdata->netdev);
5634
5635         return err;
5636 }
5637
5638 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5639 {
5640         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5641         struct mv88e6xxx_chip *chip = ds->priv;
5642
5643         if (chip->info->ptp_support) {
5644                 mv88e6xxx_hwtstamp_free(chip);
5645                 mv88e6xxx_ptp_free(chip);
5646         }
5647
5648         mv88e6xxx_phy_destroy(chip);
5649         mv88e6xxx_unregister_switch(chip);
5650         mv88e6xxx_mdios_unregister(chip);
5651
5652         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5653         mv88e6xxx_g1_atu_prob_irq_free(chip);
5654
5655         if (chip->info->g2_irqs > 0)
5656                 mv88e6xxx_g2_irq_free(chip);
5657
5658         if (chip->irq > 0)
5659                 mv88e6xxx_g1_irq_free(chip);
5660         else
5661                 mv88e6xxx_irq_poll_free(chip);
5662 }
5663
5664 static const struct of_device_id mv88e6xxx_of_match[] = {
5665         {
5666                 .compatible = "marvell,mv88e6085",
5667                 .data = &mv88e6xxx_table[MV88E6085],
5668         },
5669         {
5670                 .compatible = "marvell,mv88e6190",
5671                 .data = &mv88e6xxx_table[MV88E6190],
5672         },
5673         {
5674                 .compatible = "marvell,mv88e6250",
5675                 .data = &mv88e6xxx_table[MV88E6250],
5676         },
5677         { /* sentinel */ },
5678 };
5679
5680 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5681
5682 static struct mdio_driver mv88e6xxx_driver = {
5683         .probe  = mv88e6xxx_probe,
5684         .remove = mv88e6xxx_remove,
5685         .mdiodrv.driver = {
5686                 .name = "mv88e6085",
5687                 .of_match_table = mv88e6xxx_of_match,
5688                 .pm = &mv88e6xxx_pm_ops,
5689         },
5690 };
5691
5692 mdio_module_driver(mv88e6xxx_driver);
5693
5694 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5695 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5696 MODULE_LICENSE("GPL");