2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 static void be_mcc_notify(struct be_adapter *adapter)
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
31 /* To check if valid bit is set, check the entire word as we don't know
32 * the endianness of the data (old entry is host endian while a new entry is
34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
36 if (compl->flags != 0) {
37 compl->flags = le32_to_cpu(compl->flags);
38 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
45 /* Need to reset the entire word that houses the valid bit */
46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
51 static int be_mcc_compl_process(struct be_adapter *adapter,
52 struct be_mcc_compl *compl)
54 u16 compl_status, extd_status;
56 /* Just swap the status to host endian; mcc tag is opaquely copied
58 be_dws_le_to_cpu(compl, 4);
60 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
61 CQE_STATUS_COMPL_MASK;
62 if (compl_status == MCC_STATUS_SUCCESS) {
63 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
64 struct be_cmd_resp_get_stats *resp =
65 adapter->stats.cmd.va;
66 be_dws_le_to_cpu(&resp->hw_stats,
67 sizeof(resp->hw_stats));
68 netdev_stats_update(adapter);
70 } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
71 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
73 dev_warn(&adapter->pdev->dev,
74 "Error in cmd completion: status(compl/extd)=%d/%d\n",
75 compl_status, extd_status);
80 /* Link state evt is a string of bytes; no need for endian swapping */
81 static void be_async_link_state_process(struct be_adapter *adapter,
82 struct be_async_event_link_state *evt)
84 be_link_status_update(adapter,
85 evt->port_link_status == ASYNC_EVENT_LINK_UP);
88 static inline bool is_link_state_evt(u32 trailer)
90 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
91 ASYNC_TRAILER_EVENT_CODE_MASK) ==
92 ASYNC_EVENT_CODE_LINK_STATE);
95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
97 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
98 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
100 if (be_mcc_compl_is_new(compl)) {
101 queue_tail_inc(mcc_cq);
107 int be_process_mcc(struct be_adapter *adapter)
109 struct be_mcc_compl *compl;
110 int num = 0, status = 0;
112 spin_lock_bh(&adapter->mcc_cq_lock);
113 while ((compl = be_mcc_compl_get(adapter))) {
114 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
115 /* Interpret flags as an async trailer */
116 BUG_ON(!is_link_state_evt(compl->flags));
118 /* Interpret compl as a async link evt */
119 be_async_link_state_process(adapter,
120 (struct be_async_event_link_state *) compl);
121 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
122 status = be_mcc_compl_process(adapter, compl);
123 atomic_dec(&adapter->mcc_obj.q.used);
125 be_mcc_compl_use(compl);
130 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, num);
132 spin_unlock_bh(&adapter->mcc_cq_lock);
136 /* Wait till no more pending mcc requests are present */
137 static int be_mcc_wait_compl(struct be_adapter *adapter)
139 #define mcc_timeout 120000 /* 12s timeout */
141 for (i = 0; i < mcc_timeout; i++) {
142 status = be_process_mcc(adapter);
146 if (atomic_read(&adapter->mcc_obj.q.used) == 0)
150 if (i == mcc_timeout) {
151 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
157 /* Notify MCC requests and wait for completion */
158 static int be_mcc_notify_wait(struct be_adapter *adapter)
160 be_mcc_notify(adapter);
161 return be_mcc_wait_compl(adapter);
164 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
166 int cnt = 0, wait = 5;
170 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
175 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
189 * Insert the mailbox address into the doorbell in two steps
190 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
192 static int be_mbox_notify_wait(struct be_adapter *adapter)
196 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
197 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
198 struct be_mcc_mailbox *mbox = mbox_mem->va;
199 struct be_mcc_compl *compl = &mbox->compl;
201 val |= MPU_MAILBOX_DB_HI_MASK;
202 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
203 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
206 /* wait for ready to be set */
207 status = be_mbox_db_ready_wait(adapter, db);
212 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
213 val |= (u32)(mbox_mem->dma >> 4) << 2;
216 status = be_mbox_db_ready_wait(adapter, db);
220 /* A cq entry has been made now */
221 if (be_mcc_compl_is_new(compl)) {
222 status = be_mcc_compl_process(adapter, &mbox->compl);
223 be_mcc_compl_use(compl);
227 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
233 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
235 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
237 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
238 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
244 int be_cmd_POST(struct be_adapter *adapter)
247 int status, timeout = 0;
250 status = be_POST_stage_get(adapter, &stage);
252 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
255 } else if (stage != POST_STAGE_ARMFW_RDY) {
256 set_current_state(TASK_INTERRUPTIBLE);
257 schedule_timeout(2 * HZ);
262 } while (timeout < 20);
264 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
268 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
270 return wrb->payload.embedded_payload;
273 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
275 return &wrb->payload.sgl[0];
278 /* Don't touch the hdr after it's prepared */
279 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
280 bool embedded, u8 sge_cnt)
283 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
285 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
286 MCC_WRB_SGE_CNT_SHIFT;
287 wrb->payload_length = payload_len;
288 be_dws_cpu_to_le(wrb, 20);
291 /* Don't touch the hdr after it's prepared */
292 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
293 u8 subsystem, u8 opcode, int cmd_len)
295 req_hdr->opcode = opcode;
296 req_hdr->subsystem = subsystem;
297 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
300 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
301 struct be_dma_mem *mem)
303 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
304 u64 dma = (u64)mem->dma;
306 for (i = 0; i < buf_pages; i++) {
307 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
308 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
313 /* Converts interrupt delay in microseconds to multiplier value */
314 static u32 eq_delay_to_mult(u32 usec_delay)
316 #define MAX_INTR_RATE 651042
317 const u32 round = 10;
323 u32 interrupt_rate = 1000000 / usec_delay;
324 /* Max delay, corresponding to the lowest interrupt rate */
325 if (interrupt_rate == 0)
328 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
329 multiplier /= interrupt_rate;
330 /* Round the multiplier to the closest value.*/
331 multiplier = (multiplier + round/2) / round;
332 multiplier = min(multiplier, (u32)1023);
338 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
340 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
341 struct be_mcc_wrb *wrb
342 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
343 memset(wrb, 0, sizeof(*wrb));
347 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
349 struct be_queue_info *mccq = &adapter->mcc_obj.q;
350 struct be_mcc_wrb *wrb;
352 BUG_ON(atomic_read(&mccq->used) >= mccq->len);
353 wrb = queue_head_node(mccq);
354 queue_head_inc(mccq);
355 atomic_inc(&mccq->used);
356 memset(wrb, 0, sizeof(*wrb));
360 int be_cmd_eq_create(struct be_adapter *adapter,
361 struct be_queue_info *eq, int eq_delay)
363 struct be_mcc_wrb *wrb;
364 struct be_cmd_req_eq_create *req;
365 struct be_dma_mem *q_mem = &eq->dma_mem;
368 spin_lock(&adapter->mbox_lock);
370 wrb = wrb_from_mbox(adapter);
371 req = embedded_payload(wrb);
373 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
375 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
376 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
378 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
380 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
381 be_pci_func(adapter));
382 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
384 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
385 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
386 __ilog2_u32(eq->len/256));
387 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
388 eq_delay_to_mult(eq_delay));
389 be_dws_cpu_to_le(req->context, sizeof(req->context));
391 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
393 status = be_mbox_notify_wait(adapter);
395 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
396 eq->id = le16_to_cpu(resp->eq_id);
400 spin_unlock(&adapter->mbox_lock);
405 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
406 u8 type, bool permanent, u32 if_handle)
408 struct be_mcc_wrb *wrb;
409 struct be_cmd_req_mac_query *req;
412 spin_lock(&adapter->mbox_lock);
414 wrb = wrb_from_mbox(adapter);
415 req = embedded_payload(wrb);
417 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
419 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
420 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
426 req->if_id = cpu_to_le16((u16) if_handle);
430 status = be_mbox_notify_wait(adapter);
432 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
433 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
436 spin_unlock(&adapter->mbox_lock);
440 /* Uses synchronous MCCQ */
441 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
442 u32 if_id, u32 *pmac_id)
444 struct be_mcc_wrb *wrb;
445 struct be_cmd_req_pmac_add *req;
448 spin_lock_bh(&adapter->mcc_lock);
450 wrb = wrb_from_mccq(adapter);
451 req = embedded_payload(wrb);
453 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
455 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
456 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
458 req->if_id = cpu_to_le32(if_id);
459 memcpy(req->mac_address, mac_addr, ETH_ALEN);
461 status = be_mcc_notify_wait(adapter);
463 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
464 *pmac_id = le32_to_cpu(resp->pmac_id);
467 spin_unlock_bh(&adapter->mcc_lock);
471 /* Uses synchronous MCCQ */
472 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
474 struct be_mcc_wrb *wrb;
475 struct be_cmd_req_pmac_del *req;
478 spin_lock_bh(&adapter->mcc_lock);
480 wrb = wrb_from_mccq(adapter);
481 req = embedded_payload(wrb);
483 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
485 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
486 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
488 req->if_id = cpu_to_le32(if_id);
489 req->pmac_id = cpu_to_le32(pmac_id);
491 status = be_mcc_notify_wait(adapter);
493 spin_unlock_bh(&adapter->mcc_lock);
499 int be_cmd_cq_create(struct be_adapter *adapter,
500 struct be_queue_info *cq, struct be_queue_info *eq,
501 bool sol_evts, bool no_delay, int coalesce_wm)
503 struct be_mcc_wrb *wrb;
504 struct be_cmd_req_cq_create *req;
505 struct be_dma_mem *q_mem = &cq->dma_mem;
509 spin_lock(&adapter->mbox_lock);
511 wrb = wrb_from_mbox(adapter);
512 req = embedded_payload(wrb);
513 ctxt = &req->context;
515 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
517 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
518 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
520 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
522 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
523 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
524 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
525 __ilog2_u32(cq->len/256));
526 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
527 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
528 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
529 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
530 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
531 AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter));
532 be_dws_cpu_to_le(ctxt, sizeof(req->context));
534 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
536 status = be_mbox_notify_wait(adapter);
538 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
539 cq->id = le16_to_cpu(resp->cq_id);
543 spin_unlock(&adapter->mbox_lock);
548 static u32 be_encoded_q_len(int q_len)
550 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
551 if (len_encoded == 16)
556 int be_cmd_mccq_create(struct be_adapter *adapter,
557 struct be_queue_info *mccq,
558 struct be_queue_info *cq)
560 struct be_mcc_wrb *wrb;
561 struct be_cmd_req_mcc_create *req;
562 struct be_dma_mem *q_mem = &mccq->dma_mem;
566 spin_lock(&adapter->mbox_lock);
568 wrb = wrb_from_mbox(adapter);
569 req = embedded_payload(wrb);
570 ctxt = &req->context;
572 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
574 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
575 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
577 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
579 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter));
580 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
581 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
582 be_encoded_q_len(mccq->len));
583 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
585 be_dws_cpu_to_le(ctxt, sizeof(req->context));
587 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
589 status = be_mbox_notify_wait(adapter);
591 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
592 mccq->id = le16_to_cpu(resp->id);
593 mccq->created = true;
595 spin_unlock(&adapter->mbox_lock);
600 int be_cmd_txq_create(struct be_adapter *adapter,
601 struct be_queue_info *txq,
602 struct be_queue_info *cq)
604 struct be_mcc_wrb *wrb;
605 struct be_cmd_req_eth_tx_create *req;
606 struct be_dma_mem *q_mem = &txq->dma_mem;
610 spin_lock(&adapter->mbox_lock);
612 wrb = wrb_from_mbox(adapter);
613 req = embedded_payload(wrb);
614 ctxt = &req->context;
616 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
618 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
621 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
622 req->ulp_num = BE_ULP1_NUM;
623 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
625 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
626 be_encoded_q_len(txq->len));
627 AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
628 be_pci_func(adapter));
629 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
630 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
632 be_dws_cpu_to_le(ctxt, sizeof(req->context));
634 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
636 status = be_mbox_notify_wait(adapter);
638 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
639 txq->id = le16_to_cpu(resp->cid);
643 spin_unlock(&adapter->mbox_lock);
649 int be_cmd_rxq_create(struct be_adapter *adapter,
650 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
651 u16 max_frame_size, u32 if_id, u32 rss)
653 struct be_mcc_wrb *wrb;
654 struct be_cmd_req_eth_rx_create *req;
655 struct be_dma_mem *q_mem = &rxq->dma_mem;
658 spin_lock(&adapter->mbox_lock);
660 wrb = wrb_from_mbox(adapter);
661 req = embedded_payload(wrb);
663 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
665 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
668 req->cq_id = cpu_to_le16(cq_id);
669 req->frag_size = fls(frag_size) - 1;
671 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
672 req->interface_id = cpu_to_le32(if_id);
673 req->max_frame_size = cpu_to_le16(max_frame_size);
674 req->rss_queue = cpu_to_le32(rss);
676 status = be_mbox_notify_wait(adapter);
678 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
679 rxq->id = le16_to_cpu(resp->id);
683 spin_unlock(&adapter->mbox_lock);
688 /* Generic destroyer function for all types of queues
691 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
694 struct be_mcc_wrb *wrb;
695 struct be_cmd_req_q_destroy *req;
696 u8 subsys = 0, opcode = 0;
699 spin_lock(&adapter->mbox_lock);
701 wrb = wrb_from_mbox(adapter);
702 req = embedded_payload(wrb);
704 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
706 switch (queue_type) {
708 subsys = CMD_SUBSYSTEM_COMMON;
709 opcode = OPCODE_COMMON_EQ_DESTROY;
712 subsys = CMD_SUBSYSTEM_COMMON;
713 opcode = OPCODE_COMMON_CQ_DESTROY;
716 subsys = CMD_SUBSYSTEM_ETH;
717 opcode = OPCODE_ETH_TX_DESTROY;
720 subsys = CMD_SUBSYSTEM_ETH;
721 opcode = OPCODE_ETH_RX_DESTROY;
724 subsys = CMD_SUBSYSTEM_COMMON;
725 opcode = OPCODE_COMMON_MCC_DESTROY;
730 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
731 req->id = cpu_to_le16(q->id);
733 status = be_mbox_notify_wait(adapter);
735 spin_unlock(&adapter->mbox_lock);
740 /* Create an rx filtering policy configuration on an i/f
743 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
744 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
746 struct be_mcc_wrb *wrb;
747 struct be_cmd_req_if_create *req;
750 spin_lock(&adapter->mbox_lock);
752 wrb = wrb_from_mbox(adapter);
753 req = embedded_payload(wrb);
755 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
757 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
758 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
760 req->capability_flags = cpu_to_le32(cap_flags);
761 req->enable_flags = cpu_to_le32(en_flags);
762 req->pmac_invalid = pmac_invalid;
764 memcpy(req->mac_addr, mac, ETH_ALEN);
766 status = be_mbox_notify_wait(adapter);
768 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
769 *if_handle = le32_to_cpu(resp->interface_id);
771 *pmac_id = le32_to_cpu(resp->pmac_id);
774 spin_unlock(&adapter->mbox_lock);
779 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
781 struct be_mcc_wrb *wrb;
782 struct be_cmd_req_if_destroy *req;
785 spin_lock(&adapter->mbox_lock);
787 wrb = wrb_from_mbox(adapter);
788 req = embedded_payload(wrb);
790 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
792 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
793 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
795 req->interface_id = cpu_to_le32(interface_id);
797 status = be_mbox_notify_wait(adapter);
799 spin_unlock(&adapter->mbox_lock);
804 /* Get stats is a non embedded command: the request is not embedded inside
805 * WRB but is a separate dma memory block
806 * Uses asynchronous MCC
808 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
810 struct be_mcc_wrb *wrb;
811 struct be_cmd_req_get_stats *req;
814 spin_lock_bh(&adapter->mcc_lock);
816 wrb = wrb_from_mccq(adapter);
817 req = nonemb_cmd->va;
818 sge = nonembedded_sgl(wrb);
820 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
821 wrb->tag0 = OPCODE_ETH_GET_STATISTICS;
823 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
824 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
825 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
826 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
827 sge->len = cpu_to_le32(nonemb_cmd->size);
829 be_mcc_notify(adapter);
831 spin_unlock_bh(&adapter->mcc_lock);
835 /* Uses synchronous mcc */
836 int be_cmd_link_status_query(struct be_adapter *adapter,
839 struct be_mcc_wrb *wrb;
840 struct be_cmd_req_link_status *req;
843 spin_lock_bh(&adapter->mcc_lock);
845 wrb = wrb_from_mccq(adapter);
846 req = embedded_payload(wrb);
850 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
852 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
853 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
855 status = be_mcc_notify_wait(adapter);
857 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
858 if (resp->mac_speed != PHY_LINK_SPEED_ZERO)
862 spin_unlock_bh(&adapter->mcc_lock);
867 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
869 struct be_mcc_wrb *wrb;
870 struct be_cmd_req_get_fw_version *req;
873 spin_lock(&adapter->mbox_lock);
875 wrb = wrb_from_mbox(adapter);
876 req = embedded_payload(wrb);
878 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
880 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
881 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
883 status = be_mbox_notify_wait(adapter);
885 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
886 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
889 spin_unlock(&adapter->mbox_lock);
893 /* set the EQ delay interval of an EQ to specified value
896 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
898 struct be_mcc_wrb *wrb;
899 struct be_cmd_req_modify_eq_delay *req;
901 spin_lock_bh(&adapter->mcc_lock);
903 wrb = wrb_from_mccq(adapter);
904 req = embedded_payload(wrb);
906 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
908 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
909 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
911 req->num_eq = cpu_to_le32(1);
912 req->delay[0].eq_id = cpu_to_le32(eq_id);
913 req->delay[0].phase = 0;
914 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
916 be_mcc_notify(adapter);
918 spin_unlock_bh(&adapter->mcc_lock);
922 /* Uses sycnhronous mcc */
923 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
924 u32 num, bool untagged, bool promiscuous)
926 struct be_mcc_wrb *wrb;
927 struct be_cmd_req_vlan_config *req;
930 spin_lock_bh(&adapter->mcc_lock);
932 wrb = wrb_from_mccq(adapter);
933 req = embedded_payload(wrb);
935 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
937 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
938 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
940 req->interface_id = if_id;
941 req->promiscuous = promiscuous;
942 req->untagged = untagged;
945 memcpy(req->normal_vlan, vtag_array,
946 req->num_vlan * sizeof(vtag_array[0]));
949 status = be_mcc_notify_wait(adapter);
951 spin_unlock_bh(&adapter->mcc_lock);
955 /* Uses MCC for this command as it may be called in BH context
956 * Uses synchronous mcc
958 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
960 struct be_mcc_wrb *wrb;
961 struct be_cmd_req_promiscuous_config *req;
964 spin_lock_bh(&adapter->mcc_lock);
966 wrb = wrb_from_mccq(adapter);
967 req = embedded_payload(wrb);
969 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
971 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
972 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
975 req->port1_promiscuous = en;
977 req->port0_promiscuous = en;
979 status = be_mcc_notify_wait(adapter);
981 spin_unlock_bh(&adapter->mcc_lock);
986 * Uses MCC for this command as it may be called in BH context
987 * (mc == NULL) => multicast promiscous
989 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
990 struct dev_mc_list *mc_list, u32 mc_count)
992 #define BE_MAX_MC 32 /* set mcast promisc if > 32 */
993 struct be_mcc_wrb *wrb;
994 struct be_cmd_req_mcast_mac_config *req;
996 spin_lock_bh(&adapter->mcc_lock);
998 wrb = wrb_from_mccq(adapter);
999 req = embedded_payload(wrb);
1001 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1003 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1004 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1006 req->interface_id = if_id;
1007 if (mc_list && mc_count <= BE_MAX_MC) {
1009 struct dev_mc_list *mc;
1011 req->num_mac = cpu_to_le16(mc_count);
1013 for (mc = mc_list, i = 0; mc; mc = mc->next, i++)
1014 memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1016 req->promiscuous = 1;
1019 be_mcc_notify_wait(adapter);
1021 spin_unlock_bh(&adapter->mcc_lock);
1026 /* Uses synchrounous mcc */
1027 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1029 struct be_mcc_wrb *wrb;
1030 struct be_cmd_req_set_flow_control *req;
1033 spin_lock_bh(&adapter->mcc_lock);
1035 wrb = wrb_from_mccq(adapter);
1036 req = embedded_payload(wrb);
1038 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1040 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1041 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1043 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1044 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1046 status = be_mcc_notify_wait(adapter);
1048 spin_unlock_bh(&adapter->mcc_lock);
1053 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1055 struct be_mcc_wrb *wrb;
1056 struct be_cmd_req_get_flow_control *req;
1059 spin_lock_bh(&adapter->mcc_lock);
1061 wrb = wrb_from_mccq(adapter);
1062 req = embedded_payload(wrb);
1064 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1066 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1067 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1069 status = be_mcc_notify_wait(adapter);
1071 struct be_cmd_resp_get_flow_control *resp =
1072 embedded_payload(wrb);
1073 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1074 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1077 spin_unlock_bh(&adapter->mcc_lock);
1082 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1084 struct be_mcc_wrb *wrb;
1085 struct be_cmd_req_query_fw_cfg *req;
1088 spin_lock(&adapter->mbox_lock);
1090 wrb = wrb_from_mbox(adapter);
1091 req = embedded_payload(wrb);
1093 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1095 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1096 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1098 status = be_mbox_notify_wait(adapter);
1100 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1101 *port_num = le32_to_cpu(resp->phys_port);
1102 *cap = le32_to_cpu(resp->function_cap);
1105 spin_unlock(&adapter->mbox_lock);
1110 int be_cmd_reset_function(struct be_adapter *adapter)
1112 struct be_mcc_wrb *wrb;
1113 struct be_cmd_req_hdr *req;
1116 spin_lock(&adapter->mbox_lock);
1118 wrb = wrb_from_mbox(adapter);
1119 req = embedded_payload(wrb);
1121 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1123 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1124 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1126 status = be_mbox_notify_wait(adapter);
1128 spin_unlock(&adapter->mbox_lock);
1133 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1134 u8 bcn, u8 sts, u8 state)
1136 struct be_mcc_wrb *wrb;
1137 struct be_cmd_req_enable_disable_beacon *req;
1140 spin_lock_bh(&adapter->mcc_lock);
1142 wrb = wrb_from_mccq(adapter);
1143 req = embedded_payload(wrb);
1145 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1147 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1148 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1150 req->port_num = port_num;
1151 req->beacon_state = state;
1152 req->beacon_duration = bcn;
1153 req->status_duration = sts;
1155 status = be_mcc_notify_wait(adapter);
1157 spin_unlock_bh(&adapter->mcc_lock);
1162 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1164 struct be_mcc_wrb *wrb;
1165 struct be_cmd_req_get_beacon_state *req;
1168 spin_lock_bh(&adapter->mcc_lock);
1170 wrb = wrb_from_mccq(adapter);
1171 req = embedded_payload(wrb);
1173 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1175 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1176 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1178 req->port_num = port_num;
1180 status = be_mcc_notify_wait(adapter);
1182 struct be_cmd_resp_get_beacon_state *resp =
1183 embedded_payload(wrb);
1184 *state = resp->beacon_state;
1187 spin_unlock_bh(&adapter->mcc_lock);
1191 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1192 u32 flash_type, u32 flash_opcode, u32 buf_size)
1194 struct be_mcc_wrb *wrb;
1195 struct be_cmd_write_flashrom *req = cmd->va;
1199 spin_lock_bh(&adapter->mcc_lock);
1201 wrb = wrb_from_mccq(adapter);
1202 sge = nonembedded_sgl(wrb);
1204 be_wrb_hdr_prepare(wrb, cmd->size, false, 1);
1206 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1207 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1208 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1209 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1210 sge->len = cpu_to_le32(cmd->size);
1212 req->params.op_type = cpu_to_le32(flash_type);
1213 req->params.op_code = cpu_to_le32(flash_opcode);
1214 req->params.data_buf_size = cpu_to_le32(buf_size);
1216 status = be_mcc_notify_wait(adapter);
1218 spin_unlock_bh(&adapter->mcc_lock);