1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/mutex.h>
15 #include <linux/math64.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
18 #include <linux/sort.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/of_platform.h>
22 #include <linux/spi/flash.h>
23 #include <linux/mtd/spi-nor.h>
25 /* Define max times to check status register before we give up. */
28 * For everything but full-chip erase; probably could be much smaller, but kept
29 * around for safety for now
31 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
39 #define SPI_NOR_MAX_ID_LEN 6
40 #define SPI_NOR_MAX_ADDR_WIDTH 4
42 struct spi_nor_read_command {
46 enum spi_nor_protocol proto;
49 struct spi_nor_pp_command {
51 enum spi_nor_protocol proto;
54 enum spi_nor_read_command_index {
57 SNOR_CMD_READ_1_1_1_DTR,
63 SNOR_CMD_READ_1_2_2_DTR,
69 SNOR_CMD_READ_1_4_4_DTR,
75 SNOR_CMD_READ_1_8_8_DTR,
80 enum spi_nor_pp_command_index {
96 struct spi_nor_flash_parameter {
100 struct spi_nor_hwcaps hwcaps;
101 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
102 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
104 int (*quad_enable)(struct spi_nor *nor);
107 struct sfdp_parameter_header {
111 u8 length; /* in double words */
112 u8 parameter_table_pointer[3]; /* byte address */
116 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
117 #define SFDP_PARAM_HEADER_PTP(p) \
118 (((p)->parameter_table_pointer[2] << 16) | \
119 ((p)->parameter_table_pointer[1] << 8) | \
120 ((p)->parameter_table_pointer[0] << 0))
122 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
123 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
124 #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
126 #define SFDP_SIGNATURE 0x50444653U
127 #define SFDP_JESD216_MAJOR 1
128 #define SFDP_JESD216_MINOR 0
129 #define SFDP_JESD216A_MINOR 5
130 #define SFDP_JESD216B_MINOR 6
133 u32 signature; /* Ox50444653U <=> "SFDP" */
136 u8 nph; /* 0-base number of parameter headers */
139 /* Basic Flash Parameter Table. */
140 struct sfdp_parameter_header bfpt_header;
143 /* Basic Flash Parameter Table */
146 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
147 * They are indexed from 1 but C arrays are indexed from 0.
149 #define BFPT_DWORD(i) ((i) - 1)
150 #define BFPT_DWORD_MAX 16
152 /* The first version of JESB216 defined only 9 DWORDs. */
153 #define BFPT_DWORD_MAX_JESD216 9
156 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
157 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
158 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
159 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
160 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
161 #define BFPT_DWORD1_DTR BIT(19)
162 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
163 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
164 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
167 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
168 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
171 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
172 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
177 * (from JESD216 rev B)
178 * Quad Enable Requirements (QER):
179 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
180 * reads based on instruction. DQ3/HOLD# functions are hold during
182 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
183 * two data bytes where bit 1 of the second byte is one.
185 * Writing only one byte to the status register has the side-effect of
186 * clearing status register 2, including the QE bit. The 100b code is
187 * used if writing one byte to the status register does not modify
189 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
190 * one data byte where bit 6 is one.
192 * - 011b: QE is bit 7 of status register 2. It is set via Write status
193 * register 2 instruction 3Eh with one data byte where bit 7 is one.
195 * The status register 2 is read using instruction 3Fh.
196 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
197 * two data bytes where bit 1 of the second byte is one.
199 * In contrast to the 001b code, writing one byte to the status
200 * register does not modify status register 2.
201 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
202 * Read Status instruction 05h. Status register2 is read using
203 * instruction 35h. QE is set via Writ Status instruction 01h with
204 * two data bytes where bit 1 of the second byte is one.
207 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
208 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
209 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
210 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
211 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
212 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
213 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
216 u32 dwords[BFPT_DWORD_MAX];
220 * struct spi_nor_fixups - SPI NOR fixup hooks
221 * @post_bfpt: called after the BFPT table has been parsed
223 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
224 * table is broken or not available.
226 struct spi_nor_fixups {
227 int (*post_bfpt)(struct spi_nor *nor,
228 const struct sfdp_parameter_header *bfpt_header,
229 const struct sfdp_bfpt *bfpt,
230 struct spi_nor_flash_parameter *params);
237 * This array stores the ID bytes.
238 * The first three bytes are the JEDIC ID.
239 * JEDEC ID zero means "no ID" (mostly older chips).
241 u8 id[SPI_NOR_MAX_ID_LEN];
244 /* The size listed here is what works with SPINOR_OP_SE, which isn't
245 * necessarily called a "sector" by the vendor.
247 unsigned sector_size;
254 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
255 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
256 #define SST_WRITE BIT(2) /* use SST byte programming */
257 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
258 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
259 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
260 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
261 #define USE_FSR BIT(7) /* use flag status register */
262 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
263 #define SPI_NOR_HAS_TB BIT(9) /*
264 * Flash SR has Top/Bottom (TB) protect
265 * bit. Must be used with
268 #define SPI_S3AN BIT(10) /*
269 * Xilinx Spartan 3AN In-System Flash
270 * (MFR cannot be used for probing
271 * because it has the same value as
274 #define SPI_NOR_4B_OPCODES BIT(11) /*
275 * Use dedicated 4byte address op codes
276 * to support memory size above 128Mib.
278 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
279 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
280 #define USE_CLSR BIT(14) /* use CLSR command */
282 /* Part specific fixup hooks. */
283 const struct spi_nor_fixups *fixups;
285 int (*quad_enable)(struct spi_nor *nor);
288 #define JEDEC_MFR(info) ((info)->id[0])
291 * Read the status register, returning its value in the location
292 * Return the status register value.
293 * Returns negative if error occurred.
295 static int read_sr(struct spi_nor *nor)
300 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
302 pr_err("error %d reading SR\n", (int) ret);
310 * Read the flag status register, returning its value in the location
311 * Return the status register value.
312 * Returns negative if error occurred.
314 static int read_fsr(struct spi_nor *nor)
319 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
321 pr_err("error %d reading FSR\n", ret);
329 * Read configuration register, returning its value in the
330 * location. Return the configuration register value.
331 * Returns negative if error occurred.
333 static int read_cr(struct spi_nor *nor)
338 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
340 dev_err(nor->dev, "error %d reading CR\n", ret);
348 * Write status register 1 byte
349 * Returns negative if error occurred.
351 static int write_sr(struct spi_nor *nor, u8 val)
353 nor->cmd_buf[0] = val;
354 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
358 * Set write enable latch with Write Enable command.
359 * Returns negative if error occurred.
361 static int write_enable(struct spi_nor *nor)
363 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
367 * Send write disable instruction to the chip.
369 static int write_disable(struct spi_nor *nor)
371 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
374 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
380 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
384 for (i = 0; i < size; i++)
385 if (table[i][0] == opcode)
388 /* No conversion found, keep input op code. */
392 static u8 spi_nor_convert_3to4_read(u8 opcode)
394 static const u8 spi_nor_3to4_read[][2] = {
395 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
396 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
397 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
398 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
399 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
400 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
402 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
403 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
404 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
407 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
408 ARRAY_SIZE(spi_nor_3to4_read));
411 static u8 spi_nor_convert_3to4_program(u8 opcode)
413 static const u8 spi_nor_3to4_program[][2] = {
414 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
415 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
416 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
419 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
420 ARRAY_SIZE(spi_nor_3to4_program));
423 static u8 spi_nor_convert_3to4_erase(u8 opcode)
425 static const u8 spi_nor_3to4_erase[][2] = {
426 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
427 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
428 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
431 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
432 ARRAY_SIZE(spi_nor_3to4_erase));
435 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
437 /* Do some manufacturer fixups first */
438 switch (JEDEC_MFR(nor->info)) {
439 case SNOR_MFR_SPANSION:
440 /* No small sector erase for 4-byte command set */
441 nor->erase_opcode = SPINOR_OP_SE;
442 nor->mtd.erasesize = nor->info->sector_size;
449 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
450 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
451 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
453 if (!spi_nor_has_uniform_erase(nor)) {
454 struct spi_nor_erase_map *map = &nor->erase_map;
455 struct spi_nor_erase_type *erase;
458 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
459 erase = &map->erase_type[i];
461 spi_nor_convert_3to4_erase(erase->opcode);
466 /* Enable/disable 4-byte addressing mode. */
467 static int set_4byte(struct spi_nor *nor, bool enable)
470 bool need_wren = false;
473 switch (JEDEC_MFR(nor->info)) {
475 case SNOR_MFR_MICRON:
476 /* Some Micron need WREN command; all will accept it */
479 case SNOR_MFR_MACRONIX:
480 case SNOR_MFR_WINBOND:
484 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
485 status = nor->write_reg(nor, cmd, NULL, 0);
489 if (!status && !enable &&
490 JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND) {
492 * On Winbond W25Q256FV, leaving 4byte mode causes
493 * the Extended Address Register to be set to 1, so all
494 * 3-byte-address reads come from the second 16M.
495 * We must clear the register to enable normal behavior.
499 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
506 nor->cmd_buf[0] = enable << 7;
507 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
511 static int s3an_sr_ready(struct spi_nor *nor)
516 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
518 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
522 return !!(val & XSR_RDY);
525 static int spi_nor_sr_ready(struct spi_nor *nor)
527 int sr = read_sr(nor);
531 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
533 dev_err(nor->dev, "Erase Error occurred\n");
535 dev_err(nor->dev, "Programming Error occurred\n");
537 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
541 return !(sr & SR_WIP);
544 static int spi_nor_fsr_ready(struct spi_nor *nor)
546 int fsr = read_fsr(nor);
550 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
552 dev_err(nor->dev, "Erase operation failed.\n");
554 dev_err(nor->dev, "Program operation failed.\n");
556 if (fsr & FSR_PT_ERR)
558 "Attempted to modify a protected sector.\n");
560 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
564 return fsr & FSR_READY;
567 static int spi_nor_ready(struct spi_nor *nor)
571 if (nor->flags & SNOR_F_READY_XSR_RDY)
572 sr = s3an_sr_ready(nor);
574 sr = spi_nor_sr_ready(nor);
577 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
584 * Service routine to read status register until ready, or timeout occurs.
585 * Returns non-zero if error.
587 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
588 unsigned long timeout_jiffies)
590 unsigned long deadline;
591 int timeout = 0, ret;
593 deadline = jiffies + timeout_jiffies;
596 if (time_after_eq(jiffies, deadline))
599 ret = spi_nor_ready(nor);
608 dev_err(nor->dev, "flash operation timed out\n");
613 static int spi_nor_wait_till_ready(struct spi_nor *nor)
615 return spi_nor_wait_till_ready_with_timeout(nor,
616 DEFAULT_READY_WAIT_JIFFIES);
620 * Erase the whole flash memory
622 * Returns 0 if successful, non-zero otherwise.
624 static int erase_chip(struct spi_nor *nor)
626 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
628 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
631 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
635 mutex_lock(&nor->lock);
638 ret = nor->prepare(nor, ops);
640 dev_err(nor->dev, "failed in the preparation.\n");
641 mutex_unlock(&nor->lock);
648 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
651 nor->unprepare(nor, ops);
652 mutex_unlock(&nor->lock);
656 * This code converts an address to the Default Address Mode, that has non
657 * power of two page sizes. We must support this mode because it is the default
658 * mode supported by Xilinx tools, it can access the whole flash area and
659 * changing over to the Power-of-two mode is irreversible and corrupts the
661 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
664 static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
669 offset = addr % nor->page_size;
670 page = addr / nor->page_size;
671 page <<= (nor->page_size > 512) ? 10 : 9;
673 return page | offset;
677 * Initiate the erasure of a single sector
679 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
681 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
684 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
685 addr = spi_nor_s3an_addr_convert(nor, addr);
688 return nor->erase(nor, addr);
691 * Default implementation, if driver doesn't have a specialized HW
694 for (i = nor->addr_width - 1; i >= 0; i--) {
695 buf[i] = addr & 0xff;
699 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
703 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
704 * @erase: pointer to a structure that describes a SPI NOR erase type
705 * @dividend: dividend value
706 * @remainder: pointer to u32 remainder (will be updated)
708 * Return: the result of the division
710 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
711 u64 dividend, u32 *remainder)
713 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
714 *remainder = (u32)dividend & erase->size_mask;
715 return dividend >> erase->size_shift;
719 * spi_nor_find_best_erase_type() - find the best erase type for the given
720 * offset in the serial flash memory and the
721 * number of bytes to erase. The region in
722 * which the address fits is expected to be
724 * @map: the erase map of the SPI NOR
725 * @region: pointer to a structure that describes a SPI NOR erase region
726 * @addr: offset in the serial flash memory
727 * @len: number of bytes to erase
729 * Return: a pointer to the best fitted erase type, NULL otherwise.
731 static const struct spi_nor_erase_type *
732 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
733 const struct spi_nor_erase_region *region,
736 const struct spi_nor_erase_type *erase;
739 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
742 * Erase types are ordered by size, with the biggest erase type at
745 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
746 /* Does the erase region support the tested erase type? */
747 if (!(erase_mask & BIT(i)))
750 erase = &map->erase_type[i];
752 /* Don't erase more than what the user has asked for. */
753 if (erase->size > len)
756 /* Alignment is not mandatory for overlaid regions */
757 if (region->offset & SNOR_OVERLAID_REGION)
760 spi_nor_div_by_erase_size(erase, addr, &rem);
771 * spi_nor_region_next() - get the next spi nor region
772 * @region: pointer to a structure that describes a SPI NOR erase region
774 * Return: the next spi nor region or NULL if last region.
776 static struct spi_nor_erase_region *
777 spi_nor_region_next(struct spi_nor_erase_region *region)
779 if (spi_nor_region_is_last(region))
786 * spi_nor_find_erase_region() - find the region of the serial flash memory in
787 * which the offset fits
788 * @map: the erase map of the SPI NOR
789 * @addr: offset in the serial flash memory
791 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
794 static struct spi_nor_erase_region *
795 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
797 struct spi_nor_erase_region *region = map->regions;
798 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
799 u64 region_end = region_start + region->size;
801 while (addr < region_start || addr >= region_end) {
802 region = spi_nor_region_next(region);
804 return ERR_PTR(-EINVAL);
806 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
807 region_end = region_start + region->size;
814 * spi_nor_init_erase_cmd() - initialize an erase command
815 * @region: pointer to a structure that describes a SPI NOR erase region
816 * @erase: pointer to a structure that describes a SPI NOR erase type
818 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
821 static struct spi_nor_erase_command *
822 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
823 const struct spi_nor_erase_type *erase)
825 struct spi_nor_erase_command *cmd;
827 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
829 return ERR_PTR(-ENOMEM);
831 INIT_LIST_HEAD(&cmd->list);
832 cmd->opcode = erase->opcode;
835 if (region->offset & SNOR_OVERLAID_REGION)
836 cmd->size = region->size;
838 cmd->size = erase->size;
844 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
845 * @erase_list: list of erase commands
847 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
849 struct spi_nor_erase_command *cmd, *next;
851 list_for_each_entry_safe(cmd, next, erase_list, list) {
852 list_del(&cmd->list);
858 * spi_nor_init_erase_cmd_list() - initialize erase command list
859 * @nor: pointer to a 'struct spi_nor'
860 * @erase_list: list of erase commands to be executed once we validate that the
861 * erase can be performed
862 * @addr: offset in the serial flash memory
863 * @len: number of bytes to erase
865 * Builds the list of best fitted erase commands and verifies if the erase can
868 * Return: 0 on success, -errno otherwise.
870 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
871 struct list_head *erase_list,
874 const struct spi_nor_erase_map *map = &nor->erase_map;
875 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
876 struct spi_nor_erase_region *region;
877 struct spi_nor_erase_command *cmd = NULL;
881 region = spi_nor_find_erase_region(map, addr);
883 return PTR_ERR(region);
885 region_end = spi_nor_region_end(region);
888 erase = spi_nor_find_best_erase_type(map, region, addr, len);
890 goto destroy_erase_cmd_list;
892 if (prev_erase != erase ||
893 region->offset & SNOR_OVERLAID_REGION) {
894 cmd = spi_nor_init_erase_cmd(region, erase);
897 goto destroy_erase_cmd_list;
900 list_add_tail(&cmd->list, erase_list);
908 if (len && addr >= region_end) {
909 region = spi_nor_region_next(region);
911 goto destroy_erase_cmd_list;
912 region_end = spi_nor_region_end(region);
920 destroy_erase_cmd_list:
921 spi_nor_destroy_erase_cmd_list(erase_list);
926 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
927 * @nor: pointer to a 'struct spi_nor'
928 * @addr: offset in the serial flash memory
929 * @len: number of bytes to erase
931 * Build a list of best fitted erase commands and execute it once we validate
932 * that the erase can be performed.
934 * Return: 0 on success, -errno otherwise.
936 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
938 LIST_HEAD(erase_list);
939 struct spi_nor_erase_command *cmd, *next;
942 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
946 list_for_each_entry_safe(cmd, next, &erase_list, list) {
947 nor->erase_opcode = cmd->opcode;
951 ret = spi_nor_erase_sector(nor, addr);
953 goto destroy_erase_cmd_list;
958 ret = spi_nor_wait_till_ready(nor);
960 goto destroy_erase_cmd_list;
962 list_del(&cmd->list);
968 destroy_erase_cmd_list:
969 spi_nor_destroy_erase_cmd_list(&erase_list);
974 * Erase an address range on the nor chip. The address range may extend
975 * one or more erase sectors. Return an error is there is a problem erasing.
977 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
979 struct spi_nor *nor = mtd_to_spi_nor(mtd);
984 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
985 (long long)instr->len);
987 if (spi_nor_has_uniform_erase(nor)) {
988 div_u64_rem(instr->len, mtd->erasesize, &rem);
996 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
1000 /* whole-chip erase? */
1001 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1002 unsigned long timeout;
1006 if (erase_chip(nor)) {
1012 * Scale the timeout linearly with the size of the flash, with
1013 * a minimum calibrated to an old 2MB flash. We could try to
1014 * pull these from CFI/SFDP, but these values should be good
1017 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1018 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1019 (unsigned long)(mtd->size / SZ_2M));
1020 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1024 /* REVISIT in some cases we could speed up erasing large regions
1025 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1026 * to use "small sector erase", but that's not always optimal.
1029 /* "sector"-at-a-time erase */
1030 } else if (spi_nor_has_uniform_erase(nor)) {
1034 ret = spi_nor_erase_sector(nor, addr);
1038 addr += mtd->erasesize;
1039 len -= mtd->erasesize;
1041 ret = spi_nor_wait_till_ready(nor);
1046 /* erase multiple sectors */
1048 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1056 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
1061 /* Write status register and ensure bits in mask match written values */
1062 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
1067 ret = write_sr(nor, status_new);
1071 ret = spi_nor_wait_till_ready(nor);
1079 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
1082 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
1085 struct mtd_info *mtd = &nor->mtd;
1086 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1087 int shift = ffs(mask) - 1;
1095 pow = ((sr & mask) ^ mask) >> shift;
1096 *len = mtd->size >> pow;
1097 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
1100 *ofs = mtd->size - *len;
1105 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1106 * @locked is false); 0 otherwise
1108 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1117 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
1120 /* Requested range is a sub-range of locked range */
1121 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1123 /* Requested range does not overlap with locked range */
1124 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1127 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1130 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
1133 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1136 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
1140 * Lock a region of the flash. Compatible with ST Micro and similar flash.
1141 * Supports the block protection bits BP{0,1,2} in the status register
1142 * (SR). Does not support these features found in newer SR bitfields:
1143 * - SEC: sector/block protect - only handle SEC=0 (block protect)
1144 * - CMP: complement protect - only support CMP=0 (range is not complemented)
1146 * Support for the following is provided conditionally for some flash:
1147 * - TB: top/bottom protect
1149 * Sample table portion for 8MB flash (Winbond w25q64fw):
1151 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1152 * --------------------------------------------------------------------------
1153 * X | X | 0 | 0 | 0 | NONE | NONE
1154 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1155 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1156 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1157 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1158 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1159 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1160 * X | X | 1 | 1 | 1 | 8 MB | ALL
1161 * ------|-------|-------|-------|-------|---------------|-------------------
1162 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1163 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1164 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1165 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1166 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1167 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1169 * Returns negative on errors, 0 on success.
1171 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1173 struct mtd_info *mtd = &nor->mtd;
1174 int status_old, status_new;
1175 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1176 u8 shift = ffs(mask) - 1, pow, val;
1178 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1181 status_old = read_sr(nor);
1185 /* If nothing in our range is unlocked, we don't need to do anything */
1186 if (stm_is_locked_sr(nor, ofs, len, status_old))
1189 /* If anything below us is unlocked, we can't use 'bottom' protection */
1190 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
1191 can_be_bottom = false;
1193 /* If anything above us is unlocked, we can't use 'top' protection */
1194 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1198 if (!can_be_bottom && !can_be_top)
1201 /* Prefer top, if both are valid */
1202 use_top = can_be_top;
1204 /* lock_len: length of region that should end up locked */
1206 lock_len = mtd->size - ofs;
1208 lock_len = ofs + len;
1211 * Need smallest pow such that:
1213 * 1 / (2^pow) <= (len / size)
1215 * so (assuming power-of-2 size) we do:
1217 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
1219 pow = ilog2(mtd->size) - ilog2(lock_len);
1220 val = mask - (pow << shift);
1223 /* Don't "lock" with no region! */
1227 status_new = (status_old & ~mask & ~SR_TB) | val;
1229 /* Disallow further writes if WP pin is asserted */
1230 status_new |= SR_SRWD;
1233 status_new |= SR_TB;
1235 /* Don't bother if they're the same */
1236 if (status_new == status_old)
1239 /* Only modify protection if it will not unlock other areas */
1240 if ((status_new & mask) < (status_old & mask))
1243 return write_sr_and_check(nor, status_new, mask);
1247 * Unlock a region of the flash. See stm_lock() for more info
1249 * Returns negative on errors, 0 on success.
1251 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1253 struct mtd_info *mtd = &nor->mtd;
1254 int status_old, status_new;
1255 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1256 u8 shift = ffs(mask) - 1, pow, val;
1258 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1261 status_old = read_sr(nor);
1265 /* If nothing in our range is locked, we don't need to do anything */
1266 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1269 /* If anything below us is locked, we can't use 'top' protection */
1270 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1273 /* If anything above us is locked, we can't use 'bottom' protection */
1274 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1276 can_be_bottom = false;
1278 if (!can_be_bottom && !can_be_top)
1281 /* Prefer top, if both are valid */
1282 use_top = can_be_top;
1284 /* lock_len: length of region that should remain locked */
1286 lock_len = mtd->size - (ofs + len);
1291 * Need largest pow such that:
1293 * 1 / (2^pow) >= (len / size)
1295 * so (assuming power-of-2 size) we do:
1297 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1299 pow = ilog2(mtd->size) - order_base_2(lock_len);
1300 if (lock_len == 0) {
1301 val = 0; /* fully unlocked */
1303 val = mask - (pow << shift);
1304 /* Some power-of-two sizes are not supported */
1309 status_new = (status_old & ~mask & ~SR_TB) | val;
1311 /* Don't protect status register if we're fully unlocked */
1313 status_new &= ~SR_SRWD;
1316 status_new |= SR_TB;
1318 /* Don't bother if they're the same */
1319 if (status_new == status_old)
1322 /* Only modify protection if it will not lock other areas */
1323 if ((status_new & mask) > (status_old & mask))
1326 return write_sr_and_check(nor, status_new, mask);
1330 * Check if a region of the flash is (completely) locked. See stm_lock() for
1333 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1334 * negative on errors.
1336 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1340 status = read_sr(nor);
1344 return stm_is_locked_sr(nor, ofs, len, status);
1347 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1349 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1352 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
1356 ret = nor->flash_lock(nor, ofs, len);
1358 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
1362 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1364 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1367 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1371 ret = nor->flash_unlock(nor, ofs, len);
1373 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1377 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1379 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1382 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1386 ret = nor->flash_is_locked(nor, ofs, len);
1388 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1393 * Write status Register and configuration register with 2 bytes
1394 * The first byte will be written to the status register, while the
1395 * second byte will be written to the configuration register.
1396 * Return negative if error occurred.
1398 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1404 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1407 "error while writing configuration register\n");
1411 ret = spi_nor_wait_till_ready(nor);
1414 "timeout while writing configuration register\n");
1422 * macronix_quad_enable() - set QE bit in Status Register.
1423 * @nor: pointer to a 'struct spi_nor'
1425 * Set the Quad Enable (QE) bit in the Status Register.
1427 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1429 * Return: 0 on success, -errno otherwise.
1431 static int macronix_quad_enable(struct spi_nor *nor)
1438 if (val & SR_QUAD_EN_MX)
1443 write_sr(nor, val | SR_QUAD_EN_MX);
1445 ret = spi_nor_wait_till_ready(nor);
1450 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1451 dev_err(nor->dev, "Macronix Quad bit not set\n");
1459 * spansion_quad_enable() - set QE bit in Configuraiton Register.
1460 * @nor: pointer to a 'struct spi_nor'
1462 * Set the Quad Enable (QE) bit in the Configuration Register.
1463 * This function is kept for legacy purpose because it has been used for a
1464 * long time without anybody complaining but it should be considered as
1465 * deprecated and maybe buggy.
1466 * First, this function doesn't care about the previous values of the Status
1467 * and Configuration Registers when it sets the QE bit (bit 1) in the
1468 * Configuration Register: all other bits are cleared, which may have unwanted
1469 * side effects like removing some block protections.
1470 * Secondly, it uses the Read Configuration Register (35h) instruction though
1471 * some very old and few memories don't support this instruction. If a pull-up
1472 * resistor is present on the MISO/IO1 line, we might still be able to pass the
1473 * "read back" test because the QSPI memory doesn't recognize the command,
1474 * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
1476 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1479 * Return: 0 on success, -errno otherwise.
1481 static int spansion_quad_enable(struct spi_nor *nor)
1483 u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
1486 ret = write_sr_cr(nor, sr_cr);
1490 /* read back and check it */
1492 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1493 dev_err(nor->dev, "Spansion Quad bit not set\n");
1501 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1502 * @nor: pointer to a 'struct spi_nor'
1504 * Set the Quad Enable (QE) bit in the Configuration Register.
1505 * This function should be used with QSPI memories not supporting the Read
1506 * Configuration Register (35h) instruction.
1508 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1511 * Return: 0 on success, -errno otherwise.
1513 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1518 /* Keep the current value of the Status Register. */
1521 dev_err(nor->dev, "error while reading status register\n");
1525 sr_cr[1] = CR_QUAD_EN_SPAN;
1527 return write_sr_cr(nor, sr_cr);
1531 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1532 * @nor: pointer to a 'struct spi_nor'
1534 * Set the Quad Enable (QE) bit in the Configuration Register.
1535 * This function should be used with QSPI memories supporting the Read
1536 * Configuration Register (35h) instruction.
1538 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1541 * Return: 0 on success, -errno otherwise.
1543 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1545 struct device *dev = nor->dev;
1549 /* Check current Quad Enable bit value. */
1552 dev_err(dev, "error while reading configuration register\n");
1556 if (ret & CR_QUAD_EN_SPAN)
1559 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1561 /* Keep the current value of the Status Register. */
1564 dev_err(dev, "error while reading status register\n");
1569 ret = write_sr_cr(nor, sr_cr);
1573 /* Read back and check it. */
1575 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1576 dev_err(nor->dev, "Spansion Quad bit not set\n");
1584 * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1585 * @nor: pointer to a 'struct spi_nor'
1587 * Set the Quad Enable (QE) bit in the Status Register 2.
1589 * This is one of the procedures to set the QE bit described in the SFDP
1590 * (JESD216 rev B) specification but no manufacturer using this procedure has
1591 * been identified yet, hence the name of the function.
1593 * Return: 0 on success, -errno otherwise.
1595 static int sr2_bit7_quad_enable(struct spi_nor *nor)
1600 /* Check current Quad Enable bit value. */
1601 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1604 if (sr2 & SR2_QUAD_EN_BIT7)
1607 /* Update the Quad Enable bit. */
1608 sr2 |= SR2_QUAD_EN_BIT7;
1612 ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
1614 dev_err(nor->dev, "error while writing status register 2\n");
1618 ret = spi_nor_wait_till_ready(nor);
1620 dev_err(nor->dev, "timeout while writing status register 2\n");
1624 /* Read back and check it. */
1625 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1626 if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
1627 dev_err(nor->dev, "SR2 Quad bit not set\n");
1634 /* Used when the "_ext_id" is two bytes at most */
1635 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
1637 ((_jedec_id) >> 16) & 0xff, \
1638 ((_jedec_id) >> 8) & 0xff, \
1639 (_jedec_id) & 0xff, \
1640 ((_ext_id) >> 8) & 0xff, \
1643 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
1644 .sector_size = (_sector_size), \
1645 .n_sectors = (_n_sectors), \
1649 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
1651 ((_jedec_id) >> 16) & 0xff, \
1652 ((_jedec_id) >> 8) & 0xff, \
1653 (_jedec_id) & 0xff, \
1654 ((_ext_id) >> 16) & 0xff, \
1655 ((_ext_id) >> 8) & 0xff, \
1659 .sector_size = (_sector_size), \
1660 .n_sectors = (_n_sectors), \
1664 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
1665 .sector_size = (_sector_size), \
1666 .n_sectors = (_n_sectors), \
1667 .page_size = (_page_size), \
1668 .addr_width = (_addr_width), \
1671 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
1673 ((_jedec_id) >> 16) & 0xff, \
1674 ((_jedec_id) >> 8) & 0xff, \
1675 (_jedec_id) & 0xff \
1678 .sector_size = (8*_page_size), \
1679 .n_sectors = (_n_sectors), \
1680 .page_size = _page_size, \
1682 .flags = SPI_NOR_NO_FR | SPI_S3AN,
1685 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
1686 const struct sfdp_parameter_header *bfpt_header,
1687 const struct sfdp_bfpt *bfpt,
1688 struct spi_nor_flash_parameter *params)
1691 * MX25L25635F supports 4B opcodes but MX25L25635E does not.
1692 * Unfortunately, Macronix has re-used the same JEDEC ID for both
1693 * variants which prevents us from defining a new entry in the parts
1695 * We need a way to differentiate MX25L25635E and MX25L25635F, and it
1696 * seems that the F version advertises support for Fast Read 4-4-4 in
1699 if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
1700 nor->flags |= SNOR_F_4B_OPCODES;
1705 static struct spi_nor_fixups mx25l25635_fixups = {
1706 .post_bfpt = mx25l25635_post_bfpt_fixups,
1709 /* NOTE: double check command sets and memory organization when you add
1710 * more nor chips. This current list focusses on newer chips, which
1711 * have been converging on command sets which including JEDEC ID.
1713 * All newly added entries should describe *hardware* and should use SECT_4K
1714 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
1715 * scenarios excluding small sectors there is config option that can be
1716 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
1717 * For historical (and compatibility) reasons (before we got above config) some
1718 * old entries may be missing 4K flag.
1720 static const struct flash_info spi_nor_ids[] = {
1721 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
1722 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
1723 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
1725 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
1726 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1727 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
1728 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
1730 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
1731 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
1732 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
1733 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1735 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
1737 /* EON -- en25xxx */
1738 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
1739 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
1740 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
1741 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
1742 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
1743 { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
1744 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
1745 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
1746 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
1749 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1750 { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1751 { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
1754 { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1755 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1756 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1757 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1760 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
1764 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
1765 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1766 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1769 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
1770 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1771 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1774 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
1775 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1776 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1779 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
1780 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1781 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1784 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
1785 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1786 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1789 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
1790 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1791 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1794 "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
1795 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1796 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1797 .quad_enable = macronix_quad_enable,
1800 /* Intel/Numonyx -- xxxs33b */
1801 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
1802 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
1803 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
1806 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
1807 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
1808 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1809 { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
1810 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1811 { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
1812 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1813 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
1814 SECT_4K | SPI_NOR_DUAL_READ) },
1815 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
1816 SECT_4K | SPI_NOR_DUAL_READ) },
1817 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
1818 SECT_4K | SPI_NOR_DUAL_READ) },
1819 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
1820 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1821 SPI_NOR_4B_OPCODES) },
1822 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
1823 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1824 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
1825 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1826 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
1827 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1830 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
1831 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
1832 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
1833 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1834 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
1835 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
1836 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
1837 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
1838 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
1839 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
1840 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
1841 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
1842 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1843 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1844 { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
1845 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1846 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
1847 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
1848 .fixups = &mx25l25635_fixups },
1849 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
1850 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1851 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1852 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1853 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1854 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1856 /* Micron <--> ST Micro */
1857 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
1858 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1859 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1860 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1861 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1862 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1863 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1864 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1865 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
1866 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1867 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1868 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1869 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1870 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1874 "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
1875 SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
1879 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
1880 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
1881 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
1883 /* Spansion/Cypress -- single (large) sector size only, at least
1884 * for the chips listed here (without boot sectors).
1886 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1887 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1888 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1889 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1890 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1891 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
1892 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1893 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1894 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1895 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1896 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1897 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
1898 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1899 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1900 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1901 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1902 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1903 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1904 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1905 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1906 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1907 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
1908 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
1909 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
1910 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
1911 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1912 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1913 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1915 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1916 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1917 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1918 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1919 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1920 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1921 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
1922 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
1923 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
1924 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
1925 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1926 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1927 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1928 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1930 /* ST Microelectronics -- newer production may have feature updates */
1931 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
1932 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1933 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1934 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1935 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1936 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1937 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1938 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1939 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1941 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1942 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1943 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1944 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1945 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1946 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1947 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1948 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1949 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1951 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1952 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1953 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1955 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1956 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1957 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1959 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1960 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1961 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1962 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1963 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1964 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
1966 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1967 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
1968 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1969 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1970 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1971 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1972 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1974 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
1975 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1976 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1978 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1979 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
1980 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
1981 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
1982 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1984 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1985 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1986 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1989 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
1990 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1991 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1993 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1994 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1996 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1997 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1998 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2001 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
2002 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2003 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2006 "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
2007 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2008 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2010 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
2011 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
2012 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
2013 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2014 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
2015 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
2017 /* Catalyst / On Semiconductor -- non-JEDEC */
2018 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2019 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2020 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2021 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2022 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2024 /* Xilinx S3AN Internal Flash */
2025 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
2026 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
2027 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
2028 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
2029 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
2031 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
2032 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2033 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2037 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
2040 u8 id[SPI_NOR_MAX_ID_LEN];
2041 const struct flash_info *info;
2043 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
2045 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
2046 return ERR_PTR(tmp);
2049 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
2050 info = &spi_nor_ids[tmp];
2052 if (!memcmp(info->id, id, info->id_len))
2053 return &spi_nor_ids[tmp];
2056 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
2057 id[0], id[1], id[2]);
2058 return ERR_PTR(-ENODEV);
2061 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2062 size_t *retlen, u_char *buf)
2064 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2067 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2069 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
2076 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
2077 addr = spi_nor_s3an_addr_convert(nor, addr);
2079 ret = nor->read(nor, addr, len, buf);
2081 /* We shouldn't see 0-length reads */
2097 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
2101 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
2102 size_t *retlen, const u_char *buf)
2104 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2108 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2110 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
2116 nor->sst_write_second = false;
2119 /* Start write from odd address. */
2121 nor->program_opcode = SPINOR_OP_BP;
2123 /* write one byte. */
2124 ret = nor->write(nor, to, 1, buf);
2127 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
2129 ret = spi_nor_wait_till_ready(nor);
2135 /* Write out most of the data here. */
2136 for (; actual < len - 1; actual += 2) {
2137 nor->program_opcode = SPINOR_OP_AAI_WP;
2139 /* write two bytes. */
2140 ret = nor->write(nor, to, 2, buf + actual);
2143 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
2145 ret = spi_nor_wait_till_ready(nor);
2149 nor->sst_write_second = true;
2151 nor->sst_write_second = false;
2154 ret = spi_nor_wait_till_ready(nor);
2158 /* Write out trailing byte if it exists. */
2159 if (actual != len) {
2162 nor->program_opcode = SPINOR_OP_BP;
2163 ret = nor->write(nor, to, 1, buf + actual);
2166 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
2168 ret = spi_nor_wait_till_ready(nor);
2176 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
2181 * Write an address range to the nor chip. Data must be written in
2182 * FLASH_PAGESIZE chunks. The address range may be any size provided
2183 * it is within the physical boundaries.
2185 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2186 size_t *retlen, const u_char *buf)
2188 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2189 size_t page_offset, page_remain, i;
2192 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2194 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
2198 for (i = 0; i < len; ) {
2200 loff_t addr = to + i;
2203 * If page_size is a power of two, the offset can be quickly
2204 * calculated with an AND operation. On the other cases we
2205 * need to do a modulus operation (more expensive).
2206 * Power of two numbers have only one bit set and we can use
2207 * the instruction hweight32 to detect if we need to do a
2208 * modulus (do_div()) or not.
2210 if (hweight32(nor->page_size) == 1) {
2211 page_offset = addr & (nor->page_size - 1);
2213 uint64_t aux = addr;
2215 page_offset = do_div(aux, nor->page_size);
2217 /* the size of data remaining on the first page */
2218 page_remain = min_t(size_t,
2219 nor->page_size - page_offset, len - i);
2221 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
2222 addr = spi_nor_s3an_addr_convert(nor, addr);
2225 ret = nor->write(nor, addr, page_remain, buf + i);
2230 ret = spi_nor_wait_till_ready(nor);
2238 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
2242 static int spi_nor_check(struct spi_nor *nor)
2244 if (!nor->dev || !nor->read || !nor->write ||
2245 !nor->read_reg || !nor->write_reg) {
2246 pr_err("spi-nor: please fill all the necessary fields!\n");
2253 static int s3an_nor_scan(struct spi_nor *nor)
2258 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
2260 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
2264 nor->erase_opcode = SPINOR_OP_XSE;
2265 nor->program_opcode = SPINOR_OP_XPP;
2266 nor->read_opcode = SPINOR_OP_READ;
2267 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2270 * This flashes have a page size of 264 or 528 bytes (known as
2271 * Default addressing mode). It can be changed to a more standard
2272 * Power of two mode where the page size is 256/512. This comes
2273 * with a price: there is 3% less of space, the data is corrupted
2274 * and the page size cannot be changed back to default addressing
2277 * The current addressing mode can be read from the XRDSR register
2278 * and should not be changed, because is a destructive operation.
2280 if (val & XSR_PAGESIZE) {
2281 /* Flash in Power of 2 mode */
2282 nor->page_size = (nor->page_size == 264) ? 256 : 512;
2283 nor->mtd.writebufsize = nor->page_size;
2284 nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
2285 nor->mtd.erasesize = 8 * nor->page_size;
2287 /* Flash in Default addressing mode */
2288 nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
2295 spi_nor_set_read_settings(struct spi_nor_read_command *read,
2299 enum spi_nor_protocol proto)
2301 read->num_mode_clocks = num_mode_clocks;
2302 read->num_wait_states = num_wait_states;
2303 read->opcode = opcode;
2304 read->proto = proto;
2308 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
2310 enum spi_nor_protocol proto)
2312 pp->opcode = opcode;
2316 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2320 for (i = 0; i < size; i++)
2321 if (table[i][0] == (int)hwcaps)
2327 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2329 static const int hwcaps_read2cmd[][2] = {
2330 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2331 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2332 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2333 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2334 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2335 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2336 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2337 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2338 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2339 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2340 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2341 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2342 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2343 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2344 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2347 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2348 ARRAY_SIZE(hwcaps_read2cmd));
2351 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2353 static const int hwcaps_pp2cmd[][2] = {
2354 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2355 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2356 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2357 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2358 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2359 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2360 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2363 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2364 ARRAY_SIZE(hwcaps_pp2cmd));
2368 * Serial Flash Discoverable Parameters (SFDP) parsing.
2372 * spi_nor_read_raw() - raw read of serial flash memory. read_opcode,
2373 * addr_width and read_dummy members of the struct spi_nor
2374 * should be previously
2376 * @nor: pointer to a 'struct spi_nor'
2377 * @addr: offset in the serial flash memory
2378 * @len: number of bytes to read
2379 * @buf: buffer where the data is copied into (dma-safe memory)
2381 * Return: 0 on success, -errno otherwise.
2383 static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
2388 ret = nor->read(nor, addr, len, buf);
2389 if (!ret || ret > len)
2402 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
2403 * @nor: pointer to a 'struct spi_nor'
2404 * @addr: offset in the SFDP area to start reading data from
2405 * @len: number of bytes to read
2406 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
2408 * Whatever the actual numbers of bytes for address and dummy cycles are
2409 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
2410 * followed by a 3-byte address and 8 dummy clock cycles.
2412 * Return: 0 on success, -errno otherwise.
2414 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
2415 size_t len, void *buf)
2417 u8 addr_width, read_opcode, read_dummy;
2420 read_opcode = nor->read_opcode;
2421 addr_width = nor->addr_width;
2422 read_dummy = nor->read_dummy;
2424 nor->read_opcode = SPINOR_OP_RDSFDP;
2425 nor->addr_width = 3;
2426 nor->read_dummy = 8;
2428 ret = spi_nor_read_raw(nor, addr, len, buf);
2430 nor->read_opcode = read_opcode;
2431 nor->addr_width = addr_width;
2432 nor->read_dummy = read_dummy;
2438 * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
2439 * @nor: pointer to a 'struct spi_nor'
2440 * @addr: offset in the SFDP area to start reading data from
2441 * @len: number of bytes to read
2442 * @buf: buffer where the SFDP data are copied into
2444 * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
2445 * guaranteed to be dma-safe.
2447 * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
2450 static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
2451 size_t len, void *buf)
2456 dma_safe_buf = kmalloc(len, GFP_KERNEL);
2460 ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
2461 memcpy(buf, dma_safe_buf, len);
2462 kfree(dma_safe_buf);
2467 /* Fast Read settings. */
2470 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
2472 enum spi_nor_protocol proto)
2474 read->num_mode_clocks = (half >> 5) & 0x07;
2475 read->num_wait_states = (half >> 0) & 0x1f;
2476 read->opcode = (half >> 8) & 0xff;
2477 read->proto = proto;
2480 struct sfdp_bfpt_read {
2481 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
2485 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
2486 * whether the Fast Read x-y-z command is supported.
2488 u32 supported_dword;
2492 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
2493 * encodes the op code, the number of mode clocks and the number of wait
2494 * states to be used by Fast Read x-y-z command.
2499 /* The SPI protocol for this Fast Read x-y-z command. */
2500 enum spi_nor_protocol proto;
2503 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
2504 /* Fast Read 1-1-2 */
2506 SNOR_HWCAPS_READ_1_1_2,
2507 BFPT_DWORD(1), BIT(16), /* Supported bit */
2508 BFPT_DWORD(4), 0, /* Settings */
2512 /* Fast Read 1-2-2 */
2514 SNOR_HWCAPS_READ_1_2_2,
2515 BFPT_DWORD(1), BIT(20), /* Supported bit */
2516 BFPT_DWORD(4), 16, /* Settings */
2520 /* Fast Read 2-2-2 */
2522 SNOR_HWCAPS_READ_2_2_2,
2523 BFPT_DWORD(5), BIT(0), /* Supported bit */
2524 BFPT_DWORD(6), 16, /* Settings */
2528 /* Fast Read 1-1-4 */
2530 SNOR_HWCAPS_READ_1_1_4,
2531 BFPT_DWORD(1), BIT(22), /* Supported bit */
2532 BFPT_DWORD(3), 16, /* Settings */
2536 /* Fast Read 1-4-4 */
2538 SNOR_HWCAPS_READ_1_4_4,
2539 BFPT_DWORD(1), BIT(21), /* Supported bit */
2540 BFPT_DWORD(3), 0, /* Settings */
2544 /* Fast Read 4-4-4 */
2546 SNOR_HWCAPS_READ_4_4_4,
2547 BFPT_DWORD(5), BIT(4), /* Supported bit */
2548 BFPT_DWORD(7), 16, /* Settings */
2553 struct sfdp_bfpt_erase {
2555 * The half-word at offset <shift> in DWORD <dwoard> encodes the
2556 * op code and erase sector size to be used by Sector Erase commands.
2562 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
2563 /* Erase Type 1 in DWORD8 bits[15:0] */
2566 /* Erase Type 2 in DWORD8 bits[31:16] */
2567 {BFPT_DWORD(8), 16},
2569 /* Erase Type 3 in DWORD9 bits[15:0] */
2572 /* Erase Type 4 in DWORD9 bits[31:16] */
2573 {BFPT_DWORD(9), 16},
2577 * spi_nor_set_erase_type() - set a SPI NOR erase type
2578 * @erase: pointer to a structure that describes a SPI NOR erase type
2579 * @size: the size of the sector/block erased by the erase type
2580 * @opcode: the SPI command op code to erase the sector/block
2582 static void spi_nor_set_erase_type(struct spi_nor_erase_type *erase,
2583 u32 size, u8 opcode)
2586 erase->opcode = opcode;
2587 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2588 erase->size_shift = ffs(erase->size) - 1;
2589 erase->size_mask = (1 << erase->size_shift) - 1;
2593 * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT
2594 * @erase: pointer to a structure that describes a SPI NOR erase type
2595 * @size: the size of the sector/block erased by the erase type
2596 * @opcode: the SPI command op code to erase the sector/block
2597 * @i: erase type index as sorted in the Basic Flash Parameter Table
2599 * The supported Erase Types will be sorted at init in ascending order, with
2600 * the smallest Erase Type size being the first member in the erase_type array
2601 * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in
2602 * the Basic Flash Parameter Table since it will be used later on to
2603 * synchronize with the supported Erase Types defined in SFDP optional tables.
2606 spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase,
2607 u32 size, u8 opcode, u8 i)
2610 spi_nor_set_erase_type(erase, size, opcode);
2614 * spi_nor_map_cmp_erase_type() - compare the map's erase types by size
2615 * @l: member in the left half of the map's erase_type array
2616 * @r: member in the right half of the map's erase_type array
2618 * Comparison function used in the sort() call to sort in ascending order the
2619 * map's erase types, the smallest erase type size being the first member in the
2620 * sorted erase_type array.
2622 * Return: the result of @l->size - @r->size
2624 static int spi_nor_map_cmp_erase_type(const void *l, const void *r)
2626 const struct spi_nor_erase_type *left = l, *right = r;
2628 return left->size - right->size;
2632 * spi_nor_sort_erase_mask() - sort erase mask
2633 * @map: the erase map of the SPI NOR
2634 * @erase_mask: the erase type mask to be sorted
2636 * Replicate the sort done for the map's erase types in BFPT: sort the erase
2637 * mask in ascending order with the smallest erase type size starting from
2638 * BIT(0) in the sorted erase mask.
2640 * Return: sorted erase mask.
2642 static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask)
2644 struct spi_nor_erase_type *erase_type = map->erase_type;
2646 u8 sorted_erase_mask = 0;
2651 /* Replicate the sort done for the map's erase types. */
2652 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
2653 if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx))
2654 sorted_erase_mask |= BIT(i);
2656 return sorted_erase_mask;
2660 * spi_nor_regions_sort_erase_types() - sort erase types in each region
2661 * @map: the erase map of the SPI NOR
2663 * Function assumes that the erase types defined in the erase map are already
2664 * sorted in ascending order, with the smallest erase type size being the first
2665 * member in the erase_type array. It replicates the sort done for the map's
2666 * erase types. Each region's erase bitmask will indicate which erase types are
2667 * supported from the sorted erase types defined in the erase map.
2668 * Sort the all region's erase type at init in order to speed up the process of
2669 * finding the best erase command at runtime.
2671 static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map)
2673 struct spi_nor_erase_region *region = map->regions;
2674 u8 region_erase_mask, sorted_erase_mask;
2677 region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
2679 sorted_erase_mask = spi_nor_sort_erase_mask(map,
2682 /* Overwrite erase mask. */
2683 region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) |
2686 region = spi_nor_region_next(region);
2691 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2692 * @map: the erase map of the SPI NOR
2693 * @erase_mask: bitmask encoding erase types that can erase the entire
2695 * @flash_size: the spi nor flash memory size
2697 static void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2698 u8 erase_mask, u64 flash_size)
2700 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2701 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2703 map->uniform_region.size = flash_size;
2704 map->regions = &map->uniform_region;
2705 map->uniform_erase_type = erase_mask;
2709 spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2710 const struct sfdp_parameter_header *bfpt_header,
2711 const struct sfdp_bfpt *bfpt,
2712 struct spi_nor_flash_parameter *params)
2714 if (nor->info->fixups && nor->info->fixups->post_bfpt)
2715 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
2722 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
2723 * @nor: pointer to a 'struct spi_nor'
2724 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
2725 * the Basic Flash Parameter Table length and version
2726 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2729 * The Basic Flash Parameter Table is the main and only mandatory table as
2730 * defined by the SFDP (JESD216) specification.
2731 * It provides us with the total size (memory density) of the data array and
2732 * the number of address bytes for Fast Read, Page Program and Sector Erase
2734 * For Fast READ commands, it also gives the number of mode clock cycles and
2735 * wait states (regrouped in the number of dummy clock cycles) for each
2736 * supported instruction op code.
2737 * For Page Program, the page size is now available since JESD216 rev A, however
2738 * the supported instruction op codes are still not provided.
2739 * For Sector Erase commands, this table stores the supported instruction op
2740 * codes and the associated sector sizes.
2741 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
2742 * rev A. The QER bits encode the manufacturer dependent procedure to be
2743 * executed to set the Quad Enable (QE) bit in some internal register of the
2744 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
2745 * sending any Quad SPI command to the memory. Actually, setting the QE bit
2746 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
2747 * and IO3 hence enabling 4 (Quad) I/O lines.
2749 * Return: 0 on success, -errno otherwise.
2751 static int spi_nor_parse_bfpt(struct spi_nor *nor,
2752 const struct sfdp_parameter_header *bfpt_header,
2753 struct spi_nor_flash_parameter *params)
2755 struct spi_nor_erase_map *map = &nor->erase_map;
2756 struct spi_nor_erase_type *erase_type = map->erase_type;
2757 struct sfdp_bfpt bfpt;
2764 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
2765 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
2768 /* Read the Basic Flash Parameter Table. */
2769 len = min_t(size_t, sizeof(bfpt),
2770 bfpt_header->length * sizeof(u32));
2771 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2772 memset(&bfpt, 0, sizeof(bfpt));
2773 err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
2777 /* Fix endianness of the BFPT DWORDs. */
2778 for (i = 0; i < BFPT_DWORD_MAX; i++)
2779 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2781 /* Number of address bytes. */
2782 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2783 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2784 nor->addr_width = 3;
2787 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2788 nor->addr_width = 4;
2795 /* Flash Memory Density (in bits). */
2796 params->size = bfpt.dwords[BFPT_DWORD(2)];
2797 if (params->size & BIT(31)) {
2798 params->size &= ~BIT(31);
2801 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2802 * bits is unlikely to exist so this error probably means
2803 * the BFPT we are reading is corrupted/wrong.
2805 if (params->size > 63)
2808 params->size = 1ULL << params->size;
2812 params->size >>= 3; /* Convert to bytes. */
2814 /* Fast Read settings. */
2815 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2816 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2817 struct spi_nor_read_command *read;
2819 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2820 params->hwcaps.mask &= ~rd->hwcaps;
2824 params->hwcaps.mask |= rd->hwcaps;
2825 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2826 read = ¶ms->reads[cmd];
2827 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2828 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2832 * Sector Erase settings. Reinitialize the uniform erase map using the
2833 * Erase Types defined in the bfpt table.
2836 memset(&nor->erase_map, 0, sizeof(nor->erase_map));
2837 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2838 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2842 half = bfpt.dwords[er->dword] >> er->shift;
2843 erasesize = half & 0xff;
2845 /* erasesize == 0 means this Erase Type is not supported. */
2849 erasesize = 1U << erasesize;
2850 opcode = (half >> 8) & 0xff;
2851 erase_mask |= BIT(i);
2852 spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
2855 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2857 * Sort all the map's Erase Types in ascending order with the smallest
2858 * erase size being the first member in the erase_type array.
2860 sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]),
2861 spi_nor_map_cmp_erase_type, NULL);
2863 * Sort the erase types in the uniform region in order to update the
2864 * uniform_erase_type bitmask. The bitmask will be used later on when
2865 * selecting the uniform erase.
2867 spi_nor_regions_sort_erase_types(map);
2868 map->uniform_erase_type = map->uniform_region.offset &
2869 SNOR_ERASE_TYPE_MASK;
2871 /* Stop here if not JESD216 rev A or later. */
2872 if (bfpt_header->length < BFPT_DWORD_MAX)
2873 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2876 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2877 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2878 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2879 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2880 params->page_size = 1U << params->page_size;
2882 /* Quad Enable Requirements. */
2883 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2884 case BFPT_DWORD15_QER_NONE:
2885 params->quad_enable = NULL;
2888 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2889 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2890 params->quad_enable = spansion_no_read_cr_quad_enable;
2893 case BFPT_DWORD15_QER_SR1_BIT6:
2894 params->quad_enable = macronix_quad_enable;
2897 case BFPT_DWORD15_QER_SR2_BIT7:
2898 params->quad_enable = sr2_bit7_quad_enable;
2901 case BFPT_DWORD15_QER_SR2_BIT1:
2902 params->quad_enable = spansion_read_cr_quad_enable;
2909 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
2912 #define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
2913 #define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22)
2914 #define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22)
2915 #define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22)
2916 #define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22)
2918 #define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16)
2919 #define SMPT_CMD_READ_DUMMY_SHIFT 16
2920 #define SMPT_CMD_READ_DUMMY(_cmd) \
2921 (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT)
2922 #define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL
2924 #define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24)
2925 #define SMPT_CMD_READ_DATA_SHIFT 24
2926 #define SMPT_CMD_READ_DATA(_cmd) \
2927 (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT)
2929 #define SMPT_CMD_OPCODE_MASK GENMASK(15, 8)
2930 #define SMPT_CMD_OPCODE_SHIFT 8
2931 #define SMPT_CMD_OPCODE(_cmd) \
2932 (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT)
2934 #define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16)
2935 #define SMPT_MAP_REGION_COUNT_SHIFT 16
2936 #define SMPT_MAP_REGION_COUNT(_header) \
2937 ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \
2938 SMPT_MAP_REGION_COUNT_SHIFT) + 1)
2940 #define SMPT_MAP_ID_MASK GENMASK(15, 8)
2941 #define SMPT_MAP_ID_SHIFT 8
2942 #define SMPT_MAP_ID(_header) \
2943 (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT)
2945 #define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8)
2946 #define SMPT_MAP_REGION_SIZE_SHIFT 8
2947 #define SMPT_MAP_REGION_SIZE(_region) \
2948 (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \
2949 SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256)
2951 #define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0)
2952 #define SMPT_MAP_REGION_ERASE_TYPE(_region) \
2953 ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK)
2955 #define SMPT_DESC_TYPE_MAP BIT(1)
2956 #define SMPT_DESC_END BIT(0)
2959 * spi_nor_smpt_addr_width() - return the address width used in the
2960 * configuration detection command.
2961 * @nor: pointer to a 'struct spi_nor'
2962 * @settings: configuration detection command descriptor, dword1
2964 static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
2966 switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
2967 case SMPT_CMD_ADDRESS_LEN_0:
2969 case SMPT_CMD_ADDRESS_LEN_3:
2971 case SMPT_CMD_ADDRESS_LEN_4:
2973 case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
2976 return nor->addr_width;
2981 * spi_nor_smpt_read_dummy() - return the configuration detection command read
2982 * latency, in clock cycles.
2983 * @nor: pointer to a 'struct spi_nor'
2984 * @settings: configuration detection command descriptor, dword1
2986 * Return: the number of dummy cycles for an SMPT read
2988 static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
2990 u8 read_dummy = SMPT_CMD_READ_DUMMY(settings);
2992 if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE)
2993 return nor->read_dummy;
2998 * spi_nor_get_map_in_use() - get the configuration map in use
2999 * @nor: pointer to a 'struct spi_nor'
3000 * @smpt: pointer to the sector map parameter table
3001 * @smpt_len: sector map parameter table length
3003 * Return: pointer to the map in use, ERR_PTR(-errno) otherwise.
3005 static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
3013 u8 addr_width, read_opcode, read_dummy;
3014 u8 read_data_mask, map_id;
3016 /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
3017 buf = kmalloc(sizeof(*buf), GFP_KERNEL);
3019 return ERR_PTR(-ENOMEM);
3021 addr_width = nor->addr_width;
3022 read_dummy = nor->read_dummy;
3023 read_opcode = nor->read_opcode;
3026 /* Determine if there are any optional Detection Command Descriptors */
3027 for (i = 0; i < smpt_len; i += 2) {
3028 if (smpt[i] & SMPT_DESC_TYPE_MAP)
3031 read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
3032 nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
3033 nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
3034 nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
3037 err = spi_nor_read_raw(nor, addr, 1, buf);
3044 * Build an index value that is used to select the Sector Map
3045 * Configuration that is currently in use.
3047 map_id = map_id << 1 | !!(*buf & read_data_mask);
3051 * If command descriptors are provided, they always precede map
3052 * descriptors in the table. There is no need to start the iteration
3053 * over smpt array all over again.
3055 * Find the matching configuration map.
3057 ret = ERR_PTR(-EINVAL);
3058 while (i < smpt_len) {
3059 if (SMPT_MAP_ID(smpt[i]) == map_id) {
3065 * If there are no more configuration map descriptors and no
3066 * configuration ID matched the configuration identifier, the
3067 * sector address map is unknown.
3069 if (smpt[i] & SMPT_DESC_END)
3072 /* increment the table index to the next map */
3073 i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
3079 nor->addr_width = addr_width;
3080 nor->read_dummy = read_dummy;
3081 nor->read_opcode = read_opcode;
3086 * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid
3087 * @region: pointer to a structure that describes a SPI NOR erase region
3088 * @erase: pointer to a structure that describes a SPI NOR erase type
3089 * @erase_type: erase type bitmask
3092 spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
3093 const struct spi_nor_erase_type *erase,
3094 const u8 erase_type)
3098 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3099 if (!(erase_type & BIT(i)))
3101 if (region->size & erase[i].size_mask) {
3102 spi_nor_region_mark_overlay(region);
3109 * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
3110 * @nor: pointer to a 'struct spi_nor'
3111 * @smpt: pointer to the sector map parameter table
3113 * Return: 0 on success, -errno otherwise.
3115 static int spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
3118 struct spi_nor_erase_map *map = &nor->erase_map;
3119 struct spi_nor_erase_type *erase = map->erase_type;
3120 struct spi_nor_erase_region *region;
3124 u8 uniform_erase_type, save_uniform_erase_type;
3125 u8 erase_type, regions_erase_type;
3127 region_count = SMPT_MAP_REGION_COUNT(*smpt);
3129 * The regions will be freed when the driver detaches from the
3132 region = devm_kcalloc(nor->dev, region_count, sizeof(*region),
3136 map->regions = region;
3138 uniform_erase_type = 0xff;
3139 regions_erase_type = 0;
3141 /* Populate regions. */
3142 for (i = 0; i < region_count; i++) {
3143 j = i + 1; /* index for the region dword */
3144 region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]);
3145 erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]);
3146 region[i].offset = offset | erase_type;
3148 spi_nor_region_check_overlay(®ion[i], erase, erase_type);
3151 * Save the erase types that are supported in all regions and
3152 * can erase the entire flash memory.
3154 uniform_erase_type &= erase_type;
3157 * regions_erase_type mask will indicate all the erase types
3158 * supported in this configuration map.
3160 regions_erase_type |= erase_type;
3162 offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) +
3166 save_uniform_erase_type = map->uniform_erase_type;
3167 map->uniform_erase_type = spi_nor_sort_erase_mask(map,
3168 uniform_erase_type);
3170 if (!regions_erase_type) {
3172 * Roll back to the previous uniform_erase_type mask, SMPT is
3175 map->uniform_erase_type = save_uniform_erase_type;
3180 * BFPT advertises all the erase types supported by all the possible
3181 * map configurations. Mask out the erase types that are not supported
3182 * by the current map configuration.
3184 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
3185 if (!(regions_erase_type & BIT(erase[i].idx)))
3186 spi_nor_set_erase_type(&erase[i], 0, 0xFF);
3188 spi_nor_region_mark_end(®ion[i - 1]);
3194 * spi_nor_parse_smpt() - parse Sector Map Parameter Table
3195 * @nor: pointer to a 'struct spi_nor'
3196 * @smpt_header: sector map parameter table header
3198 * This table is optional, but when available, we parse it to identify the
3199 * location and size of sectors within the main data array of the flash memory
3200 * device and to identify which Erase Types are supported by each sector.
3202 * Return: 0 on success, -errno otherwise.
3204 static int spi_nor_parse_smpt(struct spi_nor *nor,
3205 const struct sfdp_parameter_header *smpt_header)
3207 const u32 *sector_map;
3213 /* Read the Sector Map Parameter Table. */
3214 len = smpt_header->length * sizeof(*smpt);
3215 smpt = kmalloc(len, GFP_KERNEL);
3219 addr = SFDP_PARAM_HEADER_PTP(smpt_header);
3220 ret = spi_nor_read_sfdp(nor, addr, len, smpt);
3224 /* Fix endianness of the SMPT DWORDs. */
3225 for (i = 0; i < smpt_header->length; i++)
3226 smpt[i] = le32_to_cpu(smpt[i]);
3228 sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length);
3229 if (IS_ERR(sector_map)) {
3230 ret = PTR_ERR(sector_map);
3234 ret = spi_nor_init_non_uniform_erase_map(nor, sector_map);
3238 spi_nor_regions_sort_erase_types(&nor->erase_map);
3245 #define SFDP_4BAIT_DWORD_MAX 2
3248 /* The hardware capability. */
3252 * The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether
3253 * the associated 4-byte address op code is supported.
3259 * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table
3260 * @nor: pointer to a 'struct spi_nor'.
3261 * @param_header: pointer to the 'struct sfdp_parameter_header' describing
3262 * the 4-Byte Address Instruction Table length and version.
3263 * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
3265 * Return: 0 on success, -errno otherwise.
3267 static int spi_nor_parse_4bait(struct spi_nor *nor,
3268 const struct sfdp_parameter_header *param_header,
3269 struct spi_nor_flash_parameter *params)
3271 static const struct sfdp_4bait reads[] = {
3272 { SNOR_HWCAPS_READ, BIT(0) },
3273 { SNOR_HWCAPS_READ_FAST, BIT(1) },
3274 { SNOR_HWCAPS_READ_1_1_2, BIT(2) },
3275 { SNOR_HWCAPS_READ_1_2_2, BIT(3) },
3276 { SNOR_HWCAPS_READ_1_1_4, BIT(4) },
3277 { SNOR_HWCAPS_READ_1_4_4, BIT(5) },
3278 { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) },
3279 { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) },
3280 { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) },
3282 static const struct sfdp_4bait programs[] = {
3283 { SNOR_HWCAPS_PP, BIT(6) },
3284 { SNOR_HWCAPS_PP_1_1_4, BIT(7) },
3285 { SNOR_HWCAPS_PP_1_4_4, BIT(8) },
3287 static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = {
3288 { 0u /* not used */, BIT(9) },
3289 { 0u /* not used */, BIT(10) },
3290 { 0u /* not used */, BIT(11) },
3291 { 0u /* not used */, BIT(12) },
3293 struct spi_nor_pp_command *params_pp = params->page_programs;
3294 struct spi_nor_erase_map *map = &nor->erase_map;
3295 struct spi_nor_erase_type *erase_type = map->erase_type;
3298 u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask;
3301 if (param_header->major != SFDP_JESD216_MAJOR ||
3302 param_header->length < SFDP_4BAIT_DWORD_MAX)
3305 /* Read the 4-byte Address Instruction Table. */
3306 len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX;
3308 /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
3309 dwords = kmalloc(len, GFP_KERNEL);
3313 addr = SFDP_PARAM_HEADER_PTP(param_header);
3314 ret = spi_nor_read_sfdp(nor, addr, len, dwords);
3318 /* Fix endianness of the 4BAIT DWORDs. */
3319 for (i = 0; i < SFDP_4BAIT_DWORD_MAX; i++)
3320 dwords[i] = le32_to_cpu(dwords[i]);
3323 * Compute the subset of (Fast) Read commands for which the 4-byte
3324 * version is supported.
3328 for (i = 0; i < ARRAY_SIZE(reads); i++) {
3329 const struct sfdp_4bait *read = &reads[i];
3331 discard_hwcaps |= read->hwcaps;
3332 if ((params->hwcaps.mask & read->hwcaps) &&
3333 (dwords[0] & read->supported_bit))
3334 read_hwcaps |= read->hwcaps;
3338 * Compute the subset of Page Program commands for which the 4-byte
3339 * version is supported.
3342 for (i = 0; i < ARRAY_SIZE(programs); i++) {
3343 const struct sfdp_4bait *program = &programs[i];
3346 * The 4 Byte Address Instruction (Optional) Table is the only
3347 * SFDP table that indicates support for Page Program Commands.
3348 * Bypass the params->hwcaps.mask and consider 4BAIT the biggest
3349 * authority for specifying Page Program support.
3351 discard_hwcaps |= program->hwcaps;
3352 if (dwords[0] & program->supported_bit)
3353 pp_hwcaps |= program->hwcaps;
3357 * Compute the subset of Sector Erase commands for which the 4-byte
3358 * version is supported.
3361 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3362 const struct sfdp_4bait *erase = &erases[i];
3364 if (dwords[0] & erase->supported_bit)
3365 erase_mask |= BIT(i);
3368 /* Replicate the sort done for the map's erase types in BFPT. */
3369 erase_mask = spi_nor_sort_erase_mask(map, erase_mask);
3372 * We need at least one 4-byte op code per read, program and erase
3373 * operation; the .read(), .write() and .erase() hooks share the
3374 * nor->addr_width value.
3376 if (!read_hwcaps || !pp_hwcaps || !erase_mask)
3380 * Discard all operations from the 4-byte instruction set which are
3381 * not supported by this memory.
3383 params->hwcaps.mask &= ~discard_hwcaps;
3384 params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
3386 /* Use the 4-byte address instruction set. */
3387 for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
3388 struct spi_nor_read_command *read_cmd = ¶ms->reads[i];
3390 read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
3393 /* 4BAIT is the only SFDP table that indicates page program support. */
3394 if (pp_hwcaps & SNOR_HWCAPS_PP)
3395 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP],
3396 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
3397 if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
3398 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4],
3399 SPINOR_OP_PP_1_1_4_4B,
3401 if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
3402 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
3403 SPINOR_OP_PP_1_4_4_4B,
3406 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3407 if (erase_mask & BIT(i))
3408 erase_type[i].opcode = (dwords[1] >>
3409 erase_type[i].idx * 8) & 0xFF;
3411 spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF);
3415 * We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes()
3416 * later because we already did the conversion to 4byte opcodes. Also,
3417 * this latest function implements a legacy quirk for the erase size of
3418 * Spansion memory. However this quirk is no longer needed with new
3419 * SFDP compliant memories.
3421 nor->addr_width = 4;
3422 nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
3431 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
3432 * @nor: pointer to a 'struct spi_nor'
3433 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
3436 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
3437 * specification. This is a standard which tends to supported by almost all
3438 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
3439 * runtime the main parameters needed to perform basic SPI flash operations such
3440 * as Fast Read, Page Program or Sector Erase commands.
3442 * Return: 0 on success, -errno otherwise.
3444 static int spi_nor_parse_sfdp(struct spi_nor *nor,
3445 struct spi_nor_flash_parameter *params)
3447 const struct sfdp_parameter_header *param_header, *bfpt_header;
3448 struct sfdp_parameter_header *param_headers = NULL;
3449 struct sfdp_header header;
3450 struct device *dev = nor->dev;
3454 /* Get the SFDP header. */
3455 err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
3459 /* Check the SFDP header version. */
3460 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
3461 header.major != SFDP_JESD216_MAJOR)
3465 * Verify that the first and only mandatory parameter header is a
3466 * Basic Flash Parameter Table header as specified in JESD216.
3468 bfpt_header = &header.bfpt_header;
3469 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
3470 bfpt_header->major != SFDP_JESD216_MAJOR)
3474 * Allocate memory then read all parameter headers with a single
3475 * Read SFDP command. These parameter headers will actually be parsed
3476 * twice: a first time to get the latest revision of the basic flash
3477 * parameter table, then a second time to handle the supported optional
3479 * Hence we read the parameter headers once for all to reduce the
3480 * processing time. Also we use kmalloc() instead of devm_kmalloc()
3481 * because we don't need to keep these parameter headers: the allocated
3482 * memory is always released with kfree() before exiting this function.
3485 psize = header.nph * sizeof(*param_headers);
3487 param_headers = kmalloc(psize, GFP_KERNEL);
3491 err = spi_nor_read_sfdp(nor, sizeof(header),
3492 psize, param_headers);
3494 dev_err(dev, "failed to read SFDP parameter headers\n");
3500 * Check other parameter headers to get the latest revision of
3501 * the basic flash parameter table.
3503 for (i = 0; i < header.nph; i++) {
3504 param_header = ¶m_headers[i];
3506 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
3507 param_header->major == SFDP_JESD216_MAJOR &&
3508 (param_header->minor > bfpt_header->minor ||
3509 (param_header->minor == bfpt_header->minor &&
3510 param_header->length > bfpt_header->length)))
3511 bfpt_header = param_header;
3514 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
3518 /* Parse optional parameter tables. */
3519 for (i = 0; i < header.nph; i++) {
3520 param_header = ¶m_headers[i];
3522 switch (SFDP_PARAM_HEADER_ID(param_header)) {
3523 case SFDP_SECTOR_MAP_ID:
3524 err = spi_nor_parse_smpt(nor, param_header);
3528 err = spi_nor_parse_4bait(nor, param_header, params);
3536 dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
3537 SFDP_PARAM_HEADER_ID(param_header));
3539 * Let's not drop all information we extracted so far
3540 * if optional table parsers fail. In case of failing,
3541 * each optional parser is responsible to roll back to
3542 * the previously known spi_nor data.
3549 kfree(param_headers);
3553 static int spi_nor_init_params(struct spi_nor *nor,
3554 struct spi_nor_flash_parameter *params)
3556 struct spi_nor_erase_map *map = &nor->erase_map;
3557 const struct flash_info *info = nor->info;
3560 /* Set legacy flash parameters as default. */
3561 memset(params, 0, sizeof(*params));
3563 /* Set SPI NOR sizes. */
3564 params->size = (u64)info->sector_size * info->n_sectors;
3565 params->page_size = info->page_size;
3567 /* (Fast) Read settings. */
3568 params->hwcaps.mask |= SNOR_HWCAPS_READ;
3569 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
3570 0, 0, SPINOR_OP_READ,
3573 if (!(info->flags & SPI_NOR_NO_FR)) {
3574 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
3575 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
3576 0, 8, SPINOR_OP_READ_FAST,
3580 if (info->flags & SPI_NOR_DUAL_READ) {
3581 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
3582 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
3583 0, 8, SPINOR_OP_READ_1_1_2,
3587 if (info->flags & SPI_NOR_QUAD_READ) {
3588 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
3589 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
3590 0, 8, SPINOR_OP_READ_1_1_4,
3594 /* Page Program settings. */
3595 params->hwcaps.mask |= SNOR_HWCAPS_PP;
3596 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
3597 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
3600 * Sector Erase settings. Sort Erase Types in ascending order, with the
3601 * smallest erase size starting at BIT(0).
3605 if (info->flags & SECT_4K_PMC) {
3606 erase_mask |= BIT(i);
3607 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
3608 SPINOR_OP_BE_4K_PMC);
3610 } else if (info->flags & SECT_4K) {
3611 erase_mask |= BIT(i);
3612 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
3616 erase_mask |= BIT(i);
3617 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
3619 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
3621 /* Select the procedure to set the Quad Enable bit. */
3622 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
3623 SNOR_HWCAPS_PP_QUAD)) {
3624 switch (JEDEC_MFR(info)) {
3625 case SNOR_MFR_MACRONIX:
3626 params->quad_enable = macronix_quad_enable;
3630 case SNOR_MFR_MICRON:
3634 /* Kept only for backward compatibility purpose. */
3635 params->quad_enable = spansion_quad_enable;
3640 * Some manufacturer like GigaDevice may use different
3641 * bit to set QE on different memories, so the MFR can't
3642 * indicate the quad_enable method for this case, we need
3643 * set it in flash info list.
3645 if (info->quad_enable)
3646 params->quad_enable = info->quad_enable;
3649 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
3650 !(info->flags & SPI_NOR_SKIP_SFDP)) {
3651 struct spi_nor_flash_parameter sfdp_params;
3652 struct spi_nor_erase_map prev_map;
3654 memcpy(&sfdp_params, params, sizeof(sfdp_params));
3655 memcpy(&prev_map, &nor->erase_map, sizeof(prev_map));
3657 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
3658 nor->addr_width = 0;
3659 nor->flags &= ~SNOR_F_4B_OPCODES;
3660 /* restore previous erase map */
3661 memcpy(&nor->erase_map, &prev_map,
3662 sizeof(nor->erase_map));
3664 memcpy(params, &sfdp_params, sizeof(*params));
3671 static int spi_nor_select_read(struct spi_nor *nor,
3672 const struct spi_nor_flash_parameter *params,
3675 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
3676 const struct spi_nor_read_command *read;
3681 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
3685 read = ¶ms->reads[cmd];
3686 nor->read_opcode = read->opcode;
3687 nor->read_proto = read->proto;
3690 * In the spi-nor framework, we don't need to make the difference
3691 * between mode clock cycles and wait state clock cycles.
3692 * Indeed, the value of the mode clock cycles is used by a QSPI
3693 * flash memory to know whether it should enter or leave its 0-4-4
3694 * (Continuous Read / XIP) mode.
3695 * eXecution In Place is out of the scope of the mtd sub-system.
3696 * Hence we choose to merge both mode and wait state clock cycles
3697 * into the so called dummy clock cycles.
3699 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
3703 static int spi_nor_select_pp(struct spi_nor *nor,
3704 const struct spi_nor_flash_parameter *params,
3707 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
3708 const struct spi_nor_pp_command *pp;
3713 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
3717 pp = ¶ms->page_programs[cmd];
3718 nor->program_opcode = pp->opcode;
3719 nor->write_proto = pp->proto;
3724 * spi_nor_select_uniform_erase() - select optimum uniform erase type
3725 * @map: the erase map of the SPI NOR
3726 * @wanted_size: the erase type size to search for. Contains the value of
3727 * info->sector_size or of the "small sector" size in case
3728 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
3730 * Once the optimum uniform sector erase command is found, disable all the
3733 * Return: pointer to erase type on success, NULL otherwise.
3735 static const struct spi_nor_erase_type *
3736 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
3737 const u32 wanted_size)
3739 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
3741 u8 uniform_erase_type = map->uniform_erase_type;
3743 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3744 if (!(uniform_erase_type & BIT(i)))
3747 tested_erase = &map->erase_type[i];
3750 * If the current erase size is the one, stop here:
3751 * we have found the right uniform Sector Erase command.
3753 if (tested_erase->size == wanted_size) {
3754 erase = tested_erase;
3759 * Otherwise, the current erase size is still a valid canditate.
3760 * Select the biggest valid candidate.
3762 if (!erase && tested_erase->size)
3763 erase = tested_erase;
3764 /* keep iterating to find the wanted_size */
3770 /* Disable all other Sector Erase commands. */
3771 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
3772 map->uniform_erase_type |= BIT(erase - map->erase_type);
3776 static int spi_nor_select_erase(struct spi_nor *nor, u32 wanted_size)
3778 struct spi_nor_erase_map *map = &nor->erase_map;
3779 const struct spi_nor_erase_type *erase = NULL;
3780 struct mtd_info *mtd = &nor->mtd;
3784 * The previous implementation handling Sector Erase commands assumed
3785 * that the SPI flash memory has an uniform layout then used only one
3786 * of the supported erase sizes for all Sector Erase commands.
3787 * So to be backward compatible, the new implementation also tries to
3788 * manage the SPI flash memory as uniform with a single erase sector
3789 * size, when possible.
3791 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
3792 /* prefer "small sector" erase if possible */
3793 wanted_size = 4096u;
3796 if (spi_nor_has_uniform_erase(nor)) {
3797 erase = spi_nor_select_uniform_erase(map, wanted_size);
3800 nor->erase_opcode = erase->opcode;
3801 mtd->erasesize = erase->size;
3806 * For non-uniform SPI flash memory, set mtd->erasesize to the
3807 * maximum erase sector size. No need to set nor->erase_opcode.
3809 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3810 if (map->erase_type[i].size) {
3811 erase = &map->erase_type[i];
3819 mtd->erasesize = erase->size;
3823 static int spi_nor_setup(struct spi_nor *nor,
3824 const struct spi_nor_flash_parameter *params,
3825 const struct spi_nor_hwcaps *hwcaps)
3827 u32 ignored_mask, shared_mask;
3828 bool enable_quad_io;
3832 * Keep only the hardware capabilities supported by both the SPI
3833 * controller and the SPI flash memory.
3835 shared_mask = hwcaps->mask & params->hwcaps.mask;
3837 /* SPI n-n-n protocols are not supported yet. */
3838 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
3839 SNOR_HWCAPS_READ_4_4_4 |
3840 SNOR_HWCAPS_READ_8_8_8 |
3841 SNOR_HWCAPS_PP_4_4_4 |
3842 SNOR_HWCAPS_PP_8_8_8);
3843 if (shared_mask & ignored_mask) {
3845 "SPI n-n-n protocols are not supported yet.\n");
3846 shared_mask &= ~ignored_mask;
3849 /* Select the (Fast) Read command. */
3850 err = spi_nor_select_read(nor, params, shared_mask);
3853 "can't select read settings supported by both the SPI controller and memory.\n");
3857 /* Select the Page Program command. */
3858 err = spi_nor_select_pp(nor, params, shared_mask);
3861 "can't select write settings supported by both the SPI controller and memory.\n");
3865 /* Select the Sector Erase command. */
3866 err = spi_nor_select_erase(nor, nor->info->sector_size);
3869 "can't select erase settings supported by both the SPI controller and memory.\n");
3873 /* Enable Quad I/O if needed. */
3874 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
3875 spi_nor_get_protocol_width(nor->write_proto) == 4);
3876 if (enable_quad_io && params->quad_enable)
3877 nor->quad_enable = params->quad_enable;
3879 nor->quad_enable = NULL;
3884 static int spi_nor_init(struct spi_nor *nor)
3889 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
3890 * with the software protection bits set
3892 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
3893 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
3894 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
3895 nor->info->flags & SPI_NOR_HAS_LOCK) {
3898 spi_nor_wait_till_ready(nor);
3901 if (nor->quad_enable) {
3902 err = nor->quad_enable(nor);
3904 dev_err(nor->dev, "quad mode not supported\n");
3909 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) {
3911 * If the RESET# pin isn't hooked up properly, or the system
3912 * otherwise doesn't perform a reset command in the boot
3913 * sequence, it's impossible to 100% protect against unexpected
3914 * reboots (e.g., crashes). Warn the user (or hopefully, system
3915 * designer) that this is bad.
3917 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
3918 "enabling reset hack; may not recover from unexpected reboots\n");
3919 set_4byte(nor, true);
3925 /* mtd resume handler */
3926 static void spi_nor_resume(struct mtd_info *mtd)
3928 struct spi_nor *nor = mtd_to_spi_nor(mtd);
3929 struct device *dev = nor->dev;
3932 /* re-initialize the nor chip */
3933 ret = spi_nor_init(nor);
3935 dev_err(dev, "resume() failed\n");
3938 void spi_nor_restore(struct spi_nor *nor)
3940 /* restore the addressing mode */
3941 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
3942 nor->flags & SNOR_F_BROKEN_RESET)
3943 set_4byte(nor, false);
3945 EXPORT_SYMBOL_GPL(spi_nor_restore);
3947 static const struct flash_info *spi_nor_match_id(const char *name)
3949 const struct flash_info *id = spi_nor_ids;
3952 if (!strcmp(name, id->name))
3959 int spi_nor_scan(struct spi_nor *nor, const char *name,
3960 const struct spi_nor_hwcaps *hwcaps)
3962 struct spi_nor_flash_parameter params;
3963 const struct flash_info *info = NULL;
3964 struct device *dev = nor->dev;
3965 struct mtd_info *mtd = &nor->mtd;
3966 struct device_node *np = spi_nor_get_flash_node(nor);
3970 ret = spi_nor_check(nor);
3974 /* Reset SPI protocol for all commands. */
3975 nor->reg_proto = SNOR_PROTO_1_1_1;
3976 nor->read_proto = SNOR_PROTO_1_1_1;
3977 nor->write_proto = SNOR_PROTO_1_1_1;
3980 info = spi_nor_match_id(name);
3981 /* Try to auto-detect if chip name wasn't specified or not found */
3983 info = spi_nor_read_id(nor);
3984 if (IS_ERR_OR_NULL(info))
3988 * If caller has specified name of flash model that can normally be
3989 * detected using JEDEC, let's verify it.
3991 if (name && info->id_len) {
3992 const struct flash_info *jinfo;
3994 jinfo = spi_nor_read_id(nor);
3995 if (IS_ERR(jinfo)) {
3996 return PTR_ERR(jinfo);
3997 } else if (jinfo != info) {
3999 * JEDEC knows better, so overwrite platform ID. We
4000 * can't trust partitions any longer, but we'll let
4001 * mtd apply them anyway, since some partitions may be
4002 * marked read-only, and we don't want to lose that
4003 * information, even if it's not 100% accurate.
4005 dev_warn(dev, "found %s, expected %s\n",
4006 jinfo->name, info->name);
4013 mutex_init(&nor->lock);
4016 * Make sure the XSR_RDY flag is set before calling
4017 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
4018 * with Atmel spi-nor
4020 if (info->flags & SPI_S3AN)
4021 nor->flags |= SNOR_F_READY_XSR_RDY;
4023 /* Parse the Serial Flash Discoverable Parameters table. */
4024 ret = spi_nor_init_params(nor, ¶ms);
4029 mtd->name = dev_name(dev);
4031 mtd->type = MTD_NORFLASH;
4033 mtd->flags = MTD_CAP_NORFLASH;
4034 mtd->size = params.size;
4035 mtd->_erase = spi_nor_erase;
4036 mtd->_read = spi_nor_read;
4037 mtd->_resume = spi_nor_resume;
4039 /* NOR protection support for STmicro/Micron chips and similar */
4040 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
4041 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
4042 info->flags & SPI_NOR_HAS_LOCK) {
4043 nor->flash_lock = stm_lock;
4044 nor->flash_unlock = stm_unlock;
4045 nor->flash_is_locked = stm_is_locked;
4048 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
4049 mtd->_lock = spi_nor_lock;
4050 mtd->_unlock = spi_nor_unlock;
4051 mtd->_is_locked = spi_nor_is_locked;
4054 /* sst nor chips use AAI word program */
4055 if (info->flags & SST_WRITE)
4056 mtd->_write = sst_write;
4058 mtd->_write = spi_nor_write;
4060 if (info->flags & USE_FSR)
4061 nor->flags |= SNOR_F_USE_FSR;
4062 if (info->flags & SPI_NOR_HAS_TB)
4063 nor->flags |= SNOR_F_HAS_SR_TB;
4064 if (info->flags & NO_CHIP_ERASE)
4065 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
4066 if (info->flags & USE_CLSR)
4067 nor->flags |= SNOR_F_USE_CLSR;
4069 if (info->flags & SPI_NOR_NO_ERASE)
4070 mtd->flags |= MTD_NO_ERASE;
4072 mtd->dev.parent = dev;
4073 nor->page_size = params.page_size;
4074 mtd->writebufsize = nor->page_size;
4077 /* If we were instantiated by DT, use it */
4078 if (of_property_read_bool(np, "m25p,fast-read"))
4079 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
4081 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
4083 /* If we weren't instantiated by DT, default to fast-read */
4084 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
4087 if (of_property_read_bool(np, "broken-flash-reset"))
4088 nor->flags |= SNOR_F_BROKEN_RESET;
4090 /* Some devices cannot do fast-read, no matter what DT tells us */
4091 if (info->flags & SPI_NOR_NO_FR)
4092 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
4095 * Configure the SPI memory:
4096 * - select op codes for (Fast) Read, Page Program and Sector Erase.
4097 * - set the number of dummy cycles (mode cycles + wait states).
4098 * - set the SPI protocols for register and memory accesses.
4099 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
4101 ret = spi_nor_setup(nor, ¶ms, hwcaps);
4105 if (nor->addr_width) {
4106 /* already configured from SFDP */
4107 } else if (info->addr_width) {
4108 nor->addr_width = info->addr_width;
4109 } else if (mtd->size > 0x1000000) {
4110 /* enable 4-byte addressing if the device exceeds 16MiB */
4111 nor->addr_width = 4;
4113 nor->addr_width = 3;
4116 if (info->flags & SPI_NOR_4B_OPCODES ||
4117 (JEDEC_MFR(info) == SNOR_MFR_SPANSION && mtd->size > SZ_16M))
4118 nor->flags |= SNOR_F_4B_OPCODES;
4120 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
4121 !(nor->flags & SNOR_F_HAS_4BAIT))
4122 spi_nor_set_4byte_opcodes(nor);
4124 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
4125 dev_err(dev, "address width is too large: %u\n",
4130 if (info->flags & SPI_S3AN) {
4131 ret = s3an_nor_scan(nor);
4136 /* Send all the required SPI flash commands to initialize device */
4137 ret = spi_nor_init(nor);
4141 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
4142 (long long)mtd->size >> 10);
4145 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
4146 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
4147 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
4148 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
4150 if (mtd->numeraseregions)
4151 for (i = 0; i < mtd->numeraseregions; i++)
4153 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
4154 ".erasesize = 0x%.8x (%uKiB), "
4155 ".numblocks = %d }\n",
4156 i, (long long)mtd->eraseregions[i].offset,
4157 mtd->eraseregions[i].erasesize,
4158 mtd->eraseregions[i].erasesize / 1024,
4159 mtd->eraseregions[i].numblocks);
4162 EXPORT_SYMBOL_GPL(spi_nor_scan);
4164 MODULE_LICENSE("GPL v2");
4165 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
4166 MODULE_AUTHOR("Mike Lavender");
4167 MODULE_DESCRIPTION("framework for SPI NOR");