drivers/mtd/spi-nor/intel-spi.c

   1 /*
   2  * Intel PCH/PCU SPI flash driver.
   3  *
   4  * Copyright (C) 2016, Intel Corporation
   5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/sched.h>
  17 #include <linux/sizes.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/mtd/spi-nor.h>
  21 #include <linux/platform_data/intel-spi.h>
  22
  23 #include "intel-spi.h"
  24
  25 /* Offsets are from @ispi->base */
  26 #define BFPREG                          0x00
  27
  28 #define HSFSTS_CTL                      0x04
  29 #define HSFSTS_CTL_FSMIE                BIT(31)
  30 #define HSFSTS_CTL_FDBC_SHIFT           24
  31 #define HSFSTS_CTL_FDBC_MASK            (0x3f << HSFSTS_CTL_FDBC_SHIFT)
  32
  33 #define HSFSTS_CTL_FCYCLE_SHIFT         17
  34 #define HSFSTS_CTL_FCYCLE_MASK          (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
  35 /* HW sequencer opcodes */
  36 #define HSFSTS_CTL_FCYCLE_READ          (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
  37 #define HSFSTS_CTL_FCYCLE_WRITE         (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
  38 #define HSFSTS_CTL_FCYCLE_ERASE         (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
  39 #define HSFSTS_CTL_FCYCLE_ERASE_64K     (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
  40 #define HSFSTS_CTL_FCYCLE_RDID          (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
  41 #define HSFSTS_CTL_FCYCLE_WRSR          (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
  42 #define HSFSTS_CTL_FCYCLE_RDSR          (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
  43
  44 #define HSFSTS_CTL_FGO                  BIT(16)
  45 #define HSFSTS_CTL_FLOCKDN              BIT(15)
  46 #define HSFSTS_CTL_FDV                  BIT(14)
  47 #define HSFSTS_CTL_SCIP                 BIT(5)
  48 #define HSFSTS_CTL_AEL                  BIT(2)
  49 #define HSFSTS_CTL_FCERR                BIT(1)
  50 #define HSFSTS_CTL_FDONE                BIT(0)
  51
  52 #define FADDR                           0x08
  53 #define DLOCK                           0x0c
  54 #define FDATA(n)                        (0x10 + ((n) * 4))
  55
  56 #define FRACC                           0x50
  57
  58 #define FREG(n)                         (0x54 + ((n) * 4))
  59 #define FREG_BASE_MASK                  0x3fff
  60 #define FREG_LIMIT_SHIFT                16
  61 #define FREG_LIMIT_MASK                 (0x03fff << FREG_LIMIT_SHIFT)
  62
  63 /* Offset is from @ispi->pregs */
  64 #define PR(n)                           ((n) * 4)
  65 #define PR_WPE                          BIT(31)
  66 #define PR_LIMIT_SHIFT                  16
  67 #define PR_LIMIT_MASK                   (0x3fff << PR_LIMIT_SHIFT)
  68 #define PR_RPE                          BIT(15)
  69 #define PR_BASE_MASK                    0x3fff
  70
  71 /* Offsets are from @ispi->sregs */
  72 #define SSFSTS_CTL                      0x00
  73 #define SSFSTS_CTL_FSMIE                BIT(23)
  74 #define SSFSTS_CTL_DS                   BIT(22)
  75 #define SSFSTS_CTL_DBC_SHIFT            16
  76 #define SSFSTS_CTL_SPOP                 BIT(11)
  77 #define SSFSTS_CTL_ACS                  BIT(10)
  78 #define SSFSTS_CTL_SCGO                 BIT(9)
  79 #define SSFSTS_CTL_COP_SHIFT            12
  80 #define SSFSTS_CTL_FRS                  BIT(7)
  81 #define SSFSTS_CTL_DOFRS                BIT(6)
  82 #define SSFSTS_CTL_AEL                  BIT(4)
  83 #define SSFSTS_CTL_FCERR                BIT(3)
  84 #define SSFSTS_CTL_FDONE                BIT(2)
  85 #define SSFSTS_CTL_SCIP                 BIT(0)
  86
  87 #define PREOP_OPTYPE                    0x04
  88 #define OPMENU0                         0x08
  89 #define OPMENU1                         0x0c
  90
  91 #define OPTYPE_READ_NO_ADDR             0
  92 #define OPTYPE_WRITE_NO_ADDR            1
  93 #define OPTYPE_READ_WITH_ADDR           2
  94 #define OPTYPE_WRITE_WITH_ADDR          3
  95
  96 /* CPU specifics */
  97 #define BYT_PR                          0x74
  98 #define BYT_SSFSTS_CTL                  0x90
  99 #define BYT_BCR                         0xfc
 100 #define BYT_BCR_WPD                     BIT(0)
 101 #define BYT_FREG_NUM                    5
 102 #define BYT_PR_NUM                      5
 103
 104 #define LPT_PR                          0x74
 105 #define LPT_SSFSTS_CTL                  0x90
 106 #define LPT_FREG_NUM                    5
 107 #define LPT_PR_NUM                      5
 108
 109 #define BXT_PR                          0x84
 110 #define BXT_SSFSTS_CTL                  0xa0
 111 #define BXT_FREG_NUM                    12
 112 #define BXT_PR_NUM                      6
 113
 114 #define LVSCC                           0xc4
 115 #define UVSCC                           0xc8
 116 #define ERASE_OPCODE_SHIFT              8
 117 #define ERASE_OPCODE_MASK               (0xff << ERASE_OPCODE_SHIFT)
 118 #define ERASE_64K_OPCODE_SHIFT          16
 119 #define ERASE_64K_OPCODE_MASK           (0xff << ERASE_OPCODE_SHIFT)
 120
 121 #define INTEL_SPI_TIMEOUT               5000 /* ms */
 122 #define INTEL_SPI_FIFO_SZ               64
 123
 124 /**
 125  * struct intel_spi - Driver private data
 126  * @dev: Device pointer
 127  * @info: Pointer to board specific info
 128  * @nor: SPI NOR layer structure
 129  * @base: Beginning of MMIO space
 130  * @pregs: Start of protection registers
 131  * @sregs: Start of software sequencer registers
 132  * @nregions: Maximum number of regions
 133  * @pr_num: Maximum number of protected range registers
 134  * @writeable: Is the chip writeable
 135  * @locked: Is SPI setting locked
 136  * @swseq_reg: Use SW sequencer in register reads/writes
 137  * @swseq_erase: Use SW sequencer in erase operation
 138  * @erase_64k: 64k erase supported
 139  * @opcodes: Opcodes which are supported. This are programmed by BIOS
 140  *           before it locks down the controller.
 141  * @preopcodes: Preopcodes which are supported.
 142  */
 143 struct intel_spi {
 144         struct device *dev;
 145         const struct intel_spi_boardinfo *info;
 146         struct spi_nor nor;
 147         void __iomem *base;
 148         void __iomem *pregs;
 149         void __iomem *sregs;
 150         size_t nregions;
 151         size_t pr_num;
 152         bool writeable;
 153         bool locked;
 154         bool swseq_reg;
 155         bool swseq_erase;
 156         bool erase_64k;
 157         u8 opcodes[8];
 158         u8 preopcodes[2];
 159 };
 160
 161 static bool writeable;
 162 module_param(writeable, bool, 0);
 163 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
 164
 165 static void intel_spi_dump_regs(struct intel_spi *ispi)
 166 {
 167         u32 value;
 168         int i;
 169
 170         dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
 171
 172         value = readl(ispi->base + HSFSTS_CTL);
 173         dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
 174         if (value & HSFSTS_CTL_FLOCKDN)
 175                 dev_dbg(ispi->dev, "-> Locked\n");
 176
 177         dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
 178         dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
 179
 180         for (i = 0; i < 16; i++)
 181                 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
 182                         i, readl(ispi->base + FDATA(i)));
 183
 184         dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
 185
 186         for (i = 0; i < ispi->nregions; i++)
 187                 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
 188                         readl(ispi->base + FREG(i)));
 189         for (i = 0; i < ispi->pr_num; i++)
 190                 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
 191                         readl(ispi->pregs + PR(i)));
 192
 193         value = readl(ispi->sregs + SSFSTS_CTL);
 194         dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
 195         dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
 196                 readl(ispi->sregs + PREOP_OPTYPE));
 197         dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0));
 198         dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1));
 199
 200         if (ispi->info->type == INTEL_SPI_BYT)
 201                 dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
 202
 203         dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
 204         dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
 205
 206         dev_dbg(ispi->dev, "Protected regions:\n");
 207         for (i = 0; i < ispi->pr_num; i++) {
 208                 u32 base, limit;
 209
 210                 value = readl(ispi->pregs + PR(i));
 211                 if (!(value & (PR_WPE | PR_RPE)))
 212                         continue;
 213
 214                 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
 215                 base = value & PR_BASE_MASK;
 216
 217                 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
 218                          i, base << 12, (limit << 12) | 0xfff,
 219                          value & PR_WPE ? 'W' : '.',
 220                          value & PR_RPE ? 'R' : '.');
 221         }
 222
 223         dev_dbg(ispi->dev, "Flash regions:\n");
 224         for (i = 0; i < ispi->nregions; i++) {
 225                 u32 region, base, limit;
 226
 227                 region = readl(ispi->base + FREG(i));
 228                 base = region & FREG_BASE_MASK;
 229                 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
 230
 231                 if (base >= limit || (i > 0 && limit == 0))
 232                         dev_dbg(ispi->dev, " %02d disabled\n", i);
 233                 else
 234                         dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
 235                                  i, base << 12, (limit << 12) | 0xfff);
 236         }
 237
 238         dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
 239                 ispi->swseq_reg ? 'S' : 'H');
 240         dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
 241                 ispi->swseq_erase ? 'S' : 'H');
 242 }
 243
 244 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
 245 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
 246 {
 247         size_t bytes;
 248         int i = 0;
 249
 250         if (size > INTEL_SPI_FIFO_SZ)
 251                 return -EINVAL;
 252
 253         while (size > 0) {
 254                 bytes = min_t(size_t, size, 4);
 255                 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
 256                 size -= bytes;
 257                 buf += bytes;
 258                 i++;
 259         }
 260
 261         return 0;
 262 }
 263
 264 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
 265 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
 266                                  size_t size)
 267 {
 268         size_t bytes;
 269         int i = 0;
 270
 271         if (size > INTEL_SPI_FIFO_SZ)
 272                 return -EINVAL;
 273
 274         while (size > 0) {
 275                 bytes = min_t(size_t, size, 4);
 276                 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
 277                 size -= bytes;
 278                 buf += bytes;
 279                 i++;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
 286 {
 287         u32 val;
 288
 289         return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
 290                                   !(val & HSFSTS_CTL_SCIP), 0,
 291                                   INTEL_SPI_TIMEOUT * 1000);
 292 }
 293
 294 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
 295 {
 296         u32 val;
 297
 298         return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
 299                                   !(val & SSFSTS_CTL_SCIP), 0,
 300                                   INTEL_SPI_TIMEOUT * 1000);
 301 }
 302
 303 static int intel_spi_init(struct intel_spi *ispi)
 304 {
 305         u32 opmenu0, opmenu1, lvscc, uvscc, val;
 306         int i;
 307
 308         switch (ispi->info->type) {
 309         case INTEL_SPI_BYT:
 310                 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
 311                 ispi->pregs = ispi->base + BYT_PR;
 312                 ispi->nregions = BYT_FREG_NUM;
 313                 ispi->pr_num = BYT_PR_NUM;
 314                 ispi->swseq_reg = true;
 315
 316                 if (writeable) {
 317                         /* Disable write protection */
 318                         val = readl(ispi->base + BYT_BCR);
 319                         if (!(val & BYT_BCR_WPD)) {
 320                                 val |= BYT_BCR_WPD;
 321                                 writel(val, ispi->base + BYT_BCR);
 322                                 val = readl(ispi->base + BYT_BCR);
 323                         }
 324
 325                         ispi->writeable = !!(val & BYT_BCR_WPD);
 326                 }
 327
 328                 break;
 329
 330         case INTEL_SPI_LPT:
 331                 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
 332                 ispi->pregs = ispi->base + LPT_PR;
 333                 ispi->nregions = LPT_FREG_NUM;
 334                 ispi->pr_num = LPT_PR_NUM;
 335                 ispi->swseq_reg = true;
 336                 break;
 337
 338         case INTEL_SPI_BXT:
 339                 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
 340                 ispi->pregs = ispi->base + BXT_PR;
 341                 ispi->nregions = BXT_FREG_NUM;
 342                 ispi->pr_num = BXT_PR_NUM;
 343                 ispi->erase_64k = true;
 344                 break;
 345
 346         default:
 347                 return -EINVAL;
 348         }
 349
 350         /* Disable #SMI generation from HW sequencer */
 351         val = readl(ispi->base + HSFSTS_CTL);
 352         val &= ~HSFSTS_CTL_FSMIE;
 353         writel(val, ispi->base + HSFSTS_CTL);
 354
 355         /*
 356          * Determine whether erase operation should use HW or SW sequencer.
 357          *
 358          * The HW sequencer has a predefined list of opcodes, with only the
 359          * erase opcode being programmable in LVSCC and UVSCC registers.
 360          * If these registers don't contain a valid erase opcode, erase
 361          * cannot be done using HW sequencer.
 362          */
 363         lvscc = readl(ispi->base + LVSCC);
 364         uvscc = readl(ispi->base + UVSCC);
 365         if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))
 366                 ispi->swseq_erase = true;
 367         /* SPI controller on Intel BXT supports 64K erase opcode */
 368         if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
 369                 if (!(lvscc & ERASE_64K_OPCODE_MASK) ||
 370                     !(uvscc & ERASE_64K_OPCODE_MASK))
 371                         ispi->erase_64k = false;
 372
 373         /*
 374          * Some controllers can only do basic operations using hardware
 375          * sequencer. All other operations are supposed to be carried out
 376          * using software sequencer.
 377          */
 378         if (ispi->swseq_reg) {
 379                 /* Disable #SMI generation from SW sequencer */
 380                 val = readl(ispi->sregs + SSFSTS_CTL);
 381                 val &= ~SSFSTS_CTL_FSMIE;
 382                 writel(val, ispi->sregs + SSFSTS_CTL);
 383         }
 384
 385         /* Check controller's lock status */
 386         val = readl(ispi->base + HSFSTS_CTL);
 387         ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
 388
 389         if (ispi->locked) {
 390                 /*
 391                  * BIOS programs allowed opcodes and then locks down the
 392                  * register. So read back what opcodes it decided to support.
 393                  * That's the set we are going to support as well.
 394                  */
 395                 opmenu0 = readl(ispi->sregs + OPMENU0);
 396                 opmenu1 = readl(ispi->sregs + OPMENU1);
 397
 398                 if (opmenu0 && opmenu1) {
 399                         for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
 400                                 ispi->opcodes[i] = opmenu0 >> i * 8;
 401                                 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
 402                         }
 403
 404                         val = readl(ispi->sregs + PREOP_OPTYPE);
 405                         ispi->preopcodes[0] = val;
 406                         ispi->preopcodes[1] = val >> 8;
 407                 }
 408         }
 409
 410         intel_spi_dump_regs(ispi);
 411
 412         return 0;
 413 }
 414
 415 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
 416 {
 417         int i;
 418         int preop;
 419
 420         if (ispi->locked) {
 421                 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
 422                         if (ispi->opcodes[i] == opcode)
 423                                 return i;
 424
 425                 return -EINVAL;
 426         }
 427
 428         /* The lock is off, so just use index 0 */
 429         writel(opcode, ispi->sregs + OPMENU0);
 430         preop = readw(ispi->sregs + PREOP_OPTYPE);
 431         writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
 432
 433         return 0;
 434 }
 435
 436 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)
 437 {
 438         u32 val, status;
 439         int ret;
 440
 441         val = readl(ispi->base + HSFSTS_CTL);
 442         val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
 443
 444         switch (opcode) {
 445         case SPINOR_OP_RDID:
 446                 val |= HSFSTS_CTL_FCYCLE_RDID;
 447                 break;
 448         case SPINOR_OP_WRSR:
 449                 val |= HSFSTS_CTL_FCYCLE_WRSR;
 450                 break;
 451         case SPINOR_OP_RDSR:
 452                 val |= HSFSTS_CTL_FCYCLE_RDSR;
 453                 break;
 454         default:
 455                 return -EINVAL;
 456         }
 457
 458         if (len > INTEL_SPI_FIFO_SZ)
 459                 return -EINVAL;
 460
 461         val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
 462         val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
 463         val |= HSFSTS_CTL_FGO;
 464         writel(val, ispi->base + HSFSTS_CTL);
 465
 466         ret = intel_spi_wait_hw_busy(ispi);
 467         if (ret)
 468                 return ret;
 469
 470         status = readl(ispi->base + HSFSTS_CTL);
 471         if (status & HSFSTS_CTL_FCERR)
 472                 return -EIO;
 473         else if (status & HSFSTS_CTL_AEL)
 474                 return -EACCES;
 475
 476         return 0;
 477 }
 478
 479 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
 480                               int optype)
 481 {
 482         u32 val = 0, status;
 483         u16 preop;
 484         int ret;
 485
 486         ret = intel_spi_opcode_index(ispi, opcode, optype);
 487         if (ret < 0)
 488                 return ret;
 489
 490         if (len > INTEL_SPI_FIFO_SZ)
 491                 return -EINVAL;
 492
 493         /* Only mark 'Data Cycle' bit when there is data to be transferred */
 494         if (len > 0)
 495                 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
 496         val |= ret << SSFSTS_CTL_COP_SHIFT;
 497         val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
 498         val |= SSFSTS_CTL_SCGO;
 499         preop = readw(ispi->sregs + PREOP_OPTYPE);
 500         if (preop) {
 501                 val |= SSFSTS_CTL_ACS;
 502                 if (preop >> 8)
 503                         val |= SSFSTS_CTL_SPOP;
 504         }
 505         writel(val, ispi->sregs + SSFSTS_CTL);
 506
 507         ret = intel_spi_wait_sw_busy(ispi);
 508         if (ret)
 509                 return ret;
 510
 511         status = readl(ispi->sregs + SSFSTS_CTL);
 512         if (status & SSFSTS_CTL_FCERR)
 513                 return -EIO;
 514         else if (status & SSFSTS_CTL_AEL)
 515                 return -EACCES;
 516
 517         return 0;
 518 }
 519
 520 static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 521 {
 522         struct intel_spi *ispi = nor->priv;
 523         int ret;
 524
 525         /* Address of the first chip */
 526         writel(0, ispi->base + FADDR);
 527
 528         if (ispi->swseq_reg)
 529                 ret = intel_spi_sw_cycle(ispi, opcode, len,
 530                                          OPTYPE_READ_NO_ADDR);
 531         else
 532                 ret = intel_spi_hw_cycle(ispi, opcode, len);
 533
 534         if (ret)
 535                 return ret;
 536
 537         return intel_spi_read_block(ispi, buf, len);
 538 }
 539
 540 static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 541 {
 542         struct intel_spi *ispi = nor->priv;
 543         int ret;
 544
 545         /*
 546          * This is handled with atomic operation and preop code in Intel
 547          * controller so skip it here now. If the controller is not locked,
 548          * program the opcode to the PREOP register for later use.
 549          */
 550         if (opcode == SPINOR_OP_WREN) {
 551                 if (!ispi->locked)
 552                         writel(opcode, ispi->sregs + PREOP_OPTYPE);
 553
 554                 return 0;
 555         }
 556
 557         writel(0, ispi->base + FADDR);
 558
 559         /* Write the value beforehand */
 560         ret = intel_spi_write_block(ispi, buf, len);
 561         if (ret)
 562                 return ret;
 563
 564         if (ispi->swseq_reg)
 565                 return intel_spi_sw_cycle(ispi, opcode, len,
 566                                           OPTYPE_WRITE_NO_ADDR);
 567         return intel_spi_hw_cycle(ispi, opcode, len);
 568 }
 569
 570 static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
 571                               u_char *read_buf)
 572 {
 573         struct intel_spi *ispi = nor->priv;
 574         size_t block_size, retlen = 0;
 575         u32 val, status;
 576         ssize_t ret;
 577
 578         switch (nor->read_opcode) {
 579         case SPINOR_OP_READ:
 580         case SPINOR_OP_READ_FAST:
 581                 break;
 582         default:
 583                 return -EINVAL;
 584         }
 585
 586         while (len > 0) {
 587                 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
 588
 589                 writel(from, ispi->base + FADDR);
 590
 591                 val = readl(ispi->base + HSFSTS_CTL);
 592                 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
 593                 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
 594                 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
 595                 val |= HSFSTS_CTL_FCYCLE_READ;
 596                 val |= HSFSTS_CTL_FGO;
 597                 writel(val, ispi->base + HSFSTS_CTL);
 598
 599                 ret = intel_spi_wait_hw_busy(ispi);
 600                 if (ret)
 601                         return ret;
 602
 603                 status = readl(ispi->base + HSFSTS_CTL);
 604                 if (status & HSFSTS_CTL_FCERR)
 605                         ret = -EIO;
 606                 else if (status & HSFSTS_CTL_AEL)
 607                         ret = -EACCES;
 608
 609                 if (ret < 0) {
 610                         dev_err(ispi->dev, "read error: %llx: %#x\n", from,
 611                                 status);
 612                         return ret;
 613                 }
 614
 615                 ret = intel_spi_read_block(ispi, read_buf, block_size);
 616                 if (ret)
 617                         return ret;
 618
 619                 len -= block_size;
 620                 from += block_size;
 621                 retlen += block_size;
 622                 read_buf += block_size;
 623         }
 624
 625         return retlen;
 626 }
 627
 628 static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
 629                                const u_char *write_buf)
 630 {
 631         struct intel_spi *ispi = nor->priv;
 632         size_t block_size, retlen = 0;
 633         u32 val, status;
 634         ssize_t ret;
 635
 636         while (len > 0) {
 637                 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
 638
 639                 writel(to, ispi->base + FADDR);
 640
 641                 val = readl(ispi->base + HSFSTS_CTL);
 642                 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
 643                 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
 644                 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
 645                 val |= HSFSTS_CTL_FCYCLE_WRITE;
 646
 647                 ret = intel_spi_write_block(ispi, write_buf, block_size);
 648                 if (ret) {
 649                         dev_err(ispi->dev, "failed to write block\n");
 650                         return ret;
 651                 }
 652
 653                 /* Start the write now */
 654                 val |= HSFSTS_CTL_FGO;
 655                 writel(val, ispi->base + HSFSTS_CTL);
 656
 657                 ret = intel_spi_wait_hw_busy(ispi);
 658                 if (ret) {
 659                         dev_err(ispi->dev, "timeout\n");
 660                         return ret;
 661                 }
 662
 663                 status = readl(ispi->base + HSFSTS_CTL);
 664                 if (status & HSFSTS_CTL_FCERR)
 665                         ret = -EIO;
 666                 else if (status & HSFSTS_CTL_AEL)
 667                         ret = -EACCES;
 668
 669                 if (ret < 0) {
 670                         dev_err(ispi->dev, "write error: %llx: %#x\n", to,
 671                                 status);
 672                         return ret;
 673                 }
 674
 675                 len -= block_size;
 676                 to += block_size;
 677                 retlen += block_size;
 678                 write_buf += block_size;
 679         }
 680
 681         return retlen;
 682 }
 683
 684 static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
 685 {
 686         size_t erase_size, len = nor->mtd.erasesize;
 687         struct intel_spi *ispi = nor->priv;
 688         u32 val, status, cmd;
 689         int ret;
 690
 691         /* If the hardware can do 64k erase use that when possible */
 692         if (len >= SZ_64K && ispi->erase_64k) {
 693                 cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
 694                 erase_size = SZ_64K;
 695         } else {
 696                 cmd = HSFSTS_CTL_FCYCLE_ERASE;
 697                 erase_size = SZ_4K;
 698         }
 699
 700         if (ispi->swseq_erase) {
 701                 while (len > 0) {
 702                         writel(offs, ispi->base + FADDR);
 703
 704                         ret = intel_spi_sw_cycle(ispi, nor->erase_opcode,
 705                                                  0, OPTYPE_WRITE_WITH_ADDR);
 706                         if (ret)
 707                                 return ret;
 708
 709                         offs += erase_size;
 710                         len -= erase_size;
 711                 }
 712
 713                 return 0;
 714         }
 715
 716         while (len > 0) {
 717                 writel(offs, ispi->base + FADDR);
 718
 719                 val = readl(ispi->base + HSFSTS_CTL);
 720                 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
 721                 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
 722                 val |= cmd;
 723                 val |= HSFSTS_CTL_FGO;
 724                 writel(val, ispi->base + HSFSTS_CTL);
 725
 726                 ret = intel_spi_wait_hw_busy(ispi);
 727                 if (ret)
 728                         return ret;
 729
 730                 status = readl(ispi->base + HSFSTS_CTL);
 731                 if (status & HSFSTS_CTL_FCERR)
 732                         return -EIO;
 733                 else if (status & HSFSTS_CTL_AEL)
 734                         return -EACCES;
 735
 736                 offs += erase_size;
 737                 len -= erase_size;
 738         }
 739
 740         return 0;
 741 }
 742
 743 static bool intel_spi_is_protected(const struct intel_spi *ispi,
 744                                    unsigned int base, unsigned int limit)
 745 {
 746         int i;
 747
 748         for (i = 0; i < ispi->pr_num; i++) {
 749                 u32 pr_base, pr_limit, pr_value;
 750
 751                 pr_value = readl(ispi->pregs + PR(i));
 752                 if (!(pr_value & (PR_WPE | PR_RPE)))
 753                         continue;
 754
 755                 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
 756                 pr_base = pr_value & PR_BASE_MASK;
 757
 758                 if (pr_base >= base && pr_limit <= limit)
 759                         return true;
 760         }
 761
 762         return false;
 763 }
 764
 765 /*
 766  * There will be a single partition holding all enabled flash regions. We
 767  * call this "BIOS".
 768  */
 769 static void intel_spi_fill_partition(struct intel_spi *ispi,
 770                                      struct mtd_partition *part)
 771 {
 772         u64 end;
 773         int i;
 774
 775         memset(part, 0, sizeof(*part));
 776
 777         /* Start from the mandatory descriptor region */
 778         part->size = 4096;
 779         part->name = "BIOS";
 780
 781         /*
 782          * Now try to find where this partition ends based on the flash
 783          * region registers.
 784          */
 785         for (i = 1; i < ispi->nregions; i++) {
 786                 u32 region, base, limit;
 787
 788                 region = readl(ispi->base + FREG(i));
 789                 base = region & FREG_BASE_MASK;
 790                 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
 791
 792                 if (base >= limit || limit == 0)
 793                         continue;
 794
 795                 /*
 796                  * If any of the regions have protection bits set, make the
 797                  * whole partition read-only to be on the safe side.
 798                  */
 799                 if (intel_spi_is_protected(ispi, base, limit))
 800                         ispi->writeable = false;
 801
 802                 end = (limit << 12) + 4096;
 803                 if (end > part->size)
 804                         part->size = end;
 805         }
 806 }
 807
 808 struct intel_spi *intel_spi_probe(struct device *dev,
 809         struct resource *mem, const struct intel_spi_boardinfo *info)
 810 {
 811         const struct spi_nor_hwcaps hwcaps = {
 812                 .mask = SNOR_HWCAPS_READ |
 813                         SNOR_HWCAPS_READ_FAST |
 814                         SNOR_HWCAPS_PP,
 815         };
 816         struct mtd_partition part;
 817         struct intel_spi *ispi;
 818         int ret;
 819
 820         if (!info || !mem)
 821                 return ERR_PTR(-EINVAL);
 822
 823         ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
 824         if (!ispi)
 825                 return ERR_PTR(-ENOMEM);
 826
 827         ispi->base = devm_ioremap_resource(dev, mem);
 828         if (IS_ERR(ispi->base))
 829                 return ERR_CAST(ispi->base);
 830
 831         ispi->dev = dev;
 832         ispi->info = info;
 833         ispi->writeable = info->writeable;
 834
 835         ret = intel_spi_init(ispi);
 836         if (ret)
 837                 return ERR_PTR(ret);
 838
 839         ispi->nor.dev = ispi->dev;
 840         ispi->nor.priv = ispi;
 841         ispi->nor.read_reg = intel_spi_read_reg;
 842         ispi->nor.write_reg = intel_spi_write_reg;
 843         ispi->nor.read = intel_spi_read;
 844         ispi->nor.write = intel_spi_write;
 845         ispi->nor.erase = intel_spi_erase;
 846
 847         ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
 848         if (ret) {
 849                 dev_info(dev, "failed to locate the chip\n");
 850                 return ERR_PTR(ret);
 851         }
 852
 853         intel_spi_fill_partition(ispi, &part);
 854
 855         /* Prevent writes if not explicitly enabled */
 856         if (!ispi->writeable || !writeable)
 857                 ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
 858
 859         ret = mtd_device_parse_register(&ispi->nor.mtd, NULL, NULL, &part, 1);
 860         if (ret)
 861                 return ERR_PTR(ret);
 862
 863         return ispi;
 864 }
 865 EXPORT_SYMBOL_GPL(intel_spi_probe);
 866
 867 int intel_spi_remove(struct intel_spi *ispi)
 868 {
 869         return mtd_device_unregister(&ispi->nor.mtd);
 870 }
 871 EXPORT_SYMBOL_GPL(intel_spi_remove);
 872
 873 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
 874 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 875 MODULE_LICENSE("GPL v2");