1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2017 Free Electrons
4 * Copyright (C) 2017 NextThing Co
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
9 #include <linux/sizes.h>
10 #include <linux/slab.h>
12 #include "internals.h"
14 #define NAND_HYNIX_CMD_SET_PARAMS 0x36
15 #define NAND_HYNIX_CMD_APPLY_PARAMS 0x16
17 #define NAND_HYNIX_1XNM_RR_REPEAT 8
20 * struct hynix_read_retry - read-retry data
21 * @nregs: number of register to set when applying a new read-retry mode
22 * @regs: register offsets (NAND chip dependent)
23 * @values: array of values to set in registers. The array size is equal to
26 struct hynix_read_retry {
33 * struct hynix_nand - private Hynix NAND struct
34 * @read_retry: read-retry information
37 const struct hynix_read_retry *read_retry;
41 * struct hynix_read_retry_otp - structure describing how the read-retry OTP
43 * @nregs: number of hynix private registers to set before reading the reading
45 * @regs: registers that should be configured
46 * @values: values that should be set in regs
47 * @page: the address to pass to the READ_PAGE command. Depends on the NAND
49 * @size: size of the read-retry OTP section
51 struct hynix_read_retry_otp {
59 static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip)
64 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid));
68 return !strncmp("JEDEC", jedecid, sizeof(jedecid));
71 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd)
73 if (nand_has_exec_op(chip)) {
74 struct nand_op_instr instrs[] = {
77 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
79 return nand_exec_op(chip, &op);
82 chip->legacy.cmdfunc(chip, cmd, -1, -1);
87 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val)
89 u16 column = ((u16)addr << 8) | addr;
91 if (nand_has_exec_op(chip)) {
92 struct nand_op_instr instrs[] = {
93 NAND_OP_ADDR(1, &addr, 0),
94 NAND_OP_8BIT_DATA_OUT(1, &val, 0),
96 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
98 return nand_exec_op(chip, &op);
101 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);
102 chip->legacy.write_byte(chip, val);
107 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
109 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
113 values = hynix->read_retry->values +
114 (retry_mode * hynix->read_retry->nregs);
116 /* Enter 'Set Hynix Parameters' mode */
117 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
122 * Configure the NAND in the requested read-retry mode.
123 * This is done by setting pre-defined values in internal NAND
126 * The set of registers is NAND specific, and the values are either
127 * predefined or extracted from an OTP area on the NAND (values are
128 * probably tweaked at production in this case).
130 for (i = 0; i < hynix->read_retry->nregs; i++) {
131 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i],
137 /* Apply the new settings. */
138 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
142 * hynix_get_majority - get the value that is occurring the most in a given
144 * @in: the array of values to test
145 * @repeat: the size of the in array
146 * @out: pointer used to store the output value
148 * This function implements the 'majority check' logic that is supposed to
149 * overcome the unreliability of MLC NANDs when reading the OTP area storing
150 * the read-retry parameters.
152 * It's based on a pretty simple assumption: if we repeat the same value
153 * several times and then take the one that is occurring the most, we should
154 * find the correct value.
155 * Let's hope this dummy algorithm prevents us from losing the read-retry
158 static int hynix_get_majority(const u8 *in, int repeat, u8 *out)
160 int i, j, half = repeat / 2;
163 * We only test the first half of the in array because we must ensure
164 * that the value is at least occurring repeat / 2 times.
166 * This loop is suboptimal since we may count the occurrences of the
167 * same value several time, but we are doing that on small sets, which
168 * makes it acceptable.
170 for (i = 0; i < half; i++) {
174 /* Count all values that are matching the one at index i. */
175 for (j = i + 1; j < repeat; j++) {
180 /* We found a value occurring more than repeat / 2. */
190 static int hynix_read_rr_otp(struct nand_chip *chip,
191 const struct hynix_read_retry_otp *info,
196 ret = nand_reset_op(chip);
200 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
204 for (i = 0; i < info->nregs; i++) {
205 ret = hynix_nand_reg_write_op(chip, info->regs[i],
211 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
215 /* Sequence to enter OTP mode? */
216 ret = hynix_nand_cmd_op(chip, 0x17);
220 ret = hynix_nand_cmd_op(chip, 0x4);
224 ret = hynix_nand_cmd_op(chip, 0x19);
228 /* Now read the page */
229 ret = nand_read_page_op(chip, info->page, 0, buf, info->size);
233 /* Put everything back to normal */
234 ret = nand_reset_op(chip);
238 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
242 ret = hynix_nand_reg_write_op(chip, 0x38, 0);
246 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
250 return nand_read_page_op(chip, 0, 0, NULL, 0);
253 #define NAND_HYNIX_1XNM_RR_COUNT_OFFS 0
254 #define NAND_HYNIX_1XNM_RR_REG_COUNT_OFFS 8
255 #define NAND_HYNIX_1XNM_RR_SET_OFFS(x, setsize, inv) \
256 (16 + ((((x) * 2) + ((inv) ? 1 : 0)) * (setsize)))
258 static int hynix_mlc_1xnm_rr_value(const u8 *buf, int nmodes, int nregs,
259 int mode, int reg, bool inv, u8 *val)
261 u8 tmp[NAND_HYNIX_1XNM_RR_REPEAT];
262 int val_offs = (mode * nregs) + reg;
263 int set_size = nmodes * nregs;
266 for (i = 0; i < NAND_HYNIX_1XNM_RR_REPEAT; i++) {
267 int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv);
269 tmp[i] = buf[val_offs + set_offs];
272 ret = hynix_get_majority(tmp, NAND_HYNIX_1XNM_RR_REPEAT, val);
282 static u8 hynix_1xnm_mlc_read_retry_regs[] = {
283 0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf
286 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip,
287 const struct hynix_read_retry_otp *info)
289 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
290 struct hynix_read_retry *rr = NULL;
295 buf = kmalloc(info->size, GFP_KERNEL);
299 ret = hynix_read_rr_otp(chip, info, buf);
303 ret = hynix_get_majority(buf, NAND_HYNIX_1XNM_RR_REPEAT,
308 ret = hynix_get_majority(buf + NAND_HYNIX_1XNM_RR_REPEAT,
309 NAND_HYNIX_1XNM_RR_REPEAT,
314 rr = kzalloc(sizeof(*rr) + (nregs * nmodes), GFP_KERNEL);
320 for (i = 0; i < nmodes; i++) {
321 for (j = 0; j < nregs; j++) {
322 u8 *val = rr->values + (i * nregs);
324 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
329 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
337 rr->regs = hynix_1xnm_mlc_read_retry_regs;
338 hynix->read_retry = rr;
339 chip->ops.setup_read_retry = hynix_nand_setup_read_retry;
340 chip->read_retries = nmodes;
351 static const u8 hynix_mlc_1xnm_rr_otp_regs[] = { 0x38 };
352 static const u8 hynix_mlc_1xnm_rr_otp_values[] = { 0x52 };
354 static const struct hynix_read_retry_otp hynix_mlc_1xnm_rr_otps[] = {
356 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
357 .regs = hynix_mlc_1xnm_rr_otp_regs,
358 .values = hynix_mlc_1xnm_rr_otp_values,
363 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
364 .regs = hynix_mlc_1xnm_rr_otp_regs,
365 .values = hynix_mlc_1xnm_rr_otp_values,
371 static int hynix_nand_rr_init(struct nand_chip *chip)
376 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
379 * We only support read-retry for 1xnm NANDs, and those NANDs all
380 * expose a valid JEDEC ID.
383 u8 nand_tech = chip->id.data[5] >> 4;
385 /* 1xnm technology */
386 if (nand_tech == 4) {
387 for (i = 0; i < ARRAY_SIZE(hynix_mlc_1xnm_rr_otps);
390 * FIXME: Hynix recommend to copy the
391 * read-retry OTP area into a normal page.
393 ret = hynix_mlc_1xnm_rr_init(chip,
394 hynix_mlc_1xnm_rr_otps);
402 pr_warn("failed to initialize read-retry infrastructure");
407 static void hynix_nand_extract_oobsize(struct nand_chip *chip,
410 struct mtd_info *mtd = nand_to_mtd(chip);
411 struct nand_memory_organization *memorg;
414 memorg = nanddev_get_memorg(&chip->base);
416 oobsize = ((chip->id.data[3] >> 2) & 0x3) |
417 ((chip->id.data[3] >> 4) & 0x4);
422 memorg->oobsize = 2048;
425 memorg->oobsize = 1664;
428 memorg->oobsize = 1024;
431 memorg->oobsize = 640;
435 * We should never reach this case, but if that
436 * happens, this probably means Hynix decided to use
437 * a different extended ID format, and we should find
438 * a way to support it.
440 WARN(1, "Invalid OOB size");
446 memorg->oobsize = 128;
449 memorg->oobsize = 224;
452 memorg->oobsize = 448;
455 memorg->oobsize = 64;
458 memorg->oobsize = 32;
461 memorg->oobsize = 16;
464 memorg->oobsize = 640;
468 * We should never reach this case, but if that
469 * happens, this probably means Hynix decided to use
470 * a different extended ID format, and we should find
471 * a way to support it.
473 WARN(1, "Invalid OOB size");
478 * The datasheet of H27UCG8T2BTR mentions that the "Redundant
479 * Area Size" is encoded "per 8KB" (page size). This chip uses
480 * a page size of 16KiB. The datasheet mentions an OOB size of
481 * 1.280 bytes, but the OOB size encoded in the ID bytes (using
482 * the existing logic above) is 640 bytes.
483 * Update the OOB size for this chip by taking the value
484 * determined above and scaling it to the actual page size (so
485 * the actual OOB size for this chip is: 640 * 16k / 8k).
487 if (chip->id.data[1] == 0xde)
488 memorg->oobsize *= memorg->pagesize / SZ_8K;
491 mtd->oobsize = memorg->oobsize;
494 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
497 struct nand_device *base = &chip->base;
498 struct nand_ecc_props requirements = {};
499 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;
502 /* Reference: H27UCG8T2E datasheet */
503 requirements.step_size = 1024;
507 requirements.step_size = 0;
508 requirements.strength = 0;
511 requirements.strength = 4;
514 requirements.strength = 24;
517 requirements.strength = 32;
520 requirements.strength = 40;
523 requirements.strength = 50;
526 requirements.strength = 60;
530 * We should never reach this case, but if that
531 * happens, this probably means Hynix decided to use
532 * a different extended ID format, and we should find
533 * a way to support it.
535 WARN(1, "Invalid ECC requirements");
539 * The ECC requirements field meaning depends on the
542 u8 nand_tech = chip->id.data[5] & 0x7;
545 /* > 26nm, reference: H27UBG8T2A datasheet */
547 requirements.step_size = 512;
548 requirements.strength = 1 << ecc_level;
549 } else if (ecc_level < 7) {
551 requirements.step_size = 2048;
553 requirements.step_size = 1024;
554 requirements.strength = 24;
557 * We should never reach this case, but if that
558 * happens, this probably means Hynix decided
559 * to use a different extended ID format, and
560 * we should find a way to support it.
562 WARN(1, "Invalid ECC requirements");
565 /* <= 26nm, reference: H27UBG8T2B datasheet */
567 requirements.step_size = 0;
568 requirements.strength = 0;
569 } else if (ecc_level < 5) {
570 requirements.step_size = 512;
571 requirements.strength = 1 << (ecc_level - 1);
573 requirements.step_size = 1024;
574 requirements.strength = 24 +
575 (8 * (ecc_level - 5));
580 nanddev_set_ecc_requirements(base, &requirements);
583 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
588 /* We need scrambling on all TLC NANDs*/
589 if (nanddev_bits_per_cell(&chip->base) > 2)
590 chip->options |= NAND_NEED_SCRAMBLING;
592 /* And on MLC NANDs with sub-3xnm process */
594 nand_tech = chip->id.data[5] >> 4;
598 chip->options |= NAND_NEED_SCRAMBLING;
600 nand_tech = chip->id.data[5] & 0x7;
604 chip->options |= NAND_NEED_SCRAMBLING;
608 static void hynix_nand_decode_id(struct nand_chip *chip)
610 struct mtd_info *mtd = nand_to_mtd(chip);
611 struct nand_memory_organization *memorg;
615 memorg = nanddev_get_memorg(&chip->base);
618 * Exclude all SLC NANDs from this advanced detection scheme.
619 * According to the ranges defined in several datasheets, it might
620 * appear that even SLC NANDs could fall in this extended ID scheme.
621 * If that the case rework the test to let SLC NANDs go through the
624 if (chip->id.len < 6 || nand_is_slc(chip)) {
625 nand_decode_ext_id(chip);
629 /* Extract pagesize */
630 memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);
631 mtd->writesize = memorg->pagesize;
633 tmp = (chip->id.data[3] >> 4) & 0x3;
635 * When bit7 is set that means we start counting at 1MiB, otherwise
636 * we start counting at 128KiB and shift this value the content of
638 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in
639 * this case the erasesize is set to 768KiB.
641 if (chip->id.data[3] & 0x80) {
642 memorg->pages_per_eraseblock = (SZ_1M << tmp) /
644 mtd->erasesize = SZ_1M << tmp;
645 } else if (tmp == 3) {
646 memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) /
648 mtd->erasesize = SZ_512K + SZ_256K;
650 memorg->pages_per_eraseblock = (SZ_128K << tmp) /
652 mtd->erasesize = SZ_128K << tmp;
656 * Modern Toggle DDR NANDs have a valid JEDECID even though they are
657 * not exposing a valid JEDEC parameter table.
658 * These NANDs use a different NAND ID scheme.
660 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
662 hynix_nand_extract_oobsize(chip, valid_jedecid);
663 hynix_nand_extract_ecc_requirements(chip, valid_jedecid);
664 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid);
667 static void hynix_nand_cleanup(struct nand_chip *chip)
669 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
674 kfree(hynix->read_retry);
676 nand_set_manufacturer_data(chip, NULL);
680 h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip,
681 struct nand_interface_config *iface)
683 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
685 return nand_choose_best_sdr_timings(chip, iface, NULL);
688 static int h27ucg8t2etrbc_init(struct nand_chip *chip)
690 struct mtd_info *mtd = nand_to_mtd(chip);
692 chip->options |= NAND_NEED_SCRAMBLING;
693 mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme);
698 static int hynix_nand_init(struct nand_chip *chip)
700 struct hynix_nand *hynix;
703 if (!nand_is_slc(chip))
704 chip->options |= NAND_BBM_LASTPAGE;
706 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
708 hynix = kzalloc(sizeof(*hynix), GFP_KERNEL);
712 nand_set_manufacturer_data(chip, hynix);
714 if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model,
715 sizeof("H27UCG8T2ATR-BC") - 1))
716 chip->ops.choose_interface_config =
717 h27ucg8t2atrbc_choose_interface_config;
719 if (!strncmp("H27UCG8T2ETR-BC", chip->parameters.model,
720 sizeof("H27UCG8T2ETR-BC") - 1))
721 h27ucg8t2etrbc_init(chip);
723 ret = hynix_nand_rr_init(chip);
725 hynix_nand_cleanup(chip);
730 static void hynix_fixup_onfi_param_page(struct nand_chip *chip,
731 struct nand_onfi_params *p)
734 * Certain chips might report a 0 on sdr_timing_mode field
735 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI.
736 * According to ONFI specification, bit 0 of this field "shall be 1".
737 * Forcibly set this bit.
739 p->sdr_timing_modes |= cpu_to_le16(BIT(0));
742 const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
743 .detect = hynix_nand_decode_id,
744 .init = hynix_nand_init,
745 .cleanup = hynix_nand_cleanup,
746 .fixup_onfi_param_page = hynix_fixup_onfi_param_page,