1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017 Free Electrons
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
8 * Derived from the atmel_nand.c driver which contained the following
11 * Copyright 2003 Rick Bronson
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
14 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
16 * Derived from drivers/mtd/spia.c (removed in v3.8)
17 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
21 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
25 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
27 * Add Programmable Multibit ECC support for various AT91 SoC
28 * Copyright 2012 ATMEL, Hong Xu
30 * Add Nand Flash Controller support for SAMA5 SoC
31 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
33 * A few words about the naming convention in this file. This convention
34 * applies to structure and function names.
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
40 * (at91sam9 and avr32 SoCs)
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
42 * (sama5 SoCs and later)
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
44 * that is available in the HSMC block
45 * - <soc>_nand_: all SoC specific structures/functions
48 #include <linux/clk.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/dmaengine.h>
51 #include <linux/genalloc.h>
52 #include <linux/gpio/consumer.h>
53 #include <linux/interrupt.h>
54 #include <linux/mfd/syscon.h>
55 #include <linux/mfd/syscon/atmel-matrix.h>
56 #include <linux/mfd/syscon/atmel-smc.h>
57 #include <linux/module.h>
58 #include <linux/mtd/rawnand.h>
59 #include <linux/of_address.h>
60 #include <linux/of_irq.h>
61 #include <linux/of_platform.h>
62 #include <linux/iopoll.h>
63 #include <linux/platform_device.h>
64 #include <linux/regmap.h>
65 #include <soc/at91/atmel-sfr.h>
69 #define ATMEL_HSMC_NFC_CFG 0x0
70 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
71 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
72 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
73 #define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
74 #define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
75 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
76 #define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
77 #define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
78 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
81 #define ATMEL_HSMC_NFC_CTRL 0x4
82 #define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
83 #define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
85 #define ATMEL_HSMC_NFC_SR 0x8
86 #define ATMEL_HSMC_NFC_IER 0xc
87 #define ATMEL_HSMC_NFC_IDR 0x10
88 #define ATMEL_HSMC_NFC_IMR 0x14
89 #define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
90 #define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
91 #define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
92 #define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
93 #define ATMEL_HSMC_NFC_SR_WR BIT(11)
94 #define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
95 #define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
96 #define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
97 #define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
98 #define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
99 #define ATMEL_HSMC_NFC_SR_AWB BIT(22)
100 #define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
101 #define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
102 ATMEL_HSMC_NFC_SR_UNDEF | \
103 ATMEL_HSMC_NFC_SR_AWB | \
104 ATMEL_HSMC_NFC_SR_NFCASE)
105 #define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
107 #define ATMEL_HSMC_NFC_ADDR 0x18
108 #define ATMEL_HSMC_NFC_BANK 0x1c
110 #define ATMEL_NFC_MAX_RB_ID 7
112 #define ATMEL_NFC_SRAM_SIZE 0x2400
114 #define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
115 #define ATMEL_NFC_VCMD2 BIT(18)
116 #define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
117 #define ATMEL_NFC_CSID(cs) ((cs) << 22)
118 #define ATMEL_NFC_DATAEN BIT(25)
119 #define ATMEL_NFC_NFCWR BIT(26)
121 #define ATMEL_NFC_MAX_ADDR_CYCLES 5
123 #define ATMEL_NAND_ALE_OFFSET BIT(21)
124 #define ATMEL_NAND_CLE_OFFSET BIT(22)
126 #define DEFAULT_TIMEOUT_MS 1000
127 #define MIN_DMA_LEN 128
129 static bool atmel_nand_avoid_dma __read_mostly;
131 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
132 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
134 enum atmel_nand_rb_type {
136 ATMEL_NAND_NATIVE_RB,
140 struct atmel_nand_rb {
141 enum atmel_nand_rb_type type;
143 struct gpio_desc *gpio;
148 struct atmel_nand_cs {
150 struct atmel_nand_rb rb;
151 struct gpio_desc *csgpio;
157 struct atmel_smc_cs_conf smcconf;
161 struct list_head node;
163 struct nand_chip base;
164 struct atmel_nand_cs *activecs;
165 struct atmel_pmecc_user *pmecc;
166 struct gpio_desc *cdgpio;
168 struct atmel_nand_cs cs[];
171 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
173 return container_of(chip, struct atmel_nand, base);
176 enum atmel_nfc_data_xfer {
179 ATMEL_NFC_WRITE_DATA,
182 struct atmel_nfc_op {
188 enum atmel_nfc_data_xfer data;
193 struct atmel_nand_controller;
194 struct atmel_nand_controller_caps;
196 struct atmel_nand_controller_ops {
197 int (*probe)(struct platform_device *pdev,
198 const struct atmel_nand_controller_caps *caps);
199 int (*remove)(struct atmel_nand_controller *nc);
200 void (*nand_init)(struct atmel_nand_controller *nc,
201 struct atmel_nand *nand);
202 int (*ecc_init)(struct nand_chip *chip);
203 int (*setup_interface)(struct atmel_nand *nand, int csline,
204 const struct nand_interface_config *conf);
205 int (*exec_op)(struct atmel_nand *nand,
206 const struct nand_operation *op, bool check_only);
209 struct atmel_nand_controller_caps {
211 bool legacy_of_bindings;
214 const char *ebi_csa_regmap_name;
215 const struct atmel_nand_controller_ops *ops;
218 struct atmel_nand_controller {
219 struct nand_controller base;
220 const struct atmel_nand_controller_caps *caps;
223 struct dma_chan *dmac;
224 struct atmel_pmecc *pmecc;
225 struct list_head chips;
229 static inline struct atmel_nand_controller *
230 to_nand_controller(struct nand_controller *ctl)
232 return container_of(ctl, struct atmel_nand_controller, base);
235 struct atmel_smc_nand_ebi_csa_cfg {
240 struct atmel_smc_nand_controller {
241 struct atmel_nand_controller base;
242 struct regmap *ebi_csa_regmap;
243 struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
246 static inline struct atmel_smc_nand_controller *
247 to_smc_nand_controller(struct nand_controller *ctl)
249 return container_of(to_nand_controller(ctl),
250 struct atmel_smc_nand_controller, base);
253 struct atmel_hsmc_nand_controller {
254 struct atmel_nand_controller base;
256 struct gen_pool *pool;
260 const struct atmel_hsmc_reg_layout *hsmc_layout;
262 struct atmel_nfc_op op;
263 struct completion complete;
267 /* Only used when instantiating from legacy DT bindings. */
271 static inline struct atmel_hsmc_nand_controller *
272 to_hsmc_nand_controller(struct nand_controller *ctl)
274 return container_of(to_nand_controller(ctl),
275 struct atmel_hsmc_nand_controller, base);
278 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
280 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
281 op->wait ^= status & op->wait;
283 return !op->wait || op->errors;
286 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
288 struct atmel_hsmc_nand_controller *nc = data;
292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
295 done = atmel_nfc_op_done(&nc->op, sr);
298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
301 complete(&nc->complete);
303 return rcvd ? IRQ_HANDLED : IRQ_NONE;
306 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
307 unsigned int timeout_ms)
312 timeout_ms = DEFAULT_TIMEOUT_MS;
317 ret = regmap_read_poll_timeout(nc->base.smc,
318 ATMEL_HSMC_NFC_SR, status,
319 atmel_nfc_op_done(&nc->op,
321 0, timeout_ms * 1000);
323 init_completion(&nc->complete);
324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
326 ret = wait_for_completion_timeout(&nc->complete,
327 msecs_to_jiffies(timeout_ms));
333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
342 dev_err(nc->base.dev, "Access to an undefined area\n");
346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
347 dev_err(nc->base.dev, "Access while busy\n");
351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
352 dev_err(nc->base.dev, "Wrong access size\n");
359 static void atmel_nand_dma_transfer_finished(void *data)
361 struct completion *finished = data;
366 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
367 void *buf, dma_addr_t dev_dma, size_t len,
368 enum dma_data_direction dir)
370 DECLARE_COMPLETION_ONSTACK(finished);
371 dma_addr_t src_dma, dst_dma, buf_dma;
372 struct dma_async_tx_descriptor *tx;
375 buf_dma = dma_map_single(nc->dev, buf, len, dir);
376 if (dma_mapping_error(nc->dev, dev_dma)) {
378 "Failed to prepare a buffer for DMA access\n");
382 if (dir == DMA_FROM_DEVICE) {
390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
391 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
397 tx->callback = atmel_nand_dma_transfer_finished;
398 tx->callback_param = &finished;
400 cookie = dmaengine_submit(tx);
401 if (dma_submit_error(cookie)) {
402 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
406 dma_async_issue_pending(nc->dmac);
407 wait_for_completion(&finished);
408 dma_unmap_single(nc->dev, buf_dma, len, dir);
413 dma_unmap_single(nc->dev, buf_dma, len, dir);
416 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
421 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
423 u8 *addrs = nc->op.addrs;
428 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
430 for (i = 0; i < nc->op.ncmds; i++)
431 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
433 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
434 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
436 op |= ATMEL_NFC_CSID(nc->op.cs) |
437 ATMEL_NFC_ACYCLE(nc->op.naddrs);
439 if (nc->op.ncmds > 1)
440 op |= ATMEL_NFC_VCMD2;
442 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
445 if (nc->op.data != ATMEL_NFC_NO_DATA) {
446 op |= ATMEL_NFC_DATAEN;
447 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
449 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
450 op |= ATMEL_NFC_NFCWR;
453 /* Clear all flags. */
454 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
456 /* Send the command. */
457 regmap_write(nc->io, op, addr);
459 ret = atmel_nfc_wait(nc, poll, 0);
461 dev_err(nc->base.dev,
462 "Failed to send NAND command (err = %d)!",
465 /* Reset the op state. */
466 memset(&nc->op, 0, sizeof(nc->op));
471 static void atmel_nand_data_in(struct atmel_nand *nand, void *buf,
472 unsigned int len, bool force_8bit)
474 struct atmel_nand_controller *nc;
476 nc = to_nand_controller(nand->base.controller);
479 * If the controller supports DMA, the buffer address is DMA-able and
480 * len is long enough to make DMA transfers profitable, let's trigger
481 * a DMA transfer. If it fails, fallback to PIO mode.
483 if (nc->dmac && virt_addr_valid(buf) &&
484 len >= MIN_DMA_LEN && !force_8bit &&
485 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
489 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
490 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
492 ioread8_rep(nand->activecs->io.virt, buf, len);
495 static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf,
496 unsigned int len, bool force_8bit)
498 struct atmel_nand_controller *nc;
500 nc = to_nand_controller(nand->base.controller);
503 * If the controller supports DMA, the buffer address is DMA-able and
504 * len is long enough to make DMA transfers profitable, let's trigger
505 * a DMA transfer. If it fails, fallback to PIO mode.
507 if (nc->dmac && virt_addr_valid(buf) &&
508 len >= MIN_DMA_LEN && !force_8bit &&
509 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
513 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
514 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
516 iowrite8_rep(nand->activecs->io.virt, buf, len);
519 static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms)
521 if (nand->activecs->rb.type == ATMEL_NAND_NO_RB)
522 return nand_soft_waitrdy(&nand->base, timeout_ms);
524 return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio,
528 static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand,
529 unsigned int timeout_ms)
531 struct atmel_hsmc_nand_controller *nc;
534 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
535 return atmel_nand_waitrdy(nand, timeout_ms);
537 nc = to_hsmc_nand_controller(nand->base.controller);
538 mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
539 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,
540 status, status & mask,
541 10, timeout_ms * 1000);
544 static void atmel_nand_select_target(struct atmel_nand *nand,
547 nand->activecs = &nand->cs[cs];
550 static void atmel_hsmc_nand_select_target(struct atmel_nand *nand,
553 struct mtd_info *mtd = nand_to_mtd(&nand->base);
554 struct atmel_hsmc_nand_controller *nc;
555 u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
556 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
557 ATMEL_HSMC_NFC_CFG_RSPARE;
559 nand->activecs = &nand->cs[cs];
560 nc = to_hsmc_nand_controller(nand->base.controller);
564 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
565 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
566 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
567 ATMEL_HSMC_NFC_CFG_RSPARE |
568 ATMEL_HSMC_NFC_CFG_WSPARE,
573 static int atmel_smc_nand_exec_instr(struct atmel_nand *nand,
574 const struct nand_op_instr *instr)
576 struct atmel_nand_controller *nc;
579 nc = to_nand_controller(nand->base.controller);
580 switch (instr->type) {
581 case NAND_OP_CMD_INSTR:
582 writeb(instr->ctx.cmd.opcode,
583 nand->activecs->io.virt + nc->caps->cle_offs);
585 case NAND_OP_ADDR_INSTR:
586 for (i = 0; i < instr->ctx.addr.naddrs; i++)
587 writeb(instr->ctx.addr.addrs[i],
588 nand->activecs->io.virt + nc->caps->ale_offs);
590 case NAND_OP_DATA_IN_INSTR:
591 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
593 instr->ctx.data.force_8bit);
595 case NAND_OP_DATA_OUT_INSTR:
596 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
598 instr->ctx.data.force_8bit);
600 case NAND_OP_WAITRDY_INSTR:
601 return atmel_nand_waitrdy(nand,
602 instr->ctx.waitrdy.timeout_ms);
610 static int atmel_smc_nand_exec_op(struct atmel_nand *nand,
611 const struct nand_operation *op,
620 atmel_nand_select_target(nand, op->cs);
621 gpiod_set_value(nand->activecs->csgpio, 0);
622 for (i = 0; i < op->ninstrs; i++) {
623 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]);
627 gpiod_set_value(nand->activecs->csgpio, 1);
632 static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip,
633 const struct nand_subop *subop)
635 struct atmel_nand *nand = to_atmel_nand(chip);
636 struct atmel_hsmc_nand_controller *nc;
639 nc = to_hsmc_nand_controller(chip->controller);
641 nc->op.cs = nand->activecs->id;
642 for (i = 0; i < subop->ninstrs; i++) {
643 const struct nand_op_instr *instr = &subop->instrs[i];
645 if (instr->type == NAND_OP_CMD_INSTR) {
646 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;
650 for (j = nand_subop_get_addr_start_off(subop, i);
651 j < nand_subop_get_num_addr_cyc(subop, i); j++) {
652 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];
657 return atmel_nfc_exec_op(nc, true);
660 static int atmel_hsmc_exec_rw(struct nand_chip *chip,
661 const struct nand_subop *subop)
663 const struct nand_op_instr *instr = subop->instrs;
664 struct atmel_nand *nand = to_atmel_nand(chip);
666 if (instr->type == NAND_OP_DATA_IN_INSTR)
667 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
669 instr->ctx.data.force_8bit);
671 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
673 instr->ctx.data.force_8bit);
678 static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip,
679 const struct nand_subop *subop)
681 const struct nand_op_instr *instr = subop->instrs;
682 struct atmel_nand *nand = to_atmel_nand(chip);
684 return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms);
687 static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER(
688 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr,
689 NAND_OP_PARSER_PAT_CMD_ELEM(true),
690 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
691 NAND_OP_PARSER_PAT_CMD_ELEM(true)),
692 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
693 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)),
694 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
695 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)),
696 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy,
697 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
700 static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand,
701 const struct nand_operation *op,
707 return nand_op_parser_exec_op(&nand->base,
708 &atmel_hsmc_op_parser, op, true);
710 atmel_hsmc_nand_select_target(nand, op->cs);
711 ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op,
717 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
720 struct mtd_info *mtd = nand_to_mtd(chip);
721 struct atmel_hsmc_nand_controller *nc;
724 nc = to_hsmc_nand_controller(chip->controller);
727 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
728 nc->sram.dma, mtd->writesize,
731 /* Falling back to CPU copy. */
733 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
736 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
740 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
743 struct mtd_info *mtd = nand_to_mtd(chip);
744 struct atmel_hsmc_nand_controller *nc;
747 nc = to_hsmc_nand_controller(chip->controller);
750 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
751 mtd->writesize, DMA_FROM_DEVICE);
753 /* Falling back to CPU copy. */
755 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
758 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
762 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
764 struct mtd_info *mtd = nand_to_mtd(chip);
765 struct atmel_hsmc_nand_controller *nc;
767 nc = to_hsmc_nand_controller(chip->controller);
770 nc->op.addrs[nc->op.naddrs++] = column;
773 * 2 address cycles for the column offset on large page NANDs.
775 if (mtd->writesize > 512)
776 nc->op.addrs[nc->op.naddrs++] = column >> 8;
780 nc->op.addrs[nc->op.naddrs++] = page;
781 nc->op.addrs[nc->op.naddrs++] = page >> 8;
783 if (chip->options & NAND_ROW_ADDR_3)
784 nc->op.addrs[nc->op.naddrs++] = page >> 16;
788 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
790 struct atmel_nand *nand = to_atmel_nand(chip);
791 struct atmel_nand_controller *nc;
794 nc = to_nand_controller(chip->controller);
799 ret = atmel_pmecc_enable(nand->pmecc, op);
802 "Failed to enable ECC engine (err = %d)\n", ret);
807 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
809 struct atmel_nand *nand = to_atmel_nand(chip);
812 atmel_pmecc_disable(nand->pmecc);
815 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
817 struct atmel_nand *nand = to_atmel_nand(chip);
818 struct mtd_info *mtd = nand_to_mtd(chip);
819 struct atmel_nand_controller *nc;
820 struct mtd_oob_region oobregion;
824 nc = to_nand_controller(chip->controller);
829 ret = atmel_pmecc_wait_rdy(nand->pmecc);
832 "Failed to transfer NAND page data (err = %d)\n",
837 mtd_ooblayout_ecc(mtd, 0, &oobregion);
838 eccbuf = chip->oob_poi + oobregion.offset;
840 for (i = 0; i < chip->ecc.steps; i++) {
841 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
843 eccbuf += chip->ecc.bytes;
849 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
852 struct atmel_nand *nand = to_atmel_nand(chip);
853 struct mtd_info *mtd = nand_to_mtd(chip);
854 struct atmel_nand_controller *nc;
855 struct mtd_oob_region oobregion;
856 int ret, i, max_bitflips = 0;
857 void *databuf, *eccbuf;
859 nc = to_nand_controller(chip->controller);
864 ret = atmel_pmecc_wait_rdy(nand->pmecc);
867 "Failed to read NAND page data (err = %d)\n",
872 mtd_ooblayout_ecc(mtd, 0, &oobregion);
873 eccbuf = chip->oob_poi + oobregion.offset;
876 for (i = 0; i < chip->ecc.steps; i++) {
877 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
879 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
880 ret = nand_check_erased_ecc_chunk(databuf,
888 mtd->ecc_stats.corrected += ret;
889 max_bitflips = max(ret, max_bitflips);
891 mtd->ecc_stats.failed++;
894 databuf += chip->ecc.size;
895 eccbuf += chip->ecc.bytes;
901 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
902 bool oob_required, int page, bool raw)
904 struct mtd_info *mtd = nand_to_mtd(chip);
905 struct atmel_nand *nand = to_atmel_nand(chip);
908 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
910 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
914 nand_write_data_op(chip, buf, mtd->writesize, false);
916 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
918 atmel_pmecc_disable(nand->pmecc);
922 atmel_nand_pmecc_disable(chip, raw);
924 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
926 return nand_prog_page_end_op(chip);
929 static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
930 int oob_required, int page)
932 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
935 static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
936 const u8 *buf, int oob_required,
939 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
942 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
943 bool oob_required, int page, bool raw)
945 struct mtd_info *mtd = nand_to_mtd(chip);
948 nand_read_page_op(chip, page, 0, NULL, 0);
950 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
954 ret = nand_read_data_op(chip, buf, mtd->writesize, false, false);
958 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false);
962 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
965 atmel_nand_pmecc_disable(chip, raw);
970 static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
971 int oob_required, int page)
973 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
976 static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
977 int oob_required, int page)
979 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
982 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
983 const u8 *buf, bool oob_required,
986 struct mtd_info *mtd = nand_to_mtd(chip);
987 struct atmel_nand *nand = to_atmel_nand(chip);
988 struct atmel_hsmc_nand_controller *nc;
991 atmel_hsmc_nand_select_target(nand, chip->cur_cs);
992 nc = to_hsmc_nand_controller(chip->controller);
994 atmel_nfc_copy_to_sram(chip, buf, false);
996 nc->op.cmds[0] = NAND_CMD_SEQIN;
998 atmel_nfc_set_op_addr(chip, page, 0x0);
999 nc->op.cs = nand->activecs->id;
1000 nc->op.data = ATMEL_NFC_WRITE_DATA;
1002 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
1006 ret = atmel_nfc_exec_op(nc, false);
1008 atmel_nand_pmecc_disable(chip, raw);
1009 dev_err(nc->base.dev,
1010 "Failed to transfer NAND page data (err = %d)\n",
1015 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
1017 atmel_nand_pmecc_disable(chip, raw);
1022 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
1024 return nand_prog_page_end_op(chip);
1027 static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
1028 const u8 *buf, int oob_required,
1031 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1035 static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
1037 int oob_required, int page)
1039 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1043 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
1044 bool oob_required, int page,
1047 struct mtd_info *mtd = nand_to_mtd(chip);
1048 struct atmel_nand *nand = to_atmel_nand(chip);
1049 struct atmel_hsmc_nand_controller *nc;
1052 atmel_hsmc_nand_select_target(nand, chip->cur_cs);
1053 nc = to_hsmc_nand_controller(chip->controller);
1056 * Optimized read page accessors only work when the NAND R/B pin is
1057 * connected to a native SoC R/B pin. If that's not the case, fallback
1058 * to the non-optimized one.
1060 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
1061 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1064 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1066 if (mtd->writesize > 512)
1067 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1069 atmel_nfc_set_op_addr(chip, page, 0x0);
1070 nc->op.cs = nand->activecs->id;
1071 nc->op.data = ATMEL_NFC_READ_DATA;
1073 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1077 ret = atmel_nfc_exec_op(nc, false);
1079 atmel_nand_pmecc_disable(chip, raw);
1080 dev_err(nc->base.dev,
1081 "Failed to load NAND page data (err = %d)\n",
1086 atmel_nfc_copy_from_sram(chip, buf, true);
1088 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1090 atmel_nand_pmecc_disable(chip, raw);
1095 static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
1096 int oob_required, int page)
1098 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1102 static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
1103 u8 *buf, int oob_required,
1106 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1110 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1112 const struct nand_ecc_props *requirements =
1113 nanddev_get_ecc_requirements(&chip->base);
1114 struct mtd_info *mtd = nand_to_mtd(chip);
1115 struct nand_device *nanddev = mtd_to_nanddev(mtd);
1116 struct atmel_nand *nand = to_atmel_nand(chip);
1117 struct atmel_nand_controller *nc;
1118 struct atmel_pmecc_user_req req;
1120 nc = to_nand_controller(chip->controller);
1123 dev_err(nc->dev, "HW ECC not supported\n");
1127 if (nc->caps->legacy_of_bindings) {
1130 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1132 chip->ecc.strength = val;
1134 if (!of_property_read_u32(nc->dev->of_node,
1135 "atmel,pmecc-sector-size",
1137 chip->ecc.size = val;
1140 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
1141 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1142 else if (chip->ecc.strength)
1143 req.ecc.strength = chip->ecc.strength;
1144 else if (requirements->strength)
1145 req.ecc.strength = requirements->strength;
1147 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1150 req.ecc.sectorsize = chip->ecc.size;
1151 else if (requirements->step_size)
1152 req.ecc.sectorsize = requirements->step_size;
1154 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1156 req.pagesize = mtd->writesize;
1157 req.oobsize = mtd->oobsize;
1159 if (mtd->writesize <= 512) {
1161 req.ecc.ooboffset = 0;
1163 req.ecc.bytes = mtd->oobsize - 2;
1164 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1167 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1168 if (IS_ERR(nand->pmecc))
1169 return PTR_ERR(nand->pmecc);
1171 chip->ecc.algo = NAND_ECC_ALGO_BCH;
1172 chip->ecc.size = req.ecc.sectorsize;
1173 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1174 chip->ecc.strength = req.ecc.strength;
1176 chip->options |= NAND_NO_SUBPAGE_WRITE;
1178 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1183 static int atmel_nand_ecc_init(struct nand_chip *chip)
1185 struct atmel_nand_controller *nc;
1188 nc = to_nand_controller(chip->controller);
1190 switch (chip->ecc.engine_type) {
1191 case NAND_ECC_ENGINE_TYPE_NONE:
1192 case NAND_ECC_ENGINE_TYPE_SOFT:
1194 * Nothing to do, the core will initialize everything for us.
1198 case NAND_ECC_ENGINE_TYPE_ON_HOST:
1199 ret = atmel_nand_pmecc_init(chip);
1203 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1204 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1205 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1206 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1210 /* Other modes are not supported. */
1211 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1212 chip->ecc.engine_type);
1219 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1223 ret = atmel_nand_ecc_init(chip);
1227 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
1230 /* Adjust the ECC operations for the HSMC IP. */
1231 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1232 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1233 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1234 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1239 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1240 const struct nand_interface_config *conf,
1241 struct atmel_smc_cs_conf *smcconf)
1243 u32 ncycles, totalcycles, timeps, mckperiodps;
1244 struct atmel_nand_controller *nc;
1247 nc = to_nand_controller(nand->base.controller);
1249 /* DDR interface not supported. */
1250 if (!nand_interface_is_sdr(conf))
1254 * tRC < 30ns implies EDO mode. This controller does not support this
1257 if (conf->timings.sdr.tRC_min < 30000)
1260 atmel_smc_cs_conf_init(smcconf);
1262 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1263 mckperiodps *= 1000;
1266 * Set write pulse timing. This one is easy to extract:
1270 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1271 totalcycles = ncycles;
1272 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1278 * The write setup timing depends on the operation done on the NAND.
1279 * All operations goes through the same data bus, but the operation
1280 * type depends on the address we are writing to (ALE/CLE address
1282 * Since we have no way to differentiate the different operations at
1283 * the SMC level, we must consider the worst case (the biggest setup
1284 * time among all operation types):
1286 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1288 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1289 conf->timings.sdr.tALS_min);
1290 timeps = max(timeps, conf->timings.sdr.tDS_min);
1291 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1292 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1293 totalcycles += ncycles;
1294 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1300 * As for the write setup timing, the write hold timing depends on the
1301 * operation done on the NAND:
1303 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1305 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1306 conf->timings.sdr.tALH_min);
1307 timeps = max3(timeps, conf->timings.sdr.tDH_min,
1308 conf->timings.sdr.tWH_min);
1309 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1310 totalcycles += ncycles;
1313 * The write cycle timing is directly matching tWC, but is also
1314 * dependent on the other timings on the setup and hold timings we
1315 * calculated earlier, which gives:
1317 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1319 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1320 ncycles = max(totalcycles, ncycles);
1321 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1327 * We don't want the CS line to be toggled between each byte/word
1328 * transfer to the NAND. The only way to guarantee that is to have the
1329 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1331 * NCS_WR_PULSE = NWE_CYCLE
1333 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1339 * As for the write setup timing, the read hold timing depends on the
1340 * operation done on the NAND:
1342 * NRD_HOLD = max(tREH, tRHOH)
1344 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1345 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1346 totalcycles = ncycles;
1349 * TDF = tRHZ - NRD_HOLD
1351 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1352 ncycles -= totalcycles;
1355 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1356 * we might end up with a config that does not fit in the TDF field.
1357 * Just take the max value in this case and hope that the NAND is more
1358 * tolerant than advertised.
1360 if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1361 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1362 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1363 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1365 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1366 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1369 * Read pulse timing directly matches tRP:
1373 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1374 totalcycles += ncycles;
1375 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1381 * The write cycle timing is directly matching tWC, but is also
1382 * dependent on the setup and hold timings we calculated earlier,
1385 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1387 * NRD_SETUP is always 0.
1389 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1390 ncycles = max(totalcycles, ncycles);
1391 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1397 * We don't want the CS line to be toggled between each byte/word
1398 * transfer from the NAND. The only way to guarantee that is to have
1399 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1401 * NCS_RD_PULSE = NRD_CYCLE
1403 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1408 /* Txxx timings are directly matching tXXX ones. */
1409 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1410 ret = atmel_smc_cs_conf_set_timing(smcconf,
1411 ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1416 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1417 ret = atmel_smc_cs_conf_set_timing(smcconf,
1418 ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1421 * Version 4 of the ONFI spec mandates that tADL be at least 400
1422 * nanoseconds, but, depending on the master clock rate, 400 ns may not
1423 * fit in the tADL field of the SMC reg. We need to relax the check and
1424 * accept the -ERANGE return code.
1426 * Note that previous versions of the ONFI spec had a lower tADL_min
1427 * (100 or 200 ns). It's not clear why this timing constraint got
1428 * increased but it seems most NANDs are fine with values lower than
1429 * 400ns, so we should be safe.
1431 if (ret && ret != -ERANGE)
1434 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1435 ret = atmel_smc_cs_conf_set_timing(smcconf,
1436 ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1441 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1442 ret = atmel_smc_cs_conf_set_timing(smcconf,
1443 ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1448 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1449 ret = atmel_smc_cs_conf_set_timing(smcconf,
1450 ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1455 /* Attach the CS line to the NFC logic. */
1456 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1458 /* Set the appropriate data bus width. */
1459 if (nand->base.options & NAND_BUSWIDTH_16)
1460 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1462 /* Operate in NRD/NWE READ/WRITEMODE. */
1463 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1464 ATMEL_SMC_MODE_WRITEMODE_NWE;
1469 static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
1471 const struct nand_interface_config *conf)
1473 struct atmel_nand_controller *nc;
1474 struct atmel_smc_cs_conf smcconf;
1475 struct atmel_nand_cs *cs;
1478 nc = to_nand_controller(nand->base.controller);
1480 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1484 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1487 cs = &nand->cs[csline];
1488 cs->smcconf = smcconf;
1489 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1494 static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
1496 const struct nand_interface_config *conf)
1498 struct atmel_hsmc_nand_controller *nc;
1499 struct atmel_smc_cs_conf smcconf;
1500 struct atmel_nand_cs *cs;
1503 nc = to_hsmc_nand_controller(nand->base.controller);
1505 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1509 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1512 cs = &nand->cs[csline];
1513 cs->smcconf = smcconf;
1515 if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1516 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1518 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1524 static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
1525 const struct nand_interface_config *conf)
1527 struct atmel_nand *nand = to_atmel_nand(chip);
1528 const struct nand_sdr_timings *sdr;
1529 struct atmel_nand_controller *nc;
1531 sdr = nand_get_sdr_timings(conf);
1533 return PTR_ERR(sdr);
1535 nc = to_nand_controller(nand->base.controller);
1537 if (csline >= nand->numcs ||
1538 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1541 return nc->caps->ops->setup_interface(nand, csline, conf);
1544 static int atmel_nand_exec_op(struct nand_chip *chip,
1545 const struct nand_operation *op,
1548 struct atmel_nand *nand = to_atmel_nand(chip);
1549 struct atmel_nand_controller *nc;
1551 nc = to_nand_controller(nand->base.controller);
1553 return nc->caps->ops->exec_op(nand, op, check_only);
1556 static void atmel_nand_init(struct atmel_nand_controller *nc,
1557 struct atmel_nand *nand)
1559 struct nand_chip *chip = &nand->base;
1560 struct mtd_info *mtd = nand_to_mtd(chip);
1562 mtd->dev.parent = nc->dev;
1563 nand->base.controller = &nc->base;
1565 if (!nc->mck || !nc->caps->ops->setup_interface)
1566 chip->options |= NAND_KEEP_TIMINGS;
1569 * Use a bounce buffer when the buffer passed by the MTD user is not
1573 chip->options |= NAND_USES_DMA;
1575 /* Default to HW ECC if pmecc is available. */
1577 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1580 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1581 struct atmel_nand *nand)
1583 struct nand_chip *chip = &nand->base;
1584 struct atmel_smc_nand_controller *smc_nc;
1587 atmel_nand_init(nc, nand);
1589 smc_nc = to_smc_nand_controller(chip->controller);
1590 if (!smc_nc->ebi_csa_regmap)
1593 /* Attach the CS to the NAND Flash logic. */
1594 for (i = 0; i < nand->numcs; i++)
1595 regmap_update_bits(smc_nc->ebi_csa_regmap,
1596 smc_nc->ebi_csa->offs,
1597 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1599 if (smc_nc->ebi_csa->nfd0_on_d16)
1600 regmap_update_bits(smc_nc->ebi_csa_regmap,
1601 smc_nc->ebi_csa->offs,
1602 smc_nc->ebi_csa->nfd0_on_d16,
1603 smc_nc->ebi_csa->nfd0_on_d16);
1606 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1608 struct nand_chip *chip = &nand->base;
1609 struct mtd_info *mtd = nand_to_mtd(chip);
1612 ret = mtd_device_unregister(mtd);
1617 list_del(&nand->node);
1622 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1623 struct device_node *np,
1626 struct atmel_nand *nand;
1627 struct gpio_desc *gpio;
1630 numcs = of_property_count_elems_of_size(np, "reg",
1631 reg_cells * sizeof(u32));
1633 dev_err(nc->dev, "Missing or invalid reg property\n");
1634 return ERR_PTR(-EINVAL);
1637 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
1639 return ERR_PTR(-ENOMEM);
1641 nand->numcs = numcs;
1643 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),
1644 "det", GPIOD_IN, "nand-det");
1645 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1647 "Failed to get detect gpio (err = %ld)\n",
1649 return ERR_CAST(gpio);
1653 nand->cdgpio = gpio;
1655 for (i = 0; i < numcs; i++) {
1656 struct resource res;
1659 ret = of_address_to_resource(np, 0, &res);
1661 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1663 return ERR_PTR(ret);
1666 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1669 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1671 return ERR_PTR(ret);
1674 nand->cs[i].id = val;
1676 nand->cs[i].io.dma = res.start;
1677 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1678 if (IS_ERR(nand->cs[i].io.virt))
1679 return ERR_CAST(nand->cs[i].io.virt);
1681 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1682 if (val > ATMEL_NFC_MAX_RB_ID)
1683 return ERR_PTR(-EINVAL);
1685 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1686 nand->cs[i].rb.id = val;
1688 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1689 of_fwnode_handle(np),
1692 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1694 "Failed to get R/B gpio (err = %ld)\n",
1696 return ERR_CAST(gpio);
1699 if (!IS_ERR(gpio)) {
1700 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1701 nand->cs[i].rb.gpio = gpio;
1705 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1706 of_fwnode_handle(np),
1707 "cs", i, GPIOD_OUT_HIGH,
1709 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1711 "Failed to get CS gpio (err = %ld)\n",
1713 return ERR_CAST(gpio);
1717 nand->cs[i].csgpio = gpio;
1720 nand_set_flash_node(&nand->base, np);
1726 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1727 struct atmel_nand *nand)
1729 struct nand_chip *chip = &nand->base;
1730 struct mtd_info *mtd = nand_to_mtd(chip);
1733 /* No card inserted, skip this NAND. */
1734 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1735 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1739 nc->caps->ops->nand_init(nc, nand);
1741 ret = nand_scan(chip, nand->numcs);
1743 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1747 ret = mtd_device_register(mtd, NULL, 0);
1749 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1754 list_add_tail(&nand->node, &nc->chips);
1760 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1762 struct atmel_nand *nand, *tmp;
1765 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1766 ret = atmel_nand_controller_remove_nand(nand);
1775 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1777 struct device *dev = nc->dev;
1778 struct platform_device *pdev = to_platform_device(dev);
1779 struct atmel_nand *nand;
1780 struct gpio_desc *gpio;
1781 struct resource *res;
1784 * Legacy bindings only allow connecting a single NAND with a unique CS
1785 * line to the controller.
1787 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1795 nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1796 if (IS_ERR(nand->cs[0].io.virt))
1797 return PTR_ERR(nand->cs[0].io.virt);
1799 nand->cs[0].io.dma = res->start;
1802 * The old driver was hardcoding the CS id to 3 for all sama5
1803 * controllers. Since this id is only meaningful for the sama5
1804 * controller we can safely assign this id to 3 no matter the
1806 * If one wants to connect a NAND to a different CS line, he will
1807 * have to use the new bindings.
1812 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);
1814 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1816 return PTR_ERR(gpio);
1820 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1821 nand->cs[0].rb.gpio = gpio;
1825 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1827 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1829 return PTR_ERR(gpio);
1832 nand->cs[0].csgpio = gpio;
1834 /* Card detect GPIO. */
1835 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1838 "Failed to get detect gpio (err = %ld)\n",
1840 return PTR_ERR(gpio);
1843 nand->cdgpio = gpio;
1845 nand_set_flash_node(&nand->base, nc->dev->of_node);
1847 return atmel_nand_controller_add_nand(nc, nand);
1850 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1852 struct device_node *np, *nand_np;
1853 struct device *dev = nc->dev;
1857 /* We do not retrieve the SMC syscon when parsing old DTs. */
1858 if (nc->caps->legacy_of_bindings)
1859 return atmel_nand_controller_legacy_add_nands(nc);
1863 ret = of_property_read_u32(np, "#address-cells", &val);
1865 dev_err(dev, "missing #address-cells property\n");
1871 ret = of_property_read_u32(np, "#size-cells", &val);
1873 dev_err(dev, "missing #size-cells property\n");
1879 for_each_child_of_node(np, nand_np) {
1880 struct atmel_nand *nand;
1882 nand = atmel_nand_create(nc, nand_np, reg_cells);
1884 ret = PTR_ERR(nand);
1888 ret = atmel_nand_controller_add_nand(nc, nand);
1896 atmel_nand_controller_remove_nands(nc);
1901 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1904 dma_release_channel(nc->dmac);
1909 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1910 .offs = AT91SAM9260_MATRIX_EBICSA,
1913 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1914 .offs = AT91SAM9261_MATRIX_EBICSA,
1917 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1918 .offs = AT91SAM9263_MATRIX_EBI0CSA,
1921 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1922 .offs = AT91SAM9RL_MATRIX_EBICSA,
1925 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1926 .offs = AT91SAM9G45_MATRIX_EBICSA,
1929 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1930 .offs = AT91SAM9N12_MATRIX_EBICSA,
1933 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1934 .offs = AT91SAM9X5_MATRIX_EBICSA,
1937 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1938 .offs = AT91_SFR_CCFG_EBICSA,
1939 .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1942 static const struct of_device_id __maybe_unused atmel_ebi_csa_regmap_of_ids[] = {
1944 .compatible = "atmel,at91sam9260-matrix",
1945 .data = &at91sam9260_ebi_csa,
1948 .compatible = "atmel,at91sam9261-matrix",
1949 .data = &at91sam9261_ebi_csa,
1952 .compatible = "atmel,at91sam9263-matrix",
1953 .data = &at91sam9263_ebi_csa,
1956 .compatible = "atmel,at91sam9rl-matrix",
1957 .data = &at91sam9rl_ebi_csa,
1960 .compatible = "atmel,at91sam9g45-matrix",
1961 .data = &at91sam9g45_ebi_csa,
1964 .compatible = "atmel,at91sam9n12-matrix",
1965 .data = &at91sam9n12_ebi_csa,
1968 .compatible = "atmel,at91sam9x5-matrix",
1969 .data = &at91sam9x5_ebi_csa,
1972 .compatible = "microchip,sam9x60-sfr",
1973 .data = &sam9x60_ebi_csa,
1978 static int atmel_nand_attach_chip(struct nand_chip *chip)
1980 struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1981 struct atmel_nand *nand = to_atmel_nand(chip);
1982 struct mtd_info *mtd = nand_to_mtd(chip);
1985 ret = nc->caps->ops->ecc_init(chip);
1989 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1991 * We keep the MTD name unchanged to avoid breaking platforms
1992 * where the MTD cmdline parser is used and the bootloader
1993 * has not been updated to use the new naming scheme.
1995 mtd->name = "atmel_nand";
1996 } else if (!mtd->name) {
1998 * If the new bindings are used and the bootloader has not been
1999 * updated to pass a new mtdparts parameter on the cmdline, you
2000 * should define the following property in your nand node:
2002 * label = "atmel_nand";
2004 * This way, mtd->name will be set by the core when
2005 * nand_set_flash_node() is called.
2007 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
2008 "%s:nand.%d", dev_name(nc->dev),
2011 dev_err(nc->dev, "Failed to allocate mtd->name\n");
2019 static const struct nand_controller_ops atmel_nand_controller_ops = {
2020 .attach_chip = atmel_nand_attach_chip,
2021 .setup_interface = atmel_nand_setup_interface,
2022 .exec_op = atmel_nand_exec_op,
2025 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
2026 struct platform_device *pdev,
2027 const struct atmel_nand_controller_caps *caps)
2029 struct device *dev = &pdev->dev;
2030 struct device_node *np = dev->of_node;
2033 nand_controller_init(&nc->base);
2034 nc->base.ops = &atmel_nand_controller_ops;
2035 INIT_LIST_HEAD(&nc->chips);
2039 platform_set_drvdata(pdev, nc);
2041 nc->pmecc = devm_atmel_pmecc_get(dev);
2042 if (IS_ERR(nc->pmecc))
2043 return dev_err_probe(dev, PTR_ERR(nc->pmecc),
2044 "Could not get PMECC object\n");
2046 if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
2047 dma_cap_mask_t mask;
2050 dma_cap_set(DMA_MEMCPY, mask);
2052 nc->dmac = dma_request_channel(mask, NULL, NULL);
2054 dev_err(nc->dev, "Failed to request DMA channel\n");
2057 /* We do not retrieve the SMC syscon when parsing old DTs. */
2058 if (nc->caps->legacy_of_bindings)
2061 nc->mck = of_clk_get(dev->parent->of_node, 0);
2062 if (IS_ERR(nc->mck)) {
2063 dev_err(dev, "Failed to retrieve MCK clk\n");
2064 ret = PTR_ERR(nc->mck);
2065 goto out_release_dma;
2068 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2070 dev_err(dev, "Missing or invalid atmel,smc property\n");
2072 goto out_release_dma;
2075 nc->smc = syscon_node_to_regmap(np);
2077 if (IS_ERR(nc->smc)) {
2078 ret = PTR_ERR(nc->smc);
2079 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2080 goto out_release_dma;
2087 dma_release_channel(nc->dmac);
2093 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2095 struct device *dev = nc->base.dev;
2096 const struct of_device_id *match;
2097 struct device_node *np;
2100 /* We do not retrieve the EBICSA regmap when parsing old DTs. */
2101 if (nc->base.caps->legacy_of_bindings)
2104 np = of_parse_phandle(dev->parent->of_node,
2105 nc->base.caps->ebi_csa_regmap_name, 0);
2109 match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
2115 nc->ebi_csa_regmap = syscon_node_to_regmap(np);
2117 if (IS_ERR(nc->ebi_csa_regmap)) {
2118 ret = PTR_ERR(nc->ebi_csa_regmap);
2119 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
2123 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
2126 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2127 * add 4 to ->ebi_csa->offs.
2129 if (of_device_is_compatible(dev->parent->of_node,
2130 "atmel,at91sam9263-ebi1"))
2131 nc->ebi_csa->offs += 4;
2137 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2139 struct regmap_config regmap_conf = {
2145 struct device *dev = nc->base.dev;
2146 struct device_node *nand_np, *nfc_np;
2147 void __iomem *iomem;
2148 struct resource res;
2151 nand_np = dev->of_node;
2152 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2154 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2158 nc->clk = of_clk_get(nfc_np, 0);
2159 if (IS_ERR(nc->clk)) {
2160 ret = PTR_ERR(nc->clk);
2161 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2166 ret = clk_prepare_enable(nc->clk);
2168 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2173 nc->irq = of_irq_get(nand_np, 0);
2175 ret = nc->irq ?: -ENXIO;
2176 if (ret != -EPROBE_DEFER)
2177 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2182 ret = of_address_to_resource(nfc_np, 0, &res);
2184 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2189 iomem = devm_ioremap_resource(dev, &res);
2190 if (IS_ERR(iomem)) {
2191 ret = PTR_ERR(iomem);
2195 regmap_conf.name = "nfc-io";
2196 regmap_conf.max_register = resource_size(&res) - 4;
2197 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf);
2198 if (IS_ERR(nc->io)) {
2199 ret = PTR_ERR(nc->io);
2200 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2205 ret = of_address_to_resource(nfc_np, 1, &res);
2207 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2212 iomem = devm_ioremap_resource(dev, &res);
2213 if (IS_ERR(iomem)) {
2214 ret = PTR_ERR(iomem);
2218 regmap_conf.name = "smc";
2219 regmap_conf.max_register = resource_size(&res) - 4;
2220 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf);
2221 if (IS_ERR(nc->base.smc)) {
2222 ret = PTR_ERR(nc->base.smc);
2223 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2228 ret = of_address_to_resource(nfc_np, 2, &res);
2230 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2235 nc->sram.virt = devm_ioremap_resource(dev, &res);
2236 if (IS_ERR(nc->sram.virt)) {
2237 ret = PTR_ERR(nc->sram.virt);
2241 nc->sram.dma = res.start;
2244 of_node_put(nfc_np);
2250 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2252 struct device *dev = nc->base.dev;
2253 struct device_node *np;
2256 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2258 dev_err(dev, "Missing or invalid atmel,smc property\n");
2262 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2264 nc->irq = of_irq_get(np, 0);
2267 ret = nc->irq ?: -ENXIO;
2268 if (ret != -EPROBE_DEFER)
2269 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2274 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2276 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2280 nc->io = syscon_node_to_regmap(np);
2282 if (IS_ERR(nc->io)) {
2283 ret = PTR_ERR(nc->io);
2284 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2288 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2289 "atmel,nfc-sram", 0);
2290 if (!nc->sram.pool) {
2291 dev_err(nc->base.dev, "Missing SRAM\n");
2295 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2296 ATMEL_NFC_SRAM_SIZE,
2298 if (!nc->sram.virt) {
2299 dev_err(nc->base.dev,
2300 "Could not allocate memory from the NFC SRAM pool\n");
2308 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2310 struct atmel_hsmc_nand_controller *hsmc_nc;
2313 ret = atmel_nand_controller_remove_nands(nc);
2317 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2318 regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2319 ATMEL_HSMC_NFC_CTRL_DIS);
2321 if (hsmc_nc->sram.pool)
2322 gen_pool_free(hsmc_nc->sram.pool,
2323 (unsigned long)hsmc_nc->sram.virt,
2324 ATMEL_NFC_SRAM_SIZE);
2327 clk_disable_unprepare(hsmc_nc->clk);
2328 clk_put(hsmc_nc->clk);
2331 atmel_nand_controller_cleanup(nc);
2336 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2337 const struct atmel_nand_controller_caps *caps)
2339 struct device *dev = &pdev->dev;
2340 struct atmel_hsmc_nand_controller *nc;
2343 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2347 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2351 if (caps->legacy_of_bindings)
2352 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2354 ret = atmel_hsmc_nand_controller_init(nc);
2359 /* Make sure all irqs are masked before registering our IRQ handler. */
2360 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2361 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2362 IRQF_SHARED, "nfc", nc);
2365 "Could not get register NFC interrupt handler (err = %d)\n",
2370 /* Initial NFC configuration. */
2371 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2372 ATMEL_HSMC_NFC_CFG_DTO_MAX);
2373 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2374 ATMEL_HSMC_NFC_CTRL_EN);
2376 ret = atmel_nand_controller_add_nands(&nc->base);
2383 atmel_hsmc_nand_controller_remove(&nc->base);
2388 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2389 .probe = atmel_hsmc_nand_controller_probe,
2390 .remove = atmel_hsmc_nand_controller_remove,
2391 .ecc_init = atmel_hsmc_nand_ecc_init,
2392 .nand_init = atmel_nand_init,
2393 .setup_interface = atmel_hsmc_nand_setup_interface,
2394 .exec_op = atmel_hsmc_nand_exec_op,
2397 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2399 .ale_offs = BIT(21),
2400 .cle_offs = BIT(22),
2401 .ops = &atmel_hsmc_nc_ops,
2404 /* Only used to parse old bindings. */
2405 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2407 .ale_offs = BIT(21),
2408 .cle_offs = BIT(22),
2409 .ops = &atmel_hsmc_nc_ops,
2410 .legacy_of_bindings = true,
2413 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2414 const struct atmel_nand_controller_caps *caps)
2416 struct device *dev = &pdev->dev;
2417 struct atmel_smc_nand_controller *nc;
2420 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2424 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2428 ret = atmel_smc_nand_controller_init(nc);
2432 return atmel_nand_controller_add_nands(&nc->base);
2436 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2440 ret = atmel_nand_controller_remove_nands(nc);
2444 atmel_nand_controller_cleanup(nc);
2450 * The SMC reg layout of at91rm9200 is completely different which prevents us
2451 * from re-using atmel_smc_nand_setup_interface() for the
2452 * ->setup_interface() hook.
2453 * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2454 * ->setup_interface() unassigned.
2456 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2457 .probe = atmel_smc_nand_controller_probe,
2458 .remove = atmel_smc_nand_controller_remove,
2459 .ecc_init = atmel_nand_ecc_init,
2460 .nand_init = atmel_smc_nand_init,
2461 .exec_op = atmel_smc_nand_exec_op,
2464 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2465 .ale_offs = BIT(21),
2466 .cle_offs = BIT(22),
2467 .ebi_csa_regmap_name = "atmel,matrix",
2468 .ops = &at91rm9200_nc_ops,
2471 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2472 .probe = atmel_smc_nand_controller_probe,
2473 .remove = atmel_smc_nand_controller_remove,
2474 .ecc_init = atmel_nand_ecc_init,
2475 .nand_init = atmel_smc_nand_init,
2476 .setup_interface = atmel_smc_nand_setup_interface,
2477 .exec_op = atmel_smc_nand_exec_op,
2480 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2481 .ale_offs = BIT(21),
2482 .cle_offs = BIT(22),
2483 .ebi_csa_regmap_name = "atmel,matrix",
2484 .ops = &atmel_smc_nc_ops,
2487 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2488 .ale_offs = BIT(22),
2489 .cle_offs = BIT(21),
2490 .ebi_csa_regmap_name = "atmel,matrix",
2491 .ops = &atmel_smc_nc_ops,
2494 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2496 .ale_offs = BIT(21),
2497 .cle_offs = BIT(22),
2498 .ebi_csa_regmap_name = "atmel,matrix",
2499 .ops = &atmel_smc_nc_ops,
2502 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2504 .ale_offs = BIT(21),
2505 .cle_offs = BIT(22),
2506 .ebi_csa_regmap_name = "microchip,sfr",
2507 .ops = &atmel_smc_nc_ops,
2510 /* Only used to parse old bindings. */
2511 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2512 .ale_offs = BIT(21),
2513 .cle_offs = BIT(22),
2514 .ops = &atmel_smc_nc_ops,
2515 .legacy_of_bindings = true,
2518 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2519 .ale_offs = BIT(22),
2520 .cle_offs = BIT(21),
2521 .ops = &atmel_smc_nc_ops,
2522 .legacy_of_bindings = true,
2525 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2527 .ale_offs = BIT(21),
2528 .cle_offs = BIT(22),
2529 .ops = &atmel_smc_nc_ops,
2530 .legacy_of_bindings = true,
2533 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2535 .compatible = "atmel,at91rm9200-nand-controller",
2536 .data = &atmel_rm9200_nc_caps,
2539 .compatible = "atmel,at91sam9260-nand-controller",
2540 .data = &atmel_sam9260_nc_caps,
2543 .compatible = "atmel,at91sam9261-nand-controller",
2544 .data = &atmel_sam9261_nc_caps,
2547 .compatible = "atmel,at91sam9g45-nand-controller",
2548 .data = &atmel_sam9g45_nc_caps,
2551 .compatible = "atmel,sama5d3-nand-controller",
2552 .data = &atmel_sama5_nc_caps,
2555 .compatible = "microchip,sam9x60-nand-controller",
2556 .data = µchip_sam9x60_nc_caps,
2558 /* Support for old/deprecated bindings: */
2560 .compatible = "atmel,at91rm9200-nand",
2561 .data = &atmel_rm9200_nand_caps,
2564 .compatible = "atmel,sama5d4-nand",
2565 .data = &atmel_rm9200_nand_caps,
2568 .compatible = "atmel,sama5d2-nand",
2569 .data = &atmel_rm9200_nand_caps,
2573 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2575 static int atmel_nand_controller_probe(struct platform_device *pdev)
2577 const struct atmel_nand_controller_caps *caps;
2580 caps = (void *)pdev->id_entry->driver_data;
2582 caps = of_device_get_match_data(&pdev->dev);
2585 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2589 if (caps->legacy_of_bindings) {
2590 struct device_node *nfc_node;
2594 * If we are parsing legacy DT props and the DT contains a
2595 * valid NFC node, forward the request to the sama5 logic.
2597 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2598 "atmel,sama5d3-nfc");
2600 caps = &atmel_sama5_nand_caps;
2601 of_node_put(nfc_node);
2605 * Even if the compatible says we are dealing with an
2606 * at91rm9200 controller, the atmel,nand-has-dma specify that
2607 * this controller supports DMA, which means we are in fact
2608 * dealing with an at91sam9g45+ controller.
2610 if (!caps->has_dma &&
2611 of_property_read_bool(pdev->dev.of_node,
2612 "atmel,nand-has-dma"))
2613 caps = &atmel_sam9g45_nand_caps;
2616 * All SoCs except the at91sam9261 are assigning ALE to A21 and
2617 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2618 * actually dealing with an at91sam9261 controller.
2620 of_property_read_u32(pdev->dev.of_node,
2621 "atmel,nand-addr-offset", &ale_offs);
2623 caps = &atmel_sam9261_nand_caps;
2626 return caps->ops->probe(pdev, caps);
2629 static void atmel_nand_controller_remove(struct platform_device *pdev)
2631 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2633 WARN_ON(nc->caps->ops->remove(nc));
2636 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2638 struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2639 struct atmel_nand *nand;
2642 atmel_pmecc_reset(nc->pmecc);
2644 list_for_each_entry(nand, &nc->chips, node) {
2647 for (i = 0; i < nand->numcs; i++)
2648 nand_reset(&nand->base, i);
2654 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2655 atmel_nand_controller_resume);
2657 static struct platform_driver atmel_nand_controller_driver = {
2659 .name = "atmel-nand-controller",
2660 .of_match_table = atmel_nand_controller_of_ids,
2661 .pm = &atmel_nand_controller_pm_ops,
2663 .probe = atmel_nand_controller_probe,
2664 .remove_new = atmel_nand_controller_remove,
2666 module_platform_driver(atmel_nand_controller_driver);
2668 MODULE_LICENSE("GPL");
2669 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2670 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2671 MODULE_ALIAS("platform:atmel-nand-controller");