drivers/mtd/nand/raw/atmel/nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2017 ATMEL
   4  * Copyright 2017 Free Electrons
   5  *
   6  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   7  *
   8  * Derived from the atmel_nand.c driver which contained the following
   9  * copyrights:
  10  *
  11  *   Copyright 2003 Rick Bronson
  12  *
  13  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  14  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  15  *
  16  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  17  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  18  *
  19  *
  20  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  21  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  22  *
  23  *   Derived from Das U-Boot source code
  24  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  25  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  26  *
  27  *   Add Programmable Multibit ECC support for various AT91 SoC
  28  *      Copyright 2012 ATMEL, Hong Xu
  29  *
  30  *   Add Nand Flash Controller support for SAMA5 SoC
  31  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  32  *
  33  * A few words about the naming convention in this file. This convention
  34  * applies to structure and function names.
  35  *
  36  * Prefixes:
  37  *
  38  * - atmel_nand_: all generic structures/functions
  39  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  40  *                    (at91sam9 and avr32 SoCs)
  41  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  42  *                     (sama5 SoCs and later)
  43  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  44  *               that is available in the HSMC block
  45  * - <soc>_nand_: all SoC specific structures/functions
  46  */
  47
  48 #include <linux/clk.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/genalloc.h>
  52 #include <linux/gpio/consumer.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/mfd/syscon.h>
  55 #include <linux/mfd/syscon/atmel-matrix.h>
  56 #include <linux/mfd/syscon/atmel-smc.h>
  57 #include <linux/module.h>
  58 #include <linux/mtd/rawnand.h>
  59 #include <linux/of_address.h>
  60 #include <linux/of_irq.h>
  61 #include <linux/of_platform.h>
  62 #include <linux/iopoll.h>
  63 #include <linux/platform_device.h>
  64 #include <linux/regmap.h>
  65 #include <soc/at91/atmel-sfr.h>
  66
  67 #include "pmecc.h"
  68
  69 #define ATMEL_HSMC_NFC_CFG                      0x0
  70 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  71 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  72 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  73 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  74 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  75 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  76 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  77 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  78 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  80
  81 #define ATMEL_HSMC_NFC_CTRL                     0x4
  82 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  83 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  84
  85 #define ATMEL_HSMC_NFC_SR                       0x8
  86 #define ATMEL_HSMC_NFC_IER                      0xc
  87 #define ATMEL_HSMC_NFC_IDR                      0x10
  88 #define ATMEL_HSMC_NFC_IMR                      0x14
  89 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  90 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  91 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  92 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  93 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
  94 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
  95 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
  96 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
  97 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
  98 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
  99 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 100 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 101 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 102                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 103                                                  ATMEL_HSMC_NFC_SR_AWB | \
 104                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 105 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 106
 107 #define ATMEL_HSMC_NFC_ADDR                     0x18
 108 #define ATMEL_HSMC_NFC_BANK                     0x1c
 109
 110 #define ATMEL_NFC_MAX_RB_ID                     7
 111
 112 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 113
 114 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 115 #define ATMEL_NFC_VCMD2                         BIT(18)
 116 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 117 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 118 #define ATMEL_NFC_DATAEN                        BIT(25)
 119 #define ATMEL_NFC_NFCWR                         BIT(26)
 120
 121 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 122
 123 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 124 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 125
 126 #define DEFAULT_TIMEOUT_MS                      1000
 127 #define MIN_DMA_LEN                             128
 128
 129 static bool atmel_nand_avoid_dma __read_mostly;
 130
 131 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
 132 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
 133
 134 enum atmel_nand_rb_type {
 135         ATMEL_NAND_NO_RB,
 136         ATMEL_NAND_NATIVE_RB,
 137         ATMEL_NAND_GPIO_RB,
 138 };
 139
 140 struct atmel_nand_rb {
 141         enum atmel_nand_rb_type type;
 142         union {
 143                 struct gpio_desc *gpio;
 144                 int id;
 145         };
 146 };
 147
 148 struct atmel_nand_cs {
 149         int id;
 150         struct atmel_nand_rb rb;
 151         struct gpio_desc *csgpio;
 152         struct {
 153                 void __iomem *virt;
 154                 dma_addr_t dma;
 155         } io;
 156
 157         struct atmel_smc_cs_conf smcconf;
 158 };
 159
 160 struct atmel_nand {
 161         struct list_head node;
 162         struct device *dev;
 163         struct nand_chip base;
 164         struct atmel_nand_cs *activecs;
 165         struct atmel_pmecc_user *pmecc;
 166         struct gpio_desc *cdgpio;
 167         int numcs;
 168         struct atmel_nand_cs cs[];
 169 };
 170
 171 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 172 {
 173         return container_of(chip, struct atmel_nand, base);
 174 }
 175
 176 enum atmel_nfc_data_xfer {
 177         ATMEL_NFC_NO_DATA,
 178         ATMEL_NFC_READ_DATA,
 179         ATMEL_NFC_WRITE_DATA,
 180 };
 181
 182 struct atmel_nfc_op {
 183         u8 cs;
 184         u8 ncmds;
 185         u8 cmds[2];
 186         u8 naddrs;
 187         u8 addrs[5];
 188         enum atmel_nfc_data_xfer data;
 189         u32 wait;
 190         u32 errors;
 191 };
 192
 193 struct atmel_nand_controller;
 194 struct atmel_nand_controller_caps;
 195
 196 struct atmel_nand_controller_ops {
 197         int (*probe)(struct platform_device *pdev,
 198                      const struct atmel_nand_controller_caps *caps);
 199         int (*remove)(struct atmel_nand_controller *nc);
 200         void (*nand_init)(struct atmel_nand_controller *nc,
 201                           struct atmel_nand *nand);
 202         int (*ecc_init)(struct nand_chip *chip);
 203         int (*setup_interface)(struct atmel_nand *nand, int csline,
 204                                const struct nand_interface_config *conf);
 205         int (*exec_op)(struct atmel_nand *nand,
 206                        const struct nand_operation *op, bool check_only);
 207 };
 208
 209 struct atmel_nand_controller_caps {
 210         bool has_dma;
 211         bool legacy_of_bindings;
 212         u32 ale_offs;
 213         u32 cle_offs;
 214         const char *ebi_csa_regmap_name;
 215         const struct atmel_nand_controller_ops *ops;
 216 };
 217
 218 struct atmel_nand_controller {
 219         struct nand_controller base;
 220         const struct atmel_nand_controller_caps *caps;
 221         struct device *dev;
 222         struct regmap *smc;
 223         struct dma_chan *dmac;
 224         struct atmel_pmecc *pmecc;
 225         struct list_head chips;
 226         struct clk *mck;
 227 };
 228
 229 static inline struct atmel_nand_controller *
 230 to_nand_controller(struct nand_controller *ctl)
 231 {
 232         return container_of(ctl, struct atmel_nand_controller, base);
 233 }
 234
 235 struct atmel_smc_nand_ebi_csa_cfg {
 236         u32 offs;
 237         u32 nfd0_on_d16;
 238 };
 239
 240 struct atmel_smc_nand_controller {
 241         struct atmel_nand_controller base;
 242         struct regmap *ebi_csa_regmap;
 243         struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
 244 };
 245
 246 static inline struct atmel_smc_nand_controller *
 247 to_smc_nand_controller(struct nand_controller *ctl)
 248 {
 249         return container_of(to_nand_controller(ctl),
 250                             struct atmel_smc_nand_controller, base);
 251 }
 252
 253 struct atmel_hsmc_nand_controller {
 254         struct atmel_nand_controller base;
 255         struct {
 256                 struct gen_pool *pool;
 257                 void __iomem *virt;
 258                 dma_addr_t dma;
 259         } sram;
 260         const struct atmel_hsmc_reg_layout *hsmc_layout;
 261         struct regmap *io;
 262         struct atmel_nfc_op op;
 263         struct completion complete;
 264         u32 cfg;
 265         int irq;
 266
 267         /* Only used when instantiating from legacy DT bindings. */
 268         struct clk *clk;
 269 };
 270
 271 static inline struct atmel_hsmc_nand_controller *
 272 to_hsmc_nand_controller(struct nand_controller *ctl)
 273 {
 274         return container_of(to_nand_controller(ctl),
 275                             struct atmel_hsmc_nand_controller, base);
 276 }
 277
 278 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 279 {
 280         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 281         op->wait ^= status & op->wait;
 282
 283         return !op->wait || op->errors;
 284 }
 285
 286 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
 287 {
 288         struct atmel_hsmc_nand_controller *nc = data;
 289         u32 sr, rcvd;
 290         bool done;
 291
 292         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
 293
 294         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 295         done = atmel_nfc_op_done(&nc->op, sr);
 296
 297         if (rcvd)
 298                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
 299
 300         if (done)
 301                 complete(&nc->complete);
 302
 303         return rcvd ? IRQ_HANDLED : IRQ_NONE;
 304 }
 305
 306 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 307                           unsigned int timeout_ms)
 308 {
 309         int ret;
 310
 311         if (!timeout_ms)
 312                 timeout_ms = DEFAULT_TIMEOUT_MS;
 313
 314         if (poll) {
 315                 u32 status;
 316
 317                 ret = regmap_read_poll_timeout(nc->base.smc,
 318                                                ATMEL_HSMC_NFC_SR, status,
 319                                                atmel_nfc_op_done(&nc->op,
 320                                                                  status),
 321                                                0, timeout_ms * 1000);
 322         } else {
 323                 init_completion(&nc->complete);
 324                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
 325                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 326                 ret = wait_for_completion_timeout(&nc->complete,
 327                                                 msecs_to_jiffies(timeout_ms));
 328                 if (!ret)
 329                         ret = -ETIMEDOUT;
 330                 else
 331                         ret = 0;
 332
 333                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
 334         }
 335
 336         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 337                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 338                 ret = -ETIMEDOUT;
 339         }
 340
 341         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 342                 dev_err(nc->base.dev, "Access to an undefined area\n");
 343                 ret = -EIO;
 344         }
 345
 346         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 347                 dev_err(nc->base.dev, "Access while busy\n");
 348                 ret = -EIO;
 349         }
 350
 351         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 352                 dev_err(nc->base.dev, "Wrong access size\n");
 353                 ret = -EIO;
 354         }
 355
 356         return ret;
 357 }
 358
 359 static void atmel_nand_dma_transfer_finished(void *data)
 360 {
 361         struct completion *finished = data;
 362
 363         complete(finished);
 364 }
 365
 366 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
 367                                    void *buf, dma_addr_t dev_dma, size_t len,
 368                                    enum dma_data_direction dir)
 369 {
 370         DECLARE_COMPLETION_ONSTACK(finished);
 371         dma_addr_t src_dma, dst_dma, buf_dma;
 372         struct dma_async_tx_descriptor *tx;
 373         dma_cookie_t cookie;
 374
 375         buf_dma = dma_map_single(nc->dev, buf, len, dir);
 376         if (dma_mapping_error(nc->dev, dev_dma)) {
 377                 dev_err(nc->dev,
 378                         "Failed to prepare a buffer for DMA access\n");
 379                 goto err;
 380         }
 381
 382         if (dir == DMA_FROM_DEVICE) {
 383                 src_dma = dev_dma;
 384                 dst_dma = buf_dma;
 385         } else {
 386                 src_dma = buf_dma;
 387                 dst_dma = dev_dma;
 388         }
 389
 390         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
 391                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 392         if (!tx) {
 393                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
 394                 goto err_unmap;
 395         }
 396
 397         tx->callback = atmel_nand_dma_transfer_finished;
 398         tx->callback_param = &finished;
 399
 400         cookie = dmaengine_submit(tx);
 401         if (dma_submit_error(cookie)) {
 402                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
 403                 goto err_unmap;
 404         }
 405
 406         dma_async_issue_pending(nc->dmac);
 407         wait_for_completion(&finished);
 408         dma_unmap_single(nc->dev, buf_dma, len, dir);
 409
 410         return 0;
 411
 412 err_unmap:
 413         dma_unmap_single(nc->dev, buf_dma, len, dir);
 414
 415 err:
 416         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
 417
 418         return -EIO;
 419 }
 420
 421 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 422 {
 423         u8 *addrs = nc->op.addrs;
 424         unsigned int op = 0;
 425         u32 addr, val;
 426         int i, ret;
 427
 428         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 429
 430         for (i = 0; i < nc->op.ncmds; i++)
 431                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 432
 433         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 434                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 435
 436         op |= ATMEL_NFC_CSID(nc->op.cs) |
 437               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 438
 439         if (nc->op.ncmds > 1)
 440                 op |= ATMEL_NFC_VCMD2;
 441
 442         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 443                (addrs[3] << 24);
 444
 445         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 446                 op |= ATMEL_NFC_DATAEN;
 447                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 448
 449                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 450                         op |= ATMEL_NFC_NFCWR;
 451         }
 452
 453         /* Clear all flags. */
 454         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 455
 456         /* Send the command. */
 457         regmap_write(nc->io, op, addr);
 458
 459         ret = atmel_nfc_wait(nc, poll, 0);
 460         if (ret)
 461                 dev_err(nc->base.dev,
 462                         "Failed to send NAND command (err = %d)!",
 463                         ret);
 464
 465         /* Reset the op state. */
 466         memset(&nc->op, 0, sizeof(nc->op));
 467
 468         return ret;
 469 }
 470
 471 static void atmel_nand_data_in(struct atmel_nand *nand, void *buf,
 472                                unsigned int len, bool force_8bit)
 473 {
 474         struct atmel_nand_controller *nc;
 475
 476         nc = to_nand_controller(nand->base.controller);
 477
 478         /*
 479          * If the controller supports DMA, the buffer address is DMA-able and
 480          * len is long enough to make DMA transfers profitable, let's trigger
 481          * a DMA transfer. If it fails, fallback to PIO mode.
 482          */
 483         if (nc->dmac && virt_addr_valid(buf) &&
 484             len >= MIN_DMA_LEN && !force_8bit &&
 485             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
 486                                      DMA_FROM_DEVICE))
 487                 return;
 488
 489         if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
 490                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 491         else
 492                 ioread8_rep(nand->activecs->io.virt, buf, len);
 493 }
 494
 495 static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf,
 496                                 unsigned int len, bool force_8bit)
 497 {
 498         struct atmel_nand_controller *nc;
 499
 500         nc = to_nand_controller(nand->base.controller);
 501
 502         /*
 503          * If the controller supports DMA, the buffer address is DMA-able and
 504          * len is long enough to make DMA transfers profitable, let's trigger
 505          * a DMA transfer. If it fails, fallback to PIO mode.
 506          */
 507         if (nc->dmac && virt_addr_valid(buf) &&
 508             len >= MIN_DMA_LEN && !force_8bit &&
 509             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
 510                                      len, DMA_TO_DEVICE))
 511                 return;
 512
 513         if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
 514                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 515         else
 516                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 517 }
 518
 519 static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms)
 520 {
 521         if (nand->activecs->rb.type == ATMEL_NAND_NO_RB)
 522                 return nand_soft_waitrdy(&nand->base, timeout_ms);
 523
 524         return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio,
 525                                  timeout_ms);
 526 }
 527
 528 static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand,
 529                                    unsigned int timeout_ms)
 530 {
 531         struct atmel_hsmc_nand_controller *nc;
 532         u32 status, mask;
 533
 534         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
 535                 return atmel_nand_waitrdy(nand, timeout_ms);
 536
 537         nc = to_hsmc_nand_controller(nand->base.controller);
 538         mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 539         return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,
 540                                                status, status & mask,
 541                                                10, timeout_ms * 1000);
 542 }
 543
 544 static void atmel_nand_select_target(struct atmel_nand *nand,
 545                                      unsigned int cs)
 546 {
 547         nand->activecs = &nand->cs[cs];
 548 }
 549
 550 static void atmel_hsmc_nand_select_target(struct atmel_nand *nand,
 551                                           unsigned int cs)
 552 {
 553         struct mtd_info *mtd = nand_to_mtd(&nand->base);
 554         struct atmel_hsmc_nand_controller *nc;
 555         u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 556                   ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 557                   ATMEL_HSMC_NFC_CFG_RSPARE;
 558
 559         nand->activecs = &nand->cs[cs];
 560         nc = to_hsmc_nand_controller(nand->base.controller);
 561         if (nc->cfg == cfg)
 562                 return;
 563
 564         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 565                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 566                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 567                            ATMEL_HSMC_NFC_CFG_RSPARE |
 568                            ATMEL_HSMC_NFC_CFG_WSPARE,
 569                            cfg);
 570         nc->cfg = cfg;
 571 }
 572
 573 static int atmel_smc_nand_exec_instr(struct atmel_nand *nand,
 574                                      const struct nand_op_instr *instr)
 575 {
 576         struct atmel_nand_controller *nc;
 577         unsigned int i;
 578
 579         nc = to_nand_controller(nand->base.controller);
 580         switch (instr->type) {
 581         case NAND_OP_CMD_INSTR:
 582                 writeb(instr->ctx.cmd.opcode,
 583                        nand->activecs->io.virt + nc->caps->cle_offs);
 584                 return 0;
 585         case NAND_OP_ADDR_INSTR:
 586                 for (i = 0; i < instr->ctx.addr.naddrs; i++)
 587                         writeb(instr->ctx.addr.addrs[i],
 588                                nand->activecs->io.virt + nc->caps->ale_offs);
 589                 return 0;
 590         case NAND_OP_DATA_IN_INSTR:
 591                 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
 592                                    instr->ctx.data.len,
 593                                    instr->ctx.data.force_8bit);
 594                 return 0;
 595         case NAND_OP_DATA_OUT_INSTR:
 596                 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
 597                                     instr->ctx.data.len,
 598                                     instr->ctx.data.force_8bit);
 599                 return 0;
 600         case NAND_OP_WAITRDY_INSTR:
 601                 return atmel_nand_waitrdy(nand,
 602                                           instr->ctx.waitrdy.timeout_ms);
 603         default:
 604                 break;
 605         }
 606
 607         return -EINVAL;
 608 }
 609
 610 static int atmel_smc_nand_exec_op(struct atmel_nand *nand,
 611                                   const struct nand_operation *op,
 612                                   bool check_only)
 613 {
 614         unsigned int i;
 615         int ret = 0;
 616
 617         if (check_only)
 618                 return 0;
 619
 620         atmel_nand_select_target(nand, op->cs);
 621         gpiod_set_value(nand->activecs->csgpio, 0);
 622         for (i = 0; i < op->ninstrs; i++) {
 623                 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]);
 624                 if (ret)
 625                         break;
 626         }
 627         gpiod_set_value(nand->activecs->csgpio, 1);
 628
 629         return ret;
 630 }
 631
 632 static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip,
 633                                     const struct nand_subop *subop)
 634 {
 635         struct atmel_nand *nand = to_atmel_nand(chip);
 636         struct atmel_hsmc_nand_controller *nc;
 637         unsigned int i, j;
 638
 639         nc = to_hsmc_nand_controller(chip->controller);
 640
 641         nc->op.cs = nand->activecs->id;
 642         for (i = 0; i < subop->ninstrs; i++) {
 643                 const struct nand_op_instr *instr = &subop->instrs[i];
 644
 645                 if (instr->type == NAND_OP_CMD_INSTR) {
 646                         nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;
 647                         continue;
 648                 }
 649
 650                 for (j = nand_subop_get_addr_start_off(subop, i);
 651                      j < nand_subop_get_num_addr_cyc(subop, i); j++) {
 652                         nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];
 653                         nc->op.naddrs++;
 654                 }
 655         }
 656
 657         return atmel_nfc_exec_op(nc, true);
 658 }
 659
 660 static int atmel_hsmc_exec_rw(struct nand_chip *chip,
 661                               const struct nand_subop *subop)
 662 {
 663         const struct nand_op_instr *instr = subop->instrs;
 664         struct atmel_nand *nand = to_atmel_nand(chip);
 665
 666         if (instr->type == NAND_OP_DATA_IN_INSTR)
 667                 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
 668                                    instr->ctx.data.len,
 669                                    instr->ctx.data.force_8bit);
 670         else
 671                 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
 672                                     instr->ctx.data.len,
 673                                     instr->ctx.data.force_8bit);
 674
 675         return 0;
 676 }
 677
 678 static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip,
 679                                    const struct nand_subop *subop)
 680 {
 681         const struct nand_op_instr *instr = subop->instrs;
 682         struct atmel_nand *nand = to_atmel_nand(chip);
 683
 684         return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms);
 685 }
 686
 687 static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER(
 688         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr,
 689                 NAND_OP_PARSER_PAT_CMD_ELEM(true),
 690                 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
 691                 NAND_OP_PARSER_PAT_CMD_ELEM(true)),
 692         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
 693                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)),
 694         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
 695                 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)),
 696         NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy,
 697                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 698 );
 699
 700 static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand,
 701                                    const struct nand_operation *op,
 702                                    bool check_only)
 703 {
 704         int ret;
 705
 706         if (check_only)
 707                 return nand_op_parser_exec_op(&nand->base,
 708                                               &atmel_hsmc_op_parser, op, true);
 709
 710         atmel_hsmc_nand_select_target(nand, op->cs);
 711         ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op,
 712                                      false);
 713
 714         return ret;
 715 }
 716
 717 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 718                                    bool oob_required)
 719 {
 720         struct mtd_info *mtd = nand_to_mtd(chip);
 721         struct atmel_hsmc_nand_controller *nc;
 722         int ret = -EIO;
 723
 724         nc = to_hsmc_nand_controller(chip->controller);
 725
 726         if (nc->base.dmac)
 727                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
 728                                               nc->sram.dma, mtd->writesize,
 729                                               DMA_TO_DEVICE);
 730
 731         /* Falling back to CPU copy. */
 732         if (ret)
 733                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 734
 735         if (oob_required)
 736                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 737                             mtd->oobsize);
 738 }
 739
 740 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 741                                      bool oob_required)
 742 {
 743         struct mtd_info *mtd = nand_to_mtd(chip);
 744         struct atmel_hsmc_nand_controller *nc;
 745         int ret = -EIO;
 746
 747         nc = to_hsmc_nand_controller(chip->controller);
 748
 749         if (nc->base.dmac)
 750                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
 751                                               mtd->writesize, DMA_FROM_DEVICE);
 752
 753         /* Falling back to CPU copy. */
 754         if (ret)
 755                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 756
 757         if (oob_required)
 758                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 759                               mtd->oobsize);
 760 }
 761
 762 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 763 {
 764         struct mtd_info *mtd = nand_to_mtd(chip);
 765         struct atmel_hsmc_nand_controller *nc;
 766
 767         nc = to_hsmc_nand_controller(chip->controller);
 768
 769         if (column >= 0) {
 770                 nc->op.addrs[nc->op.naddrs++] = column;
 771
 772                 /*
 773                  * 2 address cycles for the column offset on large page NANDs.
 774                  */
 775                 if (mtd->writesize > 512)
 776                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 777         }
 778
 779         if (page >= 0) {
 780                 nc->op.addrs[nc->op.naddrs++] = page;
 781                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 782
 783                 if (chip->options & NAND_ROW_ADDR_3)
 784                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 785         }
 786 }
 787
 788 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 789 {
 790         struct atmel_nand *nand = to_atmel_nand(chip);
 791         struct atmel_nand_controller *nc;
 792         int ret;
 793
 794         nc = to_nand_controller(chip->controller);
 795
 796         if (raw)
 797                 return 0;
 798
 799         ret = atmel_pmecc_enable(nand->pmecc, op);
 800         if (ret)
 801                 dev_err(nc->dev,
 802                         "Failed to enable ECC engine (err = %d)\n", ret);
 803
 804         return ret;
 805 }
 806
 807 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 808 {
 809         struct atmel_nand *nand = to_atmel_nand(chip);
 810
 811         if (!raw)
 812                 atmel_pmecc_disable(nand->pmecc);
 813 }
 814
 815 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 816 {
 817         struct atmel_nand *nand = to_atmel_nand(chip);
 818         struct mtd_info *mtd = nand_to_mtd(chip);
 819         struct atmel_nand_controller *nc;
 820         struct mtd_oob_region oobregion;
 821         void *eccbuf;
 822         int ret, i;
 823
 824         nc = to_nand_controller(chip->controller);
 825
 826         if (raw)
 827                 return 0;
 828
 829         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 830         if (ret) {
 831                 dev_err(nc->dev,
 832                         "Failed to transfer NAND page data (err = %d)\n",
 833                         ret);
 834                 return ret;
 835         }
 836
 837         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 838         eccbuf = chip->oob_poi + oobregion.offset;
 839
 840         for (i = 0; i < chip->ecc.steps; i++) {
 841                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 842                                                    eccbuf);
 843                 eccbuf += chip->ecc.bytes;
 844         }
 845
 846         return 0;
 847 }
 848
 849 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 850                                          bool raw)
 851 {
 852         struct atmel_nand *nand = to_atmel_nand(chip);
 853         struct mtd_info *mtd = nand_to_mtd(chip);
 854         struct atmel_nand_controller *nc;
 855         struct mtd_oob_region oobregion;
 856         int ret, i, max_bitflips = 0;
 857         void *databuf, *eccbuf;
 858
 859         nc = to_nand_controller(chip->controller);
 860
 861         if (raw)
 862                 return 0;
 863
 864         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 865         if (ret) {
 866                 dev_err(nc->dev,
 867                         "Failed to read NAND page data (err = %d)\n",
 868                         ret);
 869                 return ret;
 870         }
 871
 872         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 873         eccbuf = chip->oob_poi + oobregion.offset;
 874         databuf = buf;
 875
 876         for (i = 0; i < chip->ecc.steps; i++) {
 877                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 878                                                  eccbuf);
 879                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 880                         ret = nand_check_erased_ecc_chunk(databuf,
 881                                                           chip->ecc.size,
 882                                                           eccbuf,
 883                                                           chip->ecc.bytes,
 884                                                           NULL, 0,
 885                                                           chip->ecc.strength);
 886
 887                 if (ret >= 0) {
 888                         mtd->ecc_stats.corrected += ret;
 889                         max_bitflips = max(ret, max_bitflips);
 890                 } else {
 891                         mtd->ecc_stats.failed++;
 892                 }
 893
 894                 databuf += chip->ecc.size;
 895                 eccbuf += chip->ecc.bytes;
 896         }
 897
 898         return max_bitflips;
 899 }
 900
 901 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 902                                      bool oob_required, int page, bool raw)
 903 {
 904         struct mtd_info *mtd = nand_to_mtd(chip);
 905         struct atmel_nand *nand = to_atmel_nand(chip);
 906         int ret;
 907
 908         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 909
 910         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 911         if (ret)
 912                 return ret;
 913
 914         nand_write_data_op(chip, buf, mtd->writesize, false);
 915
 916         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 917         if (ret) {
 918                 atmel_pmecc_disable(nand->pmecc);
 919                 return ret;
 920         }
 921
 922         atmel_nand_pmecc_disable(chip, raw);
 923
 924         nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
 925
 926         return nand_prog_page_end_op(chip);
 927 }
 928
 929 static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
 930                                        int oob_required, int page)
 931 {
 932         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 933 }
 934
 935 static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
 936                                            const u8 *buf, int oob_required,
 937                                            int page)
 938 {
 939         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 940 }
 941
 942 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 943                                     bool oob_required, int page, bool raw)
 944 {
 945         struct mtd_info *mtd = nand_to_mtd(chip);
 946         int ret;
 947
 948         nand_read_page_op(chip, page, 0, NULL, 0);
 949
 950         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 951         if (ret)
 952                 return ret;
 953
 954         ret = nand_read_data_op(chip, buf, mtd->writesize, false, false);
 955         if (ret)
 956                 goto out_disable;
 957
 958         ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false);
 959         if (ret)
 960                 goto out_disable;
 961
 962         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 963
 964 out_disable:
 965         atmel_nand_pmecc_disable(chip, raw);
 966
 967         return ret;
 968 }
 969
 970 static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
 971                                       int oob_required, int page)
 972 {
 973         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 974 }
 975
 976 static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
 977                                           int oob_required, int page)
 978 {
 979         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 980 }
 981
 982 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 983                                           const u8 *buf, bool oob_required,
 984                                           int page, bool raw)
 985 {
 986         struct mtd_info *mtd = nand_to_mtd(chip);
 987         struct atmel_nand *nand = to_atmel_nand(chip);
 988         struct atmel_hsmc_nand_controller *nc;
 989         int ret;
 990
 991         atmel_hsmc_nand_select_target(nand, chip->cur_cs);
 992         nc = to_hsmc_nand_controller(chip->controller);
 993
 994         atmel_nfc_copy_to_sram(chip, buf, false);
 995
 996         nc->op.cmds[0] = NAND_CMD_SEQIN;
 997         nc->op.ncmds = 1;
 998         atmel_nfc_set_op_addr(chip, page, 0x0);
 999         nc->op.cs = nand->activecs->id;
1000         nc->op.data = ATMEL_NFC_WRITE_DATA;
1001
1002         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
1003         if (ret)
1004                 return ret;
1005
1006         ret = atmel_nfc_exec_op(nc, false);
1007         if (ret) {
1008                 atmel_nand_pmecc_disable(chip, raw);
1009                 dev_err(nc->base.dev,
1010                         "Failed to transfer NAND page data (err = %d)\n",
1011                         ret);
1012                 return ret;
1013         }
1014
1015         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
1016
1017         atmel_nand_pmecc_disable(chip, raw);
1018
1019         if (ret)
1020                 return ret;
1021
1022         nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
1023
1024         return nand_prog_page_end_op(chip);
1025 }
1026
1027 static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
1028                                             const u8 *buf, int oob_required,
1029                                             int page)
1030 {
1031         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1032                                               false);
1033 }
1034
1035 static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
1036                                                 const u8 *buf,
1037                                                 int oob_required, int page)
1038 {
1039         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1040                                               true);
1041 }
1042
1043 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
1044                                          bool oob_required, int page,
1045                                          bool raw)
1046 {
1047         struct mtd_info *mtd = nand_to_mtd(chip);
1048         struct atmel_nand *nand = to_atmel_nand(chip);
1049         struct atmel_hsmc_nand_controller *nc;
1050         int ret;
1051
1052         atmel_hsmc_nand_select_target(nand, chip->cur_cs);
1053         nc = to_hsmc_nand_controller(chip->controller);
1054
1055         /*
1056          * Optimized read page accessors only work when the NAND R/B pin is
1057          * connected to a native SoC R/B pin. If that's not the case, fallback
1058          * to the non-optimized one.
1059          */
1060         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
1061                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1062                                                 raw);
1063
1064         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1065
1066         if (mtd->writesize > 512)
1067                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1068
1069         atmel_nfc_set_op_addr(chip, page, 0x0);
1070         nc->op.cs = nand->activecs->id;
1071         nc->op.data = ATMEL_NFC_READ_DATA;
1072
1073         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1074         if (ret)
1075                 return ret;
1076
1077         ret = atmel_nfc_exec_op(nc, false);
1078         if (ret) {
1079                 atmel_nand_pmecc_disable(chip, raw);
1080                 dev_err(nc->base.dev,
1081                         "Failed to load NAND page data (err = %d)\n",
1082                         ret);
1083                 return ret;
1084         }
1085
1086         atmel_nfc_copy_from_sram(chip, buf, true);
1087
1088         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1089
1090         atmel_nand_pmecc_disable(chip, raw);
1091
1092         return ret;
1093 }
1094
1095 static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
1096                                            int oob_required, int page)
1097 {
1098         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1099                                              false);
1100 }
1101
1102 static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
1103                                                u8 *buf, int oob_required,
1104                                                int page)
1105 {
1106         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1107                                              true);
1108 }
1109
1110 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1111 {
1112         const struct nand_ecc_props *requirements =
1113                 nanddev_get_ecc_requirements(&chip->base);
1114         struct mtd_info *mtd = nand_to_mtd(chip);
1115         struct nand_device *nanddev = mtd_to_nanddev(mtd);
1116         struct atmel_nand *nand = to_atmel_nand(chip);
1117         struct atmel_nand_controller *nc;
1118         struct atmel_pmecc_user_req req;
1119
1120         nc = to_nand_controller(chip->controller);
1121
1122         if (!nc->pmecc) {
1123                 dev_err(nc->dev, "HW ECC not supported\n");
1124                 return -ENOTSUPP;
1125         }
1126
1127         if (nc->caps->legacy_of_bindings) {
1128                 u32 val;
1129
1130                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1131                                           &val))
1132                         chip->ecc.strength = val;
1133
1134                 if (!of_property_read_u32(nc->dev->of_node,
1135                                           "atmel,pmecc-sector-size",
1136                                           &val))
1137                         chip->ecc.size = val;
1138         }
1139
1140         if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
1141                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1142         else if (chip->ecc.strength)
1143                 req.ecc.strength = chip->ecc.strength;
1144         else if (requirements->strength)
1145                 req.ecc.strength = requirements->strength;
1146         else
1147                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1148
1149         if (chip->ecc.size)
1150                 req.ecc.sectorsize = chip->ecc.size;
1151         else if (requirements->step_size)
1152                 req.ecc.sectorsize = requirements->step_size;
1153         else
1154                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1155
1156         req.pagesize = mtd->writesize;
1157         req.oobsize = mtd->oobsize;
1158
1159         if (mtd->writesize <= 512) {
1160                 req.ecc.bytes = 4;
1161                 req.ecc.ooboffset = 0;
1162         } else {
1163                 req.ecc.bytes = mtd->oobsize - 2;
1164                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1165         }
1166
1167         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1168         if (IS_ERR(nand->pmecc))
1169                 return PTR_ERR(nand->pmecc);
1170
1171         chip->ecc.algo = NAND_ECC_ALGO_BCH;
1172         chip->ecc.size = req.ecc.sectorsize;
1173         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1174         chip->ecc.strength = req.ecc.strength;
1175
1176         chip->options |= NAND_NO_SUBPAGE_WRITE;
1177
1178         mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1179
1180         return 0;
1181 }
1182
1183 static int atmel_nand_ecc_init(struct nand_chip *chip)
1184 {
1185         struct atmel_nand_controller *nc;
1186         int ret;
1187
1188         nc = to_nand_controller(chip->controller);
1189
1190         switch (chip->ecc.engine_type) {
1191         case NAND_ECC_ENGINE_TYPE_NONE:
1192         case NAND_ECC_ENGINE_TYPE_SOFT:
1193                 /*
1194                  * Nothing to do, the core will initialize everything for us.
1195                  */
1196                 break;
1197
1198         case NAND_ECC_ENGINE_TYPE_ON_HOST:
1199                 ret = atmel_nand_pmecc_init(chip);
1200                 if (ret)
1201                         return ret;
1202
1203                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1204                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1205                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1206                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1207                 break;
1208
1209         default:
1210                 /* Other modes are not supported. */
1211                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1212                         chip->ecc.engine_type);
1213                 return -ENOTSUPP;
1214         }
1215
1216         return 0;
1217 }
1218
1219 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1220 {
1221         int ret;
1222
1223         ret = atmel_nand_ecc_init(chip);
1224         if (ret)
1225                 return ret;
1226
1227         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
1228                 return 0;
1229
1230         /* Adjust the ECC operations for the HSMC IP. */
1231         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1232         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1233         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1234         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1235
1236         return 0;
1237 }
1238
1239 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1240                                         const struct nand_interface_config *conf,
1241                                         struct atmel_smc_cs_conf *smcconf)
1242 {
1243         u32 ncycles, totalcycles, timeps, mckperiodps;
1244         struct atmel_nand_controller *nc;
1245         int ret;
1246
1247         nc = to_nand_controller(nand->base.controller);
1248
1249         /* DDR interface not supported. */
1250         if (!nand_interface_is_sdr(conf))
1251                 return -ENOTSUPP;
1252
1253         /*
1254          * tRC < 30ns implies EDO mode. This controller does not support this
1255          * mode.
1256          */
1257         if (conf->timings.sdr.tRC_min < 30000)
1258                 return -ENOTSUPP;
1259
1260         atmel_smc_cs_conf_init(smcconf);
1261
1262         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1263         mckperiodps *= 1000;
1264
1265         /*
1266          * Set write pulse timing. This one is easy to extract:
1267          *
1268          * NWE_PULSE = tWP
1269          */
1270         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1271         totalcycles = ncycles;
1272         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1273                                           ncycles);
1274         if (ret)
1275                 return ret;
1276
1277         /*
1278          * The write setup timing depends on the operation done on the NAND.
1279          * All operations goes through the same data bus, but the operation
1280          * type depends on the address we are writing to (ALE/CLE address
1281          * lines).
1282          * Since we have no way to differentiate the different operations at
1283          * the SMC level, we must consider the worst case (the biggest setup
1284          * time among all operation types):
1285          *
1286          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1287          */
1288         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1289                       conf->timings.sdr.tALS_min);
1290         timeps = max(timeps, conf->timings.sdr.tDS_min);
1291         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1292         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1293         totalcycles += ncycles;
1294         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1295                                           ncycles);
1296         if (ret)
1297                 return ret;
1298
1299         /*
1300          * As for the write setup timing, the write hold timing depends on the
1301          * operation done on the NAND:
1302          *
1303          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1304          */
1305         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1306                       conf->timings.sdr.tALH_min);
1307         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1308                       conf->timings.sdr.tWH_min);
1309         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1310         totalcycles += ncycles;
1311
1312         /*
1313          * The write cycle timing is directly matching tWC, but is also
1314          * dependent on the other timings on the setup and hold timings we
1315          * calculated earlier, which gives:
1316          *
1317          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1318          */
1319         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1320         ncycles = max(totalcycles, ncycles);
1321         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1322                                           ncycles);
1323         if (ret)
1324                 return ret;
1325
1326         /*
1327          * We don't want the CS line to be toggled between each byte/word
1328          * transfer to the NAND. The only way to guarantee that is to have the
1329          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1330          *
1331          * NCS_WR_PULSE = NWE_CYCLE
1332          */
1333         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1334                                           ncycles);
1335         if (ret)
1336                 return ret;
1337
1338         /*
1339          * As for the write setup timing, the read hold timing depends on the
1340          * operation done on the NAND:
1341          *
1342          * NRD_HOLD = max(tREH, tRHOH)
1343          */
1344         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1345         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1346         totalcycles = ncycles;
1347
1348         /*
1349          * TDF = tRHZ - NRD_HOLD
1350          */
1351         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1352         ncycles -= totalcycles;
1353
1354         /*
1355          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1356          * we might end up with a config that does not fit in the TDF field.
1357          * Just take the max value in this case and hope that the NAND is more
1358          * tolerant than advertised.
1359          */
1360         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1361                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1362         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1363                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1364
1365         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1366                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1367
1368         /*
1369          * Read pulse timing directly matches tRP:
1370          *
1371          * NRD_PULSE = tRP
1372          */
1373         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1374         totalcycles += ncycles;
1375         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1376                                           ncycles);
1377         if (ret)
1378                 return ret;
1379
1380         /*
1381          * The write cycle timing is directly matching tWC, but is also
1382          * dependent on the setup and hold timings we calculated earlier,
1383          * which gives:
1384          *
1385          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1386          *
1387          * NRD_SETUP is always 0.
1388          */
1389         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1390         ncycles = max(totalcycles, ncycles);
1391         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1392                                           ncycles);
1393         if (ret)
1394                 return ret;
1395
1396         /*
1397          * We don't want the CS line to be toggled between each byte/word
1398          * transfer from the NAND. The only way to guarantee that is to have
1399          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1400          *
1401          * NCS_RD_PULSE = NRD_CYCLE
1402          */
1403         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1404                                           ncycles);
1405         if (ret)
1406                 return ret;
1407
1408         /* Txxx timings are directly matching tXXX ones. */
1409         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1410         ret = atmel_smc_cs_conf_set_timing(smcconf,
1411                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1412                                            ncycles);
1413         if (ret)
1414                 return ret;
1415
1416         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1417         ret = atmel_smc_cs_conf_set_timing(smcconf,
1418                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1419                                            ncycles);
1420         /*
1421          * Version 4 of the ONFI spec mandates that tADL be at least 400
1422          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1423          * fit in the tADL field of the SMC reg. We need to relax the check and
1424          * accept the -ERANGE return code.
1425          *
1426          * Note that previous versions of the ONFI spec had a lower tADL_min
1427          * (100 or 200 ns). It's not clear why this timing constraint got
1428          * increased but it seems most NANDs are fine with values lower than
1429          * 400ns, so we should be safe.
1430          */
1431         if (ret && ret != -ERANGE)
1432                 return ret;
1433
1434         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1435         ret = atmel_smc_cs_conf_set_timing(smcconf,
1436                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1437                                            ncycles);
1438         if (ret)
1439                 return ret;
1440
1441         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1442         ret = atmel_smc_cs_conf_set_timing(smcconf,
1443                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1444                                            ncycles);
1445         if (ret)
1446                 return ret;
1447
1448         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1449         ret = atmel_smc_cs_conf_set_timing(smcconf,
1450                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1451                                            ncycles);
1452         if (ret)
1453                 return ret;
1454
1455         /* Attach the CS line to the NFC logic. */
1456         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1457
1458         /* Set the appropriate data bus width. */
1459         if (nand->base.options & NAND_BUSWIDTH_16)
1460                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1461
1462         /* Operate in NRD/NWE READ/WRITEMODE. */
1463         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1464                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1465
1466         return 0;
1467 }
1468
1469 static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
1470                                         int csline,
1471                                         const struct nand_interface_config *conf)
1472 {
1473         struct atmel_nand_controller *nc;
1474         struct atmel_smc_cs_conf smcconf;
1475         struct atmel_nand_cs *cs;
1476         int ret;
1477
1478         nc = to_nand_controller(nand->base.controller);
1479
1480         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1481         if (ret)
1482                 return ret;
1483
1484         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1485                 return 0;
1486
1487         cs = &nand->cs[csline];
1488         cs->smcconf = smcconf;
1489         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1490
1491         return 0;
1492 }
1493
1494 static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
1495                                         int csline,
1496                                         const struct nand_interface_config *conf)
1497 {
1498         struct atmel_hsmc_nand_controller *nc;
1499         struct atmel_smc_cs_conf smcconf;
1500         struct atmel_nand_cs *cs;
1501         int ret;
1502
1503         nc = to_hsmc_nand_controller(nand->base.controller);
1504
1505         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1506         if (ret)
1507                 return ret;
1508
1509         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1510                 return 0;
1511
1512         cs = &nand->cs[csline];
1513         cs->smcconf = smcconf;
1514
1515         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1516                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1517
1518         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1519                                  &cs->smcconf);
1520
1521         return 0;
1522 }
1523
1524 static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
1525                                       const struct nand_interface_config *conf)
1526 {
1527         struct atmel_nand *nand = to_atmel_nand(chip);
1528         const struct nand_sdr_timings *sdr;
1529         struct atmel_nand_controller *nc;
1530
1531         sdr = nand_get_sdr_timings(conf);
1532         if (IS_ERR(sdr))
1533                 return PTR_ERR(sdr);
1534
1535         nc = to_nand_controller(nand->base.controller);
1536
1537         if (csline >= nand->numcs ||
1538             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1539                 return -EINVAL;
1540
1541         return nc->caps->ops->setup_interface(nand, csline, conf);
1542 }
1543
1544 static int atmel_nand_exec_op(struct nand_chip *chip,
1545                               const struct nand_operation *op,
1546                               bool check_only)
1547 {
1548         struct atmel_nand *nand = to_atmel_nand(chip);
1549         struct atmel_nand_controller *nc;
1550
1551         nc = to_nand_controller(nand->base.controller);
1552
1553         return nc->caps->ops->exec_op(nand, op, check_only);
1554 }
1555
1556 static void atmel_nand_init(struct atmel_nand_controller *nc,
1557                             struct atmel_nand *nand)
1558 {
1559         struct nand_chip *chip = &nand->base;
1560         struct mtd_info *mtd = nand_to_mtd(chip);
1561
1562         mtd->dev.parent = nc->dev;
1563         nand->base.controller = &nc->base;
1564
1565         if (!nc->mck || !nc->caps->ops->setup_interface)
1566                 chip->options |= NAND_KEEP_TIMINGS;
1567
1568         /*
1569          * Use a bounce buffer when the buffer passed by the MTD user is not
1570          * suitable for DMA.
1571          */
1572         if (nc->dmac)
1573                 chip->options |= NAND_USES_DMA;
1574
1575         /* Default to HW ECC if pmecc is available. */
1576         if (nc->pmecc)
1577                 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1578 }
1579
1580 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1581                                 struct atmel_nand *nand)
1582 {
1583         struct nand_chip *chip = &nand->base;
1584         struct atmel_smc_nand_controller *smc_nc;
1585         int i;
1586
1587         atmel_nand_init(nc, nand);
1588
1589         smc_nc = to_smc_nand_controller(chip->controller);
1590         if (!smc_nc->ebi_csa_regmap)
1591                 return;
1592
1593         /* Attach the CS to the NAND Flash logic. */
1594         for (i = 0; i < nand->numcs; i++)
1595                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1596                                    smc_nc->ebi_csa->offs,
1597                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1598
1599         if (smc_nc->ebi_csa->nfd0_on_d16)
1600                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1601                                    smc_nc->ebi_csa->offs,
1602                                    smc_nc->ebi_csa->nfd0_on_d16,
1603                                    smc_nc->ebi_csa->nfd0_on_d16);
1604 }
1605
1606 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1607 {
1608         struct nand_chip *chip = &nand->base;
1609         struct mtd_info *mtd = nand_to_mtd(chip);
1610         int ret;
1611
1612         ret = mtd_device_unregister(mtd);
1613         if (ret)
1614                 return ret;
1615
1616         nand_cleanup(chip);
1617         list_del(&nand->node);
1618
1619         return 0;
1620 }
1621
1622 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1623                                             struct device_node *np,
1624                                             int reg_cells)
1625 {
1626         struct atmel_nand *nand;
1627         struct gpio_desc *gpio;
1628         int numcs, ret, i;
1629
1630         numcs = of_property_count_elems_of_size(np, "reg",
1631                                                 reg_cells * sizeof(u32));
1632         if (numcs < 1) {
1633                 dev_err(nc->dev, "Missing or invalid reg property\n");
1634                 return ERR_PTR(-EINVAL);
1635         }
1636
1637         nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
1638         if (!nand)
1639                 return ERR_PTR(-ENOMEM);
1640
1641         nand->numcs = numcs;
1642
1643         gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),
1644                                      "det", GPIOD_IN, "nand-det");
1645         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1646                 dev_err(nc->dev,
1647                         "Failed to get detect gpio (err = %ld)\n",
1648                         PTR_ERR(gpio));
1649                 return ERR_CAST(gpio);
1650         }
1651
1652         if (!IS_ERR(gpio))
1653                 nand->cdgpio = gpio;
1654
1655         for (i = 0; i < numcs; i++) {
1656                 struct resource res;
1657                 u32 val;
1658
1659                 ret = of_address_to_resource(np, 0, &res);
1660                 if (ret) {
1661                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1662                                 ret);
1663                         return ERR_PTR(ret);
1664                 }
1665
1666                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1667                                                  &val);
1668                 if (ret) {
1669                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1670                                 ret);
1671                         return ERR_PTR(ret);
1672                 }
1673
1674                 nand->cs[i].id = val;
1675
1676                 nand->cs[i].io.dma = res.start;
1677                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1678                 if (IS_ERR(nand->cs[i].io.virt))
1679                         return ERR_CAST(nand->cs[i].io.virt);
1680
1681                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1682                         if (val > ATMEL_NFC_MAX_RB_ID)
1683                                 return ERR_PTR(-EINVAL);
1684
1685                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1686                         nand->cs[i].rb.id = val;
1687                 } else {
1688                         gpio = devm_fwnode_gpiod_get_index(nc->dev,
1689                                                            of_fwnode_handle(np),
1690                                                            "rb", i, GPIOD_IN,
1691                                                            "nand-rb");
1692                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1693                                 dev_err(nc->dev,
1694                                         "Failed to get R/B gpio (err = %ld)\n",
1695                                         PTR_ERR(gpio));
1696                                 return ERR_CAST(gpio);
1697                         }
1698
1699                         if (!IS_ERR(gpio)) {
1700                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1701                                 nand->cs[i].rb.gpio = gpio;
1702                         }
1703                 }
1704
1705                 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1706                                                    of_fwnode_handle(np),
1707                                                    "cs", i, GPIOD_OUT_HIGH,
1708                                                    "nand-cs");
1709                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1710                         dev_err(nc->dev,
1711                                 "Failed to get CS gpio (err = %ld)\n",
1712                                 PTR_ERR(gpio));
1713                         return ERR_CAST(gpio);
1714                 }
1715
1716                 if (!IS_ERR(gpio))
1717                         nand->cs[i].csgpio = gpio;
1718         }
1719
1720         nand_set_flash_node(&nand->base, np);
1721
1722         return nand;
1723 }
1724
1725 static int
1726 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1727                                struct atmel_nand *nand)
1728 {
1729         struct nand_chip *chip = &nand->base;
1730         struct mtd_info *mtd = nand_to_mtd(chip);
1731         int ret;
1732
1733         /* No card inserted, skip this NAND. */
1734         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1735                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1736                 return 0;
1737         }
1738
1739         nc->caps->ops->nand_init(nc, nand);
1740
1741         ret = nand_scan(chip, nand->numcs);
1742         if (ret) {
1743                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1744                 return ret;
1745         }
1746
1747         ret = mtd_device_register(mtd, NULL, 0);
1748         if (ret) {
1749                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1750                 nand_cleanup(chip);
1751                 return ret;
1752         }
1753
1754         list_add_tail(&nand->node, &nc->chips);
1755
1756         return 0;
1757 }
1758
1759 static int
1760 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1761 {
1762         struct atmel_nand *nand, *tmp;
1763         int ret;
1764
1765         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1766                 ret = atmel_nand_controller_remove_nand(nand);
1767                 if (ret)
1768                         return ret;
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int
1775 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1776 {
1777         struct device *dev = nc->dev;
1778         struct platform_device *pdev = to_platform_device(dev);
1779         struct atmel_nand *nand;
1780         struct gpio_desc *gpio;
1781         struct resource *res;
1782
1783         /*
1784          * Legacy bindings only allow connecting a single NAND with a unique CS
1785          * line to the controller.
1786          */
1787         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1788                             GFP_KERNEL);
1789         if (!nand)
1790                 return -ENOMEM;
1791
1792         nand->numcs = 1;
1793
1794         nand->cs[0].io.virt = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1795         if (IS_ERR(nand->cs[0].io.virt))
1796                 return PTR_ERR(nand->cs[0].io.virt);
1797
1798         nand->cs[0].io.dma = res->start;
1799
1800         /*
1801          * The old driver was hardcoding the CS id to 3 for all sama5
1802          * controllers. Since this id is only meaningful for the sama5
1803          * controller we can safely assign this id to 3 no matter the
1804          * controller.
1805          * If one wants to connect a NAND to a different CS line, he will
1806          * have to use the new bindings.
1807          */
1808         nand->cs[0].id = 3;
1809
1810         /* R/B GPIO. */
1811         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1812         if (IS_ERR(gpio)) {
1813                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1814                         PTR_ERR(gpio));
1815                 return PTR_ERR(gpio);
1816         }
1817
1818         if (gpio) {
1819                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1820                 nand->cs[0].rb.gpio = gpio;
1821         }
1822
1823         /* CS GPIO. */
1824         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1825         if (IS_ERR(gpio)) {
1826                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1827                         PTR_ERR(gpio));
1828                 return PTR_ERR(gpio);
1829         }
1830
1831         nand->cs[0].csgpio = gpio;
1832
1833         /* Card detect GPIO. */
1834         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1835         if (IS_ERR(gpio)) {
1836                 dev_err(dev,
1837                         "Failed to get detect gpio (err = %ld)\n",
1838                         PTR_ERR(gpio));
1839                 return PTR_ERR(gpio);
1840         }
1841
1842         nand->cdgpio = gpio;
1843
1844         nand_set_flash_node(&nand->base, nc->dev->of_node);
1845
1846         return atmel_nand_controller_add_nand(nc, nand);
1847 }
1848
1849 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1850 {
1851         struct device_node *np, *nand_np;
1852         struct device *dev = nc->dev;
1853         int ret, reg_cells;
1854         u32 val;
1855
1856         /* We do not retrieve the SMC syscon when parsing old DTs. */
1857         if (nc->caps->legacy_of_bindings)
1858                 return atmel_nand_controller_legacy_add_nands(nc);
1859
1860         np = dev->of_node;
1861
1862         ret = of_property_read_u32(np, "#address-cells", &val);
1863         if (ret) {
1864                 dev_err(dev, "missing #address-cells property\n");
1865                 return ret;
1866         }
1867
1868         reg_cells = val;
1869
1870         ret = of_property_read_u32(np, "#size-cells", &val);
1871         if (ret) {
1872                 dev_err(dev, "missing #size-cells property\n");
1873                 return ret;
1874         }
1875
1876         reg_cells += val;
1877
1878         for_each_child_of_node(np, nand_np) {
1879                 struct atmel_nand *nand;
1880
1881                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1882                 if (IS_ERR(nand)) {
1883                         ret = PTR_ERR(nand);
1884                         goto err;
1885                 }
1886
1887                 ret = atmel_nand_controller_add_nand(nc, nand);
1888                 if (ret)
1889                         goto err;
1890         }
1891
1892         return 0;
1893
1894 err:
1895         atmel_nand_controller_remove_nands(nc);
1896
1897         return ret;
1898 }
1899
1900 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1901 {
1902         if (nc->dmac)
1903                 dma_release_channel(nc->dmac);
1904
1905         clk_put(nc->mck);
1906 }
1907
1908 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1909         .offs = AT91SAM9260_MATRIX_EBICSA,
1910 };
1911
1912 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1913         .offs = AT91SAM9261_MATRIX_EBICSA,
1914 };
1915
1916 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1917         .offs = AT91SAM9263_MATRIX_EBI0CSA,
1918 };
1919
1920 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1921         .offs = AT91SAM9RL_MATRIX_EBICSA,
1922 };
1923
1924 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1925         .offs = AT91SAM9G45_MATRIX_EBICSA,
1926 };
1927
1928 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1929         .offs = AT91SAM9N12_MATRIX_EBICSA,
1930 };
1931
1932 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1933         .offs = AT91SAM9X5_MATRIX_EBICSA,
1934 };
1935
1936 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1937         .offs = AT91_SFR_CCFG_EBICSA,
1938         .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1939 };
1940
1941 static const struct of_device_id __maybe_unused atmel_ebi_csa_regmap_of_ids[] = {
1942         {
1943                 .compatible = "atmel,at91sam9260-matrix",
1944                 .data = &at91sam9260_ebi_csa,
1945         },
1946         {
1947                 .compatible = "atmel,at91sam9261-matrix",
1948                 .data = &at91sam9261_ebi_csa,
1949         },
1950         {
1951                 .compatible = "atmel,at91sam9263-matrix",
1952                 .data = &at91sam9263_ebi_csa,
1953         },
1954         {
1955                 .compatible = "atmel,at91sam9rl-matrix",
1956                 .data = &at91sam9rl_ebi_csa,
1957         },
1958         {
1959                 .compatible = "atmel,at91sam9g45-matrix",
1960                 .data = &at91sam9g45_ebi_csa,
1961         },
1962         {
1963                 .compatible = "atmel,at91sam9n12-matrix",
1964                 .data = &at91sam9n12_ebi_csa,
1965         },
1966         {
1967                 .compatible = "atmel,at91sam9x5-matrix",
1968                 .data = &at91sam9x5_ebi_csa,
1969         },
1970         {
1971                 .compatible = "microchip,sam9x60-sfr",
1972                 .data = &sam9x60_ebi_csa,
1973         },
1974         { /* sentinel */ },
1975 };
1976
1977 static int atmel_nand_attach_chip(struct nand_chip *chip)
1978 {
1979         struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1980         struct atmel_nand *nand = to_atmel_nand(chip);
1981         struct mtd_info *mtd = nand_to_mtd(chip);
1982         int ret;
1983
1984         ret = nc->caps->ops->ecc_init(chip);
1985         if (ret)
1986                 return ret;
1987
1988         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1989                 /*
1990                  * We keep the MTD name unchanged to avoid breaking platforms
1991                  * where the MTD cmdline parser is used and the bootloader
1992                  * has not been updated to use the new naming scheme.
1993                  */
1994                 mtd->name = "atmel_nand";
1995         } else if (!mtd->name) {
1996                 /*
1997                  * If the new bindings are used and the bootloader has not been
1998                  * updated to pass a new mtdparts parameter on the cmdline, you
1999                  * should define the following property in your nand node:
2000                  *
2001                  *      label = "atmel_nand";
2002                  *
2003                  * This way, mtd->name will be set by the core when
2004                  * nand_set_flash_node() is called.
2005                  */
2006                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
2007                                            "%s:nand.%d", dev_name(nc->dev),
2008                                            nand->cs[0].id);
2009                 if (!mtd->name) {
2010                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
2011                         return -ENOMEM;
2012                 }
2013         }
2014
2015         return 0;
2016 }
2017
2018 static const struct nand_controller_ops atmel_nand_controller_ops = {
2019         .attach_chip = atmel_nand_attach_chip,
2020         .setup_interface = atmel_nand_setup_interface,
2021         .exec_op = atmel_nand_exec_op,
2022 };
2023
2024 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
2025                                 struct platform_device *pdev,
2026                                 const struct atmel_nand_controller_caps *caps)
2027 {
2028         struct device *dev = &pdev->dev;
2029         struct device_node *np = dev->of_node;
2030         int ret;
2031
2032         nand_controller_init(&nc->base);
2033         nc->base.ops = &atmel_nand_controller_ops;
2034         INIT_LIST_HEAD(&nc->chips);
2035         nc->dev = dev;
2036         nc->caps = caps;
2037
2038         platform_set_drvdata(pdev, nc);
2039
2040         nc->pmecc = devm_atmel_pmecc_get(dev);
2041         if (IS_ERR(nc->pmecc))
2042                 return dev_err_probe(dev, PTR_ERR(nc->pmecc),
2043                                      "Could not get PMECC object\n");
2044
2045         if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
2046                 dma_cap_mask_t mask;
2047
2048                 dma_cap_zero(mask);
2049                 dma_cap_set(DMA_MEMCPY, mask);
2050
2051                 nc->dmac = dma_request_channel(mask, NULL, NULL);
2052                 if (!nc->dmac)
2053                         dev_err(nc->dev, "Failed to request DMA channel\n");
2054         }
2055
2056         /* We do not retrieve the SMC syscon when parsing old DTs. */
2057         if (nc->caps->legacy_of_bindings)
2058                 return 0;
2059
2060         nc->mck = of_clk_get(dev->parent->of_node, 0);
2061         if (IS_ERR(nc->mck)) {
2062                 dev_err(dev, "Failed to retrieve MCK clk\n");
2063                 ret = PTR_ERR(nc->mck);
2064                 goto out_release_dma;
2065         }
2066
2067         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2068         if (!np) {
2069                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2070                 ret = -EINVAL;
2071                 goto out_release_dma;
2072         }
2073
2074         nc->smc = syscon_node_to_regmap(np);
2075         of_node_put(np);
2076         if (IS_ERR(nc->smc)) {
2077                 ret = PTR_ERR(nc->smc);
2078                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2079                 goto out_release_dma;
2080         }
2081
2082         return 0;
2083
2084 out_release_dma:
2085         if (nc->dmac)
2086                 dma_release_channel(nc->dmac);
2087
2088         return ret;
2089 }
2090
2091 static int
2092 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2093 {
2094         struct device *dev = nc->base.dev;
2095         const struct of_device_id *match;
2096         struct device_node *np;
2097         int ret;
2098
2099         /* We do not retrieve the EBICSA regmap when parsing old DTs. */
2100         if (nc->base.caps->legacy_of_bindings)
2101                 return 0;
2102
2103         np = of_parse_phandle(dev->parent->of_node,
2104                               nc->base.caps->ebi_csa_regmap_name, 0);
2105         if (!np)
2106                 return 0;
2107
2108         match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
2109         if (!match) {
2110                 of_node_put(np);
2111                 return 0;
2112         }
2113
2114         nc->ebi_csa_regmap = syscon_node_to_regmap(np);
2115         of_node_put(np);
2116         if (IS_ERR(nc->ebi_csa_regmap)) {
2117                 ret = PTR_ERR(nc->ebi_csa_regmap);
2118                 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
2119                 return ret;
2120         }
2121
2122         nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
2123
2124         /*
2125          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2126          * add 4 to ->ebi_csa->offs.
2127          */
2128         if (of_device_is_compatible(dev->parent->of_node,
2129                                     "atmel,at91sam9263-ebi1"))
2130                 nc->ebi_csa->offs += 4;
2131
2132         return 0;
2133 }
2134
2135 static int
2136 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2137 {
2138         struct regmap_config regmap_conf = {
2139                 .reg_bits = 32,
2140                 .val_bits = 32,
2141                 .reg_stride = 4,
2142         };
2143
2144         struct device *dev = nc->base.dev;
2145         struct device_node *nand_np, *nfc_np;
2146         void __iomem *iomem;
2147         struct resource res;
2148         int ret;
2149
2150         nand_np = dev->of_node;
2151         nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2152         if (!nfc_np) {
2153                 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2154                 return -ENODEV;
2155         }
2156
2157         nc->clk = of_clk_get(nfc_np, 0);
2158         if (IS_ERR(nc->clk)) {
2159                 ret = PTR_ERR(nc->clk);
2160                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2161                         ret);
2162                 goto out;
2163         }
2164
2165         ret = clk_prepare_enable(nc->clk);
2166         if (ret) {
2167                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2168                         ret);
2169                 goto out;
2170         }
2171
2172         nc->irq = of_irq_get(nand_np, 0);
2173         if (nc->irq <= 0) {
2174                 ret = nc->irq ?: -ENXIO;
2175                 if (ret != -EPROBE_DEFER)
2176                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2177                                 ret);
2178                 goto out;
2179         }
2180
2181         ret = of_address_to_resource(nfc_np, 0, &res);
2182         if (ret) {
2183                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2184                         ret);
2185                 goto out;
2186         }
2187
2188         iomem = devm_ioremap_resource(dev, &res);
2189         if (IS_ERR(iomem)) {
2190                 ret = PTR_ERR(iomem);
2191                 goto out;
2192         }
2193
2194         regmap_conf.name = "nfc-io";
2195         regmap_conf.max_register = resource_size(&res) - 4;
2196         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2197         if (IS_ERR(nc->io)) {
2198                 ret = PTR_ERR(nc->io);
2199                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2200                         ret);
2201                 goto out;
2202         }
2203
2204         ret = of_address_to_resource(nfc_np, 1, &res);
2205         if (ret) {
2206                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2207                         ret);
2208                 goto out;
2209         }
2210
2211         iomem = devm_ioremap_resource(dev, &res);
2212         if (IS_ERR(iomem)) {
2213                 ret = PTR_ERR(iomem);
2214                 goto out;
2215         }
2216
2217         regmap_conf.name = "smc";
2218         regmap_conf.max_register = resource_size(&res) - 4;
2219         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2220         if (IS_ERR(nc->base.smc)) {
2221                 ret = PTR_ERR(nc->base.smc);
2222                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2223                         ret);
2224                 goto out;
2225         }
2226
2227         ret = of_address_to_resource(nfc_np, 2, &res);
2228         if (ret) {
2229                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2230                         ret);
2231                 goto out;
2232         }
2233
2234         nc->sram.virt = devm_ioremap_resource(dev, &res);
2235         if (IS_ERR(nc->sram.virt)) {
2236                 ret = PTR_ERR(nc->sram.virt);
2237                 goto out;
2238         }
2239
2240         nc->sram.dma = res.start;
2241
2242 out:
2243         of_node_put(nfc_np);
2244
2245         return ret;
2246 }
2247
2248 static int
2249 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2250 {
2251         struct device *dev = nc->base.dev;
2252         struct device_node *np;
2253         int ret;
2254
2255         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2256         if (!np) {
2257                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2258                 return -EINVAL;
2259         }
2260
2261         nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2262
2263         nc->irq = of_irq_get(np, 0);
2264         of_node_put(np);
2265         if (nc->irq <= 0) {
2266                 ret = nc->irq ?: -ENXIO;
2267                 if (ret != -EPROBE_DEFER)
2268                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2269                                 ret);
2270                 return ret;
2271         }
2272
2273         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2274         if (!np) {
2275                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2276                 return -EINVAL;
2277         }
2278
2279         nc->io = syscon_node_to_regmap(np);
2280         of_node_put(np);
2281         if (IS_ERR(nc->io)) {
2282                 ret = PTR_ERR(nc->io);
2283                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2284                 return ret;
2285         }
2286
2287         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2288                                          "atmel,nfc-sram", 0);
2289         if (!nc->sram.pool) {
2290                 dev_err(nc->base.dev, "Missing SRAM\n");
2291                 return -ENOMEM;
2292         }
2293
2294         nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2295                                                            ATMEL_NFC_SRAM_SIZE,
2296                                                            &nc->sram.dma);
2297         if (!nc->sram.virt) {
2298                 dev_err(nc->base.dev,
2299                         "Could not allocate memory from the NFC SRAM pool\n");
2300                 return -ENOMEM;
2301         }
2302
2303         return 0;
2304 }
2305
2306 static int
2307 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2308 {
2309         struct atmel_hsmc_nand_controller *hsmc_nc;
2310         int ret;
2311
2312         ret = atmel_nand_controller_remove_nands(nc);
2313         if (ret)
2314                 return ret;
2315
2316         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2317         regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2318                      ATMEL_HSMC_NFC_CTRL_DIS);
2319
2320         if (hsmc_nc->sram.pool)
2321                 gen_pool_free(hsmc_nc->sram.pool,
2322                               (unsigned long)hsmc_nc->sram.virt,
2323                               ATMEL_NFC_SRAM_SIZE);
2324
2325         if (hsmc_nc->clk) {
2326                 clk_disable_unprepare(hsmc_nc->clk);
2327                 clk_put(hsmc_nc->clk);
2328         }
2329
2330         atmel_nand_controller_cleanup(nc);
2331
2332         return 0;
2333 }
2334
2335 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2336                                 const struct atmel_nand_controller_caps *caps)
2337 {
2338         struct device *dev = &pdev->dev;
2339         struct atmel_hsmc_nand_controller *nc;
2340         int ret;
2341
2342         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2343         if (!nc)
2344                 return -ENOMEM;
2345
2346         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2347         if (ret)
2348                 return ret;
2349
2350         if (caps->legacy_of_bindings)
2351                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2352         else
2353                 ret = atmel_hsmc_nand_controller_init(nc);
2354
2355         if (ret)
2356                 return ret;
2357
2358         /* Make sure all irqs are masked before registering our IRQ handler. */
2359         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2360         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2361                                IRQF_SHARED, "nfc", nc);
2362         if (ret) {
2363                 dev_err(dev,
2364                         "Could not get register NFC interrupt handler (err = %d)\n",
2365                         ret);
2366                 goto err;
2367         }
2368
2369         /* Initial NFC configuration. */
2370         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2371                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2372         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2373                      ATMEL_HSMC_NFC_CTRL_EN);
2374
2375         ret = atmel_nand_controller_add_nands(&nc->base);
2376         if (ret)
2377                 goto err;
2378
2379         return 0;
2380
2381 err:
2382         atmel_hsmc_nand_controller_remove(&nc->base);
2383
2384         return ret;
2385 }
2386
2387 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2388         .probe = atmel_hsmc_nand_controller_probe,
2389         .remove = atmel_hsmc_nand_controller_remove,
2390         .ecc_init = atmel_hsmc_nand_ecc_init,
2391         .nand_init = atmel_nand_init,
2392         .setup_interface = atmel_hsmc_nand_setup_interface,
2393         .exec_op = atmel_hsmc_nand_exec_op,
2394 };
2395
2396 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2397         .has_dma = true,
2398         .ale_offs = BIT(21),
2399         .cle_offs = BIT(22),
2400         .ops = &atmel_hsmc_nc_ops,
2401 };
2402
2403 /* Only used to parse old bindings. */
2404 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2405         .has_dma = true,
2406         .ale_offs = BIT(21),
2407         .cle_offs = BIT(22),
2408         .ops = &atmel_hsmc_nc_ops,
2409         .legacy_of_bindings = true,
2410 };
2411
2412 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2413                                 const struct atmel_nand_controller_caps *caps)
2414 {
2415         struct device *dev = &pdev->dev;
2416         struct atmel_smc_nand_controller *nc;
2417         int ret;
2418
2419         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2420         if (!nc)
2421                 return -ENOMEM;
2422
2423         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2424         if (ret)
2425                 return ret;
2426
2427         ret = atmel_smc_nand_controller_init(nc);
2428         if (ret)
2429                 return ret;
2430
2431         return atmel_nand_controller_add_nands(&nc->base);
2432 }
2433
2434 static int
2435 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2436 {
2437         int ret;
2438
2439         ret = atmel_nand_controller_remove_nands(nc);
2440         if (ret)
2441                 return ret;
2442
2443         atmel_nand_controller_cleanup(nc);
2444
2445         return 0;
2446 }
2447
2448 /*
2449  * The SMC reg layout of at91rm9200 is completely different which prevents us
2450  * from re-using atmel_smc_nand_setup_interface() for the
2451  * ->setup_interface() hook.
2452  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2453  * ->setup_interface() unassigned.
2454  */
2455 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2456         .probe = atmel_smc_nand_controller_probe,
2457         .remove = atmel_smc_nand_controller_remove,
2458         .ecc_init = atmel_nand_ecc_init,
2459         .nand_init = atmel_smc_nand_init,
2460         .exec_op = atmel_smc_nand_exec_op,
2461 };
2462
2463 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2464         .ale_offs = BIT(21),
2465         .cle_offs = BIT(22),
2466         .ebi_csa_regmap_name = "atmel,matrix",
2467         .ops = &at91rm9200_nc_ops,
2468 };
2469
2470 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2471         .probe = atmel_smc_nand_controller_probe,
2472         .remove = atmel_smc_nand_controller_remove,
2473         .ecc_init = atmel_nand_ecc_init,
2474         .nand_init = atmel_smc_nand_init,
2475         .setup_interface = atmel_smc_nand_setup_interface,
2476         .exec_op = atmel_smc_nand_exec_op,
2477 };
2478
2479 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2480         .ale_offs = BIT(21),
2481         .cle_offs = BIT(22),
2482         .ebi_csa_regmap_name = "atmel,matrix",
2483         .ops = &atmel_smc_nc_ops,
2484 };
2485
2486 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2487         .ale_offs = BIT(22),
2488         .cle_offs = BIT(21),
2489         .ebi_csa_regmap_name = "atmel,matrix",
2490         .ops = &atmel_smc_nc_ops,
2491 };
2492
2493 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2494         .has_dma = true,
2495         .ale_offs = BIT(21),
2496         .cle_offs = BIT(22),
2497         .ebi_csa_regmap_name = "atmel,matrix",
2498         .ops = &atmel_smc_nc_ops,
2499 };
2500
2501 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2502         .has_dma = true,
2503         .ale_offs = BIT(21),
2504         .cle_offs = BIT(22),
2505         .ebi_csa_regmap_name = "microchip,sfr",
2506         .ops = &atmel_smc_nc_ops,
2507 };
2508
2509 /* Only used to parse old bindings. */
2510 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2511         .ale_offs = BIT(21),
2512         .cle_offs = BIT(22),
2513         .ops = &atmel_smc_nc_ops,
2514         .legacy_of_bindings = true,
2515 };
2516
2517 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2518         .ale_offs = BIT(22),
2519         .cle_offs = BIT(21),
2520         .ops = &atmel_smc_nc_ops,
2521         .legacy_of_bindings = true,
2522 };
2523
2524 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2525         .has_dma = true,
2526         .ale_offs = BIT(21),
2527         .cle_offs = BIT(22),
2528         .ops = &atmel_smc_nc_ops,
2529         .legacy_of_bindings = true,
2530 };
2531
2532 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2533         {
2534                 .compatible = "atmel,at91rm9200-nand-controller",
2535                 .data = &atmel_rm9200_nc_caps,
2536         },
2537         {
2538                 .compatible = "atmel,at91sam9260-nand-controller",
2539                 .data = &atmel_sam9260_nc_caps,
2540         },
2541         {
2542                 .compatible = "atmel,at91sam9261-nand-controller",
2543                 .data = &atmel_sam9261_nc_caps,
2544         },
2545         {
2546                 .compatible = "atmel,at91sam9g45-nand-controller",
2547                 .data = &atmel_sam9g45_nc_caps,
2548         },
2549         {
2550                 .compatible = "atmel,sama5d3-nand-controller",
2551                 .data = &atmel_sama5_nc_caps,
2552         },
2553         {
2554                 .compatible = "microchip,sam9x60-nand-controller",
2555                 .data = &microchip_sam9x60_nc_caps,
2556         },
2557         /* Support for old/deprecated bindings: */
2558         {
2559                 .compatible = "atmel,at91rm9200-nand",
2560                 .data = &atmel_rm9200_nand_caps,
2561         },
2562         {
2563                 .compatible = "atmel,sama5d4-nand",
2564                 .data = &atmel_rm9200_nand_caps,
2565         },
2566         {
2567                 .compatible = "atmel,sama5d2-nand",
2568                 .data = &atmel_rm9200_nand_caps,
2569         },
2570         { /* sentinel */ },
2571 };
2572 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2573
2574 static int atmel_nand_controller_probe(struct platform_device *pdev)
2575 {
2576         const struct atmel_nand_controller_caps *caps;
2577
2578         if (pdev->id_entry)
2579                 caps = (void *)pdev->id_entry->driver_data;
2580         else
2581                 caps = of_device_get_match_data(&pdev->dev);
2582
2583         if (!caps) {
2584                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2585                 return -EINVAL;
2586         }
2587
2588         if (caps->legacy_of_bindings) {
2589                 struct device_node *nfc_node;
2590                 u32 ale_offs = 21;
2591
2592                 /*
2593                  * If we are parsing legacy DT props and the DT contains a
2594                  * valid NFC node, forward the request to the sama5 logic.
2595                  */
2596                 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2597                                                    "atmel,sama5d3-nfc");
2598                 if (nfc_node) {
2599                         caps = &atmel_sama5_nand_caps;
2600                         of_node_put(nfc_node);
2601                 }
2602
2603                 /*
2604                  * Even if the compatible says we are dealing with an
2605                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2606                  * this controller supports DMA, which means we are in fact
2607                  * dealing with an at91sam9g45+ controller.
2608                  */
2609                 if (!caps->has_dma &&
2610                     of_property_read_bool(pdev->dev.of_node,
2611                                           "atmel,nand-has-dma"))
2612                         caps = &atmel_sam9g45_nand_caps;
2613
2614                 /*
2615                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2616                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2617                  * actually dealing with an at91sam9261 controller.
2618                  */
2619                 of_property_read_u32(pdev->dev.of_node,
2620                                      "atmel,nand-addr-offset", &ale_offs);
2621                 if (ale_offs != 21)
2622                         caps = &atmel_sam9261_nand_caps;
2623         }
2624
2625         return caps->ops->probe(pdev, caps);
2626 }
2627
2628 static void atmel_nand_controller_remove(struct platform_device *pdev)
2629 {
2630         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2631
2632         WARN_ON(nc->caps->ops->remove(nc));
2633 }
2634
2635 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2636 {
2637         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2638         struct atmel_nand *nand;
2639
2640         if (nc->pmecc)
2641                 atmel_pmecc_reset(nc->pmecc);
2642
2643         list_for_each_entry(nand, &nc->chips, node) {
2644                 int i;
2645
2646                 for (i = 0; i < nand->numcs; i++)
2647                         nand_reset(&nand->base, i);
2648         }
2649
2650         return 0;
2651 }
2652
2653 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2654                          atmel_nand_controller_resume);
2655
2656 static struct platform_driver atmel_nand_controller_driver = {
2657         .driver = {
2658                 .name = "atmel-nand-controller",
2659                 .of_match_table = atmel_nand_controller_of_ids,
2660                 .pm = &atmel_nand_controller_pm_ops,
2661         },
2662         .probe = atmel_nand_controller_probe,
2663         .remove_new = atmel_nand_controller_remove,
2664 };
2665 module_platform_driver(atmel_nand_controller_driver);
2666
2667 MODULE_LICENSE("GPL");
2668 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2669 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2670 MODULE_ALIAS("platform:atmel-nand-controller");