5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/err.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/compatmac.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
50 #ifdef CONFIG_MTD_PARTITIONS
51 #include <linux/mtd/partitions.h>
54 /* Define default oob placement schemes for large and small page devices */
55 static struct nand_oobinfo nand_oob_8 = {
56 .useecc = MTD_NANDECC_AUTOPLACE,
59 .oobfree = {{3, 2}, {6, 2}}
62 static struct nand_oobinfo nand_oob_16 = {
63 .useecc = MTD_NANDECC_AUTOPLACE,
65 .eccpos = {0, 1, 2, 3, 6, 7},
69 static struct nand_oobinfo nand_oob_64 = {
70 .useecc = MTD_NANDECC_AUTOPLACE,
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
79 /* This is used for padding purposes in nand_write_oob */
80 static uint8_t ffchars[] = {
81 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
82 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
83 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
84 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
85 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
86 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
87 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
88 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
92 * NAND low-level MTD interface functions
94 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
95 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
96 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
98 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
99 size_t *retlen, uint8_t *buf);
100 static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
101 size_t *retlen, uint8_t *buf);
102 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
103 size_t *retlen, const uint8_t *buf);
104 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
105 size_t *retlen, const uint8_t *buf);
106 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr);
107 static void nand_sync(struct mtd_info *mtd);
109 /* Some internal functions */
110 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
111 int page, uint8_t * oob_buf,
112 struct nand_oobinfo *oobsel, int mode);
113 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
114 static int nand_verify_pages(struct mtd_info *mtd, struct nand_chip *chip,
115 int page, int numpages, uint8_t *oob_buf,
116 struct nand_oobinfo *oobsel, int chipnr,
119 #define nand_verify_pages(...) (0)
122 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
126 * For devices which display every fart in the system on a seperate LED. Is
127 * compiled away when LED support is disabled.
129 DEFINE_LED_TRIGGER(nand_led_trigger);
132 * nand_release_device - [GENERIC] release chip
133 * @mtd: MTD device structure
135 * Deselect, release chip lock and wake up anyone waiting on the device
137 static void nand_release_device(struct mtd_info *mtd)
139 struct nand_chip *chip = mtd->priv;
141 /* De-select the NAND device */
142 chip->select_chip(mtd, -1);
144 /* Release the controller and the chip */
145 spin_lock(&chip->controller->lock);
146 chip->controller->active = NULL;
147 chip->state = FL_READY;
148 wake_up(&chip->controller->wq);
149 spin_unlock(&chip->controller->lock);
153 * nand_read_byte - [DEFAULT] read one byte from the chip
154 * @mtd: MTD device structure
156 * Default read function for 8bit buswith
158 static uint8_t nand_read_byte(struct mtd_info *mtd)
160 struct nand_chip *chip = mtd->priv;
161 return readb(chip->IO_ADDR_R);
165 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswith with
169 * endianess conversion
171 static uint8_t nand_read_byte16(struct mtd_info *mtd)
173 struct nand_chip *chip = mtd->priv;
174 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
178 * nand_read_word - [DEFAULT] read one word from the chip
179 * @mtd: MTD device structure
181 * Default read function for 16bit buswith without
182 * endianess conversion
184 static u16 nand_read_word(struct mtd_info *mtd)
186 struct nand_chip *chip = mtd->priv;
187 return readw(chip->IO_ADDR_R);
191 * nand_select_chip - [DEFAULT] control CE line
192 * @mtd: MTD device structure
193 * @chip: chipnumber to select, -1 for deselect
195 * Default select function for 1 chip devices.
197 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
199 struct nand_chip *chip = mtd->priv;
203 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
206 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
207 NAND_NCE | NAND_CTRL_CHANGE);
216 * nand_write_buf - [DEFAULT] write buffer to chip
217 * @mtd: MTD device structure
219 * @len: number of bytes to write
221 * Default write function for 8bit buswith
223 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
226 struct nand_chip *chip = mtd->priv;
228 for (i = 0; i < len; i++)
229 writeb(buf[i], chip->IO_ADDR_W);
233 * nand_read_buf - [DEFAULT] read chip data into buffer
234 * @mtd: MTD device structure
235 * @buf: buffer to store date
236 * @len: number of bytes to read
238 * Default read function for 8bit buswith
240 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
243 struct nand_chip *chip = mtd->priv;
245 for (i = 0; i < len; i++)
246 buf[i] = readb(chip->IO_ADDR_R);
250 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
251 * @mtd: MTD device structure
252 * @buf: buffer containing the data to compare
253 * @len: number of bytes to compare
255 * Default verify function for 8bit buswith
257 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
262 for (i = 0; i < len; i++)
263 if (buf[i] != readb(chip->IO_ADDR_R))
270 * nand_write_buf16 - [DEFAULT] write buffer to chip
271 * @mtd: MTD device structure
273 * @len: number of bytes to write
275 * Default write function for 16bit buswith
277 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
280 struct nand_chip *chip = mtd->priv;
281 u16 *p = (u16 *) buf;
284 for (i = 0; i < len; i++)
285 writew(p[i], chip->IO_ADDR_W);
290 * nand_read_buf16 - [DEFAULT] read chip data into buffer
291 * @mtd: MTD device structure
292 * @buf: buffer to store date
293 * @len: number of bytes to read
295 * Default read function for 16bit buswith
297 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
300 struct nand_chip *chip = mtd->priv;
301 u16 *p = (u16 *) buf;
304 for (i = 0; i < len; i++)
305 p[i] = readw(chip->IO_ADDR_R);
309 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
310 * @mtd: MTD device structure
311 * @buf: buffer containing the data to compare
312 * @len: number of bytes to compare
314 * Default verify function for 16bit buswith
316 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
319 struct nand_chip *chip = mtd->priv;
320 u16 *p = (u16 *) buf;
323 for (i = 0; i < len; i++)
324 if (p[i] != readw(chip->IO_ADDR_R))
331 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
332 * @mtd: MTD device structure
333 * @ofs: offset from device start
334 * @getchip: 0, if the chip is already selected
336 * Check, if the block is bad.
338 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
340 int page, chipnr, res = 0;
341 struct nand_chip *chip = mtd->priv;
345 page = (int)(ofs >> chip->page_shift);
346 chipnr = (int)(ofs >> chip->chip_shift);
348 nand_get_device(chip, mtd, FL_READING);
350 /* Select the NAND device */
351 chip->select_chip(mtd, chipnr);
355 if (chip->options & NAND_BUSWIDTH_16) {
356 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
357 page & chip->pagemask);
358 bad = cpu_to_le16(chip->read_word(mtd));
359 if (chip->badblockpos & 0x1)
361 if ((bad & 0xFF) != 0xff)
364 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
365 page & chip->pagemask);
366 if (chip->read_byte(mtd) != 0xff)
371 nand_release_device(mtd);
377 * nand_default_block_markbad - [DEFAULT] mark a block bad
378 * @mtd: MTD device structure
379 * @ofs: offset from device start
381 * This is the default implementation, which can be overridden by
382 * a hardware specific driver.
384 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
386 struct nand_chip *chip = mtd->priv;
387 uint8_t buf[2] = { 0, 0 };
391 /* Get block number */
392 block = ((int)ofs) >> chip->bbt_erase_shift;
394 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
396 /* Do we have a flash based bad block table ? */
397 if (chip->options & NAND_USE_FLASH_BBT)
398 return nand_update_bbt(mtd, ofs);
400 /* We write two bytes, so we dont have to mess with 16 bit access */
401 ofs += mtd->oobsize + (chip->badblockpos & ~0x01);
402 return nand_write_oob(mtd, ofs, 2, &retlen, buf);
406 * nand_check_wp - [GENERIC] check if the chip is write protected
407 * @mtd: MTD device structure
408 * Check, if the device is write protected
410 * The function expects, that the device is already selected
412 static int nand_check_wp(struct mtd_info *mtd)
414 struct nand_chip *chip = mtd->priv;
415 /* Check the WP bit */
416 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
417 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
421 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
422 * @mtd: MTD device structure
423 * @ofs: offset from device start
424 * @getchip: 0, if the chip is already selected
425 * @allowbbt: 1, if its allowed to access the bbt area
427 * Check, if the block is bad. Either by reading the bad block table or
428 * calling of the scan function.
430 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
433 struct nand_chip *chip = mtd->priv;
436 return chip->block_bad(mtd, ofs, getchip);
438 /* Return info from the table */
439 return nand_isbad_bbt(mtd, ofs, allowbbt);
443 * Wait for the ready pin, after a command
444 * The timeout is catched later.
446 static void nand_wait_ready(struct mtd_info *mtd)
448 struct nand_chip *chip = mtd->priv;
449 unsigned long timeo = jiffies + 2;
451 led_trigger_event(nand_led_trigger, LED_FULL);
452 /* wait until command is processed or timeout occures */
454 if (chip->dev_ready(mtd))
456 touch_softlockup_watchdog();
457 } while (time_before(jiffies, timeo));
458 led_trigger_event(nand_led_trigger, LED_OFF);
462 * nand_command - [DEFAULT] Send command to NAND device
463 * @mtd: MTD device structure
464 * @command: the command to be sent
465 * @column: the column address for this command, -1 if none
466 * @page_addr: the page address for this command, -1 if none
468 * Send command to NAND device. This function is used for small page
469 * devices (256/512 Bytes per page)
471 static void nand_command(struct mtd_info *mtd, unsigned int command,
472 int column, int page_addr)
474 register struct nand_chip *chip = mtd->priv;
475 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
478 * Write out the command to the device.
480 if (command == NAND_CMD_SEQIN) {
483 if (column >= mtd->writesize) {
485 column -= mtd->writesize;
486 readcmd = NAND_CMD_READOOB;
487 } else if (column < 256) {
488 /* First 256 bytes --> READ0 */
489 readcmd = NAND_CMD_READ0;
492 readcmd = NAND_CMD_READ1;
494 chip->cmd_ctrl(mtd, readcmd, ctrl);
495 ctrl &= ~NAND_CTRL_CHANGE;
497 chip->cmd_ctrl(mtd, command, ctrl);
500 * Address cycle, when necessary
502 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
503 /* Serially input address */
505 /* Adjust columns for 16 bit buswidth */
506 if (chip->options & NAND_BUSWIDTH_16)
508 chip->cmd_ctrl(mtd, column, ctrl);
509 ctrl &= ~NAND_CTRL_CHANGE;
511 if (page_addr != -1) {
512 chip->cmd_ctrl(mtd, page_addr, ctrl);
513 ctrl &= ~NAND_CTRL_CHANGE;
514 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
515 /* One more address cycle for devices > 32MiB */
516 if (chip->chipsize > (32 << 20))
517 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
519 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
522 * program and erase have their own busy handlers
523 * status and sequential in needs no delay
527 case NAND_CMD_PAGEPROG:
528 case NAND_CMD_ERASE1:
529 case NAND_CMD_ERASE2:
531 case NAND_CMD_STATUS:
532 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
538 udelay(chip->chip_delay);
539 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
540 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
542 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
543 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
546 /* This applies to read commands */
549 * If we don't have access to the busy pin, we apply the given
552 if (!chip->dev_ready) {
553 udelay(chip->chip_delay);
557 /* Apply this short delay always to ensure that we do wait tWB in
558 * any case on any machine. */
561 nand_wait_ready(mtd);
565 * nand_command_lp - [DEFAULT] Send command to NAND large page device
566 * @mtd: MTD device structure
567 * @command: the command to be sent
568 * @column: the column address for this command, -1 if none
569 * @page_addr: the page address for this command, -1 if none
571 * Send command to NAND device. This is the version for the new large page
572 * devices We dont have the separate regions as we have in the small page
573 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
576 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
577 int column, int page_addr)
579 register struct nand_chip *chip = mtd->priv;
581 /* Emulate NAND_CMD_READOOB */
582 if (command == NAND_CMD_READOOB) {
583 column += mtd->writesize;
584 command = NAND_CMD_READ0;
587 /* Command latch cycle */
588 chip->cmd_ctrl(mtd, command & 0xff,
589 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
591 if (column != -1 || page_addr != -1) {
592 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
594 /* Serially input address */
596 /* Adjust columns for 16 bit buswidth */
597 if (chip->options & NAND_BUSWIDTH_16)
599 chip->cmd_ctrl(mtd, column, ctrl);
600 ctrl &= ~NAND_CTRL_CHANGE;
601 chip->cmd_ctrl(mtd, column >> 8, ctrl);
603 if (page_addr != -1) {
604 chip->cmd_ctrl(mtd, page_addr, ctrl);
605 chip->cmd_ctrl(mtd, page_addr >> 8,
606 NAND_NCE | NAND_ALE);
607 /* One more address cycle for devices > 128MiB */
608 if (chip->chipsize > (128 << 20))
609 chip->cmd_ctrl(mtd, page_addr >> 16,
610 NAND_NCE | NAND_ALE);
613 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
616 * program and erase have their own busy handlers
617 * status, sequential in, and deplete1 need no delay
621 case NAND_CMD_CACHEDPROG:
622 case NAND_CMD_PAGEPROG:
623 case NAND_CMD_ERASE1:
624 case NAND_CMD_ERASE2:
626 case NAND_CMD_STATUS:
627 case NAND_CMD_DEPLETE1:
631 * read error status commands require only a short delay
633 case NAND_CMD_STATUS_ERROR:
634 case NAND_CMD_STATUS_ERROR0:
635 case NAND_CMD_STATUS_ERROR1:
636 case NAND_CMD_STATUS_ERROR2:
637 case NAND_CMD_STATUS_ERROR3:
638 udelay(chip->chip_delay);
644 udelay(chip->chip_delay);
645 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
646 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
647 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
648 NAND_NCE | NAND_CTRL_CHANGE);
649 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
653 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
654 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
655 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
656 NAND_NCE | NAND_CTRL_CHANGE);
658 /* This applies to read commands */
661 * If we don't have access to the busy pin, we apply the given
664 if (!chip->dev_ready) {
665 udelay(chip->chip_delay);
670 /* Apply this short delay always to ensure that we do wait tWB in
671 * any case on any machine. */
674 nand_wait_ready(mtd);
678 * nand_get_device - [GENERIC] Get chip for selected access
679 * @this: the nand chip descriptor
680 * @mtd: MTD device structure
681 * @new_state: the state which is requested
683 * Get the device and lock it for exclusive access
686 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
688 spinlock_t *lock = &chip->controller->lock;
689 wait_queue_head_t *wq = &chip->controller->wq;
690 DECLARE_WAITQUEUE(wait, current);
694 /* Hardware controller shared among independend devices */
695 /* Hardware controller shared among independend devices */
696 if (!chip->controller->active)
697 chip->controller->active = chip;
699 if (chip->controller->active == chip && chip->state == FL_READY) {
700 chip->state = new_state;
704 if (new_state == FL_PM_SUSPENDED) {
706 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
708 set_current_state(TASK_UNINTERRUPTIBLE);
709 add_wait_queue(wq, &wait);
712 remove_wait_queue(wq, &wait);
717 * nand_wait - [DEFAULT] wait until the command is done
718 * @mtd: MTD device structure
719 * @this: NAND chip structure
720 * @state: state to select the max. timeout value
722 * Wait for command done. This applies to erase and program only
723 * Erase can take up to 400ms and program up to 20ms according to
724 * general NAND and SmartMedia specs
727 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
730 unsigned long timeo = jiffies;
733 if (state == FL_ERASING)
734 timeo += (HZ * 400) / 1000;
736 timeo += (HZ * 20) / 1000;
738 led_trigger_event(nand_led_trigger, LED_FULL);
740 /* Apply this short delay always to ensure that we do wait tWB in
741 * any case on any machine. */
744 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
745 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
747 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
749 while (time_before(jiffies, timeo)) {
750 /* Check, if we were interrupted */
751 if (chip->state != state)
754 if (chip->dev_ready) {
755 if (chip->dev_ready(mtd))
758 if (chip->read_byte(mtd) & NAND_STATUS_READY)
763 led_trigger_event(nand_led_trigger, LED_OFF);
765 status = (int)chip->read_byte(mtd);
770 * nand_write_page - [GENERIC] write one page
771 * @mtd: MTD device structure
772 * @this: NAND chip structure
773 * @page: startpage inside the chip, must be called with (page & chip->pagemask)
774 * @oob_buf: out of band data buffer
775 * @oobsel: out of band selecttion structre
776 * @cached: 1 = enable cached programming if supported by chip
778 * Nand_page_program function is used for write and writev !
779 * This function will always program a full page of data
780 * If you call it with a non page aligned buffer, you're lost :)
782 * Cached programming is not supported yet.
784 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, int page,
785 uint8_t *oob_buf, struct nand_oobinfo *oobsel, int cached)
788 uint8_t ecc_code[32];
789 int eccmode = oobsel->useecc ? chip->ecc.mode : NAND_ECC_NONE;
790 int *oob_config = oobsel->eccpos;
791 int datidx = 0, eccidx = 0, eccsteps = chip->ecc.steps;
794 /* FIXME: Enable cached programming */
797 /* Send command to begin auto page programming */
798 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
800 /* Write out complete page of data, take care of eccmode */
802 /* No ecc, write all */
804 printk(KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
805 chip->write_buf(mtd, chip->data_poi, mtd->writesize);
808 /* Software ecc 3/256, write all */
810 for (; eccsteps; eccsteps--) {
811 chip->ecc.calculate(mtd, &chip->data_poi[datidx], ecc_code);
812 for (i = 0; i < 3; i++, eccidx++)
813 oob_buf[oob_config[eccidx]] = ecc_code[i];
814 datidx += chip->ecc.size;
816 chip->write_buf(mtd, chip->data_poi, mtd->writesize);
819 eccbytes = chip->ecc.bytes;
820 for (; eccsteps; eccsteps--) {
821 /* enable hardware ecc logic for write */
822 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
823 chip->write_buf(mtd, &chip->data_poi[datidx], chip->ecc.size);
824 chip->ecc.calculate(mtd, &chip->data_poi[datidx], ecc_code);
825 for (i = 0; i < eccbytes; i++, eccidx++)
826 oob_buf[oob_config[eccidx]] = ecc_code[i];
827 /* If the hardware ecc provides syndromes then
828 * the ecc code must be written immidiately after
829 * the data bytes (words) */
830 if (chip->options & NAND_HWECC_SYNDROME)
831 chip->write_buf(mtd, ecc_code, eccbytes);
832 datidx += chip->ecc.size;
837 /* Write out OOB data */
838 if (chip->options & NAND_HWECC_SYNDROME)
839 chip->write_buf(mtd, &oob_buf[oobsel->eccbytes], mtd->oobsize - oobsel->eccbytes);
841 chip->write_buf(mtd, oob_buf, mtd->oobsize);
843 /* Send command to actually program the data */
844 chip->cmdfunc(mtd, cached ? NAND_CMD_CACHEDPROG : NAND_CMD_PAGEPROG, -1, -1);
847 /* call wait ready function */
848 status = chip->waitfunc(mtd, chip, FL_WRITING);
850 /* See if operation failed and additional status checks are available */
851 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) {
852 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
855 /* See if device thinks it succeeded */
856 if (status & NAND_STATUS_FAIL) {
857 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
861 /* FIXME: Implement cached programming ! */
862 /* wait until cache is ready */
863 // status = chip->waitfunc (mtd, this, FL_CACHEDRPG);
868 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
870 * nand_verify_pages - [GENERIC] verify the chip contents after a write
871 * @mtd: MTD device structure
872 * @this: NAND chip structure
873 * @page: startpage inside the chip, must be called with (page & chip->pagemask)
874 * @numpages: number of pages to verify
875 * @oob_buf: out of band data buffer
876 * @oobsel: out of band selecttion structre
877 * @chipnr: number of the current chip
878 * @oobmode: 1 = full buffer verify, 0 = ecc only
880 * The NAND device assumes that it is always writing to a cleanly erased page.
881 * Hence, it performs its internal write verification only on bits that
882 * transitioned from 1 to 0. The device does NOT verify the whole page on a
883 * byte by byte basis. It is possible that the page was not completely erased
884 * or the page is becoming unusable due to wear. The read with ECC would catch
885 * the error later when the ECC page check fails, but we would rather catch
886 * it early in the page write stage. Better to write no data than invalid data.
888 static int nand_verify_pages(struct mtd_info *mtd, struct nand_chip *chip, int page, int numpages,
889 uint8_t *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode)
891 int i, j, datidx = 0, oobofs = 0, res = -EIO;
892 int eccsteps = chip->eccsteps;
896 hweccbytes = (chip->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0;
898 /* Send command to read back the first page */
899 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
902 for (j = 0; j < eccsteps; j++) {
903 /* Loop through and verify the data */
904 if (chip->verify_buf(mtd, &chip->data_poi[datidx], mtd->eccsize)) {
905 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
908 datidx += mtd->eccsize;
909 /* Have we a hw generator layout ? */
912 if (chip->verify_buf(mtd, &chip->oob_buf[oobofs], hweccbytes)) {
913 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
916 oobofs += hweccbytes;
919 /* check, if we must compare all data or if we just have to
920 * compare the ecc bytes
923 if (chip->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) {
924 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
928 /* Read always, else autoincrement fails */
929 chip->read_buf(mtd, oobdata, mtd->oobsize - hweccbytes * eccsteps);
931 if (oobsel->useecc != MTD_NANDECC_OFF && !hweccbytes) {
932 int ecccnt = oobsel->eccbytes;
934 for (i = 0; i < ecccnt; i++) {
935 int idx = oobsel->eccpos[i];
936 if (oobdata[idx] != oob_buf[oobofs + idx]) {
937 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed ECC write verify, page 0x%08x, %6i bytes were succesful\n",
938 __FUNCTION__, page, i);
944 oobofs += mtd->oobsize - hweccbytes * eccsteps;
948 /* Apply delay or wait for ready/busy pin
949 * Do this before the AUTOINCR check, so no problems
950 * arise if a chip which does auto increment
951 * is marked as NOAUTOINCR by the board driver.
952 * Do this also before returning, so the chip is
953 * ready for the next command.
955 if (!chip->dev_ready)
956 udelay(chip->chip_delay);
958 nand_wait_ready(mtd);
960 /* All done, return happy */
964 /* Check, if the chip supports auto page increment */
965 if (!NAND_CANAUTOINCR(this))
966 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
969 * Terminate the read command. We come here in case of an error
970 * So we must issue a reset command.
973 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
979 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
980 * @mtd: MTD device structure
981 * @from: offset to read from
982 * @len: number of bytes to read
983 * @retlen: pointer to variable to store the number of read bytes
984 * @buf: the databuffer to put data
986 * This function simply calls nand_do_read_ecc with oob buffer and oobsel = NULL
989 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, uint8_t *buf)
991 return nand_do_read_ecc(mtd, from, len, retlen, buf, NULL, &mtd->oobinfo, 0xff);
995 * nand_do_read_ecc - [MTD Interface] Read data with ECC
996 * @mtd: MTD device structure
997 * @from: offset to read from
998 * @len: number of bytes to read
999 * @retlen: pointer to variable to store the number of read bytes
1000 * @buf: the databuffer to put data
1001 * @oob_buf: filesystem supplied oob data buffer (can be NULL)
1002 * @oobsel: oob selection structure
1003 * @flags: flag to indicate if nand_get_device/nand_release_device should be preformed
1004 * and how many corrected error bits are acceptable:
1005 * bits 0..7 - number of tolerable errors
1006 * bit 8 - 0 == do not get/release chip, 1 == get/release chip
1008 * NAND read with ECC
1010 int nand_do_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
1011 size_t *retlen, uint8_t *buf, uint8_t *oob_buf, struct nand_oobinfo *oobsel, int flags)
1014 int i, j, col, realpage, page, end, ecc, chipnr, sndcmd = 1;
1015 int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0;
1016 struct nand_chip *chip = mtd->priv;
1017 uint8_t *data_poi, *oob_data = oob_buf;
1018 uint8_t ecc_calc[32];
1019 uint8_t ecc_code[32];
1020 int eccmode, eccsteps;
1021 int *oob_config, datidx;
1022 int blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1027 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int)from, (int)len);
1029 /* Do not allow reads past end of device */
1030 if ((from + len) > mtd->size) {
1031 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
1036 /* Grab the lock and see if the device is available */
1037 if (flags & NAND_GET_DEVICE)
1038 nand_get_device(chip, mtd, FL_READING);
1040 /* Autoplace of oob data ? Use the default placement scheme */
1041 if (oobsel->useecc == MTD_NANDECC_AUTOPLACE)
1042 oobsel = chip->autooob;
1044 eccmode = oobsel->useecc ? chip->ecc.mode : NAND_ECC_NONE;
1045 oob_config = oobsel->eccpos;
1047 /* Select the NAND device */
1048 chipnr = (int)(from >> chip->chip_shift);
1049 chip->select_chip(mtd, chipnr);
1051 /* First we calculate the starting page */
1052 realpage = (int)(from >> chip->page_shift);
1053 page = realpage & chip->pagemask;
1055 /* Get raw starting column */
1056 col = from & (mtd->writesize - 1);
1058 end = mtd->writesize;
1059 ecc = chip->ecc.size;
1060 eccbytes = chip->ecc.bytes;
1062 if ((eccmode == NAND_ECC_NONE) || (chip->options & NAND_HWECC_SYNDROME))
1065 oobreadlen = mtd->oobsize;
1066 if (chip->options & NAND_HWECC_SYNDROME)
1067 oobreadlen -= oobsel->eccbytes;
1069 /* Loop until all data read */
1070 while (read < len) {
1072 int aligned = (!col && (len - read) >= end);
1074 * If the read is not page aligned, we have to read into data buffer
1075 * due to ecc, else we read into return buffer direct
1078 data_poi = &buf[read];
1080 data_poi = chip->data_buf;
1082 /* Check, if we have this page in the buffer
1084 * FIXME: Make it work when we must provide oob data too,
1085 * check the usage of data_buf oob field
1087 if (realpage == chip->pagebuf && !oob_buf) {
1088 /* aligned read ? */
1090 memcpy(data_poi, chip->data_buf, end);
1094 /* Check, if we must send the read command */
1096 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1100 /* get oob area, if we have no oob buffer from fs-driver */
1101 if (!oob_buf || oobsel->useecc == MTD_NANDECC_AUTOPLACE ||
1102 oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
1103 oob_data = &chip->data_buf[end];
1105 eccsteps = chip->ecc.steps;
1108 case NAND_ECC_NONE:{
1109 /* No ECC, Read in a page */
1110 static unsigned long lastwhinge = 0;
1111 if ((lastwhinge / HZ) != (jiffies / HZ)) {
1113 "Reading data from NAND FLASH without ECC is not recommended\n");
1114 lastwhinge = jiffies;
1116 chip->read_buf(mtd, data_poi, end);
1120 case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */
1121 chip->read_buf(mtd, data_poi, end);
1122 for (i = 0, datidx = 0; eccsteps; eccsteps--, i += 3, datidx += ecc)
1123 chip->ecc.calculate(mtd, &data_poi[datidx], &ecc_calc[i]);
1127 for (i = 0, datidx = 0; eccsteps; eccsteps--, i += eccbytes, datidx += ecc) {
1128 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1129 chip->read_buf(mtd, &data_poi[datidx], ecc);
1131 /* HW ecc with syndrome calculation must read the
1132 * syndrome from flash immidiately after the data */
1134 /* Some hw ecc generators need to know when the
1135 * syndrome is read from flash */
1136 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1137 chip->read_buf(mtd, &oob_data[i], eccbytes);
1138 /* We calc error correction directly, it checks the hw
1139 * generator for an error, reads back the syndrome and
1140 * does the error correction on the fly */
1141 ecc_status = chip->ecc.correct(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]);
1142 if ((ecc_status == -1) || (ecc_status > (flags && 0xff))) {
1143 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_ecc: "
1144 "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr);
1148 chip->ecc.calculate(mtd, &data_poi[datidx], &ecc_calc[i]);
1155 chip->read_buf(mtd, &oob_data[mtd->oobsize - oobreadlen], oobreadlen);
1157 /* Skip ECC check, if not requested (ECC_NONE or HW_ECC with syndromes) */
1161 /* Pick the ECC bytes out of the oob data */
1162 for (j = 0; j < oobsel->eccbytes; j++)
1163 ecc_code[j] = oob_data[oob_config[j]];
1165 /* correct data, if necessary */
1166 for (i = 0, j = 0, datidx = 0; i < chip->ecc.steps; i++, datidx += ecc) {
1167 ecc_status = chip->ecc.correct(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]);
1169 /* Get next chunk of ecc bytes */
1172 /* Check, if we have a fs supplied oob-buffer,
1173 * This is the legacy mode. Used by YAFFS1
1174 * Should go away some day
1176 if (oob_buf && oobsel->useecc == MTD_NANDECC_PLACE) {
1177 int *p = (int *)(&oob_data[mtd->oobsize]);
1181 if ((ecc_status == -1) || (ecc_status > (flags && 0xff))) {
1182 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
1188 /* check, if we have a fs supplied oob-buffer */
1190 /* without autoplace. Legacy mode used by YAFFS1 */
1191 switch (oobsel->useecc) {
1192 case MTD_NANDECC_AUTOPLACE:
1193 case MTD_NANDECC_AUTOPL_USR:
1194 /* Walk through the autoplace chunks */
1195 for (i = 0; oobsel->oobfree[i][1]; i++) {
1196 int from = oobsel->oobfree[i][0];
1197 int num = oobsel->oobfree[i][1];
1198 memcpy(&oob_buf[oob], &oob_data[from], num);
1202 case MTD_NANDECC_PLACE:
1203 /* YAFFS1 legacy mode */
1204 oob_data += chip->ecc.steps * sizeof(int);
1206 oob_data += mtd->oobsize;
1210 /* Partial page read, transfer data into fs buffer */
1212 for (j = col; j < end && read < len; j++)
1213 buf[read++] = data_poi[j];
1214 chip->pagebuf = realpage;
1216 read += mtd->writesize;
1218 /* Apply delay or wait for ready/busy pin
1219 * Do this before the AUTOINCR check, so no problems
1220 * arise if a chip which does auto increment
1221 * is marked as NOAUTOINCR by the board driver.
1223 if (!chip->dev_ready)
1224 udelay(chip->chip_delay);
1226 nand_wait_ready(mtd);
1231 /* For subsequent reads align to page boundary. */
1233 /* Increment page address */
1236 page = realpage & chip->pagemask;
1237 /* Check, if we cross a chip boundary */
1240 chip->select_chip(mtd, -1);
1241 chip->select_chip(mtd, chipnr);
1243 /* Check, if the chip supports auto page increment
1244 * or if we have hit a block boundary.
1246 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck))
1250 /* Deselect and wake up anyone waiting on the device */
1251 if (flags & NAND_GET_DEVICE)
1252 nand_release_device(mtd);
1255 * Return success, if no ECC failures, else -EBADMSG
1256 * fs driver will take care of that, because
1257 * retlen == desired len and result == -EBADMSG
1260 return ecc_failed ? -EBADMSG : 0;
1264 * nand_read_oob - [MTD Interface] NAND read out-of-band
1265 * @mtd: MTD device structure
1266 * @from: offset to read from
1267 * @len: number of bytes to read
1268 * @retlen: pointer to variable to store the number of read bytes
1269 * @buf: the databuffer to put data
1271 * NAND read out-of-band data from the spare area
1273 static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
1274 size_t *retlen, uint8_t *buf)
1276 int col, page, realpage, chipnr, sndcmd = 1;
1277 struct nand_chip *chip = mtd->priv;
1278 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1281 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n",
1282 (unsigned int)from, (int)len);
1284 /* Initialize return length value */
1287 /* Do not allow reads past end of device */
1288 if ((from + len) > mtd->size) {
1289 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1290 "Attempt read beyond end of device\n");
1294 nand_get_device(chip, mtd, FL_READING);
1296 chipnr = (int)(from >> chip->chip_shift);
1297 chip->select_chip(mtd, chipnr);
1299 /* Shift to get page */
1300 realpage = (int)(from >> chip->page_shift);
1301 page = realpage & chip->pagemask;
1303 /* Mask to get column */
1304 col = from & (mtd->oobsize - 1);
1307 int bytes = min((int)(mtd->oobsize - col), readlen);
1309 if (likely(sndcmd)) {
1310 chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page);
1314 chip->read_buf(mtd, buf, bytes);
1320 if (!(chip->options & NAND_NO_READRDY)) {
1322 * Apply delay or wait for ready/busy pin. Do this
1323 * before the AUTOINCR check, so no problems arise if a
1324 * chip which does auto increment is marked as
1325 * NOAUTOINCR by the board driver.
1327 if (!chip->dev_ready)
1328 udelay(chip->chip_delay);
1330 nand_wait_ready(mtd);
1334 bytes = mtd->oobsize;
1337 /* Increment page address */
1340 page = realpage & chip->pagemask;
1341 /* Check, if we cross a chip boundary */
1344 chip->select_chip(mtd, -1);
1345 chip->select_chip(mtd, chipnr);
1348 /* Check, if the chip supports auto page increment
1349 * or if we have hit a block boundary.
1351 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1355 /* Deselect and wake up anyone waiting on the device */
1356 nand_release_device(mtd);
1363 * nand_read_raw - [GENERIC] Read raw data including oob into buffer
1364 * @mtd: MTD device structure
1365 * @buf: temporary buffer
1366 * @from: offset to read from
1367 * @len: number of bytes to read
1368 * @ooblen: number of oob data bytes to read
1370 * Read raw data including oob into buffer
1372 int nand_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len,
1375 struct nand_chip *chip = mtd->priv;
1376 int page = (int)(from >> chip->page_shift);
1377 int chipnr = (int)(from >> chip->chip_shift);
1380 int pagesize = mtd->writesize + mtd->oobsize;
1383 /* Do not allow reads past end of device */
1384 if ((from + len) > mtd->size) {
1385 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: "
1386 "Attempt read beyond end of device\n");
1390 /* Grab the lock and see if the device is available */
1391 nand_get_device(chip, mtd, FL_READING);
1393 chip->select_chip(mtd, chipnr);
1395 /* Add requested oob length */
1397 blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1401 chip->cmdfunc(mtd, NAND_CMD_READ0, 0,
1402 page & chip->pagemask);
1405 chip->read_buf(mtd, &buf[cnt], pagesize);
1411 if (!chip->dev_ready)
1412 udelay(chip->chip_delay);
1414 nand_wait_ready(mtd);
1417 * Check, if the chip supports auto page increment or if we
1418 * cross a block boundary.
1420 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck))
1424 /* Deselect and wake up anyone waiting on the device */
1425 nand_release_device(mtd);
1430 * nand_write_raw - [GENERIC] Write raw data including oob
1431 * @mtd: MTD device structure
1432 * @buf: source buffer
1433 * @to: offset to write to
1434 * @len: number of bytes to write
1435 * @buf: source buffer
1438 * Write raw data including oob
1440 int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
1441 uint8_t *buf, uint8_t *oob)
1443 struct nand_chip *chip = mtd->priv;
1444 int page = (int)(to >> chip->page_shift);
1445 int chipnr = (int)(to >> chip->chip_shift);
1450 /* Do not allow writes past end of device */
1451 if ((to + len) > mtd->size) {
1452 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt write "
1453 "beyond end of device\n");
1457 /* Grab the lock and see if the device is available */
1458 nand_get_device(chip, mtd, FL_WRITING);
1460 chip->select_chip(mtd, chipnr);
1461 chip->data_poi = buf;
1463 while (len != *retlen) {
1464 ret = nand_write_page(mtd, chip, page, oob, &mtd->oobinfo, 0);
1468 *retlen += mtd->writesize;
1469 chip->data_poi += mtd->writesize;
1470 oob += mtd->oobsize;
1473 /* Deselect and wake up anyone waiting on the device */
1474 nand_release_device(mtd);
1477 EXPORT_SYMBOL_GPL(nand_write_raw);
1480 * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer
1481 * @mtd: MTD device structure
1482 * @fsbuf: buffer given by fs driver
1483 * @oobsel: out of band selection structre
1484 * @autoplace: 1 = place given buffer into the oob bytes
1485 * @numpages: number of pages to prepare
1488 * 1. Filesystem buffer available and autoplacement is off,
1489 * return filesystem buffer
1490 * 2. No filesystem buffer or autoplace is off, return internal
1492 * 3. Filesystem buffer is given and autoplace selected
1493 * put data from fs buffer into internal buffer and
1494 * retrun internal buffer
1496 * Note: The internal buffer is filled with 0xff. This must
1497 * be done only once, when no autoplacement happens
1498 * Autoplacement sets the buffer dirty flag, which
1499 * forces the 0xff fill before using the buffer again.
1502 static uint8_t *nand_prepare_oobbuf(struct mtd_info *mtd, uint8_t *fsbuf, struct nand_oobinfo *oobsel,
1503 int autoplace, int numpages)
1505 struct nand_chip *chip = mtd->priv;
1508 /* Zero copy fs supplied buffer */
1509 if (fsbuf && !autoplace)
1512 /* Check, if the buffer must be filled with ff again */
1513 if (chip->oobdirty) {
1514 memset(chip->oob_buf, 0xff, mtd->oobsize << (chip->phys_erase_shift - chip->page_shift));
1518 /* If we have no autoplacement or no fs buffer use the internal one */
1519 if (!autoplace || !fsbuf)
1520 return chip->oob_buf;
1522 /* Walk through the pages and place the data */
1525 while (numpages--) {
1526 for (i = 0, len = 0; len < mtd->oobavail; i++) {
1527 int to = ofs + oobsel->oobfree[i][0];
1528 int num = oobsel->oobfree[i][1];
1529 memcpy(&chip->oob_buf[to], fsbuf, num);
1533 ofs += mtd->oobavail;
1535 return chip->oob_buf;
1538 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
1541 * nand_write - [MTD Interface] NAND write with ECC
1542 * @mtd: MTD device structure
1543 * @to: offset to write to
1544 * @len: number of bytes to write
1545 * @retlen: pointer to variable to store the number of written bytes
1546 * @buf: the data to write
1548 * NAND write with ECC
1550 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1551 size_t *retlen, const uint8_t *buf)
1553 int startpage, page, ret = -EIO, oob = 0, written = 0, chipnr;
1554 int autoplace = 0, numpages, totalpages;
1555 struct nand_chip *chip = mtd->priv;
1556 uint8_t *oobbuf, *bufstart, *eccbuf = NULL;
1557 int ppblock = (1 << (chip->phys_erase_shift - chip->page_shift));
1558 struct nand_oobinfo *oobsel = &mtd->oobinfo;
1560 DEBUG(MTD_DEBUG_LEVEL3, "nand_write: to = 0x%08x, len = %i\n", (unsigned int)to, (int)len);
1562 /* Initialize retlen, in case of early exit */
1565 /* Do not allow write past end of device */
1566 if ((to + len) > mtd->size) {
1567 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: Attempt to write past end of page\n");
1571 /* reject writes, which are not page aligned */
1572 if (NOTALIGNED(to) || NOTALIGNED(len)) {
1573 printk(KERN_NOTICE "nand_write: Attempt to write not page aligned data\n");
1577 /* Grab the lock and see if the device is available */
1578 nand_get_device(chip, mtd, FL_WRITING);
1580 /* Calculate chipnr */
1581 chipnr = (int)(to >> chip->chip_shift);
1582 /* Select the NAND device */
1583 chip->select_chip(mtd, chipnr);
1585 /* Check, if it is write protected */
1586 if (nand_check_wp(mtd))
1589 /* Autoplace of oob data ? Use the default placement scheme */
1590 if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) {
1591 oobsel = chip->autooob;
1594 if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
1597 /* Setup variables and oob buffer */
1598 totalpages = len >> chip->page_shift;
1599 page = (int)(to >> chip->page_shift);
1600 /* Invalidate the page cache, if we write to the cached page */
1601 if (page <= chip->pagebuf && chip->pagebuf < (page + totalpages))
1604 /* Set it relative to chip */
1605 page &= chip->pagemask;
1607 /* Calc number of pages we can write in one go */
1608 numpages = min(ppblock - (startpage & (ppblock - 1)), totalpages);
1609 oobbuf = nand_prepare_oobbuf(mtd, eccbuf, oobsel, autoplace, numpages);
1610 bufstart = (uint8_t *) buf;
1612 /* Loop until all data is written */
1613 while (written < len) {
1615 chip->data_poi = (uint8_t *) &buf[written];
1616 /* Write one page. If this is the last page to write
1617 * or the last page in this block, then use the
1618 * real pageprogram command, else select cached programming
1619 * if supported by the chip.
1621 ret = nand_write_page(mtd, chip, page, &oobbuf[oob], oobsel, (--numpages > 0));
1623 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: write_page failed %d\n", ret);
1627 oob += mtd->oobsize;
1628 /* Update written bytes count */
1629 written += mtd->writesize;
1633 /* Increment page address */
1636 /* Have we hit a block boundary ? Then we have to verify and
1637 * if verify is ok, we have to setup the oob buffer for
1640 if (!(page & (ppblock - 1))) {
1642 chip->data_poi = bufstart;
1643 ret = nand_verify_pages(mtd, this, startpage, page - startpage,
1644 oobbuf, oobsel, chipnr, (eccbuf != NULL));
1646 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: verify_pages failed %d\n", ret);
1651 ofs = autoplace ? mtd->oobavail : mtd->oobsize;
1653 eccbuf += (page - startpage) * ofs;
1654 totalpages -= page - startpage;
1655 numpages = min(totalpages, ppblock);
1656 page &= chip->pagemask;
1658 oobbuf = nand_prepare_oobbuf(mtd, eccbuf, oobsel, autoplace, numpages);
1660 /* Check, if we cross a chip boundary */
1663 chip->select_chip(mtd, -1);
1664 chip->select_chip(mtd, chipnr);
1668 /* Verify the remaining pages */
1670 chip->data_poi = bufstart;
1671 ret = nand_verify_pages(mtd, this, startpage, totalpages, oobbuf, oobsel, chipnr, (eccbuf != NULL));
1675 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: verify_pages failed %d\n", ret);
1678 /* Deselect and wake up anyone waiting on the device */
1679 nand_release_device(mtd);
1686 * nand_write_oob - [MTD Interface] NAND write out-of-band
1687 * @mtd: MTD device structure
1688 * @to: offset to write to
1689 * @len: number of bytes to write
1690 * @retlen: pointer to variable to store the number of written bytes
1691 * @buf: the data to write
1693 * NAND write out-of-band
1695 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
1696 size_t *retlen, const uint8_t *buf)
1698 int column, page, status, ret = -EIO, chipnr;
1699 struct nand_chip *chip = mtd->priv;
1701 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1702 (unsigned int)to, (int)len);
1704 /* Initialize return length value */
1707 /* Do not allow write past end of page */
1708 column = to & (mtd->oobsize - 1);
1709 if ((column + len) > mtd->oobsize) {
1710 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1711 "Attempt to write past end of page\n");
1715 nand_get_device(chip, mtd, FL_WRITING);
1717 chipnr = (int)(to >> chip->chip_shift);
1718 chip->select_chip(mtd, chipnr);
1720 /* Shift to get page */
1721 page = (int)(to >> chip->page_shift);
1724 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1725 * of my DiskOnChip 2000 test units) will clear the whole data page too
1726 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1727 * it in the doc2000 driver in August 1999. dwmw2.
1729 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1731 /* Check, if it is write protected */
1732 if (nand_check_wp(mtd))
1735 /* Invalidate the page cache, if we write to the cached page */
1736 if (page == chip->pagebuf)
1739 if (NAND_MUST_PAD(chip)) {
1740 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize,
1741 page & chip->pagemask);
1742 /* prepad 0xff for partial programming */
1743 chip->write_buf(mtd, ffchars, column);
1745 chip->write_buf(mtd, buf, len);
1746 /* postpad 0xff for partial programming */
1747 chip->write_buf(mtd, ffchars, mtd->oobsize - (len + column));
1749 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize + column,
1750 page & chip->pagemask);
1751 chip->write_buf(mtd, buf, len);
1753 /* Send command to program the OOB data */
1754 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1756 status = chip->waitfunc(mtd, chip, FL_WRITING);
1758 /* See if device thinks it succeeded */
1759 if (status & NAND_STATUS_FAIL) {
1760 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1761 "Failed write, page 0x%08x\n", page);
1767 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1768 /* Send command to read back the data */
1769 chip->cmdfunc(mtd, NAND_CMD_READOOB, column, page & chip->pagemask);
1771 if (chip->verify_buf(mtd, buf, len)) {
1772 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1773 "Failed write verify, page 0x%08x\n", page);
1780 /* Deselect and wake up anyone waiting on the device */
1781 nand_release_device(mtd);
1787 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1788 * @mtd: MTD device structure
1789 * @page: the page address of the block which will be erased
1791 * Standard erase command for NAND chips
1793 static void single_erase_cmd(struct mtd_info *mtd, int page)
1795 struct nand_chip *chip = mtd->priv;
1796 /* Send commands to erase a block */
1797 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1798 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1802 * multi_erease_cmd - [GENERIC] AND specific block erase command function
1803 * @mtd: MTD device structure
1804 * @page: the page address of the block which will be erased
1806 * AND multi block erase command function
1807 * Erase 4 consecutive blocks
1809 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1811 struct nand_chip *chip = mtd->priv;
1812 /* Send commands to erase a block */
1813 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1814 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1815 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1816 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1817 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1821 * nand_erase - [MTD Interface] erase block(s)
1822 * @mtd: MTD device structure
1823 * @instr: erase instruction
1825 * Erase one ore more blocks
1827 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1829 return nand_erase_nand(mtd, instr, 0);
1832 #define BBT_PAGE_MASK 0xffffff3f
1834 * nand_erase_nand - [Internal] erase block(s)
1835 * @mtd: MTD device structure
1836 * @instr: erase instruction
1837 * @allowbbt: allow erasing the bbt area
1839 * Erase one ore more blocks
1841 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1844 int page, len, status, pages_per_block, ret, chipnr;
1845 struct nand_chip *chip = mtd->priv;
1846 int rewrite_bbt[NAND_MAX_CHIPS]={0};
1847 unsigned int bbt_masked_page = 0xffffffff;
1849 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1850 (unsigned int)instr->addr, (unsigned int)instr->len);
1852 /* Start address must align on block boundary */
1853 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1854 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1858 /* Length must align on block boundary */
1859 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1860 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1861 "Length not block aligned\n");
1865 /* Do not allow erase past end of device */
1866 if ((instr->len + instr->addr) > mtd->size) {
1867 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1868 "Erase past end of device\n");
1872 instr->fail_addr = 0xffffffff;
1874 /* Grab the lock and see if the device is available */
1875 nand_get_device(chip, mtd, FL_ERASING);
1877 /* Shift to get first page */
1878 page = (int)(instr->addr >> chip->page_shift);
1879 chipnr = (int)(instr->addr >> chip->chip_shift);
1881 /* Calculate pages in each block */
1882 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1884 /* Select the NAND device */
1885 chip->select_chip(mtd, chipnr);
1887 /* Check, if it is write protected */
1888 if (nand_check_wp(mtd)) {
1889 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1890 "Device is write protected!!!\n");
1891 instr->state = MTD_ERASE_FAILED;
1896 * If BBT requires refresh, set the BBT page mask to see if the BBT
1897 * should be rewritten. Otherwise the mask is set to 0xffffffff which
1898 * can not be matched. This is also done when the bbt is actually
1899 * erased to avoid recusrsive updates
1901 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1902 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1904 /* Loop through the pages */
1907 instr->state = MTD_ERASING;
1911 * heck if we have a bad block, we do not erase bad blocks !
1913 if (nand_block_checkbad(mtd, ((loff_t) page) <<
1914 chip->page_shift, 0, allowbbt)) {
1915 printk(KERN_WARNING "nand_erase: attempt to erase a "
1916 "bad block at page 0x%08x\n", page);
1917 instr->state = MTD_ERASE_FAILED;
1922 * Invalidate the page cache, if we erase the block which
1923 * contains the current cached page
1925 if (page <= chip->pagebuf && chip->pagebuf <
1926 (page + pages_per_block))
1929 chip->erase_cmd(mtd, page & chip->pagemask);
1931 status = chip->waitfunc(mtd, chip, FL_ERASING);
1934 * See if operation failed and additional status checks are
1937 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1938 status = chip->errstat(mtd, chip, FL_ERASING,
1941 /* See if block erase succeeded */
1942 if (status & NAND_STATUS_FAIL) {
1943 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1944 "Failed erase, page 0x%08x\n", page);
1945 instr->state = MTD_ERASE_FAILED;
1946 instr->fail_addr = (page << chip->page_shift);
1951 * If BBT requires refresh, set the BBT rewrite flag to the
1954 if (bbt_masked_page != 0xffffffff &&
1955 (page & BBT_PAGE_MASK) == bbt_masked_page)
1956 rewrite_bbt[chipnr] = (page << chip->page_shift);
1958 /* Increment page address and decrement length */
1959 len -= (1 << chip->phys_erase_shift);
1960 page += pages_per_block;
1962 /* Check, if we cross a chip boundary */
1963 if (len && !(page & chip->pagemask)) {
1965 chip->select_chip(mtd, -1);
1966 chip->select_chip(mtd, chipnr);
1969 * If BBT requires refresh and BBT-PERCHIP, set the BBT
1970 * page mask to see if this BBT should be rewritten
1972 if (bbt_masked_page != 0xffffffff &&
1973 (chip->bbt_td->options & NAND_BBT_PERCHIP))
1974 bbt_masked_page = chip->bbt_td->pages[chipnr] &
1978 instr->state = MTD_ERASE_DONE;
1982 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1983 /* Do call back function */
1985 mtd_erase_callback(instr);
1987 /* Deselect and wake up anyone waiting on the device */
1988 nand_release_device(mtd);
1991 * If BBT requires refresh and erase was successful, rewrite any
1992 * selected bad block tables
1994 if (bbt_masked_page == 0xffffffff || ret)
1997 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
1998 if (!rewrite_bbt[chipnr])
2000 /* update the BBT for chip */
2001 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2002 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2003 chip->bbt_td->pages[chipnr]);
2004 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2007 /* Return more or less happy */
2012 * nand_sync - [MTD Interface] sync
2013 * @mtd: MTD device structure
2015 * Sync is actually a wait for chip ready function
2017 static void nand_sync(struct mtd_info *mtd)
2019 struct nand_chip *chip = mtd->priv;
2021 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2023 /* Grab the lock and see if the device is available */
2024 nand_get_device(chip, mtd, FL_SYNCING);
2025 /* Release it and go back */
2026 nand_release_device(mtd);
2030 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2031 * @mtd: MTD device structure
2032 * @ofs: offset relative to mtd start
2034 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2036 /* Check for invalid offset */
2037 if (offs > mtd->size)
2040 return nand_block_checkbad(mtd, offs, 1, 0);
2044 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2045 * @mtd: MTD device structure
2046 * @ofs: offset relative to mtd start
2048 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2050 struct nand_chip *chip = mtd->priv;
2053 if ((ret = nand_block_isbad(mtd, ofs))) {
2054 /* If it was bad already, return success and do nothing. */
2060 return chip->block_markbad(mtd, ofs);
2064 * nand_suspend - [MTD Interface] Suspend the NAND flash
2065 * @mtd: MTD device structure
2067 static int nand_suspend(struct mtd_info *mtd)
2069 struct nand_chip *chip = mtd->priv;
2071 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2075 * nand_resume - [MTD Interface] Resume the NAND flash
2076 * @mtd: MTD device structure
2078 static void nand_resume(struct mtd_info *mtd)
2080 struct nand_chip *chip = mtd->priv;
2082 if (chip->state == FL_PM_SUSPENDED)
2083 nand_release_device(mtd);
2085 printk(KERN_ERR "nand_resume() called for a chip which is not "
2086 "in suspended state\n");
2090 * Free allocated data structures
2092 static void nand_free_kmem(struct nand_chip *chip)
2094 /* Buffer allocated by nand_scan ? */
2095 if (chip->options & NAND_OOBBUF_ALLOC)
2096 kfree(chip->oob_buf);
2097 /* Buffer allocated by nand_scan ? */
2098 if (chip->options & NAND_DATABUF_ALLOC)
2099 kfree(chip->data_buf);
2100 /* Controller allocated by nand_scan ? */
2101 if (chip->options & NAND_CONTROLLER_ALLOC)
2102 kfree(chip->controller);
2106 * Allocate buffers and data structures
2108 static int nand_allocate_kmem(struct mtd_info *mtd, struct nand_chip *chip)
2112 if (!chip->oob_buf) {
2113 len = mtd->oobsize <<
2114 (chip->phys_erase_shift - chip->page_shift);
2115 chip->oob_buf = kmalloc(len, GFP_KERNEL);
2118 chip->options |= NAND_OOBBUF_ALLOC;
2121 if (!chip->data_buf) {
2122 len = mtd->writesize + mtd->oobsize;
2123 chip->data_buf = kmalloc(len, GFP_KERNEL);
2124 if (!chip->data_buf)
2126 chip->options |= NAND_DATABUF_ALLOC;
2129 if (!chip->controller) {
2130 chip->controller = kzalloc(sizeof(struct nand_hw_control),
2132 if (!chip->controller)
2135 spin_lock_init(&chip->controller->lock);
2136 init_waitqueue_head(&chip->controller->wq);
2137 chip->options |= NAND_CONTROLLER_ALLOC;
2142 printk(KERN_ERR "nand_scan(): Cannot allocate buffers\n");
2143 nand_free_kmem(chip);
2148 * Set default functions
2150 static void nand_set_defaults(struct nand_chip *chip, int busw)
2152 /* check for proper chip_delay setup, set 20us if not */
2153 if (!chip->chip_delay)
2154 chip->chip_delay = 20;
2156 /* check, if a user supplied command function given */
2157 if (chip->cmdfunc == NULL)
2158 chip->cmdfunc = nand_command;
2160 /* check, if a user supplied wait function given */
2161 if (chip->waitfunc == NULL)
2162 chip->waitfunc = nand_wait;
2164 if (!chip->select_chip)
2165 chip->select_chip = nand_select_chip;
2166 if (!chip->read_byte)
2167 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2168 if (!chip->read_word)
2169 chip->read_word = nand_read_word;
2170 if (!chip->block_bad)
2171 chip->block_bad = nand_block_bad;
2172 if (!chip->block_markbad)
2173 chip->block_markbad = nand_default_block_markbad;
2174 if (!chip->write_buf)
2175 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2176 if (!chip->read_buf)
2177 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2178 if (!chip->verify_buf)
2179 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2180 if (!chip->scan_bbt)
2181 chip->scan_bbt = nand_default_bbt;
2185 * Get the flash and manufacturer id and lookup if the type is supported
2187 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2188 struct nand_chip *chip,
2189 int busw, int *maf_id)
2191 struct nand_flash_dev *type = NULL;
2192 int i, dev_id, maf_idx;
2194 /* Select the device */
2195 chip->select_chip(mtd, 0);
2197 /* Send the command for reading device ID */
2198 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2200 /* Read manufacturer and device IDs */
2201 *maf_id = chip->read_byte(mtd);
2202 dev_id = chip->read_byte(mtd);
2204 /* Lookup the flash id */
2205 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2206 if (dev_id == nand_flash_ids[i].id) {
2207 type = &nand_flash_ids[i];
2213 return ERR_PTR(-ENODEV);
2215 chip->chipsize = nand_flash_ids[i].chipsize << 20;
2217 /* Newer devices have all the information in additional id bytes */
2218 if (!nand_flash_ids[i].pagesize) {
2220 /* The 3rd id byte contains non relevant data ATM */
2221 extid = chip->read_byte(mtd);
2222 /* The 4th id byte is the important one */
2223 extid = chip->read_byte(mtd);
2225 mtd->writesize = 1024 << (extid & 0x3);
2228 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2230 /* Calc blocksize. Blocksize is multiples of 64KiB */
2231 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2233 /* Get buswidth information */
2234 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2238 * Old devices have chip data hardcoded in the device id table
2240 mtd->erasesize = nand_flash_ids[i].erasesize;
2241 mtd->writesize = nand_flash_ids[i].pagesize;
2242 mtd->oobsize = mtd->writesize / 32;
2243 busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
2246 /* Try to identify manufacturer */
2247 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) {
2248 if (nand_manuf_ids[maf_idx].id == *maf_id)
2253 * Check, if buswidth is correct. Hardware drivers should set
2256 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2257 printk(KERN_INFO "NAND device: Manufacturer ID:"
2258 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2259 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2260 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2261 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2263 return ERR_PTR(-EINVAL);
2266 /* Calculate the address shift from the page size */
2267 chip->page_shift = ffs(mtd->writesize) - 1;
2268 /* Convert chipsize to number of pages per chip -1. */
2269 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2271 chip->bbt_erase_shift = chip->phys_erase_shift =
2272 ffs(mtd->erasesize) - 1;
2273 chip->chip_shift = ffs(chip->chipsize) - 1;
2275 /* Set the bad block position */
2276 chip->badblockpos = mtd->writesize > 512 ?
2277 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2279 /* Get chip options, preserve non chip based options */
2280 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2281 chip->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
2284 * Set chip as a default. Board drivers can override it, if necessary
2286 chip->options |= NAND_NO_AUTOINCR;
2288 /* Check if chip is a not a samsung device. Do not clear the
2289 * options for chips which are not having an extended id.
2291 if (*maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
2292 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2294 /* Check for AND chips with 4 page planes */
2295 if (chip->options & NAND_4PAGE_ARRAY)
2296 chip->erase_cmd = multi_erase_cmd;
2298 chip->erase_cmd = single_erase_cmd;
2300 /* Do not replace user supplied command function ! */
2301 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2302 chip->cmdfunc = nand_command_lp;
2304 printk(KERN_INFO "NAND device: Manufacturer ID:"
2305 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2306 nand_manuf_ids[maf_idx].name, type->name);
2311 /* module_text_address() isn't exported, and it's mostly a pointless
2312 test if this is a module _anyway_ -- they'd have to try _really_ hard
2313 to call us from in-kernel code if the core NAND support is modular. */
2315 #define caller_is_module() (1)
2317 #define caller_is_module() \
2318 module_text_address((unsigned long)__builtin_return_address(0))
2322 * nand_scan - [NAND Interface] Scan for the NAND device
2323 * @mtd: MTD device structure
2324 * @maxchips: Number of chips to scan for
2326 * This fills out all the uninitialized function pointers
2327 * with the defaults.
2328 * The flash ID is read and the mtd/chip structures are
2329 * filled with the appropriate values. Buffers are allocated if
2330 * they are not provided by the board driver
2331 * The mtd->owner field must be set to the module of the caller
2334 int nand_scan(struct mtd_info *mtd, int maxchips)
2336 int i, busw, nand_maf_id;
2337 struct nand_chip *chip = mtd->priv;
2338 struct nand_flash_dev *type;
2340 /* Many callers got this wrong, so check for it for a while... */
2341 if (!mtd->owner && caller_is_module()) {
2342 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2346 /* Get buswidth to select the correct functions */
2347 busw = chip->options & NAND_BUSWIDTH_16;
2348 /* Set the default functions */
2349 nand_set_defaults(chip, busw);
2351 /* Read the flash type */
2352 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2355 printk(KERN_WARNING "No NAND device found!!!\n");
2356 chip->select_chip(mtd, -1);
2357 return PTR_ERR(type);
2360 /* Check for a chip array */
2361 for (i = 1; i < maxchips; i++) {
2362 chip->select_chip(mtd, i);
2363 /* Send the command for reading device ID */
2364 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2365 /* Read manufacturer and device IDs */
2366 if (nand_maf_id != chip->read_byte(mtd) ||
2367 type->id != chip->read_byte(mtd))
2371 printk(KERN_INFO "%d NAND chips detected\n", i);
2373 /* Store the number of chips and calc total size for mtd */
2375 mtd->size = i * chip->chipsize;
2377 /* Allocate buffers and data structures */
2378 if (nand_allocate_kmem(mtd, chip))
2381 /* Preset the internal oob buffer */
2382 memset(chip->oob_buf, 0xff,
2383 mtd->oobsize << (chip->phys_erase_shift - chip->page_shift));
2386 * If no default placement scheme is given, select an appropriate one
2388 if (!chip->autooob) {
2389 switch (mtd->oobsize) {
2391 chip->autooob = &nand_oob_8;
2394 chip->autooob = &nand_oob_16;
2397 chip->autooob = &nand_oob_64;
2400 printk(KERN_WARNING "No oob scheme defined for "
2401 "oobsize %d\n", mtd->oobsize);
2407 * The number of bytes available for the filesystem to place fs
2408 * dependend oob data
2411 for (i = 0; chip->autooob->oobfree[i][1]; i++)
2412 mtd->oobavail += chip->autooob->oobfree[i][1];
2415 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2416 * selected and we have 256 byte pagesize fallback to software ECC
2418 switch (chip->ecc.mode) {
2420 case NAND_ECC_HW_SYNDROME:
2421 if (!chip->ecc.calculate || !chip->ecc.correct ||
2423 printk(KERN_WARNING "No ECC functions supplied, "
2424 "Hardware ECC not possible\n");
2427 if (mtd->writesize >= chip->ecc.size)
2429 printk(KERN_WARNING "%d byte HW ECC not possible on "
2430 "%d byte page size, fallback to SW ECC\n",
2431 chip->ecc.size, mtd->writesize);
2432 chip->ecc.mode = NAND_ECC_SOFT;
2435 chip->ecc.calculate = nand_calculate_ecc;
2436 chip->ecc.correct = nand_correct_data;
2437 chip->ecc.size = 256;
2438 chip->ecc.bytes = 3;
2442 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2443 "This is not recommended !!\n");
2444 chip->ecc.size = mtd->writesize;
2445 chip->ecc.bytes = 0;
2448 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2454 * Set the number of read / write steps for one page depending on ECC
2457 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2458 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2459 printk(KERN_WARNING "Invalid ecc parameters\n");
2463 /* Initialize state */
2464 chip->state = FL_READY;
2466 /* De-select the device */
2467 chip->select_chip(mtd, -1);
2469 /* Invalidate the pagebuffer reference */
2472 /* Fill in remaining MTD driver data */
2473 mtd->type = MTD_NANDFLASH;
2474 mtd->flags = MTD_CAP_NANDFLASH;
2475 mtd->ecctype = MTD_ECC_SW;
2476 mtd->erase = nand_erase;
2478 mtd->unpoint = NULL;
2479 mtd->read = nand_read;
2480 mtd->write = nand_write;
2481 mtd->read_oob = nand_read_oob;
2482 mtd->write_oob = nand_write_oob;
2483 mtd->sync = nand_sync;
2486 mtd->suspend = nand_suspend;
2487 mtd->resume = nand_resume;
2488 mtd->block_isbad = nand_block_isbad;
2489 mtd->block_markbad = nand_block_markbad;
2491 /* and make the autooob the default one */
2492 memcpy(&mtd->oobinfo, chip->autooob, sizeof(mtd->oobinfo));
2494 /* Check, if we should skip the bad block table scan */
2495 if (chip->options & NAND_SKIP_BBTSCAN)
2498 /* Build bad block table */
2499 return chip->scan_bbt(mtd);
2503 * nand_release - [NAND Interface] Free resources held by the NAND device
2504 * @mtd: MTD device structure
2506 void nand_release(struct mtd_info *mtd)
2508 struct nand_chip *chip = mtd->priv;
2510 #ifdef CONFIG_MTD_PARTITIONS
2511 /* Deregister partitions */
2512 del_mtd_partitions(mtd);
2514 /* Deregister the device */
2515 del_mtd_device(mtd);
2517 /* Free bad block table memory */
2520 nand_free_kmem(chip);
2523 EXPORT_SYMBOL_GPL(nand_scan);
2524 EXPORT_SYMBOL_GPL(nand_release);
2526 static int __init nand_base_init(void)
2528 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2532 static void __exit nand_base_exit(void)
2534 led_trigger_unregister_simple(nand_led_trigger);
2537 module_init(nand_base_init);
2538 module_exit(nand_base_exit);
2540 MODULE_LICENSE("GPL");
2541 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2542 MODULE_DESCRIPTION("Generic NAND flash driver code");