drivers/mmc/host/sdhci-brcmstb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
   4  *
   5  * Copyright (C) 2015 Broadcom Corporation
   6  */
   7
   8 #include <linux/io.h>
   9 #include <linux/mmc/host.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/bitops.h>
  13 #include <linux/delay.h>
  14
  15 #include "sdhci-pltfm.h"
  16 #include "cqhci.h"
  17
  18 #define SDHCI_VENDOR 0x78
  19 #define  SDHCI_VENDOR_ENHANCED_STRB 0x1
  20 #define  SDHCI_VENDOR_GATE_SDCLK_EN 0x2
  21
  22 #define BRCMSTB_MATCH_FLAGS_NO_64BIT            BIT(0)
  23 #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT      BIT(1)
  24 #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE      BIT(2)
  25
  26 #define BRCMSTB_PRIV_FLAGS_HAS_CQE              BIT(0)
  27 #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK           BIT(1)
  28
  29 #define SDHCI_ARASAN_CQE_BASE_ADDR              0x200
  30
  31 struct sdhci_brcmstb_priv {
  32         void __iomem *cfg_regs;
  33         unsigned int flags;
  34 };
  35
  36 struct brcmstb_match_priv {
  37         void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
  38         struct sdhci_ops *ops;
  39         const unsigned int flags;
  40 };
  41
  42 static inline void enable_clock_gating(struct sdhci_host *host)
  43 {
  44         u32 reg;
  45
  46         reg = sdhci_readl(host, SDHCI_VENDOR);
  47         reg |= SDHCI_VENDOR_GATE_SDCLK_EN;
  48         sdhci_writel(host, reg, SDHCI_VENDOR);
  49 }
  50
  51 static void brcmstb_reset(struct sdhci_host *host, u8 mask)
  52 {
  53         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  54         struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
  55
  56         sdhci_reset(host, mask);
  57
  58         /* Reset will clear this, so re-enable it */
  59         if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)
  60                 enable_clock_gating(host);
  61 }
  62
  63 static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)
  64 {
  65         struct sdhci_host *host = mmc_priv(mmc);
  66
  67         u32 reg;
  68
  69         dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",
  70                 __func__);
  71         reg = readl(host->ioaddr + SDHCI_VENDOR);
  72         if (ios->enhanced_strobe)
  73                 reg |= SDHCI_VENDOR_ENHANCED_STRB;
  74         else
  75                 reg &= ~SDHCI_VENDOR_ENHANCED_STRB;
  76         writel(reg, host->ioaddr + SDHCI_VENDOR);
  77 }
  78
  79 static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
  80 {
  81         u16 clk;
  82
  83         host->mmc->actual_clock = 0;
  84
  85         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  86         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  87
  88         if (clock == 0)
  89                 return;
  90
  91         sdhci_enable_clk(host, clk);
  92 }
  93
  94 static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
  95                                             unsigned int timing)
  96 {
  97         u16 ctrl_2;
  98
  99         dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
 100                 __func__, timing);
 101         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 102         /* Select Bus Speed Mode for host */
 103         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 104         if ((timing == MMC_TIMING_MMC_HS200) ||
 105             (timing == MMC_TIMING_UHS_SDR104))
 106                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 107         else if (timing == MMC_TIMING_UHS_SDR12)
 108                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 109         else if (timing == MMC_TIMING_SD_HS ||
 110                  timing == MMC_TIMING_MMC_HS ||
 111                  timing == MMC_TIMING_UHS_SDR25)
 112                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 113         else if (timing == MMC_TIMING_UHS_SDR50)
 114                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 115         else if ((timing == MMC_TIMING_UHS_DDR50) ||
 116                  (timing == MMC_TIMING_MMC_DDR52))
 117                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 118         else if (timing == MMC_TIMING_MMC_HS400)
 119                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
 120         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 121 }
 122
 123 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
 124 {
 125         sdhci_dumpregs(mmc_priv(mmc));
 126 }
 127
 128 static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)
 129 {
 130         struct sdhci_host *host = mmc_priv(mmc);
 131         u32 reg;
 132
 133         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
 134         while (reg & SDHCI_DATA_AVAILABLE) {
 135                 sdhci_readl(host, SDHCI_BUFFER);
 136                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
 137         }
 138
 139         sdhci_cqe_enable(mmc);
 140 }
 141
 142 static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {
 143         .enable         = sdhci_brcmstb_cqe_enable,
 144         .disable        = sdhci_cqe_disable,
 145         .dumpregs       = sdhci_brcmstb_dumpregs,
 146 };
 147
 148 static struct sdhci_ops sdhci_brcmstb_ops = {
 149         .set_clock = sdhci_set_clock,
 150         .set_bus_width = sdhci_set_bus_width,
 151         .reset = sdhci_reset,
 152         .set_uhs_signaling = sdhci_set_uhs_signaling,
 153 };
 154
 155 static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
 156         .set_clock = sdhci_brcmstb_set_clock,
 157         .set_bus_width = sdhci_set_bus_width,
 158         .reset = brcmstb_reset,
 159         .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
 160 };
 161
 162 static struct brcmstb_match_priv match_priv_7425 = {
 163         .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT |
 164         BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
 165         .ops = &sdhci_brcmstb_ops,
 166 };
 167
 168 static struct brcmstb_match_priv match_priv_7445 = {
 169         .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
 170         .ops = &sdhci_brcmstb_ops,
 171 };
 172
 173 static const struct brcmstb_match_priv match_priv_7216 = {
 174         .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
 175         .hs400es = sdhci_brcmstb_hs400es,
 176         .ops = &sdhci_brcmstb_ops_7216,
 177 };
 178
 179 static const struct of_device_id sdhci_brcm_of_match[] = {
 180         { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
 181         { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
 182         { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
 183         {},
 184 };
 185
 186 static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
 187 {
 188         int cmd_error = 0;
 189         int data_error = 0;
 190
 191         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
 192                 return intmask;
 193
 194         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
 195
 196         return 0;
 197 }
 198
 199 static int sdhci_brcmstb_add_host(struct sdhci_host *host,
 200                                   struct sdhci_brcmstb_priv *priv)
 201 {
 202         struct cqhci_host *cq_host;
 203         bool dma64;
 204         int ret;
 205
 206         if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0)
 207                 return sdhci_add_host(host);
 208
 209         dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
 210         host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
 211         ret = sdhci_setup_host(host);
 212         if (ret)
 213                 return ret;
 214
 215         cq_host = devm_kzalloc(mmc_dev(host->mmc),
 216                                sizeof(*cq_host), GFP_KERNEL);
 217         if (!cq_host) {
 218                 ret = -ENOMEM;
 219                 goto cleanup;
 220         }
 221
 222         cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
 223         cq_host->ops = &sdhci_brcmstb_cqhci_ops;
 224
 225         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
 226         if (dma64) {
 227                 dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
 228                 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
 229         }
 230
 231         ret = cqhci_init(cq_host, host->mmc, dma64);
 232         if (ret)
 233                 goto cleanup;
 234
 235         ret = __sdhci_add_host(host);
 236         if (ret)
 237                 goto cleanup;
 238
 239         return 0;
 240
 241 cleanup:
 242         sdhci_cleanup_host(host);
 243         return ret;
 244 }
 245
 246 static int sdhci_brcmstb_probe(struct platform_device *pdev)
 247 {
 248         const struct brcmstb_match_priv *match_priv;
 249         struct sdhci_pltfm_data brcmstb_pdata;
 250         struct sdhci_pltfm_host *pltfm_host;
 251         const struct of_device_id *match;
 252         struct sdhci_brcmstb_priv *priv;
 253         struct sdhci_host *host;
 254         struct resource *iomem;
 255         struct clk *clk;
 256         int res;
 257
 258         match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);
 259         match_priv = match->data;
 260
 261         dev_dbg(&pdev->dev, "Probe found match for %s\n",  match->compatible);
 262
 263         clk = devm_clk_get_optional(&pdev->dev, NULL);
 264         if (IS_ERR(clk))
 265                 return dev_err_probe(&pdev->dev, PTR_ERR(clk),
 266                                      "Failed to get clock from Device Tree\n");
 267
 268         res = clk_prepare_enable(clk);
 269         if (res)
 270                 return res;
 271
 272         memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));
 273         brcmstb_pdata.ops = match_priv->ops;
 274         host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
 275                                 sizeof(struct sdhci_brcmstb_priv));
 276         if (IS_ERR(host)) {
 277                 res = PTR_ERR(host);
 278                 goto err_clk;
 279         }
 280
 281         pltfm_host = sdhci_priv(host);
 282         priv = sdhci_pltfm_priv(pltfm_host);
 283         if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
 284                 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
 285                 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
 286         }
 287
 288         /* Map in the non-standard CFG registers */
 289         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 290         priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem);
 291         if (IS_ERR(priv->cfg_regs)) {
 292                 res = PTR_ERR(priv->cfg_regs);
 293                 goto err;
 294         }
 295
 296         sdhci_get_of_property(pdev);
 297         res = mmc_of_parse(host->mmc);
 298         if (res)
 299                 goto err;
 300
 301         /*
 302          * Automatic clock gating does not work for SD cards that may
 303          * voltage switch so only enable it for non-removable devices.
 304          */
 305         if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) &&
 306             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 307                 priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK;
 308
 309         /*
 310          * If the chip has enhanced strobe and it's enabled, add
 311          * callback
 312          */
 313         if (match_priv->hs400es &&
 314             (host->mmc->caps2 & MMC_CAP2_HS400_ES))
 315                 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
 316
 317         /*
 318          * Supply the existing CAPS, but clear the UHS modes. This
 319          * will allow these modes to be specified by device tree
 320          * properties through mmc_of_parse().
 321          */
 322         host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 323         if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT)
 324                 host->caps &= ~SDHCI_CAN_64BIT;
 325         host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 326         host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
 327                          SDHCI_SUPPORT_DDR50);
 328         host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 329
 330         if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT)
 331                 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 332
 333         res = sdhci_brcmstb_add_host(host, priv);
 334         if (res)
 335                 goto err;
 336
 337         pltfm_host->clk = clk;
 338         return res;
 339
 340 err:
 341         sdhci_pltfm_free(pdev);
 342 err_clk:
 343         clk_disable_unprepare(clk);
 344         return res;
 345 }
 346
 347 static void sdhci_brcmstb_shutdown(struct platform_device *pdev)
 348 {
 349         sdhci_pltfm_suspend(&pdev->dev);
 350 }
 351
 352 MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
 353
 354 static struct platform_driver sdhci_brcmstb_driver = {
 355         .driver         = {
 356                 .name   = "sdhci-brcmstb",
 357                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 358                 .pm     = &sdhci_pltfm_pmops,
 359                 .of_match_table = of_match_ptr(sdhci_brcm_of_match),
 360         },
 361         .probe          = sdhci_brcmstb_probe,
 362         .remove         = sdhci_pltfm_unregister,
 363         .shutdown       = sdhci_brcmstb_shutdown,
 364 };
 365
 366 module_platform_driver(sdhci_brcmstb_driver);
 367
 368 MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
 369 MODULE_AUTHOR("Broadcom");
 370 MODULE_LICENSE("GPL v2");