drivers/mmc/host/rtsx_pci_sdmmc.c

   1 /* Realtek PCI-Express SD/MMC Card Interface driver
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/highmem.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 struct realtek_pci_sdmmc {
  37         struct platform_device  *pdev;
  38         struct rtsx_pcr         *pcr;
  39         struct mmc_host         *mmc;
  40         struct mmc_request      *mrq;
  41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  42
  43         struct work_struct      work;
  44         struct mutex            host_mutex;
  45
  46         u8                      ssc_depth;
  47         unsigned int            clock;
  48         bool                    vpclk;
  49         bool                    double_clk;
  50         bool                    eject;
  51         bool                    initial_mode;
  52         int                     power_state;
  53 #define SDMMC_POWER_ON          1
  54 #define SDMMC_POWER_OFF         0
  55
  56         int                     sg_count;
  57         s32                     cookie;
  58         int                     cookie_sg_count;
  59         bool                    using_cookie;
  60 };
  61
  62 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  63 {
  64         return &(host->pdev->dev);
  65 }
  66
  67 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  68 {
  69         rtsx_pci_write_register(host->pcr, CARD_STOP,
  70                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  71 }
  72
  73 #ifdef DEBUG
  74 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  75 {
  76         u16 len = end - start + 1;
  77         int i;
  78         u8 data[8];
  79
  80         for (i = 0; i < len; i += 8) {
  81                 int j;
  82                 int n = min(8, len - i);
  83
  84                 memset(&data, 0, sizeof(data));
  85                 for (j = 0; j < n; j++)
  86                         rtsx_pci_read_register(host->pcr, start + i + j,
  87                                 data + j);
  88                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  89                         start + i, n, data);
  90         }
  91 }
  92
  93 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  94 {
  95         dump_reg_range(host, 0xFDA0, 0xFDB3);
  96         dump_reg_range(host, 0xFD52, 0xFD69);
  97 }
  98 #else
  99 #define sd_print_debug_regs(host)
 100 #endif /* DEBUG */
 101
 102 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
 103 {
 104         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
 105 }
 106
 107 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
 108 {
 109         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
 110                 SD_CMD_START | cmd->opcode);
 111         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 112 }
 113
 114 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 115 {
 116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 117         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 119         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 120 }
 121
 122 static int sd_response_type(struct mmc_command *cmd)
 123 {
 124         switch (mmc_resp_type(cmd)) {
 125         case MMC_RSP_NONE:
 126                 return SD_RSP_TYPE_R0;
 127         case MMC_RSP_R1:
 128                 return SD_RSP_TYPE_R1;
 129         case MMC_RSP_R1_NO_CRC:
 130                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 131         case MMC_RSP_R1B:
 132                 return SD_RSP_TYPE_R1b;
 133         case MMC_RSP_R2:
 134                 return SD_RSP_TYPE_R2;
 135         case MMC_RSP_R3:
 136                 return SD_RSP_TYPE_R3;
 137         default:
 138                 return -EINVAL;
 139         }
 140 }
 141
 142 static int sd_status_index(int resp_type)
 143 {
 144         if (resp_type == SD_RSP_TYPE_R0)
 145                 return 0;
 146         else if (resp_type == SD_RSP_TYPE_R2)
 147                 return 16;
 148
 149         return 5;
 150 }
 151 /*
 152  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 153  *
 154  * @pre: if called in pre_req()
 155  * return:
 156  *      0 - do dma_map_sg()
 157  *      1 - using cookie
 158  */
 159 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 160                 struct mmc_data *data, bool pre)
 161 {
 162         struct rtsx_pcr *pcr = host->pcr;
 163         int read = data->flags & MMC_DATA_READ;
 164         int count = 0;
 165         int using_cookie = 0;
 166
 167         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 168                 dev_err(sdmmc_dev(host),
 169                         "error: data->host_cookie = %d, host->cookie = %d\n",
 170                         data->host_cookie, host->cookie);
 171                 data->host_cookie = 0;
 172         }
 173
 174         if (pre || data->host_cookie != host->cookie) {
 175                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 176         } else {
 177                 count = host->cookie_sg_count;
 178                 using_cookie = 1;
 179         }
 180
 181         if (pre) {
 182                 host->cookie_sg_count = count;
 183                 if (++host->cookie < 0)
 184                         host->cookie = 1;
 185                 data->host_cookie = host->cookie;
 186         } else {
 187                 host->sg_count = count;
 188         }
 189
 190         return using_cookie;
 191 }
 192
 193 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
 194 {
 195         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 196         struct mmc_data *data = mrq->data;
 197
 198         if (data->host_cookie) {
 199                 dev_err(sdmmc_dev(host),
 200                         "error: reset data->host_cookie = %d\n",
 201                         data->host_cookie);
 202                 data->host_cookie = 0;
 203         }
 204
 205         sd_pre_dma_transfer(host, data, true);
 206         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 207 }
 208
 209 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 210                 int err)
 211 {
 212         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 213         struct rtsx_pcr *pcr = host->pcr;
 214         struct mmc_data *data = mrq->data;
 215         int read = data->flags & MMC_DATA_READ;
 216
 217         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 218         data->host_cookie = 0;
 219 }
 220
 221 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 222                 struct mmc_command *cmd)
 223 {
 224         struct rtsx_pcr *pcr = host->pcr;
 225         u8 cmd_idx = (u8)cmd->opcode;
 226         u32 arg = cmd->arg;
 227         int err = 0;
 228         int timeout = 100;
 229         int i;
 230         u8 *ptr;
 231         int rsp_type;
 232         int stat_idx;
 233         bool clock_toggled = false;
 234
 235         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 236                         __func__, cmd_idx, arg);
 237
 238         rsp_type = sd_response_type(cmd);
 239         if (rsp_type < 0)
 240                 goto out;
 241
 242         stat_idx = sd_status_index(rsp_type);
 243
 244         if (rsp_type == SD_RSP_TYPE_R1b)
 245                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 246
 247         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 248                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 249                                 0xFF, SD_CLK_TOGGLE_EN);
 250                 if (err < 0)
 251                         goto out;
 252
 253                 clock_toggled = true;
 254         }
 255
 256         rtsx_pci_init_cmd(pcr);
 257         sd_cmd_set_sd_cmd(pcr, cmd);
 258         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 259         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 260                         0x01, PINGPONG_BUFFER);
 261         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 262                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 263         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 264                      SD_TRANSFER_END | SD_STAT_IDLE,
 265                      SD_TRANSFER_END | SD_STAT_IDLE);
 266
 267         if (rsp_type == SD_RSP_TYPE_R2) {
 268                 /* Read data from ping-pong buffer */
 269                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 270                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 271         } else if (rsp_type != SD_RSP_TYPE_R0) {
 272                 /* Read data from SD_CMDx registers */
 273                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 274                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 275         }
 276
 277         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 278
 279         err = rtsx_pci_send_cmd(pcr, timeout);
 280         if (err < 0) {
 281                 sd_print_debug_regs(host);
 282                 sd_clear_error(host);
 283                 dev_dbg(sdmmc_dev(host),
 284                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 285                 goto out;
 286         }
 287
 288         if (rsp_type == SD_RSP_TYPE_R0) {
 289                 err = 0;
 290                 goto out;
 291         }
 292
 293         /* Eliminate returned value of CHECK_REG_CMD */
 294         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 295
 296         /* Check (Start,Transmission) bit of Response */
 297         if ((ptr[0] & 0xC0) != 0) {
 298                 err = -EILSEQ;
 299                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 300                 goto out;
 301         }
 302
 303         /* Check CRC7 */
 304         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 305                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 306                         err = -EILSEQ;
 307                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 308                         goto out;
 309                 }
 310         }
 311
 312         if (rsp_type == SD_RSP_TYPE_R2) {
 313                 /*
 314                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 315                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 316                  * byte(ptr[16], goes into the LSB of resp[3] later).
 317                  */
 318                 ptr[16] = 1;
 319
 320                 for (i = 0; i < 4; i++) {
 321                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 322                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 323                                         i, cmd->resp[i]);
 324                 }
 325         } else {
 326                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 327                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 328                                 cmd->resp[0]);
 329         }
 330
 331 out:
 332         cmd->error = err;
 333
 334         if (err && clock_toggled)
 335                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 336                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 337 }
 338
 339 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 340         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 341 {
 342         struct rtsx_pcr *pcr = host->pcr;
 343         int err;
 344         u8 trans_mode;
 345
 346         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 347                 __func__, cmd->opcode, cmd->arg);
 348
 349         if (!buf)
 350                 buf_len = 0;
 351
 352         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 353                 trans_mode = SD_TM_AUTO_TUNING;
 354         else
 355                 trans_mode = SD_TM_NORMAL_READ;
 356
 357         rtsx_pci_init_cmd(pcr);
 358         sd_cmd_set_sd_cmd(pcr, cmd);
 359         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 360         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 361                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 362                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 363         if (trans_mode != SD_TM_AUTO_TUNING)
 364                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 365                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 366
 367         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 368                         0xFF, trans_mode | SD_TRANSFER_START);
 369         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 370                         SD_TRANSFER_END, SD_TRANSFER_END);
 371
 372         err = rtsx_pci_send_cmd(pcr, timeout);
 373         if (err < 0) {
 374                 sd_print_debug_regs(host);
 375                 dev_dbg(sdmmc_dev(host),
 376                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 377                 return err;
 378         }
 379
 380         if (buf && buf_len) {
 381                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 382                 if (err < 0) {
 383                         dev_dbg(sdmmc_dev(host),
 384                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 385                         return err;
 386                 }
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int sd_write_data(struct realtek_pci_sdmmc *host,
 393         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 394         int timeout)
 395 {
 396         struct rtsx_pcr *pcr = host->pcr;
 397         int err;
 398
 399         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 400                 __func__, cmd->opcode, cmd->arg);
 401
 402         if (!buf)
 403                 buf_len = 0;
 404
 405         sd_send_cmd_get_rsp(host, cmd);
 406         if (cmd->error)
 407                 return cmd->error;
 408
 409         if (buf && buf_len) {
 410                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 411                 if (err < 0) {
 412                         dev_dbg(sdmmc_dev(host),
 413                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 414                         return err;
 415                 }
 416         }
 417
 418         rtsx_pci_init_cmd(pcr);
 419         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 420         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 421                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 422                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 423         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 424                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 425         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 426                         SD_TRANSFER_END, SD_TRANSFER_END);
 427
 428         err = rtsx_pci_send_cmd(pcr, timeout);
 429         if (err < 0) {
 430                 sd_print_debug_regs(host);
 431                 dev_dbg(sdmmc_dev(host),
 432                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 433                 return err;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 440         struct mmc_request *mrq)
 441 {
 442         struct rtsx_pcr *pcr = host->pcr;
 443         struct mmc_host *mmc = host->mmc;
 444         struct mmc_card *card = mmc->card;
 445         struct mmc_command *cmd = mrq->cmd;
 446         struct mmc_data *data = mrq->data;
 447         int uhs = mmc_card_uhs(card);
 448         u8 cfg2 = 0;
 449         int err;
 450         int resp_type;
 451         size_t data_len = data->blksz * data->blocks;
 452
 453         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 454                 __func__, cmd->opcode, cmd->arg);
 455
 456         resp_type = sd_response_type(cmd);
 457         if (resp_type < 0)
 458                 return resp_type;
 459
 460         if (!uhs)
 461                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 462
 463         rtsx_pci_init_cmd(pcr);
 464         sd_cmd_set_sd_cmd(pcr, cmd);
 465         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 466         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 467                         DMA_DONE_INT, DMA_DONE_INT);
 468         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 469                 0xFF, (u8)(data_len >> 24));
 470         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 471                 0xFF, (u8)(data_len >> 16));
 472         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 473                 0xFF, (u8)(data_len >> 8));
 474         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 475         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 476                 0x03 | DMA_PACK_SIZE_MASK,
 477                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 478         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 479                         0x01, RING_BUFFER);
 480         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 481         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 482                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 483         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 484                         SD_TRANSFER_END, SD_TRANSFER_END);
 485         rtsx_pci_send_cmd_no_wait(pcr);
 486
 487         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 488         if (err < 0) {
 489                 sd_print_debug_regs(host);
 490                 sd_clear_error(host);
 491                 return err;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 498         struct mmc_request *mrq)
 499 {
 500         struct rtsx_pcr *pcr = host->pcr;
 501         struct mmc_host *mmc = host->mmc;
 502         struct mmc_card *card = mmc->card;
 503         struct mmc_command *cmd = mrq->cmd;
 504         struct mmc_data *data = mrq->data;
 505         int uhs = mmc_card_uhs(card);
 506         u8 cfg2;
 507         int err;
 508         size_t data_len = data->blksz * data->blocks;
 509
 510         sd_send_cmd_get_rsp(host, cmd);
 511         if (cmd->error)
 512                 return cmd->error;
 513
 514         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 515                 __func__, cmd->opcode, cmd->arg);
 516
 517         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 518                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 519
 520         if (!uhs)
 521                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 522
 523         rtsx_pci_init_cmd(pcr);
 524         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 525         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 526                         DMA_DONE_INT, DMA_DONE_INT);
 527         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 528                 0xFF, (u8)(data_len >> 24));
 529         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 530                 0xFF, (u8)(data_len >> 16));
 531         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 532                 0xFF, (u8)(data_len >> 8));
 533         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 534         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 535                 0x03 | DMA_PACK_SIZE_MASK,
 536                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 537         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 538                         0x01, RING_BUFFER);
 539         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 540         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 541                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 542         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 543                         SD_TRANSFER_END, SD_TRANSFER_END);
 544         rtsx_pci_send_cmd_no_wait(pcr);
 545         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 546         if (err < 0) {
 547                 sd_clear_error(host);
 548                 return err;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 555 {
 556         struct mmc_data *data = mrq->data;
 557
 558         if (host->sg_count < 0) {
 559                 data->error = host->sg_count;
 560                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 561                         __func__, host->sg_count);
 562                 return data->error;
 563         }
 564
 565         if (data->flags & MMC_DATA_READ)
 566                 return sd_read_long_data(host, mrq);
 567
 568         return sd_write_long_data(host, mrq);
 569 }
 570
 571 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 572 {
 573         rtsx_pci_write_register(host->pcr, SD_CFG1,
 574                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 575 }
 576
 577 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 578 {
 579         rtsx_pci_write_register(host->pcr, SD_CFG1,
 580                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 581 }
 582
 583 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 584                 struct mmc_request *mrq)
 585 {
 586         struct mmc_command *cmd = mrq->cmd;
 587         struct mmc_data *data = mrq->data;
 588         u8 *buf;
 589
 590         buf = kzalloc(data->blksz, GFP_NOIO);
 591         if (!buf) {
 592                 cmd->error = -ENOMEM;
 593                 return;
 594         }
 595
 596         if (data->flags & MMC_DATA_READ) {
 597                 if (host->initial_mode)
 598                         sd_disable_initial_mode(host);
 599
 600                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 601                                 data->blksz, 200);
 602
 603                 if (host->initial_mode)
 604                         sd_enable_initial_mode(host);
 605
 606                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 607         } else {
 608                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 609
 610                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 611                                 data->blksz, 200);
 612         }
 613
 614         kfree(buf);
 615 }
 616
 617 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 618                 u8 sample_point, bool rx)
 619 {
 620         struct rtsx_pcr *pcr = host->pcr;
 621
 622         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 623                         __func__, rx ? "RX" : "TX", sample_point);
 624
 625         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 626         if (rx)
 627                 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
 628                         PHASE_SELECT_MASK, sample_point);
 629         else
 630                 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
 631                         PHASE_SELECT_MASK, sample_point);
 632         rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 633         rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET,
 634                                 PHASE_NOT_RESET);
 635         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
 636         rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 637
 638         return 0;
 639 }
 640
 641 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 642 {
 643         bit %= RTSX_PHASE_MAX;
 644         return phase_map & (1 << bit);
 645 }
 646
 647 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 648 {
 649         int i;
 650
 651         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 652                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 653                         return i;
 654         }
 655         return RTSX_PHASE_MAX;
 656 }
 657
 658 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 659 {
 660         int start = 0, len = 0;
 661         int start_final = 0, len_final = 0;
 662         u8 final_phase = 0xFF;
 663
 664         if (phase_map == 0) {
 665                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 666                 return final_phase;
 667         }
 668
 669         while (start < RTSX_PHASE_MAX) {
 670                 len = sd_get_phase_len(phase_map, start);
 671                 if (len_final < len) {
 672                         start_final = start;
 673                         len_final = len;
 674                 }
 675                 start += len ? len : 1;
 676         }
 677
 678         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 679         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 680                 phase_map, len_final, final_phase);
 681
 682         return final_phase;
 683 }
 684
 685 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 686 {
 687         int err, i;
 688         u8 val = 0;
 689
 690         for (i = 0; i < 100; i++) {
 691                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 692                 if (val & SD_DATA_IDLE)
 693                         return;
 694
 695                 udelay(100);
 696         }
 697 }
 698
 699 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 700                 u8 opcode, u8 sample_point)
 701 {
 702         int err;
 703         struct mmc_command cmd = {};
 704         struct rtsx_pcr *pcr = host->pcr;
 705
 706         sd_change_phase(host, sample_point, true);
 707
 708         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
 709                 SD_RSP_80CLK_TIMEOUT_EN);
 710
 711         cmd.opcode = opcode;
 712         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 713         if (err < 0) {
 714                 /* Wait till SD DATA IDLE */
 715                 sd_wait_data_idle(host);
 716                 sd_clear_error(host);
 717                 rtsx_pci_write_register(pcr, SD_CFG3,
 718                         SD_RSP_80CLK_TIMEOUT_EN, 0);
 719                 return err;
 720         }
 721
 722         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
 723         return 0;
 724 }
 725
 726 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 727                 u8 opcode, u32 *phase_map)
 728 {
 729         int err, i;
 730         u32 raw_phase_map = 0;
 731
 732         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 733                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 734                 if (err == 0)
 735                         raw_phase_map |= 1 << i;
 736         }
 737
 738         if (phase_map)
 739                 *phase_map = raw_phase_map;
 740
 741         return 0;
 742 }
 743
 744 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 745 {
 746         int err, i;
 747         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 748         u8 final_phase;
 749
 750         for (i = 0; i < RX_TUNING_CNT; i++) {
 751                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 752                 if (err < 0)
 753                         return err;
 754
 755                 if (raw_phase_map[i] == 0)
 756                         break;
 757         }
 758
 759         phase_map = 0xFFFFFFFF;
 760         for (i = 0; i < RX_TUNING_CNT; i++) {
 761                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 762                                 i, raw_phase_map[i]);
 763                 phase_map &= raw_phase_map[i];
 764         }
 765         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 766
 767         if (phase_map) {
 768                 final_phase = sd_search_final_phase(host, phase_map);
 769                 if (final_phase == 0xFF)
 770                         return -EINVAL;
 771
 772                 err = sd_change_phase(host, final_phase, true);
 773                 if (err < 0)
 774                         return err;
 775         } else {
 776                 return -EINVAL;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 783         struct mmc_data *data)
 784 {
 785         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 786 }
 787
 788 static inline int sd_rw_cmd(struct mmc_command *cmd)
 789 {
 790         return mmc_op_multi(cmd->opcode) ||
 791                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 792                 (cmd->opcode == MMC_WRITE_BLOCK);
 793 }
 794
 795 static void sd_request(struct work_struct *work)
 796 {
 797         struct realtek_pci_sdmmc *host = container_of(work,
 798                         struct realtek_pci_sdmmc, work);
 799         struct rtsx_pcr *pcr = host->pcr;
 800
 801         struct mmc_host *mmc = host->mmc;
 802         struct mmc_request *mrq = host->mrq;
 803         struct mmc_command *cmd = mrq->cmd;
 804         struct mmc_data *data = mrq->data;
 805
 806         unsigned int data_size = 0;
 807         int err;
 808
 809         if (host->eject || !sd_get_cd_int(host)) {
 810                 cmd->error = -ENOMEDIUM;
 811                 goto finish;
 812         }
 813
 814         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 815         if (err) {
 816                 cmd->error = err;
 817                 goto finish;
 818         }
 819
 820         mutex_lock(&pcr->pcr_mutex);
 821
 822         rtsx_pci_start_run(pcr);
 823
 824         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 825                         host->initial_mode, host->double_clk, host->vpclk);
 826         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 827         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 828                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 829
 830         mutex_lock(&host->host_mutex);
 831         host->mrq = mrq;
 832         mutex_unlock(&host->host_mutex);
 833
 834         if (mrq->data)
 835                 data_size = data->blocks * data->blksz;
 836
 837         if (!data_size) {
 838                 sd_send_cmd_get_rsp(host, cmd);
 839         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 840                 cmd->error = sd_rw_multi(host, mrq);
 841                 if (!host->using_cookie)
 842                         sdmmc_post_req(host->mmc, host->mrq, 0);
 843
 844                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 845                         sd_send_cmd_get_rsp(host, mrq->stop);
 846         } else {
 847                 sd_normal_rw(host, mrq);
 848         }
 849
 850         if (mrq->data) {
 851                 if (cmd->error || data->error)
 852                         data->bytes_xfered = 0;
 853                 else
 854                         data->bytes_xfered = data->blocks * data->blksz;
 855         }
 856
 857         mutex_unlock(&pcr->pcr_mutex);
 858
 859 finish:
 860         if (cmd->error) {
 861                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 862                         cmd->opcode, cmd->arg, cmd->error);
 863         }
 864
 865         mutex_lock(&host->host_mutex);
 866         host->mrq = NULL;
 867         mutex_unlock(&host->host_mutex);
 868
 869         mmc_request_done(mmc, mrq);
 870 }
 871
 872 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 873 {
 874         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 875         struct mmc_data *data = mrq->data;
 876
 877         mutex_lock(&host->host_mutex);
 878         host->mrq = mrq;
 879         mutex_unlock(&host->host_mutex);
 880
 881         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 882                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 883
 884         schedule_work(&host->work);
 885 }
 886
 887 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 888                 unsigned char bus_width)
 889 {
 890         int err = 0;
 891         u8 width[] = {
 892                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 893                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 894                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 895         };
 896
 897         if (bus_width <= MMC_BUS_WIDTH_8)
 898                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 899                                 0x03, width[bus_width]);
 900
 901         return err;
 902 }
 903
 904 static int sd_power_on(struct realtek_pci_sdmmc *host)
 905 {
 906         struct rtsx_pcr *pcr = host->pcr;
 907         int err;
 908
 909         if (host->power_state == SDMMC_POWER_ON)
 910                 return 0;
 911
 912         rtsx_pci_init_cmd(pcr);
 913         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 914         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 915                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 916         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 917                         SD_CLK_EN, SD_CLK_EN);
 918         err = rtsx_pci_send_cmd(pcr, 100);
 919         if (err < 0)
 920                 return err;
 921
 922         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 923         if (err < 0)
 924                 return err;
 925
 926         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 927         if (err < 0)
 928                 return err;
 929
 930         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 931         if (err < 0)
 932                 return err;
 933
 934         host->power_state = SDMMC_POWER_ON;
 935         return 0;
 936 }
 937
 938 static int sd_power_off(struct realtek_pci_sdmmc *host)
 939 {
 940         struct rtsx_pcr *pcr = host->pcr;
 941         int err;
 942
 943         host->power_state = SDMMC_POWER_OFF;
 944
 945         rtsx_pci_init_cmd(pcr);
 946
 947         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 948         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 949
 950         err = rtsx_pci_send_cmd(pcr, 100);
 951         if (err < 0)
 952                 return err;
 953
 954         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 955         if (err < 0)
 956                 return err;
 957
 958         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 959 }
 960
 961 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 962                 unsigned char power_mode)
 963 {
 964         int err;
 965
 966         if (power_mode == MMC_POWER_OFF)
 967                 err = sd_power_off(host);
 968         else
 969                 err = sd_power_on(host);
 970
 971         return err;
 972 }
 973
 974 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 975 {
 976         struct rtsx_pcr *pcr = host->pcr;
 977         int err = 0;
 978
 979         rtsx_pci_init_cmd(pcr);
 980
 981         switch (timing) {
 982         case MMC_TIMING_UHS_SDR104:
 983         case MMC_TIMING_UHS_SDR50:
 984                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 985                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 986                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 987                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 988                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 989                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 990                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 991                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 992                 break;
 993
 994         case MMC_TIMING_MMC_DDR52:
 995         case MMC_TIMING_UHS_DDR50:
 996                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 997                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 998                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
 999                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1000                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1001                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1002                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1003                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1004                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1005                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1006                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1007                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1008                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1009                 break;
1010
1011         case MMC_TIMING_MMC_HS:
1012         case MMC_TIMING_SD_HS:
1013                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1014                                 0x0C, SD_20_MODE);
1015                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1016                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1017                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1018                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1019                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1020                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1021                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1022                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1023                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1024                 break;
1025
1026         default:
1027                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1028                                 SD_CFG1, 0x0C, SD_20_MODE);
1029                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1030                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1031                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1032                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1033                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1034                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1035                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1036                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1037                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1038                 break;
1039         }
1040
1041         err = rtsx_pci_send_cmd(pcr, 100);
1042
1043         return err;
1044 }
1045
1046 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1047 {
1048         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1049         struct rtsx_pcr *pcr = host->pcr;
1050
1051         if (host->eject)
1052                 return;
1053
1054         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1055                 return;
1056
1057         mutex_lock(&pcr->pcr_mutex);
1058
1059         rtsx_pci_start_run(pcr);
1060
1061         sd_set_bus_width(host, ios->bus_width);
1062         sd_set_power_mode(host, ios->power_mode);
1063         sd_set_timing(host, ios->timing);
1064
1065         host->vpclk = false;
1066         host->double_clk = true;
1067
1068         switch (ios->timing) {
1069         case MMC_TIMING_UHS_SDR104:
1070         case MMC_TIMING_UHS_SDR50:
1071                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1072                 host->vpclk = true;
1073                 host->double_clk = false;
1074                 break;
1075         case MMC_TIMING_MMC_DDR52:
1076         case MMC_TIMING_UHS_DDR50:
1077         case MMC_TIMING_UHS_SDR25:
1078                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1079                 break;
1080         default:
1081                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1082                 break;
1083         }
1084
1085         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1086
1087         host->clock = ios->clock;
1088         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1089                         host->initial_mode, host->double_clk, host->vpclk);
1090
1091         mutex_unlock(&pcr->pcr_mutex);
1092 }
1093
1094 static int sdmmc_get_ro(struct mmc_host *mmc)
1095 {
1096         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1097         struct rtsx_pcr *pcr = host->pcr;
1098         int ro = 0;
1099         u32 val;
1100
1101         if (host->eject)
1102                 return -ENOMEDIUM;
1103
1104         mutex_lock(&pcr->pcr_mutex);
1105
1106         rtsx_pci_start_run(pcr);
1107
1108         /* Check SD mechanical write-protect switch */
1109         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1110         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1111         if (val & SD_WRITE_PROTECT)
1112                 ro = 1;
1113
1114         mutex_unlock(&pcr->pcr_mutex);
1115
1116         return ro;
1117 }
1118
1119 static int sdmmc_get_cd(struct mmc_host *mmc)
1120 {
1121         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1122         struct rtsx_pcr *pcr = host->pcr;
1123         int cd = 0;
1124         u32 val;
1125
1126         if (host->eject)
1127                 return cd;
1128
1129         mutex_lock(&pcr->pcr_mutex);
1130
1131         rtsx_pci_start_run(pcr);
1132
1133         /* Check SD card detect */
1134         val = rtsx_pci_card_exist(pcr);
1135         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1136         if (val & SD_EXIST)
1137                 cd = 1;
1138
1139         mutex_unlock(&pcr->pcr_mutex);
1140
1141         return cd;
1142 }
1143
1144 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1145 {
1146         struct rtsx_pcr *pcr = host->pcr;
1147         int err;
1148         u8 stat;
1149
1150         /* Reference to Signal Voltage Switch Sequence in SD spec.
1151          * Wait for a period of time so that the card can drive SD_CMD and
1152          * SD_DAT[3:0] to low after sending back CMD11 response.
1153          */
1154         mdelay(1);
1155
1156         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1157          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1158          * abort the voltage switch sequence;
1159          */
1160         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1161         if (err < 0)
1162                 return err;
1163
1164         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1165                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1166                 return -EINVAL;
1167
1168         /* Stop toggle SD clock */
1169         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1170                         0xFF, SD_CLK_FORCE_STOP);
1171         if (err < 0)
1172                 return err;
1173
1174         return 0;
1175 }
1176
1177 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1178 {
1179         struct rtsx_pcr *pcr = host->pcr;
1180         int err;
1181         u8 stat, mask, val;
1182
1183         /* Wait 1.8V output of voltage regulator in card stable */
1184         msleep(50);
1185
1186         /* Toggle SD clock again */
1187         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1188         if (err < 0)
1189                 return err;
1190
1191         /* Wait for a period of time so that the card can drive
1192          * SD_DAT[3:0] to high at 1.8V
1193          */
1194         msleep(20);
1195
1196         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1197         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1198         if (err < 0)
1199                 return err;
1200
1201         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1202                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1203         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1204                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1205         if ((stat & mask) != val) {
1206                 dev_dbg(sdmmc_dev(host),
1207                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1208                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1209                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1210                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1211                 return -EINVAL;
1212         }
1213
1214         return 0;
1215 }
1216
1217 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1218 {
1219         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1220         struct rtsx_pcr *pcr = host->pcr;
1221         int err = 0;
1222         u8 voltage;
1223
1224         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1225                         __func__, ios->signal_voltage);
1226
1227         if (host->eject)
1228                 return -ENOMEDIUM;
1229
1230         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1231         if (err)
1232                 return err;
1233
1234         mutex_lock(&pcr->pcr_mutex);
1235
1236         rtsx_pci_start_run(pcr);
1237
1238         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1239                 voltage = OUTPUT_3V3;
1240         else
1241                 voltage = OUTPUT_1V8;
1242
1243         if (voltage == OUTPUT_1V8) {
1244                 err = sd_wait_voltage_stable_1(host);
1245                 if (err < 0)
1246                         goto out;
1247         }
1248
1249         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1250         if (err < 0)
1251                 goto out;
1252
1253         if (voltage == OUTPUT_1V8) {
1254                 err = sd_wait_voltage_stable_2(host);
1255                 if (err < 0)
1256                         goto out;
1257         }
1258
1259 out:
1260         /* Stop toggle SD clock in idle */
1261         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1262                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1263
1264         mutex_unlock(&pcr->pcr_mutex);
1265
1266         return err;
1267 }
1268
1269 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1270 {
1271         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1272         struct rtsx_pcr *pcr = host->pcr;
1273         int err = 0;
1274
1275         if (host->eject)
1276                 return -ENOMEDIUM;
1277
1278         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1279         if (err)
1280                 return err;
1281
1282         mutex_lock(&pcr->pcr_mutex);
1283
1284         rtsx_pci_start_run(pcr);
1285
1286         /* Set initial TX phase */
1287         switch (mmc->ios.timing) {
1288         case MMC_TIMING_UHS_SDR104:
1289                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1290                 break;
1291
1292         case MMC_TIMING_UHS_SDR50:
1293                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1294                 break;
1295
1296         case MMC_TIMING_UHS_DDR50:
1297                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1298                 break;
1299
1300         default:
1301                 err = 0;
1302         }
1303
1304         if (err)
1305                 goto out;
1306
1307         /* Tuning RX phase */
1308         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1309                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1310                 err = sd_tuning_rx(host, opcode);
1311         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1312                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1313
1314 out:
1315         mutex_unlock(&pcr->pcr_mutex);
1316
1317         return err;
1318 }
1319
1320 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1321         .pre_req = sdmmc_pre_req,
1322         .post_req = sdmmc_post_req,
1323         .request = sdmmc_request,
1324         .set_ios = sdmmc_set_ios,
1325         .get_ro = sdmmc_get_ro,
1326         .get_cd = sdmmc_get_cd,
1327         .start_signal_voltage_switch = sdmmc_switch_voltage,
1328         .execute_tuning = sdmmc_execute_tuning,
1329 };
1330
1331 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1332 {
1333         struct mmc_host *mmc = host->mmc;
1334         struct rtsx_pcr *pcr = host->pcr;
1335
1336         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1337
1338         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1339                 mmc->caps |= MMC_CAP_UHS_SDR50;
1340         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1341                 mmc->caps |= MMC_CAP_UHS_SDR104;
1342         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1343                 mmc->caps |= MMC_CAP_UHS_DDR50;
1344         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1345                 mmc->caps |= MMC_CAP_1_8V_DDR;
1346         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1347                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1348 }
1349
1350 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1351 {
1352         struct mmc_host *mmc = host->mmc;
1353
1354         mmc->f_min = 250000;
1355         mmc->f_max = 208000000;
1356         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1357         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1358                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1359                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1360         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1361         mmc->max_current_330 = 400;
1362         mmc->max_current_180 = 800;
1363         mmc->ops = &realtek_pci_sdmmc_ops;
1364
1365         init_extra_caps(host);
1366
1367         mmc->max_segs = 256;
1368         mmc->max_seg_size = 65536;
1369         mmc->max_blk_size = 512;
1370         mmc->max_blk_count = 65535;
1371         mmc->max_req_size = 524288;
1372 }
1373
1374 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1375 {
1376         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1377
1378         host->cookie = -1;
1379         mmc_detect_change(host->mmc, 0);
1380 }
1381
1382 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1383 {
1384         struct mmc_host *mmc;
1385         struct realtek_pci_sdmmc *host;
1386         struct rtsx_pcr *pcr;
1387         struct pcr_handle *handle = pdev->dev.platform_data;
1388
1389         if (!handle)
1390                 return -ENXIO;
1391
1392         pcr = handle->pcr;
1393         if (!pcr)
1394                 return -ENXIO;
1395
1396         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1397
1398         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1399         if (!mmc)
1400                 return -ENOMEM;
1401
1402         host = mmc_priv(mmc);
1403         host->pcr = pcr;
1404         host->mmc = mmc;
1405         host->pdev = pdev;
1406         host->cookie = -1;
1407         host->power_state = SDMMC_POWER_OFF;
1408         INIT_WORK(&host->work, sd_request);
1409         platform_set_drvdata(pdev, host);
1410         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1411         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1412
1413         mutex_init(&host->host_mutex);
1414
1415         realtek_init_host(host);
1416
1417         mmc_add_host(mmc);
1418
1419         return 0;
1420 }
1421
1422 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1423 {
1424         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1425         struct rtsx_pcr *pcr;
1426         struct mmc_host *mmc;
1427
1428         if (!host)
1429                 return 0;
1430
1431         pcr = host->pcr;
1432         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1433         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1434         mmc = host->mmc;
1435
1436         cancel_work_sync(&host->work);
1437
1438         mutex_lock(&host->host_mutex);
1439         if (host->mrq) {
1440                 dev_dbg(&(pdev->dev),
1441                         "%s: Controller removed during transfer\n",
1442                         mmc_hostname(mmc));
1443
1444                 rtsx_pci_complete_unfinished_transfer(pcr);
1445
1446                 host->mrq->cmd->error = -ENOMEDIUM;
1447                 if (host->mrq->stop)
1448                         host->mrq->stop->error = -ENOMEDIUM;
1449                 mmc_request_done(mmc, host->mrq);
1450         }
1451         mutex_unlock(&host->host_mutex);
1452
1453         mmc_remove_host(mmc);
1454         host->eject = true;
1455
1456         flush_work(&host->work);
1457
1458         mmc_free_host(mmc);
1459
1460         dev_dbg(&(pdev->dev),
1461                 ": Realtek PCI-E SDMMC controller has been removed\n");
1462
1463         return 0;
1464 }
1465
1466 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1467         {
1468                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1469         }, {
1470                 /* sentinel */
1471         }
1472 };
1473 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1474
1475 static struct platform_driver rtsx_pci_sdmmc_driver = {
1476         .probe          = rtsx_pci_sdmmc_drv_probe,
1477         .remove         = rtsx_pci_sdmmc_drv_remove,
1478         .id_table       = rtsx_pci_sdmmc_ids,
1479         .driver         = {
1480                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1481         },
1482 };
1483 module_platform_driver(rtsx_pci_sdmmc_driver);
1484
1485 MODULE_LICENSE("GPL");
1486 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1487 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");