4 * TI OMAP3 ISP - CSI2 module
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
27 #ifndef OMAP3_ISP_CSI2_H
28 #define OMAP3_ISP_CSI2_H
30 #include <linux/types.h>
31 #include <linux/videodev2.h>
35 /* This is not an exhaustive list */
36 enum isp_csi2_pix_formats {
37 CSI2_PIX_FMT_OTHERS = 0,
38 CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
39 CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
40 CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
41 CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
42 CSI2_PIX_FMT_RAW8 = 0x2a,
43 CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
44 CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
45 CSI2_PIX_FMT_RAW8_VP = 0x12a,
46 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
47 CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,
48 CSI2_USERDEF_8BIT_DATA1 = 0x40,
51 enum isp_csi2_irqevents {
53 SHORT_PACKET_IRQ = 0x2000,
54 ECC_CORRECTION_IRQ = 0x1000,
55 ECC_NO_CORRECTION_IRQ = 0x800,
56 COMPLEXIO2_ERR_IRQ = 0x400,
57 COMPLEXIO1_ERR_IRQ = 0x200,
69 enum isp_csi2_ctx_irqevents {
70 CTX_ECC_CORRECTION = 0x100,
71 CTX_LINE_NUMBER = 0x80,
72 CTX_FRAME_NUMBER = 0x40,
80 enum isp_csi2_frame_mode {
81 ISP_CSI2_FRAME_IMMEDIATE,
82 ISP_CSI2_FRAME_AFTERFEC,
85 #define ISP_CSI2_MAX_CTX_NUM 7
87 struct isp_csi2_ctx_cfg {
88 u8 ctxnum; /* context number 0 - 7 */
91 /* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */
93 u16 format_id; /* as in CSI2_CTx_CTRL2[9:0] */
94 u8 dpcm_predictor; /* 1: simple, 0: advanced */
96 /* Fields in CSI2_CTx_CTRL1/3 - Shadowed */
107 struct isp_csi2_timing_cfg {
108 u8 ionum; /* IO1 or IO2 as in CSI2_TIMING */
109 unsigned force_rx_mode:1;
110 unsigned stop_state_16x:1;
111 unsigned stop_state_4x:1;
112 u16 stop_state_counter;
115 struct isp_csi2_ctrl_cfg {
119 enum isp_csi2_frame_mode frame_mode;
124 #define CSI2_PAD_SINK 0
125 #define CSI2_PAD_SOURCE 1
126 #define CSI2_PADS_NUM 2
128 #define CSI2_OUTPUT_CCDC (1 << 0)
129 #define CSI2_OUTPUT_MEMORY (1 << 1)
131 struct isp_csi2_device {
132 struct v4l2_subdev subdev;
133 struct media_pad pads[CSI2_PADS_NUM];
134 struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
136 struct isp_video video_out;
137 struct isp_device *isp;
139 u8 available; /* Is the IP present on the silicon? */
141 /* mem resources - enums as defined in enum isp_mem_resources */
145 u32 output; /* output to CCDC, memory or both? */
146 bool dpcm_decompress;
147 unsigned int frame_skip;
149 struct isp_csiphy *phy;
150 struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1];
151 struct isp_csi2_timing_cfg timing[2];
152 struct isp_csi2_ctrl_cfg ctrl;
153 enum isp_pipeline_stream_state state;
154 wait_queue_head_t wait;
158 void omap3isp_csi2_isr(struct isp_csi2_device *csi2);
159 int omap3isp_csi2_reset(struct isp_csi2_device *csi2);
160 int omap3isp_csi2_init(struct isp_device *isp);
161 void omap3isp_csi2_cleanup(struct isp_device *isp);
162 void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2);
163 int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
164 struct v4l2_device *vdev);
165 #endif /* OMAP3_ISP_CSI2_H */