drivers/media/tuners/qt1010.c

   1 /*
   2  *  Driver for Quantek QT1010 silicon tuner
   3  *
   4  *  Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
   5  *                     Aapo Tahkola <aet@rasterburn.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21 #include "qt1010.h"
  22 #include "qt1010_priv.h"
  23
  24 /* read single register */
  25 static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
  26 {
  27         struct i2c_msg msg[2] = {
  28                 { .addr = priv->cfg->i2c_address,
  29                   .flags = 0, .buf = &reg, .len = 1 },
  30                 { .addr = priv->cfg->i2c_address,
  31                   .flags = I2C_M_RD, .buf = val, .len = 1 },
  32         };
  33
  34         if (i2c_transfer(priv->i2c, msg, 2) != 2) {
  35                 dev_warn(&priv->i2c->dev, "%s: i2c rd failed reg=%02x\n",
  36                                 KBUILD_MODNAME, reg);
  37                 return -EREMOTEIO;
  38         }
  39         return 0;
  40 }
  41
  42 /* write single register */
  43 static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
  44 {
  45         u8 buf[2] = { reg, val };
  46         struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
  47                                .flags = 0, .buf = buf, .len = 2 };
  48
  49         if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
  50                 dev_warn(&priv->i2c->dev, "%s: i2c wr failed reg=%02x\n",
  51                                 KBUILD_MODNAME, reg);
  52                 return -EREMOTEIO;
  53         }
  54         return 0;
  55 }
  56
  57 /* dump all registers */
  58 static void qt1010_dump_regs(struct qt1010_priv *priv)
  59 {
  60         u8 reg, val;
  61
  62         for (reg = 0; ; reg++) {
  63                 if (reg % 16 == 0) {
  64                         if (reg)
  65                                 printk(KERN_CONT "\n");
  66                         printk(KERN_DEBUG "%02x:", reg);
  67                 }
  68                 if (qt1010_readreg(priv, reg, &val) == 0)
  69                         printk(KERN_CONT " %02x", val);
  70                 else
  71                         printk(KERN_CONT " --");
  72                 if (reg == 0x2f)
  73                         break;
  74         }
  75         printk(KERN_CONT "\n");
  76 }
  77
  78 static int qt1010_set_params(struct dvb_frontend *fe)
  79 {
  80         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  81         struct qt1010_priv *priv;
  82         int err;
  83         u32 freq, div, mod1, mod2;
  84         u8 i, tmpval, reg05;
  85         qt1010_i2c_oper_t rd[48] = {
  86                 { QT1010_WR, 0x01, 0x80 },
  87                 { QT1010_WR, 0x02, 0x3f },
  88                 { QT1010_WR, 0x05, 0xff }, /* 02 c write */
  89                 { QT1010_WR, 0x06, 0x44 },
  90                 { QT1010_WR, 0x07, 0xff }, /* 04 c write */
  91                 { QT1010_WR, 0x08, 0x08 },
  92                 { QT1010_WR, 0x09, 0xff }, /* 06 c write */
  93                 { QT1010_WR, 0x0a, 0xff }, /* 07 c write */
  94                 { QT1010_WR, 0x0b, 0xff }, /* 08 c write */
  95                 { QT1010_WR, 0x0c, 0xe1 },
  96                 { QT1010_WR, 0x1a, 0xff }, /* 10 c write */
  97                 { QT1010_WR, 0x1b, 0x00 },
  98                 { QT1010_WR, 0x1c, 0x89 },
  99                 { QT1010_WR, 0x11, 0xff }, /* 13 c write */
 100                 { QT1010_WR, 0x12, 0xff }, /* 14 c write */
 101                 { QT1010_WR, 0x22, 0xff }, /* 15 c write */
 102                 { QT1010_WR, 0x1e, 0x00 },
 103                 { QT1010_WR, 0x1e, 0xd0 },
 104                 { QT1010_RD, 0x22, 0xff }, /* 16 c read */
 105                 { QT1010_WR, 0x1e, 0x00 },
 106                 { QT1010_RD, 0x05, 0xff }, /* 20 c read */
 107                 { QT1010_RD, 0x22, 0xff }, /* 21 c read */
 108                 { QT1010_WR, 0x23, 0xd0 },
 109                 { QT1010_WR, 0x1e, 0x00 },
 110                 { QT1010_WR, 0x1e, 0xe0 },
 111                 { QT1010_RD, 0x23, 0xff }, /* 25 c read */
 112                 { QT1010_RD, 0x23, 0xff }, /* 26 c read */
 113                 { QT1010_WR, 0x1e, 0x00 },
 114                 { QT1010_WR, 0x24, 0xd0 },
 115                 { QT1010_WR, 0x1e, 0x00 },
 116                 { QT1010_WR, 0x1e, 0xf0 },
 117                 { QT1010_RD, 0x24, 0xff }, /* 31 c read */
 118                 { QT1010_WR, 0x1e, 0x00 },
 119                 { QT1010_WR, 0x14, 0x7f },
 120                 { QT1010_WR, 0x15, 0x7f },
 121                 { QT1010_WR, 0x05, 0xff }, /* 35 c write */
 122                 { QT1010_WR, 0x06, 0x00 },
 123                 { QT1010_WR, 0x15, 0x1f },
 124                 { QT1010_WR, 0x16, 0xff },
 125                 { QT1010_WR, 0x18, 0xff },
 126                 { QT1010_WR, 0x1f, 0xff }, /* 40 c write */
 127                 { QT1010_WR, 0x20, 0xff }, /* 41 c write */
 128                 { QT1010_WR, 0x21, 0x53 },
 129                 { QT1010_WR, 0x25, 0xff }, /* 43 c write */
 130                 { QT1010_WR, 0x26, 0x15 },
 131                 { QT1010_WR, 0x00, 0xff }, /* 45 c write */
 132                 { QT1010_WR, 0x02, 0x00 },
 133                 { QT1010_WR, 0x01, 0x00 }
 134         };
 135
 136 #define FREQ1 32000000 /* 32 MHz */
 137 #define FREQ2  4000000 /* 4 MHz Quartz oscillator in the stick? */
 138
 139         priv = fe->tuner_priv;
 140         freq = c->frequency;
 141         div = (freq + QT1010_OFFSET) / QT1010_STEP;
 142         freq = (div * QT1010_STEP) - QT1010_OFFSET;
 143         mod1 = (freq + QT1010_OFFSET) % FREQ1;
 144         mod2 = (freq + QT1010_OFFSET) % FREQ2;
 145         priv->frequency = freq;
 146
 147         if (fe->ops.i2c_gate_ctrl)
 148                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 149
 150         /* reg 05 base value */
 151         if      (freq < 290000000) reg05 = 0x14; /* 290 MHz */
 152         else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
 153         else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
 154         else                       reg05 = 0x74;
 155
 156         /* 0x5 */
 157         rd[2].val = reg05;
 158
 159         /* 07 - set frequency: 32 MHz scale */
 160         rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
 161
 162         /* 09 - changes every 8/24 MHz */
 163         if (mod1 < 8000000) rd[6].val = 0x1d;
 164         else                rd[6].val = 0x1c;
 165
 166         /* 0a - set frequency: 4 MHz scale (max 28 MHz) */
 167         if      (mod1 < 1*FREQ2) rd[7].val = 0x09; /*  +0 MHz */
 168         else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /*  +4 MHz */
 169         else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /*  +8 MHz */
 170         else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
 171         else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
 172         else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
 173         else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
 174         else                     rd[7].val = 0x0a; /* +28 MHz */
 175
 176         /* 0b - changes every 2/2 MHz */
 177         if (mod2 < 2000000) rd[8].val = 0x45;
 178         else                rd[8].val = 0x44;
 179
 180         /* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
 181         tmpval = 0x78; /* byte, overflows intentionally */
 182         rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
 183
 184         /* 11 */
 185         rd[13].val = 0xfd; /* TODO: correct value calculation */
 186
 187         /* 12 */
 188         rd[14].val = 0x91; /* TODO: correct value calculation */
 189
 190         /* 22 */
 191         if      (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
 192         else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
 193         else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
 194         else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
 195         else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
 196         else                       rd[15].val = 0xd0;
 197
 198         /* 05 */
 199         rd[35].val = (reg05 & 0xf0);
 200
 201         /* 1f */
 202         if      (mod1 <  8000000) tmpval = 0x00;
 203         else if (mod1 < 12000000) tmpval = 0x01;
 204         else if (mod1 < 16000000) tmpval = 0x02;
 205         else if (mod1 < 24000000) tmpval = 0x03;
 206         else if (mod1 < 28000000) tmpval = 0x04;
 207         else                      tmpval = 0x05;
 208         rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
 209
 210         /* 20 */
 211         if      (mod1 <  8000000) tmpval = 0x00;
 212         else if (mod1 < 12000000) tmpval = 0x01;
 213         else if (mod1 < 20000000) tmpval = 0x02;
 214         else if (mod1 < 24000000) tmpval = 0x03;
 215         else if (mod1 < 28000000) tmpval = 0x04;
 216         else                      tmpval = 0x05;
 217         rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
 218
 219         /* 25 */
 220         rd[43].val = priv->reg25_init_val;
 221
 222         /* 00 */
 223         rd[45].val = 0x92; /* TODO: correct value calculation */
 224
 225         dev_dbg(&priv->i2c->dev,
 226                         "%s: freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \
 227                         "1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \
 228                         "20:%02x 25:%02x 00:%02x\n", __func__, \
 229                         freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \
 230                         rd[8].val, rd[10].val, rd[13].val, rd[14].val, \
 231                         rd[15].val, rd[35].val, rd[40].val, rd[41].val, \
 232                         rd[43].val, rd[45].val);
 233
 234         for (i = 0; i < ARRAY_SIZE(rd); i++) {
 235                 if (rd[i].oper == QT1010_WR) {
 236                         err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
 237                 } else { /* read is required to proper locking */
 238                         err = qt1010_readreg(priv, rd[i].reg, &tmpval);
 239                 }
 240                 if (err) return err;
 241         }
 242
 243         qt1010_dump_regs(priv);
 244
 245         if (fe->ops.i2c_gate_ctrl)
 246                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 247
 248         return 0;
 249 }
 250
 251 static int qt1010_init_meas1(struct qt1010_priv *priv,
 252                              u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
 253 {
 254         u8 i, val1, val2;
 255         int err;
 256
 257         qt1010_i2c_oper_t i2c_data[] = {
 258                 { QT1010_WR, reg, reg_init_val },
 259                 { QT1010_WR, 0x1e, 0x00 },
 260                 { QT1010_WR, 0x1e, oper },
 261                 { QT1010_RD, reg, 0xff }
 262         };
 263
 264         for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
 265                 if (i2c_data[i].oper == QT1010_WR) {
 266                         err = qt1010_writereg(priv, i2c_data[i].reg,
 267                                               i2c_data[i].val);
 268                 } else {
 269                         err = qt1010_readreg(priv, i2c_data[i].reg, &val2);
 270                 }
 271                 if (err) return err;
 272         }
 273
 274         do {
 275                 val1 = val2;
 276                 err = qt1010_readreg(priv, reg, &val2);
 277                 if (err) return err;
 278                 dev_dbg(&priv->i2c->dev, "%s: compare reg:%02x %02x %02x\n",
 279                                 __func__, reg, val1, val2);
 280         } while (val1 != val2);
 281         *retval = val1;
 282
 283         return qt1010_writereg(priv, 0x1e, 0x00);
 284 }
 285
 286 static int qt1010_init_meas2(struct qt1010_priv *priv,
 287                             u8 reg_init_val, u8 *retval)
 288 {
 289         u8 i, val;
 290         int err;
 291         qt1010_i2c_oper_t i2c_data[] = {
 292                 { QT1010_WR, 0x07, reg_init_val },
 293                 { QT1010_WR, 0x22, 0xd0 },
 294                 { QT1010_WR, 0x1e, 0x00 },
 295                 { QT1010_WR, 0x1e, 0xd0 },
 296                 { QT1010_RD, 0x22, 0xff },
 297                 { QT1010_WR, 0x1e, 0x00 },
 298                 { QT1010_WR, 0x22, 0xff }
 299         };
 300         for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
 301                 if (i2c_data[i].oper == QT1010_WR) {
 302                         err = qt1010_writereg(priv, i2c_data[i].reg,
 303                                               i2c_data[i].val);
 304                 } else {
 305                         err = qt1010_readreg(priv, i2c_data[i].reg, &val);
 306                 }
 307                 if (err) return err;
 308         }
 309         *retval = val;
 310         return 0;
 311 }
 312
 313 static int qt1010_init(struct dvb_frontend *fe)
 314 {
 315         struct qt1010_priv *priv = fe->tuner_priv;
 316         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 317         int err = 0;
 318         u8 i, tmpval, *valptr = NULL;
 319
 320         qt1010_i2c_oper_t i2c_data[] = {
 321                 { QT1010_WR, 0x01, 0x80 },
 322                 { QT1010_WR, 0x0d, 0x84 },
 323                 { QT1010_WR, 0x0e, 0xb7 },
 324                 { QT1010_WR, 0x2a, 0x23 },
 325                 { QT1010_WR, 0x2c, 0xdc },
 326                 { QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
 327                 { QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
 328                 { QT1010_WR, 0x2b, 0x70 },
 329                 { QT1010_WR, 0x2a, 0x23 },
 330                 { QT1010_M1, 0x26, 0x08 },
 331                 { QT1010_M1, 0x82, 0xff },
 332                 { QT1010_WR, 0x05, 0x14 },
 333                 { QT1010_WR, 0x06, 0x44 },
 334                 { QT1010_WR, 0x07, 0x28 },
 335                 { QT1010_WR, 0x08, 0x0b },
 336                 { QT1010_WR, 0x11, 0xfd },
 337                 { QT1010_M1, 0x22, 0x0d },
 338                 { QT1010_M1, 0xd0, 0xff },
 339                 { QT1010_WR, 0x06, 0x40 },
 340                 { QT1010_WR, 0x16, 0xf0 },
 341                 { QT1010_WR, 0x02, 0x38 },
 342                 { QT1010_WR, 0x03, 0x18 },
 343                 { QT1010_WR, 0x20, 0xe0 },
 344                 { QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
 345                 { QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
 346                 { QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
 347                 { QT1010_WR, 0x03, 0x19 },
 348                 { QT1010_WR, 0x02, 0x3f },
 349                 { QT1010_WR, 0x21, 0x53 },
 350                 { QT1010_RD, 0x21, 0xff },
 351                 { QT1010_WR, 0x11, 0xfd },
 352                 { QT1010_WR, 0x05, 0x34 },
 353                 { QT1010_WR, 0x06, 0x44 },
 354                 { QT1010_WR, 0x08, 0x08 }
 355         };
 356
 357         if (fe->ops.i2c_gate_ctrl)
 358                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 359
 360         for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
 361                 switch (i2c_data[i].oper) {
 362                 case QT1010_WR:
 363                         err = qt1010_writereg(priv, i2c_data[i].reg,
 364                                               i2c_data[i].val);
 365                         break;
 366                 case QT1010_RD:
 367                         if (i2c_data[i].val == 0x20)
 368                                 valptr = &priv->reg20_init_val;
 369                         else
 370                                 valptr = &tmpval;
 371                         err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
 372                         break;
 373                 case QT1010_M1:
 374                         if (i2c_data[i].val == 0x25)
 375                                 valptr = &priv->reg25_init_val;
 376                         else if (i2c_data[i].val == 0x1f)
 377                                 valptr = &priv->reg1f_init_val;
 378                         else
 379                                 valptr = &tmpval;
 380                         err = qt1010_init_meas1(priv, i2c_data[i+1].reg,
 381                                                 i2c_data[i].reg,
 382                                                 i2c_data[i].val, valptr);
 383                         i++;
 384                         break;
 385                 }
 386                 if (err) return err;
 387         }
 388
 389         for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
 390                 if ((err = qt1010_init_meas2(priv, i, &tmpval)))
 391                         return err;
 392
 393         if (!c->frequency)
 394                 c->frequency = 545000000; /* Sigmatek DVB-110 545000000 */
 395                                       /* MSI Megasky 580 GL861 533000000 */
 396         return qt1010_set_params(fe);
 397 }
 398
 399 static int qt1010_release(struct dvb_frontend *fe)
 400 {
 401         kfree(fe->tuner_priv);
 402         fe->tuner_priv = NULL;
 403         return 0;
 404 }
 405
 406 static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 407 {
 408         struct qt1010_priv *priv = fe->tuner_priv;
 409         *frequency = priv->frequency;
 410         return 0;
 411 }
 412
 413 static int qt1010_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
 414 {
 415         *frequency = 36125000;
 416         return 0;
 417 }
 418
 419 static const struct dvb_tuner_ops qt1010_tuner_ops = {
 420         .info = {
 421                 .name           = "Quantek QT1010",
 422                 .frequency_min  = QT1010_MIN_FREQ,
 423                 .frequency_max  = QT1010_MAX_FREQ,
 424                 .frequency_step = QT1010_STEP,
 425         },
 426
 427         .release       = qt1010_release,
 428         .init          = qt1010_init,
 429         /* TODO: implement sleep */
 430
 431         .set_params    = qt1010_set_params,
 432         .get_frequency = qt1010_get_frequency,
 433         .get_if_frequency = qt1010_get_if_frequency,
 434 };
 435
 436 struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
 437                                     struct i2c_adapter *i2c,
 438                                     struct qt1010_config *cfg)
 439 {
 440         struct qt1010_priv *priv = NULL;
 441         u8 id;
 442
 443         priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
 444         if (priv == NULL)
 445                 return NULL;
 446
 447         priv->cfg = cfg;
 448         priv->i2c = i2c;
 449
 450         if (fe->ops.i2c_gate_ctrl)
 451                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 452
 453
 454         /* Try to detect tuner chip. Probably this is not correct register. */
 455         if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
 456                 kfree(priv);
 457                 return NULL;
 458         }
 459
 460         if (fe->ops.i2c_gate_ctrl)
 461                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 462
 463         dev_info(&priv->i2c->dev,
 464                         "%s: Quantek QT1010 successfully identified\n",
 465                         KBUILD_MODNAME);
 466
 467         memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops,
 468                sizeof(struct dvb_tuner_ops));
 469
 470         fe->tuner_priv = priv;
 471         return fe;
 472 }
 473 EXPORT_SYMBOL(qt1010_attach);
 474
 475 MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
 476 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
 477 MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
 478 MODULE_VERSION("0.1");
 479 MODULE_LICENSE("GPL");