1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
4 #include <asm-generic/unaligned.h>
5 #include <linux/acpi.h>
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/pm_runtime.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
14 #define OV08X40_REG_VALUE_08BIT 1
15 #define OV08X40_REG_VALUE_16BIT 2
16 #define OV08X40_REG_VALUE_24BIT 3
18 #define OV08X40_REG_MODE_SELECT 0x0100
19 #define OV08X40_MODE_STANDBY 0x00
20 #define OV08X40_MODE_STREAMING 0x01
22 #define OV08X40_REG_AO_STANDBY 0x1000
23 #define OV08X40_AO_STREAMING 0x04
25 #define OV08X40_REG_MS_SELECT 0x1001
26 #define OV08X40_MS_STANDBY 0x00
27 #define OV08X40_MS_STREAMING 0x04
29 #define OV08X40_REG_SOFTWARE_RST 0x0103
30 #define OV08X40_SOFTWARE_RST 0x01
33 #define OV08X40_REG_CHIP_ID 0x300a
34 #define OV08X40_CHIP_ID 0x560858
36 /* V_TIMING internal */
37 #define OV08X40_REG_VTS 0x380e
38 #define OV08X40_VTS_30FPS 0x09c4 /* the VTS need to be half in normal mode */
39 #define OV08X40_VTS_BIN_30FPS 0x115c
40 #define OV08X40_VTS_MAX 0x7fff
42 /* H TIMING internal */
43 #define OV08X40_REG_HTS 0x380c
44 #define OV08X40_HTS_30FPS 0x0280
46 /* Exposure control */
47 #define OV08X40_REG_EXPOSURE 0x3500
48 #define OV08X40_EXPOSURE_MAX_MARGIN 8
49 #define OV08X40_EXPOSURE_BIN_MAX_MARGIN 2
50 #define OV08X40_EXPOSURE_MIN 4
51 #define OV08X40_EXPOSURE_STEP 1
52 #define OV08X40_EXPOSURE_DEFAULT 0x40
54 /* Short Exposure control */
55 #define OV08X40_REG_SHORT_EXPOSURE 0x3540
57 /* Analog gain control */
58 #define OV08X40_REG_ANALOG_GAIN 0x3508
59 #define OV08X40_ANA_GAIN_MIN 0x80
60 #define OV08X40_ANA_GAIN_MAX 0x07c0
61 #define OV08X40_ANA_GAIN_STEP 1
62 #define OV08X40_ANA_GAIN_DEFAULT 0x80
64 /* Digital gain control */
65 #define OV08X40_REG_DGTL_GAIN_H 0x350a
66 #define OV08X40_REG_DGTL_GAIN_M 0x350b
67 #define OV08X40_REG_DGTL_GAIN_L 0x350c
69 #define OV08X40_DGTL_GAIN_MIN 1024 /* Min = 1 X */
70 #define OV08X40_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */
71 #define OV08X40_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */
72 #define OV08X40_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
74 #define OV08X40_DGTL_GAIN_L_SHIFT 6
75 #define OV08X40_DGTL_GAIN_L_MASK 0x3
76 #define OV08X40_DGTL_GAIN_M_SHIFT 2
77 #define OV08X40_DGTL_GAIN_M_MASK 0xff
78 #define OV08X40_DGTL_GAIN_H_SHIFT 10
79 #define OV08X40_DGTL_GAIN_H_MASK 0x1F
81 /* Test Pattern Control */
82 #define OV08X40_REG_TEST_PATTERN 0x50C1
83 #define OV08X40_REG_ISP 0x5000
84 #define OV08X40_REG_SHORT_TEST_PATTERN 0x53C1
85 #define OV08X40_TEST_PATTERN_ENABLE BIT(0)
86 #define OV08X40_TEST_PATTERN_MASK 0xcf
87 #define OV08X40_TEST_PATTERN_BAR_SHIFT 4
90 #define OV08X40_REG_VFLIP 0x3820
91 #define OV08X40_REG_MIRROR 0x3821
93 /* Horizontal Window Offset */
94 #define OV08X40_REG_H_WIN_OFFSET 0x3811
96 /* Vertical Window Offset */
97 #define OV08X40_REG_V_WIN_OFFSET 0x3813
100 #define OV08X40_REG_XTALK_FIRST_A 0x5a80
101 #define OV08X40_REG_XTALK_LAST_A 0x5b9f
102 #define OV08X40_REG_XTALK_FIRST_B 0x5bc0
103 #define OV08X40_REG_XTALK_LAST_B 0x5f1f
106 OV08X40_LINK_FREQ_400MHZ_INDEX,
114 struct ov08x40_reg_list {
116 const struct ov08x40_reg *regs;
119 /* Link frequency config */
120 struct ov08x40_link_freq_config {
121 /* registers for this link frequency */
122 struct ov08x40_reg_list reg_list;
125 /* Mode : resolution and related config&values */
126 struct ov08x40_mode {
137 /* Line Length Pixels */
140 /* Index of Link frequency config to be used */
142 /* Default register values */
143 struct ov08x40_reg_list reg_list;
145 /* Exposure calculation */
150 static const struct ov08x40_reg mipi_data_rate_800mbps[] = {
170 static const struct ov08x40_reg mode_3856x2416_regs[] = {
682 static const struct ov08x40_reg mode_1928x1208_regs[] = {
1207 static const char * const ov08x40_test_pattern_menu[] = {
1209 "Vertical Color Bar Type 1",
1210 "Vertical Color Bar Type 2",
1211 "Vertical Color Bar Type 3",
1212 "Vertical Color Bar Type 4"
1215 /* Configurations for supported link frequencies */
1216 #define OV08X40_LINK_FREQ_400MHZ 400000000ULL
1217 #define OV08X40_SCLK_96MHZ 96000000ULL
1218 #define OV08X40_EXT_CLK 19200000
1219 #define OV08X40_DATA_LANES 4
1222 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
1223 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
1225 static u64 link_freq_to_pixel_rate(u64 f)
1227 f *= 2 * OV08X40_DATA_LANES;
1233 /* Menu items for LINK_FREQ V4L2 control */
1234 static const s64 link_freq_menu_items[] = {
1235 OV08X40_LINK_FREQ_400MHZ,
1238 /* Link frequency configs */
1239 static const struct ov08x40_link_freq_config link_freq_configs[] = {
1240 [OV08X40_LINK_FREQ_400MHZ_INDEX] = {
1242 .num_of_regs = ARRAY_SIZE(mipi_data_rate_800mbps),
1243 .regs = mipi_data_rate_800mbps,
1249 static const struct ov08x40_mode supported_modes[] = {
1253 .vts_def = OV08X40_VTS_30FPS,
1254 .vts_min = OV08X40_VTS_30FPS,
1255 .llp = 0x10aa, /* in normal mode, tline time = 2 * HTS / SCLK */
1258 .num_of_regs = ARRAY_SIZE(mode_3856x2416_regs),
1259 .regs = mode_3856x2416_regs,
1261 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX,
1262 .exposure_shift = 1,
1263 .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN,
1268 .vts_def = OV08X40_VTS_BIN_30FPS,
1269 .vts_min = OV08X40_VTS_BIN_30FPS,
1273 .num_of_regs = ARRAY_SIZE(mode_1928x1208_regs),
1274 .regs = mode_1928x1208_regs,
1276 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX,
1277 .exposure_shift = 0,
1278 .exposure_margin = OV08X40_EXPOSURE_BIN_MAX_MARGIN,
1283 struct v4l2_subdev sd;
1284 struct media_pad pad;
1286 struct v4l2_ctrl_handler ctrl_handler;
1288 struct v4l2_ctrl *link_freq;
1289 struct v4l2_ctrl *pixel_rate;
1290 struct v4l2_ctrl *vblank;
1291 struct v4l2_ctrl *hblank;
1292 struct v4l2_ctrl *exposure;
1295 const struct ov08x40_mode *cur_mode;
1297 /* Mutex for serialized access */
1300 /* True if the device has been identified */
1304 #define to_ov08x40(_sd) container_of(_sd, struct ov08x40, sd)
1306 /* Read registers up to 4 at a time */
1307 static int ov08x40_read_reg(struct ov08x40 *ov08x,
1308 u16 reg, u32 len, u32 *val)
1310 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1311 struct i2c_msg msgs[2];
1315 __be16 reg_addr_be = cpu_to_be16(reg);
1320 data_be_p = (u8 *)&data_be;
1321 /* Write register address */
1322 msgs[0].addr = client->addr;
1325 msgs[0].buf = (u8 *)®_addr_be;
1327 /* Read data from register */
1328 msgs[1].addr = client->addr;
1329 msgs[1].flags = I2C_M_RD;
1331 msgs[1].buf = &data_be_p[4 - len];
1333 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1334 if (ret != ARRAY_SIZE(msgs))
1337 *val = be32_to_cpu(data_be);
1342 static int ov08x40_burst_fill_regs(struct ov08x40 *ov08x, u16 first_reg,
1343 u16 last_reg, u8 val)
1345 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1346 struct i2c_msg msgs;
1350 num_regs = last_reg - first_reg + 1;
1351 msgs.addr = client->addr;
1353 msgs.len = 2 + num_regs;
1354 msgs.buf = kmalloc(msgs.len, GFP_KERNEL);
1359 put_unaligned_be16(first_reg, msgs.buf);
1361 for (i = 0; i < num_regs; ++i)
1362 msgs.buf[2 + i] = val;
1364 ret = i2c_transfer(client->adapter, &msgs, 1);
1369 dev_err(&client->dev, "Failed regs transferred: %d\n", ret);
1376 /* Write registers up to 4 at a time */
1377 static int ov08x40_write_reg(struct ov08x40 *ov08x,
1378 u16 reg, u32 len, u32 __val)
1380 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1389 buf[1] = reg & 0xff;
1391 val = cpu_to_be32(__val);
1397 buf[buf_i++] = val_p[val_i++];
1399 if (i2c_master_send(client, buf, len + 2) != len + 2)
1405 /* Write a list of registers */
1406 static int ov08x40_write_regs(struct ov08x40 *ov08x,
1407 const struct ov08x40_reg *regs, u32 len)
1409 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1413 for (i = 0; i < len; i++) {
1414 ret = ov08x40_write_reg(ov08x, regs[i].address, 1,
1418 dev_err_ratelimited(&client->dev,
1419 "Failed to write reg 0x%4.4x. error = %d\n",
1420 regs[i].address, ret);
1429 static int ov08x40_write_reg_list(struct ov08x40 *ov08x,
1430 const struct ov08x40_reg_list *r_list)
1432 return ov08x40_write_regs(ov08x, r_list->regs, r_list->num_of_regs);
1435 static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1437 const struct ov08x40_mode *default_mode = &supported_modes[0];
1438 struct ov08x40 *ov08x = to_ov08x40(sd);
1439 struct v4l2_mbus_framefmt *try_fmt =
1440 v4l2_subdev_state_get_format(fh->state, 0);
1442 mutex_lock(&ov08x->mutex);
1444 /* Initialize try_fmt */
1445 try_fmt->width = default_mode->width;
1446 try_fmt->height = default_mode->height;
1447 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1448 try_fmt->field = V4L2_FIELD_NONE;
1450 /* No crop or compose */
1451 mutex_unlock(&ov08x->mutex);
1456 static int ov08x40_update_digital_gain(struct ov08x40 *ov08x, u32 d_gain)
1462 * 0x350C[1:0], 0x350B[7:0], 0x350A[4:0]
1465 val = (d_gain & OV08X40_DGTL_GAIN_L_MASK) << OV08X40_DGTL_GAIN_L_SHIFT;
1466 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_L,
1467 OV08X40_REG_VALUE_08BIT, val);
1471 val = (d_gain >> OV08X40_DGTL_GAIN_M_SHIFT) & OV08X40_DGTL_GAIN_M_MASK;
1472 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_M,
1473 OV08X40_REG_VALUE_08BIT, val);
1477 val = (d_gain >> OV08X40_DGTL_GAIN_H_SHIFT) & OV08X40_DGTL_GAIN_H_MASK;
1479 return ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_H,
1480 OV08X40_REG_VALUE_08BIT, val);
1483 static int ov08x40_enable_test_pattern(struct ov08x40 *ov08x, u32 pattern)
1488 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN,
1489 OV08X40_REG_VALUE_08BIT, &val);
1494 ret = ov08x40_read_reg(ov08x, OV08X40_REG_ISP,
1495 OV08X40_REG_VALUE_08BIT, &val);
1499 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ISP,
1500 OV08X40_REG_VALUE_08BIT,
1505 ret = ov08x40_read_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN,
1506 OV08X40_REG_VALUE_08BIT, &val);
1510 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN,
1511 OV08X40_REG_VALUE_08BIT,
1516 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN,
1517 OV08X40_REG_VALUE_08BIT, &val);
1521 val &= OV08X40_TEST_PATTERN_MASK;
1522 val |= ((pattern - 1) << OV08X40_TEST_PATTERN_BAR_SHIFT) |
1523 OV08X40_TEST_PATTERN_ENABLE;
1525 val &= ~OV08X40_TEST_PATTERN_ENABLE;
1528 return ov08x40_write_reg(ov08x, OV08X40_REG_TEST_PATTERN,
1529 OV08X40_REG_VALUE_08BIT, val);
1532 static int ov08x40_set_ctrl_hflip(struct ov08x40 *ov08x, u32 ctrl_val)
1537 ret = ov08x40_read_reg(ov08x, OV08X40_REG_MIRROR,
1538 OV08X40_REG_VALUE_08BIT, &val);
1542 return ov08x40_write_reg(ov08x, OV08X40_REG_MIRROR,
1543 OV08X40_REG_VALUE_08BIT,
1544 ctrl_val ? val | BIT(2) : val & ~BIT(2));
1547 static int ov08x40_set_ctrl_vflip(struct ov08x40 *ov08x, u32 ctrl_val)
1552 ret = ov08x40_read_reg(ov08x, OV08X40_REG_VFLIP,
1553 OV08X40_REG_VALUE_08BIT, &val);
1557 return ov08x40_write_reg(ov08x, OV08X40_REG_VFLIP,
1558 OV08X40_REG_VALUE_08BIT,
1559 ctrl_val ? val | BIT(2) : val & ~BIT(2));
1562 static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl)
1564 struct ov08x40 *ov08x = container_of(ctrl->handler,
1565 struct ov08x40, ctrl_handler);
1566 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1572 /* Propagate change of current control to all related controls */
1574 case V4L2_CID_VBLANK:
1575 /* Update max exposure while meeting expected vblanking */
1577 * because in normal mode, 1 HTS = 0.5 tline
1578 * fps = sclk / hts / vts
1579 * so the vts value needs to be double
1581 max = ((ov08x->cur_mode->height + ctrl->val) <<
1582 ov08x->cur_mode->exposure_shift) -
1583 ov08x->cur_mode->exposure_margin;
1585 __v4l2_ctrl_modify_range(ov08x->exposure,
1586 ov08x->exposure->minimum,
1587 max, ov08x->exposure->step, max);
1592 * Applying V4L2 control value only happens
1593 * when power is up for streaming
1595 if (!pm_runtime_get_if_in_use(&client->dev))
1599 case V4L2_CID_ANALOGUE_GAIN:
1600 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ANALOG_GAIN,
1601 OV08X40_REG_VALUE_16BIT,
1604 case V4L2_CID_DIGITAL_GAIN:
1605 ret = ov08x40_update_digital_gain(ov08x, ctrl->val);
1607 case V4L2_CID_EXPOSURE:
1608 exp = (ctrl->val << ov08x->cur_mode->exposure_shift) -
1609 ov08x->cur_mode->exposure_margin;
1611 ret = ov08x40_write_reg(ov08x, OV08X40_REG_EXPOSURE,
1612 OV08X40_REG_VALUE_24BIT,
1615 case V4L2_CID_VBLANK:
1616 fll = ((ov08x->cur_mode->height + ctrl->val) <<
1617 ov08x->cur_mode->exposure_shift);
1619 ret = ov08x40_write_reg(ov08x, OV08X40_REG_VTS,
1620 OV08X40_REG_VALUE_16BIT,
1623 case V4L2_CID_TEST_PATTERN:
1624 ret = ov08x40_enable_test_pattern(ov08x, ctrl->val);
1626 case V4L2_CID_HFLIP:
1627 ov08x40_set_ctrl_hflip(ov08x, ctrl->val);
1629 case V4L2_CID_VFLIP:
1630 ov08x40_set_ctrl_vflip(ov08x, ctrl->val);
1633 dev_info(&client->dev,
1634 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1635 ctrl->id, ctrl->val);
1639 pm_runtime_put(&client->dev);
1644 static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = {
1645 .s_ctrl = ov08x40_set_ctrl,
1648 static int ov08x40_enum_mbus_code(struct v4l2_subdev *sd,
1649 struct v4l2_subdev_state *sd_state,
1650 struct v4l2_subdev_mbus_code_enum *code)
1652 /* Only one bayer order(GRBG) is supported */
1653 if (code->index > 0)
1656 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1661 static int ov08x40_enum_frame_size(struct v4l2_subdev *sd,
1662 struct v4l2_subdev_state *sd_state,
1663 struct v4l2_subdev_frame_size_enum *fse)
1665 if (fse->index >= ARRAY_SIZE(supported_modes))
1668 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1671 fse->min_width = supported_modes[fse->index].width;
1672 fse->max_width = fse->min_width;
1673 fse->min_height = supported_modes[fse->index].height;
1674 fse->max_height = fse->min_height;
1679 static void ov08x40_update_pad_format(const struct ov08x40_mode *mode,
1680 struct v4l2_subdev_format *fmt)
1682 fmt->format.width = mode->width;
1683 fmt->format.height = mode->height;
1684 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1685 fmt->format.field = V4L2_FIELD_NONE;
1688 static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x,
1689 struct v4l2_subdev_state *sd_state,
1690 struct v4l2_subdev_format *fmt)
1692 struct v4l2_mbus_framefmt *framefmt;
1694 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1695 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1696 fmt->format = *framefmt;
1698 ov08x40_update_pad_format(ov08x->cur_mode, fmt);
1704 static int ov08x40_get_pad_format(struct v4l2_subdev *sd,
1705 struct v4l2_subdev_state *sd_state,
1706 struct v4l2_subdev_format *fmt)
1708 struct ov08x40 *ov08x = to_ov08x40(sd);
1711 mutex_lock(&ov08x->mutex);
1712 ret = ov08x40_do_get_pad_format(ov08x, sd_state, fmt);
1713 mutex_unlock(&ov08x->mutex);
1719 ov08x40_set_pad_format(struct v4l2_subdev *sd,
1720 struct v4l2_subdev_state *sd_state,
1721 struct v4l2_subdev_format *fmt)
1723 struct ov08x40 *ov08x = to_ov08x40(sd);
1724 const struct ov08x40_mode *mode;
1725 struct v4l2_mbus_framefmt *framefmt;
1733 mutex_lock(&ov08x->mutex);
1735 /* Only one raw bayer(GRBG) order is supported */
1736 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1737 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1739 mode = v4l2_find_nearest_size(supported_modes,
1740 ARRAY_SIZE(supported_modes),
1742 fmt->format.width, fmt->format.height);
1743 ov08x40_update_pad_format(mode, fmt);
1744 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1745 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1746 *framefmt = fmt->format;
1748 ov08x->cur_mode = mode;
1749 __v4l2_ctrl_s_ctrl(ov08x->link_freq, mode->link_freq_index);
1750 link_freq = link_freq_menu_items[mode->link_freq_index];
1751 pixel_rate = link_freq_to_pixel_rate(link_freq);
1752 __v4l2_ctrl_s_ctrl_int64(ov08x->pixel_rate, pixel_rate);
1754 /* Update limits and set FPS to default */
1755 vblank_def = ov08x->cur_mode->vts_def -
1756 ov08x->cur_mode->height;
1757 vblank_min = ov08x->cur_mode->vts_min -
1758 ov08x->cur_mode->height;
1761 * The frame length line should be aligned to a multiple of 4,
1762 * as provided by the sensor vendor, in normal mode.
1764 steps = mode->exposure_shift == 1 ? 4 : 1;
1766 __v4l2_ctrl_modify_range(ov08x->vblank, vblank_min,
1768 - ov08x->cur_mode->height,
1771 __v4l2_ctrl_s_ctrl(ov08x->vblank, vblank_def);
1773 h_blank = ov08x->cur_mode->llp - ov08x->cur_mode->width;
1775 __v4l2_ctrl_modify_range(ov08x->hblank, h_blank,
1776 h_blank, 1, h_blank);
1779 mutex_unlock(&ov08x->mutex);
1784 static int ov08x40_start_streaming(struct ov08x40 *ov08x)
1786 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1787 const struct ov08x40_reg_list *reg_list;
1788 int ret, link_freq_index;
1790 /* Get out of from software reset */
1791 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SOFTWARE_RST,
1792 OV08X40_REG_VALUE_08BIT, OV08X40_SOFTWARE_RST);
1794 dev_err(&client->dev, "%s failed to set powerup registers\n",
1799 link_freq_index = ov08x->cur_mode->link_freq_index;
1800 reg_list = &link_freq_configs[link_freq_index].reg_list;
1802 ret = ov08x40_write_reg_list(ov08x, reg_list);
1804 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1808 /* Apply default values of current mode */
1809 reg_list = &ov08x->cur_mode->reg_list;
1810 ret = ov08x40_write_reg_list(ov08x, reg_list);
1812 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1816 /* Use i2c burst to write register on full size registers */
1817 if (ov08x->cur_mode->exposure_shift == 1) {
1818 ret = ov08x40_burst_fill_regs(ov08x, OV08X40_REG_XTALK_FIRST_A,
1819 OV08X40_REG_XTALK_LAST_A, 0x75);
1821 ret = ov08x40_burst_fill_regs(ov08x,
1822 OV08X40_REG_XTALK_FIRST_B,
1823 OV08X40_REG_XTALK_LAST_B,
1828 dev_err(&client->dev, "%s failed to set regs\n", __func__);
1832 /* Apply customized values from user */
1833 ret = __v4l2_ctrl_handler_setup(ov08x->sd.ctrl_handler);
1837 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT,
1838 OV08X40_REG_VALUE_08BIT,
1839 OV08X40_MODE_STREAMING);
1842 /* Stop streaming */
1843 static int ov08x40_stop_streaming(struct ov08x40 *ov08x)
1845 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT,
1846 OV08X40_REG_VALUE_08BIT, OV08X40_MODE_STANDBY);
1849 static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable)
1851 struct ov08x40 *ov08x = to_ov08x40(sd);
1852 struct i2c_client *client = v4l2_get_subdevdata(sd);
1855 mutex_lock(&ov08x->mutex);
1858 ret = pm_runtime_resume_and_get(&client->dev);
1863 * Apply default & customized values
1864 * and then start streaming.
1866 ret = ov08x40_start_streaming(ov08x);
1870 ov08x40_stop_streaming(ov08x);
1871 pm_runtime_put(&client->dev);
1874 mutex_unlock(&ov08x->mutex);
1879 pm_runtime_put(&client->dev);
1881 mutex_unlock(&ov08x->mutex);
1886 /* Verify chip ID */
1887 static int ov08x40_identify_module(struct ov08x40 *ov08x)
1889 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1893 if (ov08x->identified)
1896 ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID,
1897 OV08X40_REG_VALUE_24BIT, &val);
1901 if (val != OV08X40_CHIP_ID) {
1902 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1903 OV08X40_CHIP_ID, val);
1907 ov08x->identified = true;
1912 static const struct v4l2_subdev_video_ops ov08x40_video_ops = {
1913 .s_stream = ov08x40_set_stream,
1916 static const struct v4l2_subdev_pad_ops ov08x40_pad_ops = {
1917 .enum_mbus_code = ov08x40_enum_mbus_code,
1918 .get_fmt = ov08x40_get_pad_format,
1919 .set_fmt = ov08x40_set_pad_format,
1920 .enum_frame_size = ov08x40_enum_frame_size,
1923 static const struct v4l2_subdev_ops ov08x40_subdev_ops = {
1924 .video = &ov08x40_video_ops,
1925 .pad = &ov08x40_pad_ops,
1928 static const struct media_entity_operations ov08x40_subdev_entity_ops = {
1929 .link_validate = v4l2_subdev_link_validate,
1932 static const struct v4l2_subdev_internal_ops ov08x40_internal_ops = {
1933 .open = ov08x40_open,
1936 static int ov08x40_init_controls(struct ov08x40 *ov08x)
1938 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1939 struct v4l2_fwnode_device_properties props;
1940 struct v4l2_ctrl_handler *ctrl_hdlr;
1947 const struct ov08x40_mode *mode;
1951 ctrl_hdlr = &ov08x->ctrl_handler;
1952 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1956 mutex_init(&ov08x->mutex);
1957 ctrl_hdlr->lock = &ov08x->mutex;
1958 max = ARRAY_SIZE(link_freq_menu_items) - 1;
1959 ov08x->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1964 link_freq_menu_items);
1965 if (ov08x->link_freq)
1966 ov08x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1968 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1970 /* By default, PIXEL_RATE is read only */
1971 ov08x->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
1972 V4L2_CID_PIXEL_RATE,
1973 pixel_rate_min, pixel_rate_max,
1976 mode = ov08x->cur_mode;
1977 vblank_def = mode->vts_def - mode->height;
1978 vblank_min = mode->vts_min - mode->height;
1979 ov08x->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
1982 OV08X40_VTS_MAX - mode->height, 1,
1985 hblank = ov08x->cur_mode->llp - ov08x->cur_mode->width;
1987 ov08x->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
1989 hblank, hblank, 1, hblank);
1991 ov08x->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1993 exposure_max = mode->vts_def - OV08X40_EXPOSURE_MAX_MARGIN;
1994 ov08x->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
1996 OV08X40_EXPOSURE_MIN,
1997 exposure_max, OV08X40_EXPOSURE_STEP,
2000 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
2001 OV08X40_ANA_GAIN_MIN, OV08X40_ANA_GAIN_MAX,
2002 OV08X40_ANA_GAIN_STEP, OV08X40_ANA_GAIN_DEFAULT);
2005 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
2006 OV08X40_DGTL_GAIN_MIN, OV08X40_DGTL_GAIN_MAX,
2007 OV08X40_DGTL_GAIN_STEP, OV08X40_DGTL_GAIN_DEFAULT);
2009 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08x40_ctrl_ops,
2010 V4L2_CID_TEST_PATTERN,
2011 ARRAY_SIZE(ov08x40_test_pattern_menu) - 1,
2012 0, 0, ov08x40_test_pattern_menu);
2014 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2015 V4L2_CID_HFLIP, 0, 1, 1, 0);
2016 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2017 V4L2_CID_VFLIP, 0, 1, 1, 0);
2019 if (ctrl_hdlr->error) {
2020 ret = ctrl_hdlr->error;
2021 dev_err(&client->dev, "%s control init failed (%d)\n",
2026 ret = v4l2_fwnode_device_parse(&client->dev, &props);
2030 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov08x40_ctrl_ops,
2035 ov08x->sd.ctrl_handler = ctrl_hdlr;
2040 v4l2_ctrl_handler_free(ctrl_hdlr);
2041 mutex_destroy(&ov08x->mutex);
2046 static void ov08x40_free_controls(struct ov08x40 *ov08x)
2048 v4l2_ctrl_handler_free(ov08x->sd.ctrl_handler);
2049 mutex_destroy(&ov08x->mutex);
2052 static int ov08x40_check_hwcfg(struct device *dev)
2054 struct v4l2_fwnode_endpoint bus_cfg = {
2055 .bus_type = V4L2_MBUS_CSI2_DPHY
2057 struct fwnode_handle *ep;
2058 struct fwnode_handle *fwnode = dev_fwnode(dev);
2066 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
2069 dev_err(dev, "can't get clock frequency");
2073 if (ext_clk != OV08X40_EXT_CLK) {
2074 dev_err(dev, "external clock %d is not supported",
2079 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
2083 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
2084 fwnode_handle_put(ep);
2088 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV08X40_DATA_LANES) {
2089 dev_err(dev, "number of CSI2 data lanes %d is not supported",
2090 bus_cfg.bus.mipi_csi2.num_data_lanes);
2095 if (!bus_cfg.nr_of_link_frequencies) {
2096 dev_err(dev, "no link frequencies defined");
2101 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
2102 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
2103 if (link_freq_menu_items[i] ==
2104 bus_cfg.link_frequencies[j])
2108 if (j == bus_cfg.nr_of_link_frequencies) {
2109 dev_err(dev, "no link frequency %lld supported",
2110 link_freq_menu_items[i]);
2117 v4l2_fwnode_endpoint_free(&bus_cfg);
2122 static int ov08x40_probe(struct i2c_client *client)
2124 struct ov08x40 *ov08x;
2128 /* Check HW config */
2129 ret = ov08x40_check_hwcfg(&client->dev);
2131 dev_err(&client->dev, "failed to check hwcfg: %d", ret);
2135 ov08x = devm_kzalloc(&client->dev, sizeof(*ov08x), GFP_KERNEL);
2139 /* Initialize subdev */
2140 v4l2_i2c_subdev_init(&ov08x->sd, client, &ov08x40_subdev_ops);
2142 full_power = acpi_dev_state_d0(&client->dev);
2144 /* Check module identity */
2145 ret = ov08x40_identify_module(ov08x);
2147 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
2152 /* Set default mode to max resolution */
2153 ov08x->cur_mode = &supported_modes[0];
2155 ret = ov08x40_init_controls(ov08x);
2159 /* Initialize subdev */
2160 ov08x->sd.internal_ops = &ov08x40_internal_ops;
2161 ov08x->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2162 ov08x->sd.entity.ops = &ov08x40_subdev_entity_ops;
2163 ov08x->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
2165 /* Initialize source pad */
2166 ov08x->pad.flags = MEDIA_PAD_FL_SOURCE;
2167 ret = media_entity_pads_init(&ov08x->sd.entity, 1, &ov08x->pad);
2169 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
2170 goto error_handler_free;
2173 ret = v4l2_async_register_subdev_sensor(&ov08x->sd);
2175 goto error_media_entity;
2178 pm_runtime_set_active(&client->dev);
2179 pm_runtime_enable(&client->dev);
2180 pm_runtime_idle(&client->dev);
2185 media_entity_cleanup(&ov08x->sd.entity);
2188 ov08x40_free_controls(ov08x);
2193 static void ov08x40_remove(struct i2c_client *client)
2195 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2196 struct ov08x40 *ov08x = to_ov08x40(sd);
2198 v4l2_async_unregister_subdev(sd);
2199 media_entity_cleanup(&sd->entity);
2200 ov08x40_free_controls(ov08x);
2202 pm_runtime_disable(&client->dev);
2203 pm_runtime_set_suspended(&client->dev);
2207 static const struct acpi_device_id ov08x40_acpi_ids[] = {
2212 MODULE_DEVICE_TABLE(acpi, ov08x40_acpi_ids);
2215 static struct i2c_driver ov08x40_i2c_driver = {
2218 .acpi_match_table = ACPI_PTR(ov08x40_acpi_ids),
2220 .probe = ov08x40_probe,
2221 .remove = ov08x40_remove,
2222 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
2225 module_i2c_driver(ov08x40_i2c_driver);
2227 MODULE_AUTHOR("Jason Chen <jason.z.chen@intel.com>");
2228 MODULE_AUTHOR("Qingwu Zhang <qingwu.zhang@intel.com>");
2229 MODULE_AUTHOR("Shawn Tu");
2230 MODULE_DESCRIPTION("OmniVision OV08X40 sensor driver");
2231 MODULE_LICENSE("GPL");