drivers/media/dvb/frontends/dib3000mb.c

   1 /*
   2  * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
   3  * DiBcom (http://www.dibcom.fr/)
   4  *
   5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
   6  *
   7  * based on GPL code from DibCom, which has
   8  *
   9  * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License as
  13  *      published by the Free Software Foundation, version 2.
  14  *
  15  * Acknowledgements
  16  *
  17  *  Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
  18  *  sources, on which this driver (and the dvb-dibusb) are based.
  19  *
  20  * see Documentation/dvb/README.dibusb for more information
  21  *
  22  */
  23
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/delay.h>
  30 #include <linux/string.h>
  31 #include <linux/slab.h>
  32
  33 #include "dib3000-common.h"
  34 #include "dib3000mb_priv.h"
  35 #include "dib3000.h"
  36
  37 /* Version information */
  38 #define DRIVER_VERSION "0.1"
  39 #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
  40 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
  41
  42 #ifdef CONFIG_DVB_DIBCOM_DEBUG
  43 static int debug;
  44 module_param(debug, int, 0644);
  45 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
  46 #endif
  47 #define deb_info(args...) dprintk(0x01,args)
  48 #define deb_xfer(args...) dprintk(0x02,args)
  49 #define deb_setf(args...) dprintk(0x04,args)
  50 #define deb_getf(args...) dprintk(0x08,args)
  51
  52 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
  53                                   struct dvb_frontend_parameters *fep);
  54
  55 static int dib3000mb_set_frontend(struct dvb_frontend* fe,
  56                                   struct dvb_frontend_parameters *fep, int tuner)
  57 {
  58         struct dib3000_state* state = fe->demodulator_priv;
  59         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
  60         fe_code_rate_t fe_cr = FEC_NONE;
  61         int search_state, seq;
  62
  63         if (tuner && fe->ops.tuner_ops.set_params) {
  64                 fe->ops.tuner_ops.set_params(fe, fep);
  65                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
  66
  67                 deb_setf("bandwidth: ");
  68                 switch (ofdm->bandwidth) {
  69                         case BANDWIDTH_8_MHZ:
  70                                 deb_setf("8 MHz\n");
  71                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
  72                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
  73                                 break;
  74                         case BANDWIDTH_7_MHZ:
  75                                 deb_setf("7 MHz\n");
  76                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
  77                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
  78                                 break;
  79                         case BANDWIDTH_6_MHZ:
  80                                 deb_setf("6 MHz\n");
  81                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
  82                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
  83                                 break;
  84                         case BANDWIDTH_AUTO:
  85                                 return -EOPNOTSUPP;
  86                         default:
  87                                 err("unkown bandwidth value.");
  88                                 return -EINVAL;
  89                 }
  90         }
  91         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
  92
  93         deb_setf("transmission mode: ");
  94         switch (ofdm->transmission_mode) {
  95                 case TRANSMISSION_MODE_2K:
  96                         deb_setf("2k\n");
  97                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
  98                         break;
  99                 case TRANSMISSION_MODE_8K:
 100                         deb_setf("8k\n");
 101                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
 102                         break;
 103                 case TRANSMISSION_MODE_AUTO:
 104                         deb_setf("auto\n");
 105                         break;
 106                 default:
 107                         return -EINVAL;
 108         }
 109
 110         deb_setf("guard: ");
 111         switch (ofdm->guard_interval) {
 112                 case GUARD_INTERVAL_1_32:
 113                         deb_setf("1_32\n");
 114                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
 115                         break;
 116                 case GUARD_INTERVAL_1_16:
 117                         deb_setf("1_16\n");
 118                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
 119                         break;
 120                 case GUARD_INTERVAL_1_8:
 121                         deb_setf("1_8\n");
 122                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
 123                         break;
 124                 case GUARD_INTERVAL_1_4:
 125                         deb_setf("1_4\n");
 126                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
 127                         break;
 128                 case GUARD_INTERVAL_AUTO:
 129                         deb_setf("auto\n");
 130                         break;
 131                 default:
 132                         return -EINVAL;
 133         }
 134
 135         deb_setf("inversion: ");
 136         switch (fep->inversion) {
 137                 case INVERSION_OFF:
 138                         deb_setf("off\n");
 139                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
 140                         break;
 141                 case INVERSION_AUTO:
 142                         deb_setf("auto ");
 143                         break;
 144                 case INVERSION_ON:
 145                         deb_setf("on\n");
 146                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
 147                         break;
 148                 default:
 149                         return -EINVAL;
 150         }
 151
 152         deb_setf("constellation: ");
 153         switch (ofdm->constellation) {
 154                 case QPSK:
 155                         deb_setf("qpsk\n");
 156                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
 157                         break;
 158                 case QAM_16:
 159                         deb_setf("qam16\n");
 160                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
 161                         break;
 162                 case QAM_64:
 163                         deb_setf("qam64\n");
 164                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
 165                         break;
 166                 case QAM_AUTO:
 167                         break;
 168                 default:
 169                         return -EINVAL;
 170         }
 171         deb_setf("hierachy: ");
 172         switch (ofdm->hierarchy_information) {
 173                 case HIERARCHY_NONE:
 174                         deb_setf("none ");
 175                         /* fall through */
 176                 case HIERARCHY_1:
 177                         deb_setf("alpha=1\n");
 178                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
 179                         break;
 180                 case HIERARCHY_2:
 181                         deb_setf("alpha=2\n");
 182                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
 183                         break;
 184                 case HIERARCHY_4:
 185                         deb_setf("alpha=4\n");
 186                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
 187                         break;
 188                 case HIERARCHY_AUTO:
 189                         deb_setf("alpha=auto\n");
 190                         break;
 191                 default:
 192                         return -EINVAL;
 193         }
 194
 195         deb_setf("hierarchy: ");
 196         if (ofdm->hierarchy_information == HIERARCHY_NONE) {
 197                 deb_setf("none\n");
 198                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
 199                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
 200                 fe_cr = ofdm->code_rate_HP;
 201         } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
 202                 deb_setf("on\n");
 203                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
 204                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
 205                 fe_cr = ofdm->code_rate_LP;
 206         }
 207         deb_setf("fec: ");
 208         switch (fe_cr) {
 209                 case FEC_1_2:
 210                         deb_setf("1_2\n");
 211                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
 212                         break;
 213                 case FEC_2_3:
 214                         deb_setf("2_3\n");
 215                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
 216                         break;
 217                 case FEC_3_4:
 218                         deb_setf("3_4\n");
 219                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
 220                         break;
 221                 case FEC_5_6:
 222                         deb_setf("5_6\n");
 223                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
 224                         break;
 225                 case FEC_7_8:
 226                         deb_setf("7_8\n");
 227                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
 228                         break;
 229                 case FEC_NONE:
 230                         deb_setf("none ");
 231                         break;
 232                 case FEC_AUTO:
 233                         deb_setf("auto\n");
 234                         break;
 235                 default:
 236                         return -EINVAL;
 237         }
 238
 239         seq = dib3000_seq
 240                 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
 241                 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
 242                 [fep->inversion == INVERSION_AUTO];
 243
 244         deb_setf("seq? %d\n", seq);
 245
 246         wr(DIB3000MB_REG_SEQ, seq);
 247
 248         wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
 249
 250         if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
 251                 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
 252                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
 253                 } else {
 254                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
 255                 }
 256
 257                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
 258         } else {
 259                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
 260         }
 261
 262         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
 263         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
 264         wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
 265
 266         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
 267
 268         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
 269
 270         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
 271         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
 272
 273         /* wait for AGC lock */
 274         msleep(70);
 275
 276         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
 277
 278         /* something has to be auto searched */
 279         if (ofdm->constellation == QAM_AUTO ||
 280                 ofdm->hierarchy_information == HIERARCHY_AUTO ||
 281                 fe_cr == FEC_AUTO ||
 282                 fep->inversion == INVERSION_AUTO) {
 283                 int as_count=0;
 284
 285                 deb_setf("autosearch enabled.\n");
 286
 287                 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
 288
 289                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
 290                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
 291
 292                 while ((search_state =
 293                                 dib3000_search_status(
 294                                         rd(DIB3000MB_REG_AS_IRQ_PENDING),
 295                                         rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
 296                         msleep(1);
 297
 298                 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
 299
 300                 if (search_state == 1) {
 301                         struct dvb_frontend_parameters feps;
 302                         if (dib3000mb_get_frontend(fe, &feps) == 0) {
 303                                 deb_setf("reading tuning data from frontend succeeded.\n");
 304                                 return dib3000mb_set_frontend(fe, &feps, 0);
 305                         }
 306                 }
 307
 308         } else {
 309                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
 310                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
 317 {
 318         struct dib3000_state* state = fe->demodulator_priv;
 319
 320         deb_info("dib3000mb is getting up.\n");
 321         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
 322
 323         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
 324
 325         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
 326         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
 327
 328         wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
 329
 330         wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
 331
 332         wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
 333         wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
 334
 335         wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
 336
 337         wr_foreach(dib3000mb_reg_impulse_noise,
 338                         dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
 339
 340         wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
 341
 342         wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
 343
 344         wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
 345
 346         wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
 347
 348         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
 349
 350         wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
 351         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
 352         wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
 353         wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
 354
 355         wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
 356
 357         wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
 358         wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
 359         wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
 360         wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
 361         wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
 362         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
 363         wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
 364         wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
 365         wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
 366         wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
 367         wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
 368         wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
 369         wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
 370         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
 371         wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
 372
 373         wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
 374
 375         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
 376         wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
 377         wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
 378
 379         wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
 380
 381         wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
 382         wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
 383         wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
 384         wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
 385         wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
 386         wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
 387
 388         wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
 389
 390         return 0;
 391 }
 392
 393 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
 394                                   struct dvb_frontend_parameters *fep)
 395 {
 396         struct dib3000_state* state = fe->demodulator_priv;
 397         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
 398         fe_code_rate_t *cr;
 399         u16 tps_val;
 400         int inv_test1,inv_test2;
 401         u32 dds_val, threshold = 0x800000;
 402
 403         if (!rd(DIB3000MB_REG_TPS_LOCK))
 404                 return 0;
 405
 406         dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
 407         deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
 408         if (dds_val < threshold)
 409                 inv_test1 = 0;
 410         else if (dds_val == threshold)
 411                 inv_test1 = 1;
 412         else
 413                 inv_test1 = 2;
 414
 415         dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
 416         deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
 417         if (dds_val < threshold)
 418                 inv_test2 = 0;
 419         else if (dds_val == threshold)
 420                 inv_test2 = 1;
 421         else
 422                 inv_test2 = 2;
 423
 424         fep->inversion =
 425                 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
 426                 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
 427                 INVERSION_ON : INVERSION_OFF;
 428
 429         deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
 430
 431         switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
 432                 case DIB3000_CONSTELLATION_QPSK:
 433                         deb_getf("QPSK ");
 434                         ofdm->constellation = QPSK;
 435                         break;
 436                 case DIB3000_CONSTELLATION_16QAM:
 437                         deb_getf("QAM16 ");
 438                         ofdm->constellation = QAM_16;
 439                         break;
 440                 case DIB3000_CONSTELLATION_64QAM:
 441                         deb_getf("QAM64 ");
 442                         ofdm->constellation = QAM_64;
 443                         break;
 444                 default:
 445                         err("Unexpected constellation returned by TPS (%d)", tps_val);
 446                         break;
 447         }
 448         deb_getf("TPS: %d\n", tps_val);
 449
 450         if (rd(DIB3000MB_REG_TPS_HRCH)) {
 451                 deb_getf("HRCH ON\n");
 452                 cr = &ofdm->code_rate_LP;
 453                 ofdm->code_rate_HP = FEC_NONE;
 454                 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
 455                         case DIB3000_ALPHA_0:
 456                                 deb_getf("HIERARCHY_NONE ");
 457                                 ofdm->hierarchy_information = HIERARCHY_NONE;
 458                                 break;
 459                         case DIB3000_ALPHA_1:
 460                                 deb_getf("HIERARCHY_1 ");
 461                                 ofdm->hierarchy_information = HIERARCHY_1;
 462                                 break;
 463                         case DIB3000_ALPHA_2:
 464                                 deb_getf("HIERARCHY_2 ");
 465                                 ofdm->hierarchy_information = HIERARCHY_2;
 466                                 break;
 467                         case DIB3000_ALPHA_4:
 468                                 deb_getf("HIERARCHY_4 ");
 469                                 ofdm->hierarchy_information = HIERARCHY_4;
 470                                 break;
 471                         default:
 472                                 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
 473                                 break;
 474                 }
 475                 deb_getf("TPS: %d\n", tps_val);
 476
 477                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
 478         } else {
 479                 deb_getf("HRCH OFF\n");
 480                 cr = &ofdm->code_rate_HP;
 481                 ofdm->code_rate_LP = FEC_NONE;
 482                 ofdm->hierarchy_information = HIERARCHY_NONE;
 483
 484                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
 485         }
 486
 487         switch (tps_val) {
 488                 case DIB3000_FEC_1_2:
 489                         deb_getf("FEC_1_2 ");
 490                         *cr = FEC_1_2;
 491                         break;
 492                 case DIB3000_FEC_2_3:
 493                         deb_getf("FEC_2_3 ");
 494                         *cr = FEC_2_3;
 495                         break;
 496                 case DIB3000_FEC_3_4:
 497                         deb_getf("FEC_3_4 ");
 498                         *cr = FEC_3_4;
 499                         break;
 500                 case DIB3000_FEC_5_6:
 501                         deb_getf("FEC_5_6 ");
 502                         *cr = FEC_4_5;
 503                         break;
 504                 case DIB3000_FEC_7_8:
 505                         deb_getf("FEC_7_8 ");
 506                         *cr = FEC_7_8;
 507                         break;
 508                 default:
 509                         err("Unexpected FEC returned by TPS (%d)", tps_val);
 510                         break;
 511         }
 512         deb_getf("TPS: %d\n",tps_val);
 513
 514         switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
 515                 case DIB3000_GUARD_TIME_1_32:
 516                         deb_getf("GUARD_INTERVAL_1_32 ");
 517                         ofdm->guard_interval = GUARD_INTERVAL_1_32;
 518                         break;
 519                 case DIB3000_GUARD_TIME_1_16:
 520                         deb_getf("GUARD_INTERVAL_1_16 ");
 521                         ofdm->guard_interval = GUARD_INTERVAL_1_16;
 522                         break;
 523                 case DIB3000_GUARD_TIME_1_8:
 524                         deb_getf("GUARD_INTERVAL_1_8 ");
 525                         ofdm->guard_interval = GUARD_INTERVAL_1_8;
 526                         break;
 527                 case DIB3000_GUARD_TIME_1_4:
 528                         deb_getf("GUARD_INTERVAL_1_4 ");
 529                         ofdm->guard_interval = GUARD_INTERVAL_1_4;
 530                         break;
 531                 default:
 532                         err("Unexpected Guard Time returned by TPS (%d)", tps_val);
 533                         break;
 534         }
 535         deb_getf("TPS: %d\n", tps_val);
 536
 537         switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
 538                 case DIB3000_TRANSMISSION_MODE_2K:
 539                         deb_getf("TRANSMISSION_MODE_2K ");
 540                         ofdm->transmission_mode = TRANSMISSION_MODE_2K;
 541                         break;
 542                 case DIB3000_TRANSMISSION_MODE_8K:
 543                         deb_getf("TRANSMISSION_MODE_8K ");
 544                         ofdm->transmission_mode = TRANSMISSION_MODE_8K;
 545                         break;
 546                 default:
 547                         err("unexpected transmission mode return by TPS (%d)", tps_val);
 548                         break;
 549         }
 550         deb_getf("TPS: %d\n", tps_val);
 551
 552         return 0;
 553 }
 554
 555 static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
 556 {
 557         struct dib3000_state* state = fe->demodulator_priv;
 558
 559         *stat = 0;
 560
 561         if (rd(DIB3000MB_REG_AGC_LOCK))
 562                 *stat |= FE_HAS_SIGNAL;
 563         if (rd(DIB3000MB_REG_CARRIER_LOCK))
 564                 *stat |= FE_HAS_CARRIER;
 565         if (rd(DIB3000MB_REG_VIT_LCK))
 566                 *stat |= FE_HAS_VITERBI;
 567         if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
 568                 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
 569
 570         deb_getf("actual status is %2x\n",*stat);
 571
 572         deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
 573                         rd(DIB3000MB_REG_TPS_LOCK),
 574                         rd(DIB3000MB_REG_TPS_QAM),
 575                         rd(DIB3000MB_REG_TPS_HRCH),
 576                         rd(DIB3000MB_REG_TPS_VIT_ALPHA),
 577                         rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
 578                         rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
 579                         rd(DIB3000MB_REG_TPS_GUARD_TIME),
 580                         rd(DIB3000MB_REG_TPS_FFT),
 581                         rd(DIB3000MB_REG_TPS_CELL_ID));
 582
 583         //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 584         return 0;
 585 }
 586
 587 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
 588 {
 589         struct dib3000_state* state = fe->demodulator_priv;
 590
 591         *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
 592         return 0;
 593 }
 594
 595 /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
 596 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
 597 {
 598         struct dib3000_state* state = fe->demodulator_priv;
 599
 600         *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
 601         return 0;
 602 }
 603
 604 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
 605 {
 606         struct dib3000_state* state = fe->demodulator_priv;
 607         short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
 608         int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
 609                 rd(DIB3000MB_REG_NOISE_POWER_LSB);
 610         *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
 611         return 0;
 612 }
 613
 614 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
 615 {
 616         struct dib3000_state* state = fe->demodulator_priv;
 617
 618         *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
 619         return 0;
 620 }
 621
 622 static int dib3000mb_sleep(struct dvb_frontend* fe)
 623 {
 624         struct dib3000_state* state = fe->demodulator_priv;
 625         deb_info("dib3000mb is going to bed.\n");
 626         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
 627         return 0;
 628 }
 629
 630 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
 631 {
 632         tune->min_delay_ms = 800;
 633         return 0;
 634 }
 635
 636 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
 637 {
 638         return dib3000mb_fe_init(fe, 0);
 639 }
 640
 641 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
 642 {
 643         return dib3000mb_set_frontend(fe, fep, 1);
 644 }
 645
 646 static void dib3000mb_release(struct dvb_frontend* fe)
 647 {
 648         struct dib3000_state *state = fe->demodulator_priv;
 649         kfree(state);
 650 }
 651
 652 /* pid filter and transfer stuff */
 653 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
 654 {
 655         struct dib3000_state *state = fe->demodulator_priv;
 656         pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
 657         wr(index+DIB3000MB_REG_FIRST_PID,pid);
 658         return 0;
 659 }
 660
 661 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
 662 {
 663         struct dib3000_state *state = fe->demodulator_priv;
 664
 665         deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
 666         if (onoff) {
 667                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
 668         } else {
 669                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
 670         }
 671         return 0;
 672 }
 673
 674 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
 675 {
 676         struct dib3000_state *state = fe->demodulator_priv;
 677         deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
 678         wr(DIB3000MB_REG_PID_PARSE,onoff);
 679         return 0;
 680 }
 681
 682 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
 683 {
 684         struct dib3000_state *state = fe->demodulator_priv;
 685         if (onoff) {
 686                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
 687         } else {
 688                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
 689         }
 690         return 0;
 691 }
 692
 693 static struct dvb_frontend_ops dib3000mb_ops;
 694
 695 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
 696                                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
 697 {
 698         struct dib3000_state* state = NULL;
 699
 700         /* allocate memory for the internal state */
 701         state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
 702         if (state == NULL)
 703                 goto error;
 704
 705         /* setup the state */
 706         state->i2c = i2c;
 707         memcpy(&state->config,config,sizeof(struct dib3000_config));
 708
 709         /* check for the correct demod */
 710         if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
 711                 goto error;
 712
 713         if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
 714                 goto error;
 715
 716         /* create dvb_frontend */
 717         memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
 718         state->frontend.demodulator_priv = state;
 719
 720         /* set the xfer operations */
 721         xfer_ops->pid_parse = dib3000mb_pid_parse;
 722         xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
 723         xfer_ops->pid_ctrl = dib3000mb_pid_control;
 724         xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
 725
 726         return &state->frontend;
 727
 728 error:
 729         kfree(state);
 730         return NULL;
 731 }
 732
 733 static struct dvb_frontend_ops dib3000mb_ops = {
 734
 735         .info = {
 736                 .name                   = "DiBcom 3000M-B DVB-T",
 737                 .type                   = FE_OFDM,
 738                 .frequency_min          = 44250000,
 739                 .frequency_max          = 867250000,
 740                 .frequency_stepsize     = 62500,
 741                 .caps = FE_CAN_INVERSION_AUTO |
 742                                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 743                                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 744                                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 745                                 FE_CAN_TRANSMISSION_MODE_AUTO |
 746                                 FE_CAN_GUARD_INTERVAL_AUTO |
 747                                 FE_CAN_RECOVER |
 748                                 FE_CAN_HIERARCHY_AUTO,
 749         },
 750
 751         .release = dib3000mb_release,
 752
 753         .init = dib3000mb_fe_init_nonmobile,
 754         .sleep = dib3000mb_sleep,
 755
 756         .set_frontend = dib3000mb_set_frontend_and_tuner,
 757         .get_frontend = dib3000mb_get_frontend,
 758         .get_tune_settings = dib3000mb_fe_get_tune_settings,
 759
 760         .read_status = dib3000mb_read_status,
 761         .read_ber = dib3000mb_read_ber,
 762         .read_signal_strength = dib3000mb_read_signal_strength,
 763         .read_snr = dib3000mb_read_snr,
 764         .read_ucblocks = dib3000mb_read_unc_blocks,
 765 };
 766
 767 MODULE_AUTHOR(DRIVER_AUTHOR);
 768 MODULE_DESCRIPTION(DRIVER_DESC);
 769 MODULE_LICENSE("GPL");
 770
 771 EXPORT_SYMBOL(dib3000mb_attach);