1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 #include <linux/bitops.h>
9 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/irqchip.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/syscore_ops.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #define IRQS_PER_BANK 32
23 struct stm32_exti_bank {
35 struct stm32_desc_irq {
40 struct stm32_exti_drv_data {
41 const struct stm32_exti_bank **exti_banks;
42 const struct stm32_desc_irq *desc_irqs;
47 struct stm32_exti_chip_data {
48 struct stm32_exti_host_data *host_data;
49 const struct stm32_exti_bank *reg_bank;
50 struct raw_spinlock rlock;
57 struct stm32_exti_host_data {
59 struct stm32_exti_chip_data *chips_data;
60 const struct stm32_exti_drv_data *drv_data;
63 static struct stm32_exti_host_data *stm32_host_data;
65 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
72 .fpr_ofst = UNDEF_REG,
75 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
79 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
80 .exti_banks = stm32f4xx_exti_banks,
81 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
84 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
91 .fpr_ofst = UNDEF_REG,
94 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
101 .fpr_ofst = UNDEF_REG,
104 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
111 .fpr_ofst = UNDEF_REG,
114 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
120 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
121 .exti_banks = stm32h7xx_exti_banks,
122 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
125 static const struct stm32_exti_bank stm32mp1_exti_b1 = {
135 static const struct stm32_exti_bank stm32mp1_exti_b2 = {
145 static const struct stm32_exti_bank stm32mp1_exti_b3 = {
155 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
161 static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
162 { .exti = 1, .irq_parent = 7 },
163 { .exti = 2, .irq_parent = 8 },
164 { .exti = 3, .irq_parent = 9 },
165 { .exti = 4, .irq_parent = 10 },
166 { .exti = 5, .irq_parent = 23 },
167 { .exti = 6, .irq_parent = 64 },
168 { .exti = 7, .irq_parent = 65 },
169 { .exti = 8, .irq_parent = 66 },
170 { .exti = 9, .irq_parent = 67 },
171 { .exti = 10, .irq_parent = 40 },
172 { .exti = 11, .irq_parent = 42 },
173 { .exti = 12, .irq_parent = 76 },
174 { .exti = 13, .irq_parent = 77 },
175 { .exti = 14, .irq_parent = 121 },
176 { .exti = 15, .irq_parent = 127 },
177 { .exti = 16, .irq_parent = 1 },
178 { .exti = 65, .irq_parent = 144 },
179 { .exti = 68, .irq_parent = 143 },
180 { .exti = 73, .irq_parent = 129 },
183 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
184 .exti_banks = stm32mp1_exti_banks,
185 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
186 .desc_irqs = stm32mp1_desc_irq,
187 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
190 static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
191 irq_hw_number_t hwirq)
193 const struct stm32_desc_irq *desc_irq;
196 if (!drv_data->desc_irqs)
199 for (i = 0; i < drv_data->irq_nr; i++) {
200 desc_irq = &drv_data->desc_irqs[i];
201 if (desc_irq->exti == hwirq)
202 return desc_irq->irq_parent;
208 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
210 struct stm32_exti_chip_data *chip_data = gc->private;
211 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
212 unsigned long pending;
214 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
215 if (stm32_bank->fpr_ofst != UNDEF_REG)
216 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
221 static void stm32_irq_handler(struct irq_desc *desc)
223 struct irq_domain *domain = irq_desc_get_handler_data(desc);
224 struct irq_chip *chip = irq_desc_get_chip(desc);
225 unsigned int virq, nbanks = domain->gc->num_chips;
226 struct irq_chip_generic *gc;
227 unsigned long pending;
228 int n, i, irq_base = 0;
230 chained_irq_enter(chip, desc);
232 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
233 gc = irq_get_domain_generic_chip(domain, irq_base);
235 while ((pending = stm32_exti_pending(gc))) {
236 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
237 virq = irq_find_mapping(domain, irq_base + n);
238 generic_handle_irq(virq);
243 chained_irq_exit(chip, desc);
246 static int stm32_exti_set_type(struct irq_data *d,
247 unsigned int type, u32 *rtsr, u32 *ftsr)
249 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
252 case IRQ_TYPE_EDGE_RISING:
256 case IRQ_TYPE_EDGE_FALLING:
260 case IRQ_TYPE_EDGE_BOTH:
271 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
273 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
274 struct stm32_exti_chip_data *chip_data = gc->private;
275 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
281 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
282 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
284 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
290 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
291 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
298 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
301 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
302 void __iomem *base = chip_data->host_data->base;
304 /* save rtsr, ftsr registers */
305 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
306 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
308 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
311 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
314 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
315 void __iomem *base = chip_data->host_data->base;
317 /* restore rtsr, ftsr, registers */
318 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
319 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
321 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
324 static void stm32_irq_suspend(struct irq_chip_generic *gc)
326 struct stm32_exti_chip_data *chip_data = gc->private;
329 stm32_chip_suspend(chip_data, gc->wake_active);
333 static void stm32_irq_resume(struct irq_chip_generic *gc)
335 struct stm32_exti_chip_data *chip_data = gc->private;
338 stm32_chip_resume(chip_data, gc->mask_cache);
342 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
343 unsigned int nr_irqs, void *data)
345 struct irq_fwspec *fwspec = data;
346 irq_hw_number_t hwirq;
348 hwirq = fwspec->param[0];
350 irq_map_generic_chip(d, virq, hwirq);
355 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
356 unsigned int nr_irqs)
358 struct irq_data *data = irq_domain_get_irq_data(d, virq);
360 irq_domain_reset_irq_data(data);
363 static const struct irq_domain_ops irq_exti_domain_ops = {
364 .map = irq_map_generic_chip,
365 .alloc = stm32_exti_alloc,
366 .free = stm32_exti_free,
369 static void stm32_irq_ack(struct irq_data *d)
371 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
372 struct stm32_exti_chip_data *chip_data = gc->private;
373 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
377 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
378 if (stm32_bank->fpr_ofst != UNDEF_REG)
379 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
384 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
386 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
387 void __iomem *base = chip_data->host_data->base;
390 val = readl_relaxed(base + reg);
391 val |= BIT(d->hwirq % IRQS_PER_BANK);
392 writel_relaxed(val, base + reg);
397 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
399 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
400 void __iomem *base = chip_data->host_data->base;
403 val = readl_relaxed(base + reg);
404 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
405 writel_relaxed(val, base + reg);
410 static void stm32_exti_h_eoi(struct irq_data *d)
412 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
413 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
415 raw_spin_lock(&chip_data->rlock);
417 stm32_exti_set_bit(d, stm32_bank->rpr_ofst);
418 if (stm32_bank->fpr_ofst != UNDEF_REG)
419 stm32_exti_set_bit(d, stm32_bank->fpr_ofst);
421 raw_spin_unlock(&chip_data->rlock);
423 if (d->parent_data->chip)
424 irq_chip_eoi_parent(d);
427 static void stm32_exti_h_mask(struct irq_data *d)
429 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
430 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
432 raw_spin_lock(&chip_data->rlock);
433 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
434 raw_spin_unlock(&chip_data->rlock);
436 if (d->parent_data->chip)
437 irq_chip_mask_parent(d);
440 static void stm32_exti_h_unmask(struct irq_data *d)
442 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
443 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
445 raw_spin_lock(&chip_data->rlock);
446 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
447 raw_spin_unlock(&chip_data->rlock);
449 if (d->parent_data->chip)
450 irq_chip_unmask_parent(d);
453 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
455 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
456 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
457 void __iomem *base = chip_data->host_data->base;
461 raw_spin_lock(&chip_data->rlock);
462 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
463 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
465 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
467 raw_spin_unlock(&chip_data->rlock);
471 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
472 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
473 raw_spin_unlock(&chip_data->rlock);
478 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
480 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
481 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
483 raw_spin_lock(&chip_data->rlock);
486 chip_data->wake_active |= mask;
488 chip_data->wake_active &= ~mask;
490 raw_spin_unlock(&chip_data->rlock);
495 static int stm32_exti_h_set_affinity(struct irq_data *d,
496 const struct cpumask *dest, bool force)
498 if (d->parent_data->chip)
499 return irq_chip_set_affinity_parent(d, dest, force);
505 static int stm32_exti_h_suspend(void)
507 struct stm32_exti_chip_data *chip_data;
510 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
511 chip_data = &stm32_host_data->chips_data[i];
512 raw_spin_lock(&chip_data->rlock);
513 stm32_chip_suspend(chip_data, chip_data->wake_active);
514 raw_spin_unlock(&chip_data->rlock);
520 static void stm32_exti_h_resume(void)
522 struct stm32_exti_chip_data *chip_data;
525 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
526 chip_data = &stm32_host_data->chips_data[i];
527 raw_spin_lock(&chip_data->rlock);
528 stm32_chip_resume(chip_data, chip_data->mask_cache);
529 raw_spin_unlock(&chip_data->rlock);
533 static struct syscore_ops stm32_exti_h_syscore_ops = {
534 .suspend = stm32_exti_h_suspend,
535 .resume = stm32_exti_h_resume,
538 static void stm32_exti_h_syscore_init(void)
540 register_syscore_ops(&stm32_exti_h_syscore_ops);
543 static inline void stm32_exti_h_syscore_init(void) {}
546 static struct irq_chip stm32_exti_h_chip = {
547 .name = "stm32-exti-h",
548 .irq_eoi = stm32_exti_h_eoi,
549 .irq_mask = stm32_exti_h_mask,
550 .irq_unmask = stm32_exti_h_unmask,
551 .irq_retrigger = irq_chip_retrigger_hierarchy,
552 .irq_set_type = stm32_exti_h_set_type,
553 .irq_set_wake = stm32_exti_h_set_wake,
554 .flags = IRQCHIP_MASK_ON_SUSPEND,
555 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
558 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
560 unsigned int nr_irqs, void *data)
562 struct stm32_exti_host_data *host_data = dm->host_data;
563 struct stm32_exti_chip_data *chip_data;
564 struct irq_fwspec *fwspec = data;
565 struct irq_fwspec p_fwspec;
566 irq_hw_number_t hwirq;
569 hwirq = fwspec->param[0];
570 bank = hwirq / IRQS_PER_BANK;
571 chip_data = &host_data->chips_data[bank];
573 irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
574 &stm32_exti_h_chip, chip_data);
576 p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
578 p_fwspec.fwnode = dm->parent->fwnode;
579 p_fwspec.param_count = 3;
580 p_fwspec.param[0] = GIC_SPI;
581 p_fwspec.param[1] = p_irq;
582 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
584 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
591 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
592 struct device_node *node)
594 struct stm32_exti_host_data *host_data;
596 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
600 host_data->drv_data = dd;
601 host_data->chips_data = kcalloc(dd->bank_nr,
602 sizeof(struct stm32_exti_chip_data),
604 if (!host_data->chips_data)
607 host_data->base = of_iomap(node, 0);
608 if (!host_data->base) {
609 pr_err("%pOF: Unable to map registers\n", node);
613 stm32_host_data = host_data;
619 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
621 struct device_node *node)
623 const struct stm32_exti_bank *stm32_bank;
624 struct stm32_exti_chip_data *chip_data;
625 void __iomem *base = h_data->base;
628 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
629 chip_data = &h_data->chips_data[bank_idx];
630 chip_data->host_data = h_data;
631 chip_data->reg_bank = stm32_bank;
633 raw_spin_lock_init(&chip_data->rlock);
635 /* Determine number of irqs supported */
636 writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
637 irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
640 * This IP has no reset, so after hot reboot we should
641 * clear registers to avoid residue
643 writel_relaxed(0, base + stm32_bank->imr_ofst);
644 writel_relaxed(0, base + stm32_bank->emr_ofst);
645 writel_relaxed(0, base + stm32_bank->rtsr_ofst);
646 writel_relaxed(0, base + stm32_bank->ftsr_ofst);
647 writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
648 if (stm32_bank->fpr_ofst != UNDEF_REG)
649 writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
651 pr_info("%s: bank%d, External IRQs available:%#x\n",
652 node->full_name, bank_idx, irqs_mask);
657 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
658 struct device_node *node)
660 struct stm32_exti_host_data *host_data;
661 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
663 struct irq_chip_generic *gc;
664 struct irq_domain *domain;
666 host_data = stm32_exti_host_init(drv_data, node);
672 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
673 &irq_exti_domain_ops, NULL);
675 pr_err("%s: Could not register interrupt domain.\n",
681 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
682 handle_edge_irq, clr, 0, 0);
684 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
686 goto out_free_domain;
689 for (i = 0; i < drv_data->bank_nr; i++) {
690 const struct stm32_exti_bank *stm32_bank;
691 struct stm32_exti_chip_data *chip_data;
693 stm32_bank = drv_data->exti_banks[i];
694 chip_data = stm32_exti_chip_init(host_data, i, node);
696 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
698 gc->reg_base = host_data->base;
699 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
700 gc->chip_types->chip.irq_ack = stm32_irq_ack;
701 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
702 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
703 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
704 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
705 gc->suspend = stm32_irq_suspend;
706 gc->resume = stm32_irq_resume;
707 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
709 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
710 gc->private = (void *)chip_data;
713 nr_irqs = of_irq_count(node);
714 for (i = 0; i < nr_irqs; i++) {
715 unsigned int irq = irq_of_parse_and_map(node, i);
717 irq_set_handler_data(irq, domain);
718 irq_set_chained_handler(irq, stm32_irq_handler);
724 irq_domain_remove(domain);
726 iounmap(host_data->base);
728 kfree(host_data->chips_data);
733 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
734 .alloc = stm32_exti_h_domain_alloc,
735 .free = irq_domain_free_irqs_common,
739 __init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data,
740 struct device_node *node,
741 struct device_node *parent)
743 struct irq_domain *parent_domain, *domain;
744 struct stm32_exti_host_data *host_data;
747 parent_domain = irq_find_host(parent);
748 if (!parent_domain) {
749 pr_err("interrupt-parent not found\n");
753 host_data = stm32_exti_host_init(drv_data, node);
759 for (i = 0; i < drv_data->bank_nr; i++)
760 stm32_exti_chip_init(host_data, i, node);
762 domain = irq_domain_add_hierarchy(parent_domain, 0,
763 drv_data->bank_nr * IRQS_PER_BANK,
764 node, &stm32_exti_h_domain_ops,
768 pr_err("%s: Could not register exti domain.\n", node->name);
773 stm32_exti_h_syscore_init();
778 iounmap(host_data->base);
780 kfree(host_data->chips_data);
785 static int __init stm32f4_exti_of_init(struct device_node *np,
786 struct device_node *parent)
788 return stm32_exti_init(&stm32f4xx_drv_data, np);
791 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
793 static int __init stm32h7_exti_of_init(struct device_node *np,
794 struct device_node *parent)
796 return stm32_exti_init(&stm32h7xx_drv_data, np);
799 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
801 static int __init stm32mp1_exti_of_init(struct device_node *np,
802 struct device_node *parent)
804 return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent);
807 IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init);