drivers/interconnect/qcom/x1e80100.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2023, Linaro Limited
   5  *
   6  */
   7
   8 #include <linux/device.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/interconnect-provider.h>
  11 #include <linux/module.h>
  12 #include <linux/of_platform.h>
  13 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
  14
  15 #include "bcm-voter.h"
  16 #include "icc-common.h"
  17 #include "icc-rpmh.h"
  18 #include "x1e80100.h"
  19
  20 static struct qcom_icc_node qhm_qspi = {
  21         .name = "qhm_qspi",
  22         .id = X1E80100_MASTER_QSPI_0,
  23         .channels = 1,
  24         .buswidth = 4,
  25         .num_links = 1,
  26         .links = { X1E80100_SLAVE_A1NOC_SNOC },
  27 };
  28
  29 static struct qcom_icc_node qhm_qup1 = {
  30         .name = "qhm_qup1",
  31         .id = X1E80100_MASTER_QUP_1,
  32         .channels = 1,
  33         .buswidth = 4,
  34         .num_links = 1,
  35         .links = { X1E80100_SLAVE_A1NOC_SNOC },
  36 };
  37
  38 static struct qcom_icc_node xm_sdc4 = {
  39         .name = "xm_sdc4",
  40         .id = X1E80100_MASTER_SDCC_4,
  41         .channels = 1,
  42         .buswidth = 8,
  43         .num_links = 1,
  44         .links = { X1E80100_SLAVE_A1NOC_SNOC },
  45 };
  46
  47 static struct qcom_icc_node xm_ufs_mem = {
  48         .name = "xm_ufs_mem",
  49         .id = X1E80100_MASTER_UFS_MEM,
  50         .channels = 1,
  51         .buswidth = 16,
  52         .num_links = 1,
  53         .links = { X1E80100_SLAVE_A1NOC_SNOC },
  54 };
  55
  56 static struct qcom_icc_node qhm_qup0 = {
  57         .name = "qhm_qup0",
  58         .id = X1E80100_MASTER_QUP_0,
  59         .channels = 1,
  60         .buswidth = 4,
  61         .num_links = 1,
  62         .links = { X1E80100_SLAVE_A2NOC_SNOC },
  63 };
  64
  65 static struct qcom_icc_node qhm_qup2 = {
  66         .name = "qhm_qup2",
  67         .id = X1E80100_MASTER_QUP_2,
  68         .channels = 1,
  69         .buswidth = 4,
  70         .num_links = 1,
  71         .links = { X1E80100_SLAVE_A2NOC_SNOC },
  72 };
  73
  74 static struct qcom_icc_node qxm_crypto = {
  75         .name = "qxm_crypto",
  76         .id = X1E80100_MASTER_CRYPTO,
  77         .channels = 1,
  78         .buswidth = 8,
  79         .num_links = 1,
  80         .links = { X1E80100_SLAVE_A2NOC_SNOC },
  81 };
  82
  83 static struct qcom_icc_node qxm_sp = {
  84         .name = "qxm_sp",
  85         .id = X1E80100_MASTER_SP,
  86         .channels = 1,
  87         .buswidth = 8,
  88         .num_links = 1,
  89         .links = { X1E80100_SLAVE_A2NOC_SNOC },
  90 };
  91
  92 static struct qcom_icc_node xm_qdss_etr_0 = {
  93         .name = "xm_qdss_etr_0",
  94         .id = X1E80100_MASTER_QDSS_ETR,
  95         .channels = 1,
  96         .buswidth = 8,
  97         .num_links = 1,
  98         .links = { X1E80100_SLAVE_A2NOC_SNOC },
  99 };
 100
 101 static struct qcom_icc_node xm_qdss_etr_1 = {
 102         .name = "xm_qdss_etr_1",
 103         .id = X1E80100_MASTER_QDSS_ETR_1,
 104         .channels = 1,
 105         .buswidth = 8,
 106         .num_links = 1,
 107         .links = { X1E80100_SLAVE_A2NOC_SNOC },
 108 };
 109
 110 static struct qcom_icc_node xm_sdc2 = {
 111         .name = "xm_sdc2",
 112         .id = X1E80100_MASTER_SDCC_2,
 113         .channels = 1,
 114         .buswidth = 8,
 115         .num_links = 1,
 116         .links = { X1E80100_SLAVE_A2NOC_SNOC },
 117 };
 118
 119 static struct qcom_icc_node ddr_perf_mode_master = {
 120         .name = "ddr_perf_mode_master",
 121         .id = X1E80100_MASTER_DDR_PERF_MODE,
 122         .channels = 1,
 123         .buswidth = 4,
 124         .num_links = 1,
 125         .links = { X1E80100_SLAVE_DDR_PERF_MODE },
 126 };
 127
 128 static struct qcom_icc_node qup0_core_master = {
 129         .name = "qup0_core_master",
 130         .id = X1E80100_MASTER_QUP_CORE_0,
 131         .channels = 1,
 132         .buswidth = 4,
 133         .num_links = 1,
 134         .links = { X1E80100_SLAVE_QUP_CORE_0 },
 135 };
 136
 137 static struct qcom_icc_node qup1_core_master = {
 138         .name = "qup1_core_master",
 139         .id = X1E80100_MASTER_QUP_CORE_1,
 140         .channels = 1,
 141         .buswidth = 4,
 142         .num_links = 1,
 143         .links = { X1E80100_SLAVE_QUP_CORE_1 },
 144 };
 145
 146 static struct qcom_icc_node qup2_core_master = {
 147         .name = "qup2_core_master",
 148         .id = X1E80100_MASTER_QUP_CORE_2,
 149         .channels = 1,
 150         .buswidth = 4,
 151         .num_links = 1,
 152         .links = { X1E80100_SLAVE_QUP_CORE_2 },
 153 };
 154
 155 static struct qcom_icc_node qsm_cfg = {
 156         .name = "qsm_cfg",
 157         .id = X1E80100_MASTER_CNOC_CFG,
 158         .channels = 1,
 159         .buswidth = 4,
 160         .num_links = 47,
 161         .links = { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH,
 162                    X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG,
 163                    X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL,
 164                    X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG,
 165                    X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG,
 166                    X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG,
 167                    X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG,
 168                    X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG,
 169                    X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG,
 170                    X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG,
 171                    X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG,
 172                    X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0,
 173                    X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1,
 174                    X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2,
 175                    X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG,
 176                    X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM,
 177                    X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2,
 178                    X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1,
 179                    X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP,
 180                    X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1,
 181                    X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG,
 182                    X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG,
 183                    X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM,
 184                    X1E80100_SLAVE_TCU },
 185 };
 186
 187 static struct qcom_icc_node qnm_gemnoc_cnoc = {
 188         .name = "qnm_gemnoc_cnoc",
 189         .id = X1E80100_MASTER_GEM_NOC_CNOC,
 190         .channels = 1,
 191         .buswidth = 16,
 192         .num_links = 6,
 193         .links = { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG,
 194                    X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG,
 195                    X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM },
 196 };
 197
 198 static struct qcom_icc_node qnm_gemnoc_pcie = {
 199         .name = "qnm_gemnoc_pcie",
 200         .id = X1E80100_MASTER_GEM_NOC_PCIE_SNOC,
 201         .channels = 1,
 202         .buswidth = 32,
 203         .num_links = 8,
 204         .links = { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1,
 205                    X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3,
 206                    X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5,
 207                    X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B },
 208 };
 209
 210 static struct qcom_icc_node alm_gpu_tcu = {
 211         .name = "alm_gpu_tcu",
 212         .id = X1E80100_MASTER_GPU_TCU,
 213         .channels = 1,
 214         .buswidth = 8,
 215         .num_links = 2,
 216         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
 217 };
 218
 219 static struct qcom_icc_node alm_pcie_tcu = {
 220         .name = "alm_pcie_tcu",
 221         .id = X1E80100_MASTER_PCIE_TCU,
 222         .channels = 1,
 223         .buswidth = 8,
 224         .num_links = 2,
 225         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
 226 };
 227
 228 static struct qcom_icc_node alm_sys_tcu = {
 229         .name = "alm_sys_tcu",
 230         .id = X1E80100_MASTER_SYS_TCU,
 231         .channels = 1,
 232         .buswidth = 8,
 233         .num_links = 2,
 234         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
 235 };
 236
 237 static struct qcom_icc_node chm_apps = {
 238         .name = "chm_apps",
 239         .id = X1E80100_MASTER_APPSS_PROC,
 240         .channels = 6,
 241         .buswidth = 32,
 242         .num_links = 3,
 243         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
 244                    X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
 245 };
 246
 247 static struct qcom_icc_node qnm_gpu = {
 248         .name = "qnm_gpu",
 249         .id = X1E80100_MASTER_GFX3D,
 250         .channels = 4,
 251         .buswidth = 32,
 252         .num_links = 2,
 253         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
 254 };
 255
 256 static struct qcom_icc_node qnm_lpass = {
 257         .name = "qnm_lpass",
 258         .id = X1E80100_MASTER_LPASS_GEM_NOC,
 259         .channels = 1,
 260         .buswidth = 16,
 261         .num_links = 3,
 262         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
 263                    X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
 264 };
 265
 266 static struct qcom_icc_node qnm_mnoc_hf = {
 267         .name = "qnm_mnoc_hf",
 268         .id = X1E80100_MASTER_MNOC_HF_MEM_NOC,
 269         .channels = 2,
 270         .buswidth = 32,
 271         .num_links = 2,
 272         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
 273 };
 274
 275 static struct qcom_icc_node qnm_mnoc_sf = {
 276         .name = "qnm_mnoc_sf",
 277         .id = X1E80100_MASTER_MNOC_SF_MEM_NOC,
 278         .channels = 2,
 279         .buswidth = 32,
 280         .num_links = 2,
 281         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
 282 };
 283
 284 static struct qcom_icc_node qnm_nsp_noc = {
 285         .name = "qnm_nsp_noc",
 286         .id = X1E80100_MASTER_COMPUTE_NOC,
 287         .channels = 2,
 288         .buswidth = 32,
 289         .num_links = 3,
 290         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
 291                    X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
 292 };
 293
 294 static struct qcom_icc_node qnm_pcie = {
 295         .name = "qnm_pcie",
 296         .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC,
 297         .channels = 1,
 298         .buswidth = 64,
 299         .num_links = 2,
 300         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },
 301 };
 302
 303 static struct qcom_icc_node qnm_snoc_sf = {
 304         .name = "qnm_snoc_sf",
 305         .id = X1E80100_MASTER_SNOC_SF_MEM_NOC,
 306         .channels = 1,
 307         .buswidth = 64,
 308         .num_links = 3,
 309         .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,
 310                    X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },
 311 };
 312
 313 static struct qcom_icc_node xm_gic = {
 314         .name = "xm_gic",
 315         .id = X1E80100_MASTER_GIC2,
 316         .channels = 1,
 317         .buswidth = 8,
 318         .num_links = 1,
 319         .links = { X1E80100_SLAVE_LLCC },
 320 };
 321
 322 static struct qcom_icc_node qnm_lpiaon_noc = {
 323         .name = "qnm_lpiaon_noc",
 324         .id = X1E80100_MASTER_LPIAON_NOC,
 325         .channels = 1,
 326         .buswidth = 16,
 327         .num_links = 1,
 328         .links = { X1E80100_SLAVE_LPASS_GEM_NOC },
 329 };
 330
 331 static struct qcom_icc_node qnm_lpass_lpinoc = {
 332         .name = "qnm_lpass_lpinoc",
 333         .id = X1E80100_MASTER_LPASS_LPINOC,
 334         .channels = 1,
 335         .buswidth = 16,
 336         .num_links = 1,
 337         .links = { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
 338 };
 339
 340 static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
 341         .name = "qxm_lpinoc_dsp_axim",
 342         .id = X1E80100_MASTER_LPASS_PROC,
 343         .channels = 1,
 344         .buswidth = 16,
 345         .num_links = 1,
 346         .links = { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC },
 347 };
 348
 349 static struct qcom_icc_node llcc_mc = {
 350         .name = "llcc_mc",
 351         .id = X1E80100_MASTER_LLCC,
 352         .channels = 8,
 353         .buswidth = 4,
 354         .num_links = 1,
 355         .links = { X1E80100_SLAVE_EBI1 },
 356 };
 357
 358 static struct qcom_icc_node qnm_av1_enc = {
 359         .name = "qnm_av1_enc",
 360         .id = X1E80100_MASTER_AV1_ENC,
 361         .channels = 1,
 362         .buswidth = 32,
 363         .num_links = 1,
 364         .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
 365 };
 366
 367 static struct qcom_icc_node qnm_camnoc_hf = {
 368         .name = "qnm_camnoc_hf",
 369         .id = X1E80100_MASTER_CAMNOC_HF,
 370         .channels = 2,
 371         .buswidth = 32,
 372         .num_links = 1,
 373         .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC },
 374 };
 375
 376 static struct qcom_icc_node qnm_camnoc_icp = {
 377         .name = "qnm_camnoc_icp",
 378         .id = X1E80100_MASTER_CAMNOC_ICP,
 379         .channels = 1,
 380         .buswidth = 8,
 381         .num_links = 1,
 382         .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
 383 };
 384
 385 static struct qcom_icc_node qnm_camnoc_sf = {
 386         .name = "qnm_camnoc_sf",
 387         .id = X1E80100_MASTER_CAMNOC_SF,
 388         .channels = 2,
 389         .buswidth = 32,
 390         .num_links = 1,
 391         .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
 392 };
 393
 394 static struct qcom_icc_node qnm_eva = {
 395         .name = "qnm_eva",
 396         .id = X1E80100_MASTER_EVA,
 397         .channels = 1,
 398         .buswidth = 32,
 399         .num_links = 1,
 400         .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
 401 };
 402
 403 static struct qcom_icc_node qnm_mdp = {
 404         .name = "qnm_mdp",
 405         .id = X1E80100_MASTER_MDP,
 406         .channels = 2,
 407         .buswidth = 32,
 408         .num_links = 1,
 409         .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC },
 410 };
 411
 412 static struct qcom_icc_node qnm_video = {
 413         .name = "qnm_video",
 414         .id = X1E80100_MASTER_VIDEO,
 415         .channels = 2,
 416         .buswidth = 32,
 417         .num_links = 1,
 418         .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
 419 };
 420
 421 static struct qcom_icc_node qnm_video_cv_cpu = {
 422         .name = "qnm_video_cv_cpu",
 423         .id = X1E80100_MASTER_VIDEO_CV_PROC,
 424         .channels = 1,
 425         .buswidth = 8,
 426         .num_links = 1,
 427         .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
 428 };
 429
 430 static struct qcom_icc_node qnm_video_v_cpu = {
 431         .name = "qnm_video_v_cpu",
 432         .id = X1E80100_MASTER_VIDEO_V_PROC,
 433         .channels = 1,
 434         .buswidth = 8,
 435         .num_links = 1,
 436         .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },
 437 };
 438
 439 static struct qcom_icc_node qsm_mnoc_cfg = {
 440         .name = "qsm_mnoc_cfg",
 441         .id = X1E80100_MASTER_CNOC_MNOC_CFG,
 442         .channels = 1,
 443         .buswidth = 4,
 444         .num_links = 1,
 445         .links = { X1E80100_SLAVE_SERVICE_MNOC },
 446 };
 447
 448 static struct qcom_icc_node qxm_nsp = {
 449         .name = "qxm_nsp",
 450         .id = X1E80100_MASTER_CDSP_PROC,
 451         .channels = 2,
 452         .buswidth = 32,
 453         .num_links = 1,
 454         .links = { X1E80100_SLAVE_CDSP_MEM_NOC },
 455 };
 456
 457 static struct qcom_icc_node qnm_pcie_north_gem_noc = {
 458         .name = "qnm_pcie_north_gem_noc",
 459         .id = X1E80100_MASTER_PCIE_NORTH,
 460         .channels = 1,
 461         .buswidth = 64,
 462         .num_links = 1,
 463         .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC },
 464 };
 465
 466 static struct qcom_icc_node qnm_pcie_south_gem_noc = {
 467         .name = "qnm_pcie_south_gem_noc",
 468         .id = X1E80100_MASTER_PCIE_SOUTH,
 469         .channels = 1,
 470         .buswidth = 64,
 471         .num_links = 1,
 472         .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC },
 473 };
 474
 475 static struct qcom_icc_node xm_pcie_3 = {
 476         .name = "xm_pcie_3",
 477         .id = X1E80100_MASTER_PCIE_3,
 478         .channels = 1,
 479         .buswidth = 64,
 480         .num_links = 1,
 481         .links = { X1E80100_SLAVE_PCIE_NORTH },
 482 };
 483
 484 static struct qcom_icc_node xm_pcie_4 = {
 485         .name = "xm_pcie_4",
 486         .id = X1E80100_MASTER_PCIE_4,
 487         .channels = 1,
 488         .buswidth = 8,
 489         .num_links = 1,
 490         .links = { X1E80100_SLAVE_PCIE_NORTH },
 491 };
 492
 493 static struct qcom_icc_node xm_pcie_5 = {
 494         .name = "xm_pcie_5",
 495         .id = X1E80100_MASTER_PCIE_5,
 496         .channels = 1,
 497         .buswidth = 8,
 498         .num_links = 1,
 499         .links = { X1E80100_SLAVE_PCIE_NORTH },
 500 };
 501
 502 static struct qcom_icc_node xm_pcie_0 = {
 503         .name = "xm_pcie_0",
 504         .id = X1E80100_MASTER_PCIE_0,
 505         .channels = 1,
 506         .buswidth = 16,
 507         .num_links = 1,
 508         .links = { X1E80100_SLAVE_PCIE_SOUTH },
 509 };
 510
 511 static struct qcom_icc_node xm_pcie_1 = {
 512         .name = "xm_pcie_1",
 513         .id = X1E80100_MASTER_PCIE_1,
 514         .channels = 1,
 515         .buswidth = 16,
 516         .num_links = 1,
 517         .links = { X1E80100_SLAVE_PCIE_SOUTH },
 518 };
 519
 520 static struct qcom_icc_node xm_pcie_2 = {
 521         .name = "xm_pcie_2",
 522         .id = X1E80100_MASTER_PCIE_2,
 523         .channels = 1,
 524         .buswidth = 16,
 525         .num_links = 1,
 526         .links = { X1E80100_SLAVE_PCIE_SOUTH },
 527 };
 528
 529 static struct qcom_icc_node xm_pcie_6a = {
 530         .name = "xm_pcie_6a",
 531         .id = X1E80100_MASTER_PCIE_6A,
 532         .channels = 1,
 533         .buswidth = 32,
 534         .num_links = 1,
 535         .links = { X1E80100_SLAVE_PCIE_SOUTH },
 536 };
 537
 538 static struct qcom_icc_node xm_pcie_6b = {
 539         .name = "xm_pcie_6b",
 540         .id = X1E80100_MASTER_PCIE_6B,
 541         .channels = 1,
 542         .buswidth = 16,
 543         .num_links = 1,
 544         .links = { X1E80100_SLAVE_PCIE_SOUTH },
 545 };
 546
 547 static struct qcom_icc_node qnm_aggre1_noc = {
 548         .name = "qnm_aggre1_noc",
 549         .id = X1E80100_MASTER_A1NOC_SNOC,
 550         .channels = 1,
 551         .buswidth = 16,
 552         .num_links = 1,
 553         .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
 554 };
 555
 556 static struct qcom_icc_node qnm_aggre2_noc = {
 557         .name = "qnm_aggre2_noc",
 558         .id = X1E80100_MASTER_A2NOC_SNOC,
 559         .channels = 1,
 560         .buswidth = 16,
 561         .num_links = 1,
 562         .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
 563 };
 564
 565 static struct qcom_icc_node qnm_gic = {
 566         .name = "qnm_gic",
 567         .id = X1E80100_MASTER_GIC1,
 568         .channels = 1,
 569         .buswidth = 8,
 570         .num_links = 1,
 571         .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
 572 };
 573
 574 static struct qcom_icc_node qnm_usb_anoc = {
 575         .name = "qnm_usb_anoc",
 576         .id = X1E80100_MASTER_USB_NOC_SNOC,
 577         .channels = 1,
 578         .buswidth = 64,
 579         .num_links = 1,
 580         .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },
 581 };
 582
 583 static struct qcom_icc_node qnm_aggre_usb_north_snoc = {
 584         .name = "qnm_aggre_usb_north_snoc",
 585         .id = X1E80100_MASTER_AGGRE_USB_NORTH,
 586         .channels = 1,
 587         .buswidth = 64,
 588         .num_links = 1,
 589         .links = { X1E80100_SLAVE_USB_NOC_SNOC },
 590 };
 591
 592 static struct qcom_icc_node qnm_aggre_usb_south_snoc = {
 593         .name = "qnm_aggre_usb_south_snoc",
 594         .id = X1E80100_MASTER_AGGRE_USB_SOUTH,
 595         .channels = 1,
 596         .buswidth = 64,
 597         .num_links = 1,
 598         .links = { X1E80100_SLAVE_USB_NOC_SNOC },
 599 };
 600
 601 static struct qcom_icc_node xm_usb2_0 = {
 602         .name = "xm_usb2_0",
 603         .id = X1E80100_MASTER_USB2,
 604         .channels = 1,
 605         .buswidth = 8,
 606         .num_links = 1,
 607         .links = { X1E80100_SLAVE_AGGRE_USB_NORTH },
 608 };
 609
 610 static struct qcom_icc_node xm_usb3_mp = {
 611         .name = "xm_usb3_mp",
 612         .id = X1E80100_MASTER_USB3_MP,
 613         .channels = 1,
 614         .buswidth = 16,
 615         .num_links = 1,
 616         .links = { X1E80100_SLAVE_AGGRE_USB_NORTH },
 617 };
 618
 619 static struct qcom_icc_node xm_usb3_0 = {
 620         .name = "xm_usb3_0",
 621         .id = X1E80100_MASTER_USB3_0,
 622         .channels = 1,
 623         .buswidth = 8,
 624         .num_links = 1,
 625         .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
 626 };
 627
 628 static struct qcom_icc_node xm_usb3_1 = {
 629         .name = "xm_usb3_1",
 630         .id = X1E80100_MASTER_USB3_1,
 631         .channels = 1,
 632         .buswidth = 8,
 633         .num_links = 1,
 634         .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
 635 };
 636
 637 static struct qcom_icc_node xm_usb3_2 = {
 638         .name = "xm_usb3_2",
 639         .id = X1E80100_MASTER_USB3_2,
 640         .channels = 1,
 641         .buswidth = 8,
 642         .num_links = 1,
 643         .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
 644 };
 645
 646 static struct qcom_icc_node xm_usb4_0 = {
 647         .name = "xm_usb4_0",
 648         .id = X1E80100_MASTER_USB4_0,
 649         .channels = 1,
 650         .buswidth = 16,
 651         .num_links = 1,
 652         .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
 653 };
 654
 655 static struct qcom_icc_node xm_usb4_1 = {
 656         .name = "xm_usb4_1",
 657         .id = X1E80100_MASTER_USB4_1,
 658         .channels = 1,
 659         .buswidth = 16,
 660         .num_links = 1,
 661         .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
 662 };
 663
 664 static struct qcom_icc_node xm_usb4_2 = {
 665         .name = "xm_usb4_2",
 666         .id = X1E80100_MASTER_USB4_2,
 667         .channels = 1,
 668         .buswidth = 16,
 669         .num_links = 1,
 670         .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
 671 };
 672
 673 static struct qcom_icc_node qns_a1noc_snoc = {
 674         .name = "qns_a1noc_snoc",
 675         .id = X1E80100_SLAVE_A1NOC_SNOC,
 676         .channels = 1,
 677         .buswidth = 16,
 678         .num_links = 1,
 679         .links = { X1E80100_MASTER_A1NOC_SNOC },
 680 };
 681
 682 static struct qcom_icc_node qns_a2noc_snoc = {
 683         .name = "qns_a2noc_snoc",
 684         .id = X1E80100_SLAVE_A2NOC_SNOC,
 685         .channels = 1,
 686         .buswidth = 16,
 687         .num_links = 1,
 688         .links = { X1E80100_MASTER_A2NOC_SNOC },
 689 };
 690
 691 static struct qcom_icc_node ddr_perf_mode_slave = {
 692         .name = "ddr_perf_mode_slave",
 693         .id = X1E80100_SLAVE_DDR_PERF_MODE,
 694         .channels = 1,
 695         .buswidth = 4,
 696         .num_links = 0,
 697 };
 698
 699 static struct qcom_icc_node qup0_core_slave = {
 700         .name = "qup0_core_slave",
 701         .id = X1E80100_SLAVE_QUP_CORE_0,
 702         .channels = 1,
 703         .buswidth = 4,
 704         .num_links = 0,
 705 };
 706
 707 static struct qcom_icc_node qup1_core_slave = {
 708         .name = "qup1_core_slave",
 709         .id = X1E80100_SLAVE_QUP_CORE_1,
 710         .channels = 1,
 711         .buswidth = 4,
 712         .num_links = 0,
 713 };
 714
 715 static struct qcom_icc_node qup2_core_slave = {
 716         .name = "qup2_core_slave",
 717         .id = X1E80100_SLAVE_QUP_CORE_2,
 718         .channels = 1,
 719         .buswidth = 4,
 720         .num_links = 0,
 721 };
 722
 723 static struct qcom_icc_node qhs_ahb2phy0 = {
 724         .name = "qhs_ahb2phy0",
 725         .id = X1E80100_SLAVE_AHB2PHY_SOUTH,
 726         .channels = 1,
 727         .buswidth = 4,
 728         .num_links = 0,
 729 };
 730
 731 static struct qcom_icc_node qhs_ahb2phy1 = {
 732         .name = "qhs_ahb2phy1",
 733         .id = X1E80100_SLAVE_AHB2PHY_NORTH,
 734         .channels = 1,
 735         .buswidth = 4,
 736         .num_links = 0,
 737 };
 738
 739 static struct qcom_icc_node qhs_ahb2phy2 = {
 740         .name = "qhs_ahb2phy2",
 741         .id = X1E80100_SLAVE_AHB2PHY_2,
 742         .channels = 1,
 743         .buswidth = 4,
 744         .num_links = 0,
 745 };
 746
 747 static struct qcom_icc_node qhs_av1_enc_cfg = {
 748         .name = "qhs_av1_enc_cfg",
 749         .id = X1E80100_SLAVE_AV1_ENC_CFG,
 750         .channels = 1,
 751         .buswidth = 4,
 752         .num_links = 0,
 753 };
 754
 755 static struct qcom_icc_node qhs_camera_cfg = {
 756         .name = "qhs_camera_cfg",
 757         .id = X1E80100_SLAVE_CAMERA_CFG,
 758         .channels = 1,
 759         .buswidth = 4,
 760         .num_links = 0,
 761 };
 762
 763 static struct qcom_icc_node qhs_clk_ctl = {
 764         .name = "qhs_clk_ctl",
 765         .id = X1E80100_SLAVE_CLK_CTL,
 766         .channels = 1,
 767         .buswidth = 4,
 768         .num_links = 0,
 769 };
 770
 771 static struct qcom_icc_node qhs_crypto0_cfg = {
 772         .name = "qhs_crypto0_cfg",
 773         .id = X1E80100_SLAVE_CRYPTO_0_CFG,
 774         .channels = 1,
 775         .buswidth = 4,
 776         .num_links = 0,
 777 };
 778
 779 static struct qcom_icc_node qhs_display_cfg = {
 780         .name = "qhs_display_cfg",
 781         .id = X1E80100_SLAVE_DISPLAY_CFG,
 782         .channels = 1,
 783         .buswidth = 4,
 784         .num_links = 0,
 785 };
 786
 787 static struct qcom_icc_node qhs_gpuss_cfg = {
 788         .name = "qhs_gpuss_cfg",
 789         .id = X1E80100_SLAVE_GFX3D_CFG,
 790         .channels = 1,
 791         .buswidth = 8,
 792         .num_links = 0,
 793 };
 794
 795 static struct qcom_icc_node qhs_imem_cfg = {
 796         .name = "qhs_imem_cfg",
 797         .id = X1E80100_SLAVE_IMEM_CFG,
 798         .channels = 1,
 799         .buswidth = 4,
 800         .num_links = 0,
 801 };
 802
 803 static struct qcom_icc_node qhs_ipc_router = {
 804         .name = "qhs_ipc_router",
 805         .id = X1E80100_SLAVE_IPC_ROUTER_CFG,
 806         .channels = 1,
 807         .buswidth = 4,
 808         .num_links = 0,
 809 };
 810
 811 static struct qcom_icc_node qhs_pcie0_cfg = {
 812         .name = "qhs_pcie0_cfg",
 813         .id = X1E80100_SLAVE_PCIE_0_CFG,
 814         .channels = 1,
 815         .buswidth = 4,
 816         .num_links = 0,
 817 };
 818
 819 static struct qcom_icc_node qhs_pcie1_cfg = {
 820         .name = "qhs_pcie1_cfg",
 821         .id = X1E80100_SLAVE_PCIE_1_CFG,
 822         .channels = 1,
 823         .buswidth = 4,
 824         .num_links = 0,
 825 };
 826
 827 static struct qcom_icc_node qhs_pcie2_cfg = {
 828         .name = "qhs_pcie2_cfg",
 829         .id = X1E80100_SLAVE_PCIE_2_CFG,
 830         .channels = 1,
 831         .buswidth = 4,
 832         .num_links = 0,
 833 };
 834
 835 static struct qcom_icc_node qhs_pcie3_cfg = {
 836         .name = "qhs_pcie3_cfg",
 837         .id = X1E80100_SLAVE_PCIE_3_CFG,
 838         .channels = 1,
 839         .buswidth = 4,
 840         .num_links = 0,
 841 };
 842
 843 static struct qcom_icc_node qhs_pcie4_cfg = {
 844         .name = "qhs_pcie4_cfg",
 845         .id = X1E80100_SLAVE_PCIE_4_CFG,
 846         .channels = 1,
 847         .buswidth = 4,
 848         .num_links = 0,
 849 };
 850
 851 static struct qcom_icc_node qhs_pcie5_cfg = {
 852         .name = "qhs_pcie5_cfg",
 853         .id = X1E80100_SLAVE_PCIE_5_CFG,
 854         .channels = 1,
 855         .buswidth = 4,
 856         .num_links = 0,
 857 };
 858
 859 static struct qcom_icc_node qhs_pcie6a_cfg = {
 860         .name = "qhs_pcie6a_cfg",
 861         .id = X1E80100_SLAVE_PCIE_6A_CFG,
 862         .channels = 1,
 863         .buswidth = 4,
 864         .num_links = 0,
 865 };
 866
 867 static struct qcom_icc_node qhs_pcie6b_cfg = {
 868         .name = "qhs_pcie6b_cfg",
 869         .id = X1E80100_SLAVE_PCIE_6B_CFG,
 870         .channels = 1,
 871         .buswidth = 4,
 872         .num_links = 0,
 873 };
 874
 875 static struct qcom_icc_node qhs_pcie_rsc_cfg = {
 876         .name = "qhs_pcie_rsc_cfg",
 877         .id = X1E80100_SLAVE_PCIE_RSC_CFG,
 878         .channels = 1,
 879         .buswidth = 4,
 880         .num_links = 0,
 881 };
 882
 883 static struct qcom_icc_node qhs_pdm = {
 884         .name = "qhs_pdm",
 885         .id = X1E80100_SLAVE_PDM,
 886         .channels = 1,
 887         .buswidth = 4,
 888         .num_links = 0,
 889 };
 890
 891 static struct qcom_icc_node qhs_prng = {
 892         .name = "qhs_prng",
 893         .id = X1E80100_SLAVE_PRNG,
 894         .channels = 1,
 895         .buswidth = 4,
 896         .num_links = 0,
 897 };
 898
 899 static struct qcom_icc_node qhs_qdss_cfg = {
 900         .name = "qhs_qdss_cfg",
 901         .id = X1E80100_SLAVE_QDSS_CFG,
 902         .channels = 1,
 903         .buswidth = 4,
 904         .num_links = 0,
 905 };
 906
 907 static struct qcom_icc_node qhs_qspi = {
 908         .name = "qhs_qspi",
 909         .id = X1E80100_SLAVE_QSPI_0,
 910         .channels = 1,
 911         .buswidth = 4,
 912         .num_links = 0,
 913 };
 914
 915 static struct qcom_icc_node qhs_qup0 = {
 916         .name = "qhs_qup0",
 917         .id = X1E80100_SLAVE_QUP_0,
 918         .channels = 1,
 919         .buswidth = 4,
 920         .num_links = 0,
 921 };
 922
 923 static struct qcom_icc_node qhs_qup1 = {
 924         .name = "qhs_qup1",
 925         .id = X1E80100_SLAVE_QUP_1,
 926         .channels = 1,
 927         .buswidth = 4,
 928         .num_links = 0,
 929 };
 930
 931 static struct qcom_icc_node qhs_qup2 = {
 932         .name = "qhs_qup2",
 933         .id = X1E80100_SLAVE_QUP_2,
 934         .channels = 1,
 935         .buswidth = 4,
 936         .num_links = 0,
 937 };
 938
 939 static struct qcom_icc_node qhs_sdc2 = {
 940         .name = "qhs_sdc2",
 941         .id = X1E80100_SLAVE_SDCC_2,
 942         .channels = 1,
 943         .buswidth = 4,
 944         .num_links = 0,
 945 };
 946
 947 static struct qcom_icc_node qhs_sdc4 = {
 948         .name = "qhs_sdc4",
 949         .id = X1E80100_SLAVE_SDCC_4,
 950         .channels = 1,
 951         .buswidth = 4,
 952         .num_links = 0,
 953 };
 954
 955 static struct qcom_icc_node qhs_smmuv3_cfg = {
 956         .name = "qhs_smmuv3_cfg",
 957         .id = X1E80100_SLAVE_SMMUV3_CFG,
 958         .channels = 1,
 959         .buswidth = 8,
 960         .num_links = 0,
 961 };
 962
 963 static struct qcom_icc_node qhs_tcsr = {
 964         .name = "qhs_tcsr",
 965         .id = X1E80100_SLAVE_TCSR,
 966         .channels = 1,
 967         .buswidth = 4,
 968         .num_links = 0,
 969 };
 970
 971 static struct qcom_icc_node qhs_tlmm = {
 972         .name = "qhs_tlmm",
 973         .id = X1E80100_SLAVE_TLMM,
 974         .channels = 1,
 975         .buswidth = 4,
 976         .num_links = 0,
 977 };
 978
 979 static struct qcom_icc_node qhs_ufs_mem_cfg = {
 980         .name = "qhs_ufs_mem_cfg",
 981         .id = X1E80100_SLAVE_UFS_MEM_CFG,
 982         .channels = 1,
 983         .buswidth = 4,
 984         .num_links = 0,
 985 };
 986
 987 static struct qcom_icc_node qhs_usb2_0_cfg = {
 988         .name = "qhs_usb2_0_cfg",
 989         .id = X1E80100_SLAVE_USB2,
 990         .channels = 1,
 991         .buswidth = 4,
 992         .num_links = 0,
 993 };
 994
 995 static struct qcom_icc_node qhs_usb3_0_cfg = {
 996         .name = "qhs_usb3_0_cfg",
 997         .id = X1E80100_SLAVE_USB3_0,
 998         .channels = 1,
 999         .buswidth = 4,
1000         .num_links = 0,
1001 };
1002
1003 static struct qcom_icc_node qhs_usb3_1_cfg = {
1004         .name = "qhs_usb3_1_cfg",
1005         .id = X1E80100_SLAVE_USB3_1,
1006         .channels = 1,
1007         .buswidth = 4,
1008         .num_links = 0,
1009 };
1010
1011 static struct qcom_icc_node qhs_usb3_2_cfg = {
1012         .name = "qhs_usb3_2_cfg",
1013         .id = X1E80100_SLAVE_USB3_2,
1014         .channels = 1,
1015         .buswidth = 4,
1016         .num_links = 0,
1017 };
1018
1019 static struct qcom_icc_node qhs_usb3_mp_cfg = {
1020         .name = "qhs_usb3_mp_cfg",
1021         .id = X1E80100_SLAVE_USB3_MP,
1022         .channels = 1,
1023         .buswidth = 4,
1024         .num_links = 0,
1025 };
1026
1027 static struct qcom_icc_node qhs_usb4_0_cfg = {
1028         .name = "qhs_usb4_0_cfg",
1029         .id = X1E80100_SLAVE_USB4_0,
1030         .channels = 1,
1031         .buswidth = 4,
1032         .num_links = 0,
1033 };
1034
1035 static struct qcom_icc_node qhs_usb4_1_cfg = {
1036         .name = "qhs_usb4_1_cfg",
1037         .id = X1E80100_SLAVE_USB4_1,
1038         .channels = 1,
1039         .buswidth = 4,
1040         .num_links = 0,
1041 };
1042
1043 static struct qcom_icc_node qhs_usb4_2_cfg = {
1044         .name = "qhs_usb4_2_cfg",
1045         .id = X1E80100_SLAVE_USB4_2,
1046         .channels = 1,
1047         .buswidth = 4,
1048         .num_links = 0,
1049 };
1050
1051 static struct qcom_icc_node qhs_venus_cfg = {
1052         .name = "qhs_venus_cfg",
1053         .id = X1E80100_SLAVE_VENUS_CFG,
1054         .channels = 1,
1055         .buswidth = 4,
1056         .num_links = 0,
1057 };
1058
1059 static struct qcom_icc_node qss_lpass_qtb_cfg = {
1060         .name = "qss_lpass_qtb_cfg",
1061         .id = X1E80100_SLAVE_LPASS_QTB_CFG,
1062         .channels = 1,
1063         .buswidth = 4,
1064         .num_links = 0,
1065 };
1066
1067 static struct qcom_icc_node qss_mnoc_cfg = {
1068         .name = "qss_mnoc_cfg",
1069         .id = X1E80100_SLAVE_CNOC_MNOC_CFG,
1070         .channels = 1,
1071         .buswidth = 4,
1072         .num_links = 1,
1073         .links = { X1E80100_MASTER_CNOC_MNOC_CFG },
1074 };
1075
1076 static struct qcom_icc_node qss_nsp_qtb_cfg = {
1077         .name = "qss_nsp_qtb_cfg",
1078         .id = X1E80100_SLAVE_NSP_QTB_CFG,
1079         .channels = 1,
1080         .buswidth = 4,
1081         .num_links = 0,
1082 };
1083
1084 static struct qcom_icc_node xs_qdss_stm = {
1085         .name = "xs_qdss_stm",
1086         .id = X1E80100_SLAVE_QDSS_STM,
1087         .channels = 1,
1088         .buswidth = 4,
1089         .num_links = 0,
1090 };
1091
1092 static struct qcom_icc_node xs_sys_tcu_cfg = {
1093         .name = "xs_sys_tcu_cfg",
1094         .id = X1E80100_SLAVE_TCU,
1095         .channels = 1,
1096         .buswidth = 8,
1097         .num_links = 0,
1098 };
1099
1100 static struct qcom_icc_node qhs_aoss = {
1101         .name = "qhs_aoss",
1102         .id = X1E80100_SLAVE_AOSS,
1103         .channels = 1,
1104         .buswidth = 4,
1105         .num_links = 0,
1106 };
1107
1108 static struct qcom_icc_node qhs_tme_cfg = {
1109         .name = "qhs_tme_cfg",
1110         .id = X1E80100_SLAVE_TME_CFG,
1111         .channels = 1,
1112         .buswidth = 4,
1113         .num_links = 0,
1114 };
1115
1116 static struct qcom_icc_node qns_apss = {
1117         .name = "qns_apss",
1118         .id = X1E80100_SLAVE_APPSS,
1119         .channels = 1,
1120         .buswidth = 8,
1121         .num_links = 0,
1122 };
1123
1124 static struct qcom_icc_node qss_cfg = {
1125         .name = "qss_cfg",
1126         .id = X1E80100_SLAVE_CNOC_CFG,
1127         .channels = 1,
1128         .buswidth = 4,
1129         .num_links = 1,
1130         .links = { X1E80100_MASTER_CNOC_CFG },
1131 };
1132
1133 static struct qcom_icc_node qxs_boot_imem = {
1134         .name = "qxs_boot_imem",
1135         .id = X1E80100_SLAVE_BOOT_IMEM,
1136         .channels = 1,
1137         .buswidth = 16,
1138         .num_links = 0,
1139 };
1140
1141 static struct qcom_icc_node qxs_imem = {
1142         .name = "qxs_imem",
1143         .id = X1E80100_SLAVE_IMEM,
1144         .channels = 1,
1145         .buswidth = 8,
1146         .num_links = 0,
1147 };
1148
1149 static struct qcom_icc_node xs_pcie_0 = {
1150         .name = "xs_pcie_0",
1151         .id = X1E80100_SLAVE_PCIE_0,
1152         .channels = 1,
1153         .buswidth = 16,
1154         .num_links = 0,
1155 };
1156
1157 static struct qcom_icc_node xs_pcie_1 = {
1158         .name = "xs_pcie_1",
1159         .id = X1E80100_SLAVE_PCIE_1,
1160         .channels = 1,
1161         .buswidth = 16,
1162         .num_links = 0,
1163 };
1164
1165 static struct qcom_icc_node xs_pcie_2 = {
1166         .name = "xs_pcie_2",
1167         .id = X1E80100_SLAVE_PCIE_2,
1168         .channels = 1,
1169         .buswidth = 16,
1170         .num_links = 0,
1171 };
1172
1173 static struct qcom_icc_node xs_pcie_3 = {
1174         .name = "xs_pcie_3",
1175         .id = X1E80100_SLAVE_PCIE_3,
1176         .channels = 1,
1177         .buswidth = 64,
1178         .num_links = 0,
1179 };
1180
1181 static struct qcom_icc_node xs_pcie_4 = {
1182         .name = "xs_pcie_4",
1183         .id = X1E80100_SLAVE_PCIE_4,
1184         .channels = 1,
1185         .buswidth = 8,
1186         .num_links = 0,
1187 };
1188
1189 static struct qcom_icc_node xs_pcie_5 = {
1190         .name = "xs_pcie_5",
1191         .id = X1E80100_SLAVE_PCIE_5,
1192         .channels = 1,
1193         .buswidth = 8,
1194         .num_links = 0,
1195 };
1196
1197 static struct qcom_icc_node xs_pcie_6a = {
1198         .name = "xs_pcie_6a",
1199         .id = X1E80100_SLAVE_PCIE_6A,
1200         .channels = 1,
1201         .buswidth = 32,
1202         .num_links = 0,
1203 };
1204
1205 static struct qcom_icc_node xs_pcie_6b = {
1206         .name = "xs_pcie_6b",
1207         .id = X1E80100_SLAVE_PCIE_6B,
1208         .channels = 1,
1209         .buswidth = 16,
1210         .num_links = 0,
1211 };
1212
1213 static struct qcom_icc_node qns_gem_noc_cnoc = {
1214         .name = "qns_gem_noc_cnoc",
1215         .id = X1E80100_SLAVE_GEM_NOC_CNOC,
1216         .channels = 1,
1217         .buswidth = 16,
1218         .num_links = 1,
1219         .links = { X1E80100_MASTER_GEM_NOC_CNOC },
1220 };
1221
1222 static struct qcom_icc_node qns_llcc = {
1223         .name = "qns_llcc",
1224         .id = X1E80100_SLAVE_LLCC,
1225         .channels = 8,
1226         .buswidth = 16,
1227         .num_links = 1,
1228         .links = { X1E80100_MASTER_LLCC },
1229 };
1230
1231 static struct qcom_icc_node qns_pcie = {
1232         .name = "qns_pcie",
1233         .id = X1E80100_SLAVE_MEM_NOC_PCIE_SNOC,
1234         .channels = 1,
1235         .buswidth = 32,
1236         .num_links = 1,
1237         .links = { X1E80100_MASTER_GEM_NOC_PCIE_SNOC },
1238 };
1239
1240 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
1241         .name = "qns_lpass_ag_noc_gemnoc",
1242         .id = X1E80100_SLAVE_LPASS_GEM_NOC,
1243         .channels = 1,
1244         .buswidth = 16,
1245         .num_links = 1,
1246         .links = { X1E80100_MASTER_LPASS_GEM_NOC },
1247 };
1248
1249 static struct qcom_icc_node qns_lpass_aggnoc = {
1250         .name = "qns_lpass_aggnoc",
1251         .id = X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
1252         .channels = 1,
1253         .buswidth = 16,
1254         .num_links = 1,
1255         .links = { X1E80100_MASTER_LPIAON_NOC },
1256 };
1257
1258 static struct qcom_icc_node qns_lpi_aon_noc = {
1259         .name = "qns_lpi_aon_noc",
1260         .id = X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC,
1261         .channels = 1,
1262         .buswidth = 16,
1263         .num_links = 1,
1264         .links = { X1E80100_MASTER_LPASS_LPINOC },
1265 };
1266
1267 static struct qcom_icc_node ebi = {
1268         .name = "ebi",
1269         .id = X1E80100_SLAVE_EBI1,
1270         .channels = 8,
1271         .buswidth = 4,
1272         .num_links = 0,
1273 };
1274
1275 static struct qcom_icc_node qns_mem_noc_hf = {
1276         .name = "qns_mem_noc_hf",
1277         .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC,
1278         .channels = 2,
1279         .buswidth = 32,
1280         .num_links = 1,
1281         .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC },
1282 };
1283
1284 static struct qcom_icc_node qns_mem_noc_sf = {
1285         .name = "qns_mem_noc_sf",
1286         .id = X1E80100_SLAVE_MNOC_SF_MEM_NOC,
1287         .channels = 2,
1288         .buswidth = 32,
1289         .num_links = 1,
1290         .links = { X1E80100_MASTER_MNOC_SF_MEM_NOC },
1291 };
1292
1293 static struct qcom_icc_node srvc_mnoc = {
1294         .name = "srvc_mnoc",
1295         .id = X1E80100_SLAVE_SERVICE_MNOC,
1296         .channels = 1,
1297         .buswidth = 4,
1298         .num_links = 0,
1299 };
1300
1301 static struct qcom_icc_node qns_nsp_gemnoc = {
1302         .name = "qns_nsp_gemnoc",
1303         .id = X1E80100_SLAVE_CDSP_MEM_NOC,
1304         .channels = 2,
1305         .buswidth = 32,
1306         .num_links = 1,
1307         .links = { X1E80100_MASTER_COMPUTE_NOC },
1308 };
1309
1310 static struct qcom_icc_node qns_pcie_mem_noc = {
1311         .name = "qns_pcie_mem_noc",
1312         .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC,
1313         .channels = 1,
1314         .buswidth = 64,
1315         .num_links = 1,
1316         .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC },
1317 };
1318
1319 static struct qcom_icc_node qns_pcie_north_gem_noc = {
1320         .name = "qns_pcie_north_gem_noc",
1321         .id = X1E80100_SLAVE_PCIE_NORTH,
1322         .channels = 1,
1323         .buswidth = 64,
1324         .num_links = 1,
1325         .links = { X1E80100_MASTER_PCIE_NORTH },
1326 };
1327
1328 static struct qcom_icc_node qns_pcie_south_gem_noc = {
1329         .name = "qns_pcie_south_gem_noc",
1330         .id = X1E80100_SLAVE_PCIE_SOUTH,
1331         .channels = 1,
1332         .buswidth = 64,
1333         .num_links = 1,
1334         .links = { X1E80100_MASTER_PCIE_SOUTH },
1335 };
1336
1337 static struct qcom_icc_node qns_gemnoc_sf = {
1338         .name = "qns_gemnoc_sf",
1339         .id = X1E80100_SLAVE_SNOC_GEM_NOC_SF,
1340         .channels = 1,
1341         .buswidth = 64,
1342         .num_links = 1,
1343         .links = { X1E80100_MASTER_SNOC_SF_MEM_NOC },
1344 };
1345
1346 static struct qcom_icc_node qns_aggre_usb_snoc = {
1347         .name = "qns_aggre_usb_snoc",
1348         .id = X1E80100_SLAVE_USB_NOC_SNOC,
1349         .channels = 1,
1350         .buswidth = 64,
1351         .num_links = 1,
1352         .links = { X1E80100_MASTER_USB_NOC_SNOC },
1353 };
1354
1355 static struct qcom_icc_node qns_aggre_usb_north_snoc = {
1356         .name = "qns_aggre_usb_north_snoc",
1357         .id = X1E80100_SLAVE_AGGRE_USB_NORTH,
1358         .channels = 1,
1359         .buswidth = 64,
1360         .num_links = 1,
1361         .links = { X1E80100_MASTER_AGGRE_USB_NORTH },
1362 };
1363
1364 static struct qcom_icc_node qns_aggre_usb_south_snoc = {
1365         .name = "qns_aggre_usb_south_snoc",
1366         .id = X1E80100_SLAVE_AGGRE_USB_SOUTH,
1367         .channels = 1,
1368         .buswidth = 64,
1369         .num_links = 1,
1370         .links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
1371 };
1372
1373 static struct qcom_icc_bcm bcm_acv = {
1374         .name = "ACV",
1375         .enable_mask = BIT(3),
1376         .num_nodes = 1,
1377         .nodes = { &ebi },
1378 };
1379
1380 static struct qcom_icc_bcm bcm_acv_perf = {
1381         .name = "ACV_PERF",
1382         .num_nodes = 1,
1383         .nodes = { &ddr_perf_mode_slave },
1384 };
1385
1386 static struct qcom_icc_bcm bcm_ce0 = {
1387         .name = "CE0",
1388         .num_nodes = 1,
1389         .nodes = { &qxm_crypto },
1390 };
1391
1392 static struct qcom_icc_bcm bcm_cn0 = {
1393         .name = "CN0",
1394         .keepalive = true,
1395         .num_nodes = 63,
1396         .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1397                    &qhs_ahb2phy1, &qhs_ahb2phy2,
1398                    &qhs_av1_enc_cfg, &qhs_camera_cfg,
1399                    &qhs_clk_ctl, &qhs_crypto0_cfg,
1400                    &qhs_gpuss_cfg, &qhs_imem_cfg,
1401                    &qhs_ipc_router, &qhs_pcie0_cfg,
1402                    &qhs_pcie1_cfg, &qhs_pcie2_cfg,
1403                    &qhs_pcie3_cfg, &qhs_pcie4_cfg,
1404                    &qhs_pcie5_cfg, &qhs_pcie6a_cfg,
1405                    &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg,
1406                    &qhs_pdm, &qhs_prng,
1407                    &qhs_qdss_cfg, &qhs_qspi,
1408                    &qhs_qup0, &qhs_qup1,
1409                    &qhs_qup2, &qhs_sdc2,
1410                    &qhs_sdc4, &qhs_smmuv3_cfg,
1411                    &qhs_tcsr, &qhs_tlmm,
1412                    &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg,
1413                    &qhs_usb3_0_cfg, &qhs_usb3_1_cfg,
1414                    &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg,
1415                    &qhs_usb4_0_cfg, &qhs_usb4_1_cfg,
1416                    &qhs_usb4_2_cfg, &qhs_venus_cfg,
1417                    &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1418                    &qss_nsp_qtb_cfg, &xs_qdss_stm,
1419                    &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc,
1420                    &qnm_gemnoc_pcie, &qhs_aoss,
1421                    &qhs_tme_cfg, &qns_apss,
1422                    &qss_cfg, &qxs_boot_imem,
1423                    &qxs_imem, &xs_pcie_0,
1424                    &xs_pcie_1, &xs_pcie_2,
1425                    &xs_pcie_3, &xs_pcie_4,
1426                    &xs_pcie_5, &xs_pcie_6a,
1427                    &xs_pcie_6b },
1428 };
1429
1430 static struct qcom_icc_bcm bcm_cn1 = {
1431         .name = "CN1",
1432         .num_nodes = 1,
1433         .nodes = { &qhs_display_cfg },
1434 };
1435
1436 static struct qcom_icc_bcm bcm_co0 = {
1437         .name = "CO0",
1438         .num_nodes = 2,
1439         .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1440 };
1441
1442 static struct qcom_icc_bcm bcm_lp0 = {
1443         .name = "LP0",
1444         .num_nodes = 2,
1445         .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1446 };
1447
1448 static struct qcom_icc_bcm bcm_mc0 = {
1449         .name = "MC0",
1450         .keepalive = true,
1451         .num_nodes = 1,
1452         .nodes = { &ebi },
1453 };
1454
1455 static struct qcom_icc_bcm bcm_mm0 = {
1456         .name = "MM0",
1457         .num_nodes = 1,
1458         .nodes = { &qns_mem_noc_hf },
1459 };
1460
1461 static struct qcom_icc_bcm bcm_mm1 = {
1462         .name = "MM1",
1463         .num_nodes = 10,
1464         .nodes = { &qnm_av1_enc, &qnm_camnoc_hf,
1465                    &qnm_camnoc_icp, &qnm_camnoc_sf,
1466                    &qnm_eva, &qnm_mdp,
1467                    &qnm_video, &qnm_video_cv_cpu,
1468                    &qnm_video_v_cpu, &qns_mem_noc_sf },
1469 };
1470
1471 static struct qcom_icc_bcm bcm_pc0 = {
1472         .name = "PC0",
1473         .num_nodes = 1,
1474         .nodes = { &qns_pcie_mem_noc },
1475 };
1476
1477 static struct qcom_icc_bcm bcm_qup0 = {
1478         .name = "QUP0",
1479         .keepalive = true,
1480         .vote_scale = 1,
1481         .num_nodes = 1,
1482         .nodes = { &qup0_core_slave },
1483 };
1484
1485 static struct qcom_icc_bcm bcm_qup1 = {
1486         .name = "QUP1",
1487         .keepalive = true,
1488         .vote_scale = 1,
1489         .num_nodes = 1,
1490         .nodes = { &qup1_core_slave },
1491 };
1492
1493 static struct qcom_icc_bcm bcm_qup2 = {
1494         .name = "QUP2",
1495         .keepalive = true,
1496         .vote_scale = 1,
1497         .num_nodes = 1,
1498         .nodes = { &qup2_core_slave },
1499 };
1500
1501 static struct qcom_icc_bcm bcm_sh0 = {
1502         .name = "SH0",
1503         .keepalive = true,
1504         .num_nodes = 1,
1505         .nodes = { &qns_llcc },
1506 };
1507
1508 static struct qcom_icc_bcm bcm_sh1 = {
1509         .name = "SH1",
1510         .num_nodes = 13,
1511         .nodes = { &alm_gpu_tcu, &alm_pcie_tcu,
1512                    &alm_sys_tcu, &chm_apps,
1513                    &qnm_gpu, &qnm_lpass,
1514                    &qnm_mnoc_hf, &qnm_mnoc_sf,
1515                    &qnm_nsp_noc, &qnm_pcie,
1516                    &xm_gic, &qns_gem_noc_cnoc,
1517                    &qns_pcie },
1518 };
1519
1520 static struct qcom_icc_bcm bcm_sn0 = {
1521         .name = "SN0",
1522         .keepalive = true,
1523         .num_nodes = 1,
1524         .nodes = { &qns_gemnoc_sf },
1525 };
1526
1527 static struct qcom_icc_bcm bcm_sn2 = {
1528         .name = "SN2",
1529         .num_nodes = 1,
1530         .nodes = { &qnm_aggre1_noc },
1531 };
1532
1533 static struct qcom_icc_bcm bcm_sn3 = {
1534         .name = "SN3",
1535         .num_nodes = 1,
1536         .nodes = { &qnm_aggre2_noc },
1537 };
1538
1539 static struct qcom_icc_bcm bcm_sn4 = {
1540         .name = "SN4",
1541         .num_nodes = 1,
1542         .nodes = { &qnm_usb_anoc },
1543 };
1544
1545 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1546 };
1547
1548 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1549         [MASTER_QSPI_0] = &qhm_qspi,
1550         [MASTER_QUP_1] = &qhm_qup1,
1551         [MASTER_SDCC_4] = &xm_sdc4,
1552         [MASTER_UFS_MEM] = &xm_ufs_mem,
1553         [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1554 };
1555
1556 static const struct qcom_icc_desc x1e80100_aggre1_noc = {
1557         .nodes = aggre1_noc_nodes,
1558         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1559         .bcms = aggre1_noc_bcms,
1560         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1561 };
1562
1563 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1564         &bcm_ce0,
1565 };
1566
1567 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1568         [MASTER_QUP_0] = &qhm_qup0,
1569         [MASTER_QUP_2] = &qhm_qup2,
1570         [MASTER_CRYPTO] = &qxm_crypto,
1571         [MASTER_SP] = &qxm_sp,
1572         [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1573         [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1574         [MASTER_SDCC_2] = &xm_sdc2,
1575         [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1576 };
1577
1578 static const struct qcom_icc_desc x1e80100_aggre2_noc = {
1579         .nodes = aggre2_noc_nodes,
1580         .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1581         .bcms = aggre2_noc_bcms,
1582         .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1583 };
1584
1585 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1586         &bcm_acv_perf,
1587         &bcm_qup0,
1588         &bcm_qup1,
1589         &bcm_qup2,
1590 };
1591
1592 static struct qcom_icc_node * const clk_virt_nodes[] = {
1593         [MASTER_DDR_PERF_MODE] = &ddr_perf_mode_master,
1594         [MASTER_QUP_CORE_0] = &qup0_core_master,
1595         [MASTER_QUP_CORE_1] = &qup1_core_master,
1596         [MASTER_QUP_CORE_2] = &qup2_core_master,
1597         [SLAVE_DDR_PERF_MODE] = &ddr_perf_mode_slave,
1598         [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1599         [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1600         [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1601 };
1602
1603 static const struct qcom_icc_desc x1e80100_clk_virt = {
1604         .nodes = clk_virt_nodes,
1605         .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1606         .bcms = clk_virt_bcms,
1607         .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1608 };
1609
1610 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
1611         &bcm_cn0,
1612         &bcm_cn1,
1613 };
1614
1615 static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
1616         [MASTER_CNOC_CFG] = &qsm_cfg,
1617         [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1618         [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1619         [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1620         [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg,
1621         [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1622         [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1623         [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1624         [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1625         [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1626         [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1627         [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1628         [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1629         [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1630         [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
1631         [SLAVE_PCIE_3_CFG] = &qhs_pcie3_cfg,
1632         [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg,
1633         [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg,
1634         [SLAVE_PCIE_6A_CFG] = &qhs_pcie6a_cfg,
1635         [SLAVE_PCIE_6B_CFG] = &qhs_pcie6b_cfg,
1636         [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
1637         [SLAVE_PDM] = &qhs_pdm,
1638         [SLAVE_PRNG] = &qhs_prng,
1639         [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1640         [SLAVE_QSPI_0] = &qhs_qspi,
1641         [SLAVE_QUP_0] = &qhs_qup0,
1642         [SLAVE_QUP_1] = &qhs_qup1,
1643         [SLAVE_QUP_2] = &qhs_qup2,
1644         [SLAVE_SDCC_2] = &qhs_sdc2,
1645         [SLAVE_SDCC_4] = &qhs_sdc4,
1646         [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg,
1647         [SLAVE_TCSR] = &qhs_tcsr,
1648         [SLAVE_TLMM] = &qhs_tlmm,
1649         [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1650         [SLAVE_USB2] = &qhs_usb2_0_cfg,
1651         [SLAVE_USB3_0] = &qhs_usb3_0_cfg,
1652         [SLAVE_USB3_1] = &qhs_usb3_1_cfg,
1653         [SLAVE_USB3_2] = &qhs_usb3_2_cfg,
1654         [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg,
1655         [SLAVE_USB4_0] = &qhs_usb4_0_cfg,
1656         [SLAVE_USB4_1] = &qhs_usb4_1_cfg,
1657         [SLAVE_USB4_2] = &qhs_usb4_2_cfg,
1658         [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1659         [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
1660         [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1661         [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1662         [SLAVE_QDSS_STM] = &xs_qdss_stm,
1663         [SLAVE_TCU] = &xs_sys_tcu_cfg,
1664 };
1665
1666 static const struct qcom_icc_desc x1e80100_cnoc_cfg = {
1667         .nodes = cnoc_cfg_nodes,
1668         .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
1669         .bcms = cnoc_cfg_bcms,
1670         .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
1671 };
1672
1673 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1674         &bcm_cn0,
1675 };
1676
1677 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1678         [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1679         [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1680         [SLAVE_AOSS] = &qhs_aoss,
1681         [SLAVE_TME_CFG] = &qhs_tme_cfg,
1682         [SLAVE_APPSS] = &qns_apss,
1683         [SLAVE_CNOC_CFG] = &qss_cfg,
1684         [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1685         [SLAVE_IMEM] = &qxs_imem,
1686         [SLAVE_PCIE_0] = &xs_pcie_0,
1687         [SLAVE_PCIE_1] = &xs_pcie_1,
1688         [SLAVE_PCIE_2] = &xs_pcie_2,
1689         [SLAVE_PCIE_3] = &xs_pcie_3,
1690         [SLAVE_PCIE_4] = &xs_pcie_4,
1691         [SLAVE_PCIE_5] = &xs_pcie_5,
1692         [SLAVE_PCIE_6A] = &xs_pcie_6a,
1693         [SLAVE_PCIE_6B] = &xs_pcie_6b,
1694 };
1695
1696 static const struct qcom_icc_desc x1e80100_cnoc_main = {
1697         .nodes = cnoc_main_nodes,
1698         .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1699         .bcms = cnoc_main_bcms,
1700         .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1701 };
1702
1703 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1704         &bcm_sh0,
1705         &bcm_sh1,
1706 };
1707
1708 static struct qcom_icc_node * const gem_noc_nodes[] = {
1709         [MASTER_GPU_TCU] = &alm_gpu_tcu,
1710         [MASTER_PCIE_TCU] = &alm_pcie_tcu,
1711         [MASTER_SYS_TCU] = &alm_sys_tcu,
1712         [MASTER_APPSS_PROC] = &chm_apps,
1713         [MASTER_GFX3D] = &qnm_gpu,
1714         [MASTER_LPASS_GEM_NOC] = &qnm_lpass,
1715         [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1716         [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1717         [MASTER_COMPUTE_NOC] = &qnm_nsp_noc,
1718         [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1719         [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1720         [MASTER_GIC2] = &xm_gic,
1721         [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1722         [SLAVE_LLCC] = &qns_llcc,
1723         [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1724 };
1725
1726 static const struct qcom_icc_desc x1e80100_gem_noc = {
1727         .nodes = gem_noc_nodes,
1728         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1729         .bcms = gem_noc_bcms,
1730         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1731 };
1732
1733 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1734 };
1735
1736 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1737         [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1738         [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1739 };
1740
1741 static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {
1742         .nodes = lpass_ag_noc_nodes,
1743         .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1744         .bcms = lpass_ag_noc_bcms,
1745         .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1746 };
1747
1748 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1749         &bcm_lp0,
1750 };
1751
1752 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1753         [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1754         [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1755 };
1756
1757 static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {
1758         .nodes = lpass_lpiaon_noc_nodes,
1759         .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1760         .bcms = lpass_lpiaon_noc_bcms,
1761         .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1762 };
1763
1764 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {
1765 };
1766
1767 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1768         [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
1769         [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1770 };
1771
1772 static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
1773         .nodes = lpass_lpicx_noc_nodes,
1774         .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1775         .bcms = lpass_lpicx_noc_bcms,
1776         .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),
1777 };
1778
1779 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1780         &bcm_acv,
1781         &bcm_mc0,
1782 };
1783
1784 static struct qcom_icc_node * const mc_virt_nodes[] = {
1785         [MASTER_LLCC] = &llcc_mc,
1786         [SLAVE_EBI1] = &ebi,
1787 };
1788
1789 static const struct qcom_icc_desc x1e80100_mc_virt = {
1790         .nodes = mc_virt_nodes,
1791         .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1792         .bcms = mc_virt_bcms,
1793         .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1794 };
1795
1796 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1797         &bcm_mm0,
1798         &bcm_mm1,
1799 };
1800
1801 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1802         [MASTER_AV1_ENC] = &qnm_av1_enc,
1803         [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1804         [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1805         [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1806         [MASTER_EVA] = &qnm_eva,
1807         [MASTER_MDP] = &qnm_mdp,
1808         [MASTER_VIDEO] = &qnm_video,
1809         [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1810         [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1811         [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
1812         [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1813         [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1814         [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1815 };
1816
1817 static const struct qcom_icc_desc x1e80100_mmss_noc = {
1818         .nodes = mmss_noc_nodes,
1819         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1820         .bcms = mmss_noc_bcms,
1821         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1822 };
1823
1824 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1825         &bcm_co0,
1826 };
1827
1828 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1829         [MASTER_CDSP_PROC] = &qxm_nsp,
1830         [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1831 };
1832
1833 static const struct qcom_icc_desc x1e80100_nsp_noc = {
1834         .nodes = nsp_noc_nodes,
1835         .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1836         .bcms = nsp_noc_bcms,
1837         .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1838 };
1839
1840 static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
1841         &bcm_pc0,
1842 };
1843
1844 static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
1845         [MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
1846         [MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
1847         [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1848 };
1849
1850 static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
1851         .nodes = pcie_center_anoc_nodes,
1852         .num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),
1853         .bcms = pcie_center_anoc_bcms,
1854         .num_bcms = ARRAY_SIZE(pcie_center_anoc_bcms),
1855 };
1856
1857 static struct qcom_icc_bcm * const pcie_north_anoc_bcms[] = {
1858 };
1859
1860 static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
1861         [MASTER_PCIE_3] = &xm_pcie_3,
1862         [MASTER_PCIE_4] = &xm_pcie_4,
1863         [MASTER_PCIE_5] = &xm_pcie_5,
1864         [SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
1865 };
1866
1867 static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
1868         .nodes = pcie_north_anoc_nodes,
1869         .num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),
1870         .bcms = pcie_north_anoc_bcms,
1871         .num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms),
1872 };
1873
1874 static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = {
1875 };
1876
1877 static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
1878         [MASTER_PCIE_0] = &xm_pcie_0,
1879         [MASTER_PCIE_1] = &xm_pcie_1,
1880         [MASTER_PCIE_2] = &xm_pcie_2,
1881         [MASTER_PCIE_6A] = &xm_pcie_6a,
1882         [MASTER_PCIE_6B] = &xm_pcie_6b,
1883         [SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
1884 };
1885
1886 static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
1887         .nodes = pcie_south_anoc_nodes,
1888         .num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),
1889         .bcms = pcie_south_anoc_bcms,
1890         .num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms),
1891 };
1892
1893 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1894         &bcm_sn0,
1895         &bcm_sn2,
1896         &bcm_sn3,
1897         &bcm_sn4,
1898 };
1899
1900 static struct qcom_icc_node * const system_noc_nodes[] = {
1901         [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1902         [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1903         [MASTER_GIC1] = &qnm_gic,
1904         [MASTER_USB_NOC_SNOC] = &qnm_usb_anoc,
1905         [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1906 };
1907
1908 static const struct qcom_icc_desc x1e80100_system_noc = {
1909         .nodes = system_noc_nodes,
1910         .num_nodes = ARRAY_SIZE(system_noc_nodes),
1911         .bcms = system_noc_bcms,
1912         .num_bcms = ARRAY_SIZE(system_noc_bcms),
1913 };
1914
1915 static struct qcom_icc_bcm * const usb_center_anoc_bcms[] = {
1916 };
1917
1918 static struct qcom_icc_node * const usb_center_anoc_nodes[] = {
1919         [MASTER_AGGRE_USB_NORTH] = &qnm_aggre_usb_north_snoc,
1920         [MASTER_AGGRE_USB_SOUTH] = &qnm_aggre_usb_south_snoc,
1921         [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc,
1922 };
1923
1924 static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
1925         .nodes = usb_center_anoc_nodes,
1926         .num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),
1927         .bcms = usb_center_anoc_bcms,
1928         .num_bcms = ARRAY_SIZE(usb_center_anoc_bcms),
1929 };
1930
1931 static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = {
1932 };
1933
1934 static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
1935         [MASTER_USB2] = &xm_usb2_0,
1936         [MASTER_USB3_MP] = &xm_usb3_mp,
1937         [SLAVE_AGGRE_USB_NORTH] = &qns_aggre_usb_north_snoc,
1938 };
1939
1940 static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
1941         .nodes = usb_north_anoc_nodes,
1942         .num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),
1943         .bcms = usb_north_anoc_bcms,
1944         .num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
1945 };
1946
1947 static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
1948 };
1949
1950 static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
1951         [MASTER_USB3_0] = &xm_usb3_0,
1952         [MASTER_USB3_1] = &xm_usb3_1,
1953         [MASTER_USB3_2] = &xm_usb3_2,
1954         [MASTER_USB4_0] = &xm_usb4_0,
1955         [MASTER_USB4_1] = &xm_usb4_1,
1956         [MASTER_USB4_2] = &xm_usb4_2,
1957         [SLAVE_AGGRE_USB_SOUTH] = &qns_aggre_usb_south_snoc,
1958 };
1959
1960 static const struct qcom_icc_desc x1e80100_usb_south_anoc = {
1961         .nodes = usb_south_anoc_nodes,
1962         .num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),
1963         .bcms = usb_south_anoc_bcms,
1964         .num_bcms = ARRAY_SIZE(usb_south_anoc_bcms),
1965 };
1966
1967 static const struct of_device_id qnoc_of_match[] = {
1968         { .compatible = "qcom,x1e80100-aggre1-noc", .data = &x1e80100_aggre1_noc},
1969         { .compatible = "qcom,x1e80100-aggre2-noc", .data = &x1e80100_aggre2_noc},
1970         { .compatible = "qcom,x1e80100-clk-virt", .data = &x1e80100_clk_virt},
1971         { .compatible = "qcom,x1e80100-cnoc-cfg", .data = &x1e80100_cnoc_cfg},
1972         { .compatible = "qcom,x1e80100-cnoc-main", .data = &x1e80100_cnoc_main},
1973         { .compatible = "qcom,x1e80100-gem-noc", .data = &x1e80100_gem_noc},
1974         { .compatible = "qcom,x1e80100-lpass-ag-noc", .data = &x1e80100_lpass_ag_noc},
1975         { .compatible = "qcom,x1e80100-lpass-lpiaon-noc", .data = &x1e80100_lpass_lpiaon_noc},
1976         { .compatible = "qcom,x1e80100-lpass-lpicx-noc", .data = &x1e80100_lpass_lpicx_noc},
1977         { .compatible = "qcom,x1e80100-mc-virt", .data = &x1e80100_mc_virt},
1978         { .compatible = "qcom,x1e80100-mmss-noc", .data = &x1e80100_mmss_noc},
1979         { .compatible = "qcom,x1e80100-nsp-noc", .data = &x1e80100_nsp_noc},
1980         { .compatible = "qcom,x1e80100-pcie-center-anoc", .data = &x1e80100_pcie_center_anoc},
1981         { .compatible = "qcom,x1e80100-pcie-north-anoc", .data = &x1e80100_pcie_north_anoc},
1982         { .compatible = "qcom,x1e80100-pcie-south-anoc", .data = &x1e80100_pcie_south_anoc},
1983         { .compatible = "qcom,x1e80100-system-noc", .data = &x1e80100_system_noc},
1984         { .compatible = "qcom,x1e80100-usb-center-anoc", .data = &x1e80100_usb_center_anoc},
1985         { .compatible = "qcom,x1e80100-usb-north-anoc", .data = &x1e80100_usb_north_anoc},
1986         { .compatible = "qcom,x1e80100-usb-south-anoc", .data = &x1e80100_usb_south_anoc},
1987         { }
1988 };
1989 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1990
1991 static struct platform_driver qnoc_driver = {
1992         .probe = qcom_icc_rpmh_probe,
1993         .remove_new = qcom_icc_rpmh_remove,
1994         .driver = {
1995                 .name = "qnoc-x1e80100",
1996                 .of_match_table = qnoc_of_match,
1997                 .sync_state = icc_sync_state,
1998         },
1999 };
2000
2001 static int __init qnoc_driver_init(void)
2002 {
2003         return platform_driver_register(&qnoc_driver);
2004 }
2005 core_initcall(qnoc_driver_init);
2006
2007 static void __exit qnoc_driver_exit(void)
2008 {
2009         platform_driver_unregister(&qnoc_driver);
2010 }
2011 module_exit(qnoc_driver_exit);
2012
2013 MODULE_DESCRIPTION("x1e80100 NoC driver");
2014 MODULE_LICENSE("GPL");