2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <rdma/rdma_counter.h>
38 #include <linux/mlx5/fs.h>
46 MLX5_IB_ACK_REQ_FREQ = 8,
50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
52 MLX5_IB_LINK_TYPE_IB = 0,
53 MLX5_IB_LINK_TYPE_ETH = 1
56 enum raw_qp_set_mask_map {
57 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
58 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
61 struct mlx5_modify_raw_qp_param {
64 u32 set_mask; /* raw_qp_set_mask_map */
66 struct mlx5_rate_limit rl;
72 static void get_cqs(enum ib_qp_type qp_type,
73 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
74 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
76 static int is_qp0(enum ib_qp_type qp_type)
78 return qp_type == IB_QPT_SMI;
81 static int is_sqp(enum ib_qp_type qp_type)
83 return is_qp0(qp_type) || is_qp1(qp_type);
87 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
90 * @umem: User space memory where the WQ is
91 * @buffer: buffer to copy to
92 * @buflen: buffer length
93 * @wqe_index: index of WQE to copy from
94 * @wq_offset: offset to start of WQ
95 * @wq_wqe_cnt: number of WQEs in WQ
96 * @wq_wqe_shift: log2 of WQE size
97 * @bcnt: number of bytes to copy
98 * @bytes_copied: number of bytes to copy (return value)
100 * Copies from start of WQE bcnt or less bytes.
101 * Does not gurantee to copy the entire WQE.
103 * Return: zero on success, or an error code.
105 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
106 size_t buflen, int wqe_index,
107 int wq_offset, int wq_wqe_cnt,
108 int wq_wqe_shift, int bcnt,
109 size_t *bytes_copied)
111 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
112 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
116 /* don't copy more than requested, more than buffer length or
119 copy_length = min_t(u32, buflen, wq_end - offset);
120 copy_length = min_t(u32, copy_length, bcnt);
122 ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
126 if (!ret && bytes_copied)
127 *bytes_copied = copy_length;
132 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
133 void *buffer, size_t buflen, size_t *bc)
135 struct mlx5_wqe_ctrl_seg *ctrl;
136 size_t bytes_copied = 0;
141 wqe_index = wqe_index & qp->sq.fbc.sz_m1;
143 /* read the control segment first */
144 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
146 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
147 wqe_length = ds * MLX5_WQE_DS_UNITS;
149 /* read rest of WQE if it spreads over more than one stride */
150 while (bytes_copied < wqe_length) {
152 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
157 memcpy(buffer + bytes_copied, p, copy_length);
158 bytes_copied += copy_length;
160 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
161 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
167 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
168 void *buffer, size_t buflen, size_t *bc)
170 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
171 struct ib_umem *umem = base->ubuffer.umem;
172 struct mlx5_ib_wq *wq = &qp->sq;
173 struct mlx5_wqe_ctrl_seg *ctrl;
175 size_t bytes_copied2;
180 /* at first read as much as possible */
181 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
182 wq->offset, wq->wqe_cnt,
183 wq->wqe_shift, buflen,
188 /* we need at least control segment size to proceed */
189 if (bytes_copied < sizeof(*ctrl))
193 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
194 wqe_length = ds * MLX5_WQE_DS_UNITS;
196 /* if we copied enough then we are done */
197 if (bytes_copied >= wqe_length) {
202 /* otherwise this a wrapped around wqe
203 * so read the remaining bytes starting
206 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
207 buflen - bytes_copied, 0, wq->offset,
208 wq->wqe_cnt, wq->wqe_shift,
209 wqe_length - bytes_copied,
214 *bc = bytes_copied + bytes_copied2;
218 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
219 size_t buflen, size_t *bc)
221 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
222 struct ib_umem *umem = base->ubuffer.umem;
224 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
228 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
231 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
234 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
235 void *buffer, size_t buflen, size_t *bc)
237 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
238 struct ib_umem *umem = base->ubuffer.umem;
239 struct mlx5_ib_wq *wq = &qp->rq;
243 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
244 wq->offset, wq->wqe_cnt,
245 wq->wqe_shift, buflen,
254 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
255 size_t buflen, size_t *bc)
257 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
258 struct ib_umem *umem = base->ubuffer.umem;
259 struct mlx5_ib_wq *wq = &qp->rq;
260 size_t wqe_size = 1 << wq->wqe_shift;
262 if (buflen < wqe_size)
268 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
271 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
272 void *buffer, size_t buflen, size_t *bc)
274 struct ib_umem *umem = srq->umem;
278 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
279 srq->msrq.max, srq->msrq.wqe_shift,
280 buflen, &bytes_copied);
288 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
289 size_t buflen, size_t *bc)
291 struct ib_umem *umem = srq->umem;
292 size_t wqe_size = 1 << srq->msrq.wqe_shift;
294 if (buflen < wqe_size)
300 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
303 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
305 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
306 struct ib_event event;
308 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
309 /* This event is only valid for trans_qps */
310 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
313 if (ibqp->event_handler) {
314 event.device = ibqp->device;
315 event.element.qp = ibqp;
317 case MLX5_EVENT_TYPE_PATH_MIG:
318 event.event = IB_EVENT_PATH_MIG;
320 case MLX5_EVENT_TYPE_COMM_EST:
321 event.event = IB_EVENT_COMM_EST;
323 case MLX5_EVENT_TYPE_SQ_DRAINED:
324 event.event = IB_EVENT_SQ_DRAINED;
326 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
327 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
329 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
330 event.event = IB_EVENT_QP_FATAL;
332 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
333 event.event = IB_EVENT_PATH_MIG_ERR;
335 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
336 event.event = IB_EVENT_QP_REQ_ERR;
338 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
339 event.event = IB_EVENT_QP_ACCESS_ERR;
342 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
346 ibqp->event_handler(&event, ibqp->qp_context);
350 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
351 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
356 /* Sanity check RQ size before proceeding */
357 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
363 qp->rq.wqe_shift = 0;
364 cap->max_recv_wr = 0;
365 cap->max_recv_sge = 0;
367 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
370 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
371 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
373 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
374 if ((1 << qp->rq.wqe_shift) /
375 sizeof(struct mlx5_wqe_data_seg) <
379 (1 << qp->rq.wqe_shift) /
380 sizeof(struct mlx5_wqe_data_seg) -
382 qp->rq.max_post = qp->rq.wqe_cnt;
385 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
387 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
388 wqe_size = roundup_pow_of_two(wqe_size);
389 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
390 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
391 qp->rq.wqe_cnt = wq_size / wqe_size;
392 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
393 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
395 MLX5_CAP_GEN(dev->mdev,
399 qp->rq.wqe_shift = ilog2(wqe_size);
401 (1 << qp->rq.wqe_shift) /
402 sizeof(struct mlx5_wqe_data_seg) -
404 qp->rq.max_post = qp->rq.wqe_cnt;
411 static int sq_overhead(struct ib_qp_init_attr *attr)
415 switch (attr->qp_type) {
417 size += sizeof(struct mlx5_wqe_xrc_seg);
420 size += sizeof(struct mlx5_wqe_ctrl_seg) +
421 max(sizeof(struct mlx5_wqe_atomic_seg) +
422 sizeof(struct mlx5_wqe_raddr_seg),
423 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
424 sizeof(struct mlx5_mkey_seg) +
425 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
426 MLX5_IB_UMR_OCTOWORD);
433 size += sizeof(struct mlx5_wqe_ctrl_seg) +
434 max(sizeof(struct mlx5_wqe_raddr_seg),
435 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
436 sizeof(struct mlx5_mkey_seg));
440 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
441 size += sizeof(struct mlx5_wqe_eth_pad) +
442 sizeof(struct mlx5_wqe_eth_seg);
445 case MLX5_IB_QPT_HW_GSI:
446 size += sizeof(struct mlx5_wqe_ctrl_seg) +
447 sizeof(struct mlx5_wqe_datagram_seg);
450 case MLX5_IB_QPT_REG_UMR:
451 size += sizeof(struct mlx5_wqe_ctrl_seg) +
452 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
453 sizeof(struct mlx5_mkey_seg);
463 static int calc_send_wqe(struct ib_qp_init_attr *attr)
468 size = sq_overhead(attr);
472 if (attr->cap.max_inline_data) {
473 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
474 attr->cap.max_inline_data;
477 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
478 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
479 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
480 return MLX5_SIG_WQE_SIZE;
482 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
485 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
489 if (attr->qp_type == IB_QPT_RC)
490 max_sge = (min_t(int, wqe_size, 512) -
491 sizeof(struct mlx5_wqe_ctrl_seg) -
492 sizeof(struct mlx5_wqe_raddr_seg)) /
493 sizeof(struct mlx5_wqe_data_seg);
494 else if (attr->qp_type == IB_QPT_XRC_INI)
495 max_sge = (min_t(int, wqe_size, 512) -
496 sizeof(struct mlx5_wqe_ctrl_seg) -
497 sizeof(struct mlx5_wqe_xrc_seg) -
498 sizeof(struct mlx5_wqe_raddr_seg)) /
499 sizeof(struct mlx5_wqe_data_seg);
501 max_sge = (wqe_size - sq_overhead(attr)) /
502 sizeof(struct mlx5_wqe_data_seg);
504 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
505 sizeof(struct mlx5_wqe_data_seg));
508 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
509 struct mlx5_ib_qp *qp)
514 if (!attr->cap.max_send_wr)
517 wqe_size = calc_send_wqe(attr);
518 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
522 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
523 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
524 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
528 qp->max_inline_data = wqe_size - sq_overhead(attr) -
529 sizeof(struct mlx5_wqe_inline_seg);
530 attr->cap.max_inline_data = qp->max_inline_data;
532 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
533 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
534 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
535 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
536 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
538 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
541 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
542 qp->sq.max_gs = get_send_sge(attr, wqe_size);
543 if (qp->sq.max_gs < attr->cap.max_send_sge)
546 attr->cap.max_send_sge = qp->sq.max_gs;
547 qp->sq.max_post = wq_size / wqe_size;
548 attr->cap.max_send_wr = qp->sq.max_post;
553 static int set_user_buf_size(struct mlx5_ib_dev *dev,
554 struct mlx5_ib_qp *qp,
555 struct mlx5_ib_create_qp *ucmd,
556 struct mlx5_ib_qp_base *base,
557 struct ib_qp_init_attr *attr)
559 int desc_sz = 1 << qp->sq.wqe_shift;
561 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
562 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
563 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
567 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
568 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
573 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
575 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
576 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
578 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
582 if (attr->qp_type == IB_QPT_RAW_PACKET ||
583 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
584 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
585 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
587 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
588 (qp->sq.wqe_cnt << 6);
594 static int qp_has_rq(struct ib_qp_init_attr *attr)
596 if (attr->qp_type == IB_QPT_XRC_INI ||
597 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
598 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
599 !attr->cap.max_recv_wr)
606 /* this is the first blue flame register in the array of bfregs assigned
607 * to a processes. Since we do not use it for blue flame but rather
608 * regular 64 bit doorbells, we do not need a lock for maintaiing
611 NUM_NON_BLUE_FLAME_BFREGS = 1,
614 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
616 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
619 static int num_med_bfreg(struct mlx5_ib_dev *dev,
620 struct mlx5_bfreg_info *bfregi)
624 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
625 NUM_NON_BLUE_FLAME_BFREGS;
627 return n >= 0 ? n : 0;
630 static int first_med_bfreg(struct mlx5_ib_dev *dev,
631 struct mlx5_bfreg_info *bfregi)
633 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
636 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
637 struct mlx5_bfreg_info *bfregi)
641 med = num_med_bfreg(dev, bfregi);
645 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
646 struct mlx5_bfreg_info *bfregi)
650 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
651 if (!bfregi->count[i]) {
660 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
661 struct mlx5_bfreg_info *bfregi)
663 int minidx = first_med_bfreg(dev, bfregi);
669 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
670 if (bfregi->count[i] < bfregi->count[minidx])
672 if (!bfregi->count[minidx])
676 bfregi->count[minidx]++;
680 static int alloc_bfreg(struct mlx5_ib_dev *dev,
681 struct mlx5_bfreg_info *bfregi)
683 int bfregn = -ENOMEM;
685 if (bfregi->lib_uar_dyn)
688 mutex_lock(&bfregi->lock);
689 if (bfregi->ver >= 2) {
690 bfregn = alloc_high_class_bfreg(dev, bfregi);
692 bfregn = alloc_med_class_bfreg(dev, bfregi);
696 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
698 bfregi->count[bfregn]++;
700 mutex_unlock(&bfregi->lock);
705 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
707 mutex_lock(&bfregi->lock);
708 bfregi->count[bfregn]--;
709 mutex_unlock(&bfregi->lock);
712 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
715 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
716 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
717 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
718 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
719 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
720 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
721 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
726 static int to_mlx5_st(enum ib_qp_type type)
729 case IB_QPT_RC: return MLX5_QP_ST_RC;
730 case IB_QPT_UC: return MLX5_QP_ST_UC;
731 case IB_QPT_UD: return MLX5_QP_ST_UD;
732 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
734 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
735 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
736 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
737 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
738 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE;
739 default: return -EINVAL;
743 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
744 struct mlx5_ib_cq *recv_cq);
745 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
746 struct mlx5_ib_cq *recv_cq);
748 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
749 struct mlx5_bfreg_info *bfregi, u32 bfregn,
752 unsigned int bfregs_per_sys_page;
753 u32 index_of_sys_page;
756 if (bfregi->lib_uar_dyn)
759 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
760 MLX5_NON_FP_BFREGS_PER_UAR;
761 index_of_sys_page = bfregn / bfregs_per_sys_page;
764 index_of_sys_page += bfregi->num_static_sys_pages;
766 if (index_of_sys_page >= bfregi->num_sys_pages)
769 if (bfregn > bfregi->num_dyn_bfregs ||
770 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
771 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
776 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
777 return bfregi->sys_pages[index_of_sys_page] + offset;
780 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
781 unsigned long addr, size_t size,
782 struct ib_umem **umem, int *npages, int *page_shift,
783 int *ncont, u32 *offset)
787 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
789 mlx5_ib_dbg(dev, "umem_get failed\n");
790 return PTR_ERR(*umem);
793 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
795 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
797 mlx5_ib_warn(dev, "bad offset\n");
801 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
802 addr, size, *npages, *page_shift, *ncont, *offset);
807 ib_umem_release(*umem);
813 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
814 struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
816 struct mlx5_ib_ucontext *context =
817 rdma_udata_to_drv_context(
819 struct mlx5_ib_ucontext,
822 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
823 atomic_dec(&dev->delay_drop.rqs_cnt);
825 mlx5_ib_db_unmap_user(context, &rwq->db);
826 ib_umem_release(rwq->umem);
829 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
830 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
831 struct mlx5_ib_create_wq *ucmd)
833 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
834 udata, struct mlx5_ib_ucontext, ibucontext);
844 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
845 if (IS_ERR(rwq->umem)) {
846 mlx5_ib_dbg(dev, "umem_get failed\n");
847 err = PTR_ERR(rwq->umem);
851 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
853 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
854 &rwq->rq_page_offset);
856 mlx5_ib_warn(dev, "bad offset\n");
860 rwq->rq_num_pas = ncont;
861 rwq->page_shift = page_shift;
862 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
863 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
865 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
866 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
867 npages, page_shift, ncont, offset);
869 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
871 mlx5_ib_dbg(dev, "map failed\n");
878 ib_umem_release(rwq->umem);
882 static int adjust_bfregn(struct mlx5_ib_dev *dev,
883 struct mlx5_bfreg_info *bfregi, int bfregn)
885 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
886 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
889 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
890 struct mlx5_ib_qp *qp, struct ib_udata *udata,
891 struct ib_qp_init_attr *attr, u32 **in,
892 struct mlx5_ib_create_qp_resp *resp, int *inlen,
893 struct mlx5_ib_qp_base *base,
894 struct mlx5_ib_create_qp *ucmd)
896 struct mlx5_ib_ucontext *context;
897 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
910 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
912 uar_flags = qp->flags_en &
913 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
915 case MLX5_QP_FLAG_UAR_PAGE_INDEX:
916 uar_index = ucmd->bfreg_index;
917 bfregn = MLX5_IB_INVALID_BFREG;
919 case MLX5_QP_FLAG_BFREG_INDEX:
920 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
921 ucmd->bfreg_index, true);
924 bfregn = MLX5_IB_INVALID_BFREG;
927 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
929 bfregn = alloc_bfreg(dev, &context->bfregi);
937 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
938 if (bfregn != MLX5_IB_INVALID_BFREG)
939 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
943 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
944 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
946 err = set_user_buf_size(dev, qp, ucmd, base, attr);
950 if (ucmd->buf_addr && ubuffer->buf_size) {
951 ubuffer->buf_addr = ucmd->buf_addr;
952 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
953 ubuffer->buf_size, &ubuffer->umem,
954 &npages, &page_shift, &ncont, &offset);
958 ubuffer->umem = NULL;
961 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
962 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
963 *in = kvzalloc(*inlen, GFP_KERNEL);
969 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
970 MLX5_SET(create_qp_in, *in, uid, uid);
971 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
973 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
975 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
977 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
978 MLX5_SET(qpc, qpc, page_offset, offset);
980 MLX5_SET(qpc, qpc, uar_page, uar_index);
981 if (bfregn != MLX5_IB_INVALID_BFREG)
982 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
984 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
987 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
989 mlx5_ib_dbg(dev, "map failed\n");
999 ib_umem_release(ubuffer->umem);
1002 if (bfregn != MLX5_IB_INVALID_BFREG)
1003 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1007 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1008 struct mlx5_ib_qp_base *base, struct ib_udata *udata)
1010 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1011 udata, struct mlx5_ib_ucontext, ibucontext);
1015 mlx5_ib_db_unmap_user(context, &qp->db);
1016 ib_umem_release(base->ubuffer.umem);
1019 * Free only the BFREGs which are handled by the kernel.
1020 * BFREGs of UARs allocated dynamically are handled by user.
1022 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1023 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1028 kvfree(qp->sq.wqe_head);
1029 kvfree(qp->sq.w_list);
1030 kvfree(qp->sq.wrid);
1031 kvfree(qp->sq.wr_data);
1032 kvfree(qp->rq.wrid);
1034 mlx5_db_free(dev->mdev, &qp->db);
1036 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1039 static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1040 struct ib_qp_init_attr *init_attr,
1041 struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1042 struct mlx5_ib_qp_base *base)
1048 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1049 qp->bf.bfreg = &dev->fp_bfreg;
1050 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
1051 qp->bf.bfreg = &dev->wc_bfreg;
1053 qp->bf.bfreg = &dev->bfreg;
1055 /* We need to divide by two since each register is comprised of
1056 * two buffers of identical size, namely odd and even
1058 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1059 uar_index = qp->bf.bfreg->index;
1061 err = calc_sq_size(dev, init_attr, qp);
1063 mlx5_ib_dbg(dev, "err %d\n", err);
1068 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1069 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1071 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1072 &qp->buf, dev->mdev->priv.numa_node);
1074 mlx5_ib_dbg(dev, "err %d\n", err);
1079 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1080 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1082 if (qp->sq.wqe_cnt) {
1083 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
1085 mlx5_init_fbc_offset(qp->buf.frags +
1086 (qp->sq.offset / PAGE_SIZE),
1087 ilog2(MLX5_SEND_WQE_BB),
1088 ilog2(qp->sq.wqe_cnt),
1089 sq_strides_offset, &qp->sq.fbc);
1091 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1094 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1095 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1096 *in = kvzalloc(*inlen, GFP_KERNEL);
1102 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1103 MLX5_SET(qpc, qpc, uar_page, uar_index);
1104 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1106 /* Set "fast registration enabled" for all kernel QPs */
1107 MLX5_SET(qpc, qpc, fre, 1);
1108 MLX5_SET(qpc, qpc, rlky, 1);
1110 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
1111 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1113 mlx5_fill_page_frag_array(&qp->buf,
1114 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1117 err = mlx5_db_alloc(dev->mdev, &qp->db);
1119 mlx5_ib_dbg(dev, "err %d\n", err);
1123 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1124 sizeof(*qp->sq.wrid), GFP_KERNEL);
1125 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1126 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1127 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1128 sizeof(*qp->rq.wrid), GFP_KERNEL);
1129 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1130 sizeof(*qp->sq.w_list), GFP_KERNEL);
1131 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1132 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1134 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1135 !qp->sq.w_list || !qp->sq.wqe_head) {
1143 kvfree(qp->sq.wqe_head);
1144 kvfree(qp->sq.w_list);
1145 kvfree(qp->sq.wrid);
1146 kvfree(qp->sq.wr_data);
1147 kvfree(qp->rq.wrid);
1148 mlx5_db_free(dev->mdev, &qp->db);
1154 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1158 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1160 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1161 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
1163 else if (!qp->has_rq)
1164 return MLX5_ZERO_LEN_RQ;
1166 return MLX5_NON_ZERO_RQ;
1169 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1170 struct mlx5_ib_qp *qp,
1171 struct mlx5_ib_sq *sq, u32 tdn,
1174 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1175 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1177 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1178 MLX5_SET(tisc, tisc, transport_domain, tdn);
1179 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1180 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1182 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1185 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1186 struct mlx5_ib_sq *sq, struct ib_pd *pd)
1188 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1191 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1194 mlx5_del_flow_rules(sq->flow_rule);
1195 sq->flow_rule = NULL;
1198 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1199 struct ib_udata *udata,
1200 struct mlx5_ib_sq *sq, void *qpin,
1203 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1207 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1216 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1217 &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1222 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1223 in = kvzalloc(inlen, GFP_KERNEL);
1229 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1230 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1231 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1232 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1233 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1234 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1235 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1236 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1237 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1238 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1239 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1240 MLX5_CAP_ETH(dev->mdev, swp))
1241 MLX5_SET(sqc, sqc, allow_swp, 1);
1243 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1244 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1245 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1246 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1247 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1248 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1249 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1250 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1251 MLX5_SET(wq, wq, page_offset, offset);
1253 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1254 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1256 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1266 ib_umem_release(sq->ubuffer.umem);
1267 sq->ubuffer.umem = NULL;
1272 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1273 struct mlx5_ib_sq *sq)
1275 destroy_flow_rule_vport_sq(sq);
1276 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1277 ib_umem_release(sq->ubuffer.umem);
1280 static size_t get_rq_pas_size(void *qpc)
1282 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1283 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1284 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1285 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1286 u32 po_quanta = 1 << (log_page_size - 6);
1287 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1288 u32 page_size = 1 << log_page_size;
1289 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1290 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1292 return rq_num_pas * sizeof(u64);
1295 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1296 struct mlx5_ib_rq *rq, void *qpin,
1297 size_t qpinlen, struct ib_pd *pd)
1299 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1305 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1306 size_t rq_pas_size = get_rq_pas_size(qpc);
1310 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1313 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1314 in = kvzalloc(inlen, GFP_KERNEL);
1318 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1319 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1320 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1321 MLX5_SET(rqc, rqc, vsd, 1);
1322 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1323 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1324 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1325 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1326 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1328 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
1329 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1331 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1332 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1333 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1334 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1335 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1336 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1337 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1338 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1339 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1340 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1342 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1343 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1344 memcpy(pas, qp_pas, rq_pas_size);
1346 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1353 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1354 struct mlx5_ib_rq *rq)
1356 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1359 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1360 struct mlx5_ib_rq *rq,
1364 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1365 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1366 mlx5_ib_disable_lb(dev, false, true);
1367 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1370 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1371 struct mlx5_ib_rq *rq, u32 tdn,
1372 u32 *qp_flags_en, struct ib_pd *pd,
1381 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1382 in = kvzalloc(inlen, GFP_KERNEL);
1386 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1387 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1388 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1389 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1390 MLX5_SET(tirc, tirc, transport_domain, tdn);
1391 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1392 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1394 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1395 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1397 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1398 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1401 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1402 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1405 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1406 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1407 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1408 rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1409 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1410 err = mlx5_ib_enable_lb(dev, false, true);
1413 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1420 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1421 u32 *in, size_t inlen,
1423 struct ib_udata *udata,
1424 struct mlx5_ib_create_qp_resp *resp)
1426 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1427 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1428 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1429 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1430 udata, struct mlx5_ib_ucontext, ibucontext);
1432 u32 tdn = mucontext->tdn;
1433 u16 uid = to_mpd(pd)->uid;
1434 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1436 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt)
1438 if (qp->sq.wqe_cnt) {
1439 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1443 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1445 goto err_destroy_tis;
1448 resp->tisn = sq->tisn;
1449 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1450 resp->sqn = sq->base.mqp.qpn;
1451 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1454 sq->base.container_mibqp = qp;
1455 sq->base.mqp.event = mlx5_ib_qp_event;
1458 if (qp->rq.wqe_cnt) {
1459 rq->base.container_mibqp = qp;
1461 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
1462 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1463 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
1464 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1465 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1467 goto err_destroy_sq;
1469 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1472 goto err_destroy_rq;
1475 resp->rqn = rq->base.mqp.qpn;
1476 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1477 resp->tirn = rq->tirn;
1478 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1479 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1480 resp->tir_icm_addr = MLX5_GET(
1481 create_tir_out, out, icm_address_31_0);
1482 resp->tir_icm_addr |=
1483 (u64)MLX5_GET(create_tir_out, out,
1486 resp->tir_icm_addr |=
1487 (u64)MLX5_GET(create_tir_out, out,
1491 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1496 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1501 destroy_raw_packet_qp_rq(dev, rq);
1503 if (!qp->sq.wqe_cnt)
1505 destroy_raw_packet_qp_sq(dev, sq);
1507 destroy_raw_packet_qp_tis(dev, sq, pd);
1512 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1513 struct mlx5_ib_qp *qp)
1515 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1516 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1517 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1519 if (qp->rq.wqe_cnt) {
1520 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1521 destroy_raw_packet_qp_rq(dev, rq);
1524 if (qp->sq.wqe_cnt) {
1525 destroy_raw_packet_qp_sq(dev, sq);
1526 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1530 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1531 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1533 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1534 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1538 sq->doorbell = &qp->db;
1539 rq->doorbell = &qp->db;
1542 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1544 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1545 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1546 mlx5_ib_disable_lb(dev, false, true);
1547 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1548 to_mpd(qp->ibqp.pd)->uid);
1551 struct mlx5_create_qp_params {
1552 struct ib_udata *udata;
1558 struct ib_qp_init_attr *attr;
1560 struct mlx5_ib_create_qp_resp resp;
1563 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1564 struct mlx5_ib_qp *qp,
1565 struct mlx5_create_qp_params *params)
1567 struct ib_qp_init_attr *init_attr = params->attr;
1568 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd;
1569 struct ib_udata *udata = params->udata;
1570 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1571 udata, struct mlx5_ib_ucontext, ibucontext);
1579 u32 selected_fields = 0;
1581 u32 tdn = mucontext->tdn;
1584 if (ucmd->comp_mask) {
1585 mlx5_ib_dbg(dev, "invalid comp mask\n");
1589 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1590 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1591 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1596 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1598 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1599 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1601 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1602 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1604 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1605 outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1606 in = kvzalloc(inlen + outlen, GFP_KERNEL);
1610 out = in + MLX5_ST_SZ_DW(create_tir_in);
1611 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1612 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1613 MLX5_SET(tirc, tirc, disp_type,
1614 MLX5_TIRC_DISP_TYPE_INDIRECT);
1615 MLX5_SET(tirc, tirc, indirect_table,
1616 init_attr->rwq_ind_tbl->ind_tbl_num);
1617 MLX5_SET(tirc, tirc, transport_domain, tdn);
1619 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1621 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1622 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1624 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1626 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1627 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1629 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1631 switch (ucmd->rx_hash_function) {
1632 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1634 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1635 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1637 if (len != ucmd->rx_key_len) {
1642 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1643 memcpy(rss_key, ucmd->rx_hash_key, len);
1651 if (!ucmd->rx_hash_fields_mask) {
1652 /* special case when this TIR serves as steering entry without hashing */
1653 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1659 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1660 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1661 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1662 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1667 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1668 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1669 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1670 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1671 MLX5_L3_PROT_TYPE_IPV4);
1672 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1673 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1674 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1675 MLX5_L3_PROT_TYPE_IPV6);
1677 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1678 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1680 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1681 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1683 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1685 /* Check that only one l4 protocol is set */
1686 if (outer_l4 & (outer_l4 - 1)) {
1691 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1692 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1693 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1694 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1695 MLX5_L4_PROT_TYPE_TCP);
1696 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1697 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1698 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1699 MLX5_L4_PROT_TYPE_UDP);
1701 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1702 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1703 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1705 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1706 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1707 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1709 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1710 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1711 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1713 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1714 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1715 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1717 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1718 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1720 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1723 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1724 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1726 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1727 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1728 err = mlx5_ib_enable_lb(dev, false, true);
1731 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1738 if (mucontext->devx_uid) {
1739 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1740 params->resp.tirn = qp->rss_qp.tirn;
1741 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1742 params->resp.tir_icm_addr =
1743 MLX5_GET(create_tir_out, out, icm_address_31_0);
1744 params->resp.tir_icm_addr |=
1745 (u64)MLX5_GET(create_tir_out, out,
1748 params->resp.tir_icm_addr |=
1749 (u64)MLX5_GET(create_tir_out, out,
1752 params->resp.comp_mask |=
1753 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1758 /* qpn is reserved for that QP */
1759 qp->trans_qp.base.mqp.qpn = 0;
1768 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1769 struct ib_qp_init_attr *init_attr,
1770 struct mlx5_ib_create_qp *ucmd,
1774 bool allow_scat_cqe = false;
1777 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1779 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1782 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1783 if (scqe_sz == 128) {
1784 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1788 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1789 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1790 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1793 static int atomic_size_to_mode(int size_mask)
1795 /* driver does not support atomic_size > 256B
1796 * and does not know how to translate bigger sizes
1798 int supported_size_mask = size_mask & 0x1ff;
1801 if (!supported_size_mask)
1804 log_max_size = __fls(supported_size_mask);
1806 if (log_max_size > 3)
1807 return log_max_size;
1809 return MLX5_ATOMIC_MODE_8B;
1812 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1813 enum ib_qp_type qp_type)
1815 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1816 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1817 int atomic_mode = -EOPNOTSUPP;
1818 int atomic_size_mask;
1823 if (qp_type == MLX5_IB_QPT_DCT)
1824 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1826 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1828 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1829 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1830 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1832 if (atomic_mode <= 0 &&
1833 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1834 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1835 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1840 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1841 struct mlx5_create_qp_params *params)
1843 struct mlx5_ib_create_qp *ucmd = params->ucmd;
1844 struct ib_qp_init_attr *attr = params->attr;
1845 u32 uidx = params->uidx;
1846 struct mlx5_ib_resources *devr = &dev->devr;
1847 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1848 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1849 struct mlx5_core_dev *mdev = dev->mdev;
1850 struct mlx5_ib_qp_base *base;
1851 unsigned long flags;
1856 mutex_init(&qp->mutex);
1858 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1859 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1861 in = kvzalloc(inlen, GFP_KERNEL);
1865 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd)
1866 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
1867 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1869 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1870 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1871 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1873 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1874 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1875 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1876 MLX5_SET(qpc, qpc, cd_master, 1);
1877 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1878 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1879 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1880 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1882 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1883 MLX5_SET(qpc, qpc, no_sq, 1);
1884 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1885 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1886 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1887 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1888 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1890 /* 0xffffff means we ask to work with cqe version 0 */
1891 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1892 MLX5_SET(qpc, qpc, user_index, uidx);
1894 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1895 MLX5_SET(qpc, qpc, end_padding_mode,
1896 MLX5_WQ_END_PAD_MODE_ALIGN);
1897 /* Special case to clean flag */
1898 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1901 base = &qp->trans_qp.base;
1902 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
1907 base->container_mibqp = qp;
1908 base->mqp.event = mlx5_ib_qp_event;
1909 if (MLX5_CAP_GEN(mdev, ece_support))
1910 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
1912 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1913 list_add_tail(&qp->qps_list, &dev->qp_list);
1914 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1916 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn;
1920 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1921 struct mlx5_ib_qp *qp,
1922 struct mlx5_create_qp_params *params)
1924 struct ib_qp_init_attr *init_attr = params->attr;
1925 struct mlx5_ib_create_qp *ucmd = params->ucmd;
1926 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1927 struct ib_udata *udata = params->udata;
1928 u32 uidx = params->uidx;
1929 struct mlx5_ib_resources *devr = &dev->devr;
1930 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1931 struct mlx5_core_dev *mdev = dev->mdev;
1932 struct mlx5_ib_cq *send_cq;
1933 struct mlx5_ib_cq *recv_cq;
1934 unsigned long flags;
1935 struct mlx5_ib_qp_base *base;
1941 mutex_init(&qp->mutex);
1942 spin_lock_init(&qp->sq.lock);
1943 spin_lock_init(&qp->rq.lock);
1945 mlx5_st = to_mlx5_st(qp->type);
1949 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1950 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1952 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1953 qp->underlay_qpn = init_attr->source_qpn;
1955 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1956 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
1957 &qp->raw_packet_qp.rq.base :
1960 qp->has_rq = qp_has_rq(init_attr);
1961 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
1963 mlx5_ib_dbg(dev, "err %d\n", err);
1967 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1968 ucmd->rq_wqe_count != qp->rq.wqe_cnt)
1971 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1974 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp,
1975 &inlen, base, ucmd);
1979 if (is_sqp(init_attr->qp_type))
1980 qp->port = init_attr->port_num;
1982 if (MLX5_CAP_GEN(mdev, ece_support))
1983 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
1984 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1986 MLX5_SET(qpc, qpc, st, mlx5_st);
1987 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1988 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
1990 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
1991 MLX5_SET(qpc, qpc, wq_signature, 1);
1993 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1994 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1996 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1997 MLX5_SET(qpc, qpc, cd_master, 1);
1998 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1999 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2000 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
2001 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2002 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
2003 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2004 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2005 (init_attr->qp_type == IB_QPT_RC ||
2006 init_attr->qp_type == IB_QPT_UC)) {
2007 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
2009 MLX5_SET(qpc, qpc, cs_res,
2010 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2011 MLX5_RES_SCAT_DATA32_CQE);
2013 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2014 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
2015 configure_requester_scat_cqe(dev, init_attr, ucmd, qpc);
2017 if (qp->rq.wqe_cnt) {
2018 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2019 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2022 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2024 if (qp->sq.wqe_cnt) {
2025 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2027 MLX5_SET(qpc, qpc, no_sq, 1);
2028 if (init_attr->srq &&
2029 init_attr->srq->srq_type == IB_SRQT_TM)
2030 MLX5_SET(qpc, qpc, offload_type,
2031 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2034 /* Set default resources */
2035 switch (init_attr->qp_type) {
2036 case IB_QPT_XRC_INI:
2037 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2038 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2039 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2042 if (init_attr->srq) {
2043 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2044 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2046 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2047 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2051 if (init_attr->send_cq)
2052 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2054 if (init_attr->recv_cq)
2055 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2057 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2059 /* 0xffffff means we ask to work with cqe version 0 */
2060 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2061 MLX5_SET(qpc, qpc, user_index, uidx);
2063 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2064 init_attr->qp_type != IB_QPT_RAW_PACKET) {
2065 MLX5_SET(qpc, qpc, end_padding_mode,
2066 MLX5_WQ_END_PAD_MODE_ALIGN);
2067 /* Special case to clean flag */
2068 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
2071 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2072 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2073 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
2074 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2075 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2078 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2084 base->container_mibqp = qp;
2085 base->mqp.event = mlx5_ib_qp_event;
2086 if (MLX5_CAP_GEN(mdev, ece_support))
2087 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
2089 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
2090 &send_cq, &recv_cq);
2091 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2092 mlx5_ib_lock_cqs(send_cq, recv_cq);
2093 /* Maintain device to QPs access, needed for further handling via reset
2096 list_add_tail(&qp->qps_list, &dev->qp_list);
2097 /* Maintain CQ to QPs access, needed for further handling via reset flow
2100 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2102 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2103 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2104 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2109 destroy_qp(dev, qp, base, udata);
2113 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2114 struct mlx5_ib_qp *qp,
2115 struct mlx5_create_qp_params *params)
2117 struct ib_qp_init_attr *attr = params->attr;
2118 u32 uidx = params->uidx;
2119 struct mlx5_ib_resources *devr = &dev->devr;
2120 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
2121 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2122 struct mlx5_core_dev *mdev = dev->mdev;
2123 struct mlx5_ib_cq *send_cq;
2124 struct mlx5_ib_cq *recv_cq;
2125 unsigned long flags;
2126 struct mlx5_ib_qp_base *base;
2132 mutex_init(&qp->mutex);
2133 spin_lock_init(&qp->sq.lock);
2134 spin_lock_init(&qp->rq.lock);
2136 mlx5_st = to_mlx5_st(qp->type);
2140 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2141 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2143 base = &qp->trans_qp.base;
2145 qp->has_rq = qp_has_rq(attr);
2146 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2148 mlx5_ib_dbg(dev, "err %d\n", err);
2152 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2156 if (is_sqp(attr->qp_type))
2157 qp->port = attr->port_num;
2159 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2161 MLX5_SET(qpc, qpc, st, mlx5_st);
2162 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2164 if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2165 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2167 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2170 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2171 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2173 if (qp->rq.wqe_cnt) {
2174 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2175 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2178 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2181 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2183 MLX5_SET(qpc, qpc, no_sq, 1);
2186 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2187 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2188 to_msrq(attr->srq)->msrq.srqn);
2190 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2191 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2192 to_msrq(devr->s1)->msrq.srqn);
2196 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2199 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2201 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2203 /* 0xffffff means we ask to work with cqe version 0 */
2204 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2205 MLX5_SET(qpc, qpc, user_index, uidx);
2207 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2208 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2209 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2211 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2216 base->container_mibqp = qp;
2217 base->mqp.event = mlx5_ib_qp_event;
2219 get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2220 &send_cq, &recv_cq);
2221 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2222 mlx5_ib_lock_cqs(send_cq, recv_cq);
2223 /* Maintain device to QPs access, needed for further handling via reset
2226 list_add_tail(&qp->qps_list, &dev->qp_list);
2227 /* Maintain CQ to QPs access, needed for further handling via reset flow
2230 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2232 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2233 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2234 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2239 destroy_qp(dev, qp, base, NULL);
2243 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2244 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2248 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2249 spin_lock(&send_cq->lock);
2250 spin_lock_nested(&recv_cq->lock,
2251 SINGLE_DEPTH_NESTING);
2252 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2253 spin_lock(&send_cq->lock);
2254 __acquire(&recv_cq->lock);
2256 spin_lock(&recv_cq->lock);
2257 spin_lock_nested(&send_cq->lock,
2258 SINGLE_DEPTH_NESTING);
2261 spin_lock(&send_cq->lock);
2262 __acquire(&recv_cq->lock);
2264 } else if (recv_cq) {
2265 spin_lock(&recv_cq->lock);
2266 __acquire(&send_cq->lock);
2268 __acquire(&send_cq->lock);
2269 __acquire(&recv_cq->lock);
2273 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2274 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2278 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2279 spin_unlock(&recv_cq->lock);
2280 spin_unlock(&send_cq->lock);
2281 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2282 __release(&recv_cq->lock);
2283 spin_unlock(&send_cq->lock);
2285 spin_unlock(&send_cq->lock);
2286 spin_unlock(&recv_cq->lock);
2289 __release(&recv_cq->lock);
2290 spin_unlock(&send_cq->lock);
2292 } else if (recv_cq) {
2293 __release(&send_cq->lock);
2294 spin_unlock(&recv_cq->lock);
2296 __release(&recv_cq->lock);
2297 __release(&send_cq->lock);
2301 static void get_cqs(enum ib_qp_type qp_type,
2302 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2303 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2306 case IB_QPT_XRC_TGT:
2310 case MLX5_IB_QPT_REG_UMR:
2311 case IB_QPT_XRC_INI:
2312 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2317 case MLX5_IB_QPT_HW_GSI:
2321 case IB_QPT_RAW_PACKET:
2322 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2323 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2332 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2333 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2334 u8 lag_tx_affinity);
2336 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2337 struct ib_udata *udata)
2339 struct mlx5_ib_cq *send_cq, *recv_cq;
2340 struct mlx5_ib_qp_base *base;
2341 unsigned long flags;
2345 destroy_rss_raw_qp_tir(dev, qp);
2349 base = (qp->type == IB_QPT_RAW_PACKET ||
2350 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2351 &qp->raw_packet_qp.rq.base :
2354 if (qp->state != IB_QPS_RESET) {
2355 if (qp->type != IB_QPT_RAW_PACKET &&
2356 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
2357 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2358 NULL, &base->mqp, NULL);
2360 struct mlx5_modify_raw_qp_param raw_qp_param = {
2361 .operation = MLX5_CMD_OP_2RST_QP
2364 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2367 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2371 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq,
2374 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2375 mlx5_ib_lock_cqs(send_cq, recv_cq);
2376 /* del from lists under both locks above to protect reset flow paths */
2377 list_del(&qp->qps_list);
2379 list_del(&qp->cq_send_list);
2382 list_del(&qp->cq_recv_list);
2385 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2386 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2387 if (send_cq != recv_cq)
2388 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2391 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2392 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2394 if (qp->type == IB_QPT_RAW_PACKET ||
2395 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2396 destroy_raw_packet_qp(dev, qp);
2398 err = mlx5_core_destroy_qp(dev, &base->mqp);
2400 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2404 destroy_qp(dev, qp, base, udata);
2407 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2408 struct mlx5_ib_qp *qp,
2409 struct mlx5_create_qp_params *params)
2411 struct ib_qp_init_attr *attr = params->attr;
2412 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2413 u32 uidx = params->uidx;
2416 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2420 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2421 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2422 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2423 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2424 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2425 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2426 MLX5_SET(dctc, dctc, user_index, uidx);
2427 if (MLX5_CAP_GEN(dev->mdev, ece_support))
2428 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
2430 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
2431 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2434 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2437 qp->state = IB_QPS_RESET;
2442 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2443 enum ib_qp_type *type)
2445 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2448 switch (attr->qp_type) {
2449 case IB_QPT_XRC_TGT:
2450 case IB_QPT_XRC_INI:
2451 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2457 case MLX5_IB_QPT_HW_GSI:
2460 if (dev->profile == &raw_eth_profile)
2462 case IB_QPT_RAW_PACKET:
2464 case MLX5_IB_QPT_REG_UMR:
2470 *type = attr->qp_type;
2474 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2478 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2479 struct ib_qp_init_attr *attr,
2480 struct ib_udata *udata)
2482 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2483 udata, struct mlx5_ib_ucontext, ibucontext);
2486 /* Kernel create_qp callers */
2487 if (attr->rwq_ind_tbl)
2490 switch (attr->qp_type) {
2491 case IB_QPT_RAW_PACKET:
2499 /* Userspace create_qp callers */
2500 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2502 "Raw Packet QP is only supported for CQE version > 0\n");
2506 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2508 "Wrong QP type %d for the RWQ indirect table\n",
2513 switch (attr->qp_type) {
2515 case MLX5_IB_QPT_HW_GSI:
2516 case MLX5_IB_QPT_REG_UMR:
2518 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2526 * We don't need to see this warning, it means that kernel code
2527 * missing ib_pd. Placed here to catch developer's mistakes.
2529 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2530 "There is a missing PD pointer assignment\n");
2534 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2535 bool cond, struct mlx5_ib_qp *qp)
2537 if (!(*flags & flag))
2541 qp->flags_en |= flag;
2546 if (flag == MLX5_QP_FLAG_SCATTER_CQE) {
2548 * We don't return error if this flag was provided,
2549 * and mlx5 doesn't have right capability.
2551 *flags &= ~MLX5_QP_FLAG_SCATTER_CQE;
2554 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2557 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2558 void *ucmd, struct ib_qp_init_attr *attr)
2560 struct mlx5_core_dev *mdev = dev->mdev;
2564 if (attr->rwq_ind_tbl)
2565 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2567 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
2569 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2570 case MLX5_QP_FLAG_TYPE_DCI:
2571 qp->type = MLX5_IB_QPT_DCI;
2573 case MLX5_QP_FLAG_TYPE_DCT:
2574 qp->type = MLX5_IB_QPT_DCT;
2577 if (qp->type != IB_QPT_DRIVER)
2580 * It is IB_QPT_DRIVER and or no subtype or
2581 * wrong subtype were provided.
2586 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2587 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2589 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2590 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2591 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2593 if (qp->type == IB_QPT_RAW_PACKET) {
2594 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2595 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2596 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2597 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2599 process_vendor_flag(dev, &flags,
2600 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2602 process_vendor_flag(dev, &flags,
2603 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2607 if (qp->type == IB_QPT_RC)
2608 process_vendor_flag(dev, &flags,
2609 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2610 MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2612 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2613 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2615 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2616 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2617 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC);
2618 if (attr->rwq_ind_tbl && cond) {
2619 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n",
2625 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2627 return (flags) ? -EINVAL : 0;
2630 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2631 bool cond, struct mlx5_ib_qp *qp)
2633 if (!(*flags & flag))
2642 if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2644 * Special case, if condition didn't meet, it won't be error,
2645 * just different in-kernel flow.
2647 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2650 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2653 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2654 struct ib_qp_init_attr *attr)
2656 enum ib_qp_type qp_type = qp->type;
2657 struct mlx5_core_dev *mdev = dev->mdev;
2658 int create_flags = attr->create_flags;
2661 if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile)
2662 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST)
2665 if (qp_type == MLX5_IB_QPT_DCT)
2666 return (create_flags) ? -EINVAL : 0;
2668 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2669 return (create_flags) ? -EINVAL : 0;
2671 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP,
2672 mlx5_get_flow_namespace(dev->mdev,
2673 MLX5_FLOW_NAMESPACE_BYPASS),
2675 process_create_flag(dev, &create_flags,
2676 IB_QP_CREATE_INTEGRITY_EN,
2677 MLX5_CAP_GEN(mdev, sho), qp);
2678 process_create_flag(dev, &create_flags,
2679 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2680 MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2681 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2682 MLX5_CAP_GEN(mdev, cd), qp);
2683 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2684 MLX5_CAP_GEN(mdev, cd), qp);
2685 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2686 MLX5_CAP_GEN(mdev, cd), qp);
2688 if (qp_type == IB_QPT_UD) {
2689 process_create_flag(dev, &create_flags,
2690 IB_QP_CREATE_IPOIB_UD_LSO,
2691 MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2693 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2694 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2698 if (qp_type == IB_QPT_RAW_PACKET) {
2699 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2700 MLX5_CAP_ETH(mdev, scatter_fcs);
2701 process_create_flag(dev, &create_flags,
2702 IB_QP_CREATE_SCATTER_FCS, cond, qp);
2704 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2705 MLX5_CAP_ETH(mdev, vlan_cap);
2706 process_create_flag(dev, &create_flags,
2707 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2710 process_create_flag(dev, &create_flags,
2711 IB_QP_CREATE_PCI_WRITE_END_PADDING,
2712 MLX5_CAP_GEN(mdev, end_pad), qp);
2714 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2715 qp_type != MLX5_IB_QPT_REG_UMR, qp);
2716 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2720 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2723 return (create_flags) ? -EINVAL : 0;
2726 static int process_udata_size(struct mlx5_ib_dev *dev,
2727 struct mlx5_create_qp_params *params)
2729 size_t ucmd = sizeof(struct mlx5_ib_create_qp);
2730 struct ib_udata *udata = params->udata;
2731 size_t outlen = udata->outlen;
2732 size_t inlen = udata->inlen;
2734 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp));
2735 params->ucmd_size = ucmd;
2736 if (!params->is_rss_raw) {
2737 /* User has old rdma-core, which doesn't support ECE */
2739 offsetof(struct mlx5_ib_create_qp, ece_options);
2742 * We will check in check_ucmd_data() that user
2743 * cleared everything after inlen.
2745 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd);
2750 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
2753 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index))
2756 ucmd = sizeof(struct mlx5_ib_create_qp_rss);
2757 params->ucmd_size = ucmd;
2758 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
2761 params->inlen = min(ucmd, inlen);
2764 mlx5_ib_dbg(dev, "udata is too small\n");
2766 return (params->inlen) ? 0 : -EINVAL;
2769 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2770 struct mlx5_ib_qp *qp,
2771 struct mlx5_create_qp_params *params)
2775 if (params->is_rss_raw) {
2776 err = create_rss_raw_qp_tir(dev, pd, qp, params);
2780 if (qp->type == MLX5_IB_QPT_DCT) {
2781 err = create_dct(dev, pd, qp, params);
2785 if (qp->type == IB_QPT_XRC_TGT) {
2786 err = create_xrc_tgt_qp(dev, qp, params);
2791 err = create_user_qp(dev, pd, qp, params);
2793 err = create_kernel_qp(dev, pd, qp, params);
2797 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type);
2801 if (is_qp0(qp->type))
2802 qp->ibqp.qp_num = 0;
2803 else if (is_qp1(qp->type))
2804 qp->ibqp.qp_num = 1;
2806 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2809 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n",
2810 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2811 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn :
2813 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn :
2815 params->resp.ece_options);
2820 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2821 struct ib_qp_init_attr *attr)
2826 case MLX5_IB_QPT_DCT:
2827 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2829 case MLX5_IB_QPT_DCI:
2830 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2834 case IB_QPT_RAW_PACKET:
2835 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2842 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2847 static int get_qp_uidx(struct mlx5_ib_qp *qp,
2848 struct mlx5_create_qp_params *params)
2850 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2851 struct ib_udata *udata = params->udata;
2852 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2853 udata, struct mlx5_ib_ucontext, ibucontext);
2855 if (params->is_rss_raw)
2858 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx);
2861 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2863 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2865 if (mqp->state == IB_QPS_RTR) {
2868 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2870 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2880 static int check_ucmd_data(struct mlx5_ib_dev *dev,
2881 struct mlx5_create_qp_params *params)
2883 struct ib_udata *udata = params->udata;
2887 if (params->is_rss_raw)
2889 * These QPs don't have "reserved" field in their
2890 * create_qp input struct, so their data is always valid.
2892 last = sizeof(struct mlx5_ib_create_qp_rss);
2894 last = offsetof(struct mlx5_ib_create_qp, reserved);
2896 if (udata->inlen <= last)
2900 * User provides different create_qp structures based on the
2901 * flow and we need to know if he cleared memory after our
2902 * struct create_qp ends.
2904 size = udata->inlen - last;
2905 ret = ib_is_udata_cleared(params->udata, last, size);
2909 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n",
2910 udata->inlen, params->ucmd_size, last, size);
2911 return ret ? 0 : -EINVAL;
2914 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr,
2915 struct ib_udata *udata)
2917 struct mlx5_create_qp_params params = {};
2918 struct mlx5_ib_dev *dev;
2919 struct mlx5_ib_qp *qp;
2920 enum ib_qp_type type;
2923 dev = pd ? to_mdev(pd->device) :
2924 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device);
2926 err = check_qp_type(dev, attr, &type);
2928 return ERR_PTR(err);
2930 err = check_valid_flow(dev, pd, attr, udata);
2932 return ERR_PTR(err);
2934 if (attr->qp_type == IB_QPT_GSI)
2935 return mlx5_ib_gsi_create_qp(pd, attr);
2937 params.udata = udata;
2938 params.uidx = MLX5_IB_DEFAULT_UIDX;
2940 params.is_rss_raw = !!attr->rwq_ind_tbl;
2943 err = process_udata_size(dev, ¶ms);
2945 return ERR_PTR(err);
2947 err = check_ucmd_data(dev, ¶ms);
2949 return ERR_PTR(err);
2951 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL);
2953 return ERR_PTR(-ENOMEM);
2955 err = ib_copy_from_udata(params.ucmd, udata, params.inlen);
2960 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2968 err = process_vendor_flags(dev, qp, params.ucmd, attr);
2972 err = get_qp_uidx(qp, ¶ms);
2976 err = process_create_flags(dev, qp, attr);
2980 err = check_qp_attr(dev, qp, attr);
2984 err = create_qp(dev, pd, qp, ¶ms);
2993 * It is safe to copy response for all user create QP flows,
2994 * including MLX5_IB_QPT_DCT, which doesn't need it.
2995 * In that case, resp will be filled with zeros.
2997 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen);
3004 if (qp->type == MLX5_IB_QPT_DCT) {
3005 mlx5_ib_destroy_dct(qp);
3008 * These lines below are temp solution till QP allocation
3009 * will be moved to be under IB/core responsiblity.
3011 qp->ibqp.send_cq = attr->send_cq;
3012 qp->ibqp.recv_cq = attr->recv_cq;
3014 destroy_qp_common(dev, qp, udata);
3022 return ERR_PTR(err);
3025 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
3027 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3028 struct mlx5_ib_qp *mqp = to_mqp(qp);
3030 if (unlikely(qp->qp_type == IB_QPT_GSI))
3031 return mlx5_ib_gsi_destroy_qp(qp);
3033 if (mqp->type == MLX5_IB_QPT_DCT)
3034 return mlx5_ib_destroy_dct(mqp);
3036 destroy_qp_common(dev, mqp, udata);
3043 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
3044 const struct ib_qp_attr *attr, int attr_mask,
3047 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
3051 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3052 dest_rd_atomic = attr->max_dest_rd_atomic;
3054 dest_rd_atomic = qp->trans_qp.resp_depth;
3056 if (attr_mask & IB_QP_ACCESS_FLAGS)
3057 access_flags = attr->qp_access_flags;
3059 access_flags = qp->trans_qp.atomic_rd_en;
3061 if (!dest_rd_atomic)
3062 access_flags &= IB_ACCESS_REMOTE_WRITE;
3064 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
3066 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3069 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3070 if (atomic_mode < 0)
3073 MLX5_SET(qpc, qpc, rae, 1);
3074 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
3077 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3082 MLX5_PATH_FLAG_FL = 1 << 0,
3083 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
3084 MLX5_PATH_FLAG_COUNTER = 1 << 2,
3087 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3089 if (rate == IB_RATE_PORT_CURRENT)
3092 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
3095 while (rate != IB_RATE_PORT_CURRENT &&
3096 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
3097 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
3100 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
3103 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
3104 struct mlx5_ib_sq *sq, u8 sl,
3112 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3113 in = kvzalloc(inlen, GFP_KERNEL);
3117 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
3118 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3120 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3121 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3123 err = mlx5_core_modify_tis(dev, sq->tisn, in);
3130 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
3131 struct mlx5_ib_sq *sq, u8 tx_affinity,
3139 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3140 in = kvzalloc(inlen, GFP_KERNEL);
3144 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
3145 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3147 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3148 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3150 err = mlx5_core_modify_tis(dev, sq->tisn, in);
3157 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
3161 u32 fl = ah->grh.flow_label;
3164 fl = rdma_calc_flow_label(lqpn, rqpn);
3166 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
3169 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3170 const struct rdma_ah_attr *ah, void *path, u8 port,
3171 int attr_mask, u32 path_flags,
3172 const struct ib_qp_attr *attr, bool alt)
3174 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
3176 enum ib_gid_type gid_type;
3177 u8 ah_flags = rdma_ah_get_ah_flags(ah);
3178 u8 sl = rdma_ah_get_sl(ah);
3180 if (attr_mask & IB_QP_PKEY_INDEX)
3181 MLX5_SET(ads, path, pkey_index,
3182 alt ? attr->alt_pkey_index : attr->pkey_index);
3184 if (ah_flags & IB_AH_GRH) {
3185 if (grh->sgid_index >=
3186 dev->mdev->port_caps[port - 1].gid_table_len) {
3187 pr_err("sgid_index (%u) too large. max is %d\n",
3189 dev->mdev->port_caps[port - 1].gid_table_len);
3194 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
3195 if (!(ah_flags & IB_AH_GRH))
3198 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
3200 if ((qp->ibqp.qp_type == IB_QPT_RC ||
3201 qp->ibqp.qp_type == IB_QPT_UC ||
3202 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3203 qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
3204 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) &&
3205 (attr_mask & IB_QP_DEST_QPN))
3206 mlx5_set_path_udp_sport(path, ah,
3209 MLX5_SET(ads, path, eth_prio, sl & 0x7);
3210 gid_type = ah->grh.sgid_attr->gid_type;
3211 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3212 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
3214 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
3215 MLX5_SET(ads, path, free_ar,
3216 !!(path_flags & MLX5_PATH_FLAG_FREE_AR));
3217 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
3218 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
3219 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
3220 MLX5_SET(ads, path, sl, sl);
3223 if (ah_flags & IB_AH_GRH) {
3224 MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
3225 MLX5_SET(ads, path, hop_limit, grh->hop_limit);
3226 MLX5_SET(ads, path, tclass, grh->traffic_class);
3227 MLX5_SET(ads, path, flow_label, grh->flow_label);
3228 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
3229 sizeof(grh->dgid.raw));
3232 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3235 MLX5_SET(ads, path, stat_rate, err);
3236 MLX5_SET(ads, path, vhca_port_num, port);
3238 if (attr_mask & IB_QP_TIMEOUT)
3239 MLX5_SET(ads, path, ack_timeout,
3240 alt ? attr->alt_timeout : attr->timeout);
3242 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3243 return modify_raw_packet_eth_prio(dev->mdev,
3244 &qp->raw_packet_qp.sq,
3245 sl & 0xf, qp->ibqp.pd);
3250 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3251 [MLX5_QP_STATE_INIT] = {
3252 [MLX5_QP_STATE_INIT] = {
3253 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3254 MLX5_QP_OPTPAR_RAE |
3255 MLX5_QP_OPTPAR_RWE |
3256 MLX5_QP_OPTPAR_PKEY_INDEX |
3257 MLX5_QP_OPTPAR_PRI_PORT |
3258 MLX5_QP_OPTPAR_LAG_TX_AFF,
3259 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3260 MLX5_QP_OPTPAR_PKEY_INDEX |
3261 MLX5_QP_OPTPAR_PRI_PORT |
3262 MLX5_QP_OPTPAR_LAG_TX_AFF,
3263 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3264 MLX5_QP_OPTPAR_Q_KEY |
3265 MLX5_QP_OPTPAR_PRI_PORT,
3266 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3267 MLX5_QP_OPTPAR_RAE |
3268 MLX5_QP_OPTPAR_RWE |
3269 MLX5_QP_OPTPAR_PKEY_INDEX |
3270 MLX5_QP_OPTPAR_PRI_PORT |
3271 MLX5_QP_OPTPAR_LAG_TX_AFF,
3273 [MLX5_QP_STATE_RTR] = {
3274 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3275 MLX5_QP_OPTPAR_RRE |
3276 MLX5_QP_OPTPAR_RAE |
3277 MLX5_QP_OPTPAR_RWE |
3278 MLX5_QP_OPTPAR_PKEY_INDEX |
3279 MLX5_QP_OPTPAR_LAG_TX_AFF,
3280 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3281 MLX5_QP_OPTPAR_RWE |
3282 MLX5_QP_OPTPAR_PKEY_INDEX |
3283 MLX5_QP_OPTPAR_LAG_TX_AFF,
3284 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3285 MLX5_QP_OPTPAR_Q_KEY,
3286 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
3287 MLX5_QP_OPTPAR_Q_KEY,
3288 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3289 MLX5_QP_OPTPAR_RRE |
3290 MLX5_QP_OPTPAR_RAE |
3291 MLX5_QP_OPTPAR_RWE |
3292 MLX5_QP_OPTPAR_PKEY_INDEX |
3293 MLX5_QP_OPTPAR_LAG_TX_AFF,
3296 [MLX5_QP_STATE_RTR] = {
3297 [MLX5_QP_STATE_RTS] = {
3298 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3299 MLX5_QP_OPTPAR_RRE |
3300 MLX5_QP_OPTPAR_RAE |
3301 MLX5_QP_OPTPAR_RWE |
3302 MLX5_QP_OPTPAR_PM_STATE |
3303 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3304 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3305 MLX5_QP_OPTPAR_RWE |
3306 MLX5_QP_OPTPAR_PM_STATE,
3307 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3308 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3309 MLX5_QP_OPTPAR_RRE |
3310 MLX5_QP_OPTPAR_RAE |
3311 MLX5_QP_OPTPAR_RWE |
3312 MLX5_QP_OPTPAR_PM_STATE |
3313 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3316 [MLX5_QP_STATE_RTS] = {
3317 [MLX5_QP_STATE_RTS] = {
3318 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3319 MLX5_QP_OPTPAR_RAE |
3320 MLX5_QP_OPTPAR_RWE |
3321 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3322 MLX5_QP_OPTPAR_PM_STATE |
3323 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3324 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3325 MLX5_QP_OPTPAR_PM_STATE |
3326 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3327 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
3328 MLX5_QP_OPTPAR_SRQN |
3329 MLX5_QP_OPTPAR_CQN_RCV,
3330 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3331 MLX5_QP_OPTPAR_RAE |
3332 MLX5_QP_OPTPAR_RWE |
3333 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3334 MLX5_QP_OPTPAR_PM_STATE |
3335 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3338 [MLX5_QP_STATE_SQER] = {
3339 [MLX5_QP_STATE_RTS] = {
3340 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3341 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3342 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
3343 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3344 MLX5_QP_OPTPAR_RWE |
3345 MLX5_QP_OPTPAR_RAE |
3347 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3348 MLX5_QP_OPTPAR_RWE |
3349 MLX5_QP_OPTPAR_RAE |
3355 static int ib_nr_to_mlx5_nr(int ib_mask)
3360 case IB_QP_CUR_STATE:
3362 case IB_QP_EN_SQD_ASYNC_NOTIFY:
3364 case IB_QP_ACCESS_FLAGS:
3365 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3367 case IB_QP_PKEY_INDEX:
3368 return MLX5_QP_OPTPAR_PKEY_INDEX;
3370 return MLX5_QP_OPTPAR_PRI_PORT;
3372 return MLX5_QP_OPTPAR_Q_KEY;
3374 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3375 MLX5_QP_OPTPAR_PRI_PORT;
3376 case IB_QP_PATH_MTU:
3379 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3380 case IB_QP_RETRY_CNT:
3381 return MLX5_QP_OPTPAR_RETRY_COUNT;
3382 case IB_QP_RNR_RETRY:
3383 return MLX5_QP_OPTPAR_RNR_RETRY;
3386 case IB_QP_MAX_QP_RD_ATOMIC:
3387 return MLX5_QP_OPTPAR_SRA_MAX;
3388 case IB_QP_ALT_PATH:
3389 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3390 case IB_QP_MIN_RNR_TIMER:
3391 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3394 case IB_QP_MAX_DEST_RD_ATOMIC:
3395 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3396 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3397 case IB_QP_PATH_MIG_STATE:
3398 return MLX5_QP_OPTPAR_PM_STATE;
3401 case IB_QP_DEST_QPN:
3407 static int ib_mask_to_mlx5_opt(int ib_mask)
3412 for (i = 0; i < 8 * sizeof(int); i++) {
3413 if ((1 << i) & ib_mask)
3414 result |= ib_nr_to_mlx5_nr(1 << i);
3420 static int modify_raw_packet_qp_rq(
3421 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3422 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3429 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3430 in = kvzalloc(inlen, GFP_KERNEL);
3434 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3435 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3437 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3438 MLX5_SET(rqc, rqc, state, new_state);
3440 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3441 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3442 MLX5_SET64(modify_rq_in, in, modify_bitmask,
3443 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3444 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3448 "RAW PACKET QP counters are not supported on current FW\n");
3451 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3455 rq->state = new_state;
3462 static int modify_raw_packet_qp_sq(
3463 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3464 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3466 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3467 struct mlx5_rate_limit old_rl = ibqp->rl;
3468 struct mlx5_rate_limit new_rl = old_rl;
3469 bool new_rate_added = false;
3476 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3477 in = kvzalloc(inlen, GFP_KERNEL);
3481 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3482 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3484 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3485 MLX5_SET(sqc, sqc, state, new_state);
3487 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3488 if (new_state != MLX5_SQC_STATE_RDY)
3489 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3492 new_rl = raw_qp_param->rl;
3495 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3497 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3499 pr_err("Failed configuring rate limit(err %d): \
3500 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3501 err, new_rl.rate, new_rl.max_burst_sz,
3502 new_rl.typical_pkt_sz);
3506 new_rate_added = true;
3509 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3510 /* index 0 means no limit */
3511 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3514 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3516 /* Remove new rate from table if failed */
3518 mlx5_rl_remove_rate(dev, &new_rl);
3522 /* Only remove the old rate after new rate was set */
3523 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3524 (new_state != MLX5_SQC_STATE_RDY)) {
3525 mlx5_rl_remove_rate(dev, &old_rl);
3526 if (new_state != MLX5_SQC_STATE_RDY)
3527 memset(&new_rl, 0, sizeof(new_rl));
3531 sq->state = new_state;
3538 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3539 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3542 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3543 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3544 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3545 int modify_rq = !!qp->rq.wqe_cnt;
3546 int modify_sq = !!qp->sq.wqe_cnt;
3551 switch (raw_qp_param->operation) {
3552 case MLX5_CMD_OP_RST2INIT_QP:
3553 rq_state = MLX5_RQC_STATE_RDY;
3554 sq_state = MLX5_SQC_STATE_RDY;
3556 case MLX5_CMD_OP_2ERR_QP:
3557 rq_state = MLX5_RQC_STATE_ERR;
3558 sq_state = MLX5_SQC_STATE_ERR;
3560 case MLX5_CMD_OP_2RST_QP:
3561 rq_state = MLX5_RQC_STATE_RST;
3562 sq_state = MLX5_SQC_STATE_RST;
3564 case MLX5_CMD_OP_RTR2RTS_QP:
3565 case MLX5_CMD_OP_RTS2RTS_QP:
3566 if (raw_qp_param->set_mask ==
3567 MLX5_RAW_QP_RATE_LIMIT) {
3569 sq_state = sq->state;
3571 return raw_qp_param->set_mask ? -EINVAL : 0;
3574 case MLX5_CMD_OP_INIT2INIT_QP:
3575 case MLX5_CMD_OP_INIT2RTR_QP:
3576 if (raw_qp_param->set_mask)
3586 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3593 struct mlx5_flow_handle *flow_rule;
3596 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3603 flow_rule = create_flow_rule_vport_sq(dev, sq,
3604 raw_qp_param->port);
3605 if (IS_ERR(flow_rule))
3606 return PTR_ERR(flow_rule);
3608 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3609 raw_qp_param, qp->ibqp.pd);
3612 mlx5_del_flow_rules(flow_rule);
3617 destroy_flow_rule_vport_sq(sq);
3618 sq->flow_rule = flow_rule;
3627 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev,
3628 struct ib_udata *udata)
3630 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3631 udata, struct mlx5_ib_ucontext, ibucontext);
3632 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3633 atomic_t *tx_port_affinity;
3636 tx_port_affinity = &ucontext->tx_port_affinity;
3638 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity;
3640 return (unsigned int)atomic_add_return(1, tx_port_affinity) %
3644 static bool qp_supports_affinity(struct ib_qp *qp)
3646 if ((qp->qp_type == IB_QPT_RC) ||
3647 (qp->qp_type == IB_QPT_UD) ||
3648 (qp->qp_type == IB_QPT_UC) ||
3649 (qp->qp_type == IB_QPT_RAW_PACKET) ||
3650 (qp->qp_type == IB_QPT_XRC_INI) ||
3651 (qp->qp_type == IB_QPT_XRC_TGT))
3656 static unsigned int get_tx_affinity(struct ib_qp *qp,
3657 const struct ib_qp_attr *attr,
3658 int attr_mask, u8 init,
3659 struct ib_udata *udata)
3661 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3662 udata, struct mlx5_ib_ucontext, ibucontext);
3663 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3664 struct mlx5_ib_qp *mqp = to_mqp(qp);
3665 struct mlx5_ib_qp_base *qp_base;
3666 unsigned int tx_affinity;
3668 if (!(mlx5_ib_lag_should_assign_affinity(dev) &&
3669 qp_supports_affinity(qp)))
3672 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3673 tx_affinity = mqp->gsi_lag_port;
3675 tx_affinity = get_tx_affinity_rr(dev, udata);
3676 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave)
3678 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3682 qp_base = &mqp->trans_qp.base;
3684 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3685 tx_affinity, qp_base->mqp.qpn, ucontext);
3687 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3688 tx_affinity, qp_base->mqp.qpn);
3692 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3693 struct rdma_counter *counter)
3695 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3696 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {};
3697 struct mlx5_ib_qp *mqp = to_mqp(qp);
3698 struct mlx5_ib_qp_base *base;
3703 set_id = counter->id;
3705 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3707 base = &mqp->trans_qp.base;
3708 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
3709 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);
3710 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid);
3711 MLX5_SET(rts2rts_qp_in, in, opt_param_mask,
3712 MLX5_QP_OPTPAR_COUNTER_SET_ID);
3714 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc);
3715 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3716 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
3719 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3720 const struct ib_qp_attr *attr, int attr_mask,
3721 enum ib_qp_state cur_state,
3722 enum ib_qp_state new_state,
3723 const struct mlx5_ib_modify_qp *ucmd,
3724 struct mlx5_ib_modify_qp_resp *resp,
3725 struct ib_udata *udata)
3727 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3728 [MLX5_QP_STATE_RST] = {
3729 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3730 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3731 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3733 [MLX5_QP_STATE_INIT] = {
3734 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3735 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3736 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3737 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3739 [MLX5_QP_STATE_RTR] = {
3740 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3741 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3742 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3744 [MLX5_QP_STATE_RTS] = {
3745 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3746 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3747 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3749 [MLX5_QP_STATE_SQD] = {
3750 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3751 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3753 [MLX5_QP_STATE_SQER] = {
3754 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3755 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3756 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3758 [MLX5_QP_STATE_ERR] = {
3759 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3760 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3764 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3765 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3766 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3767 struct mlx5_ib_cq *send_cq, *recv_cq;
3768 struct mlx5_ib_pd *pd;
3769 enum mlx5_qp_state mlx5_cur, mlx5_new;
3770 void *qpc, *pri_path, *alt_path;
3771 enum mlx5_qp_optpar optpar = 0;
3778 mlx5_st = to_mlx5_st(qp->type);
3782 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
3786 pd = to_mpd(qp->ibqp.pd);
3787 MLX5_SET(qpc, qpc, st, mlx5_st);
3789 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3790 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3792 switch (attr->path_mig_state) {
3793 case IB_MIG_MIGRATED:
3794 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3797 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
3800 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
3805 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
3806 cur_state == IB_QPS_RESET &&
3807 new_state == IB_QPS_INIT, udata);
3809 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
3810 if (tx_affinity && new_state == IB_QPS_RTR &&
3811 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3812 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
3814 if (is_sqp(ibqp->qp_type)) {
3815 MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
3816 MLX5_SET(qpc, qpc, log_msg_max, 8);
3817 } else if ((ibqp->qp_type == IB_QPT_UD &&
3818 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
3819 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3820 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
3821 MLX5_SET(qpc, qpc, log_msg_max, 12);
3822 } else if (attr_mask & IB_QP_PATH_MTU) {
3823 if (attr->path_mtu < IB_MTU_256 ||
3824 attr->path_mtu > IB_MTU_4096) {
3825 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3829 MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
3830 MLX5_SET(qpc, qpc, log_msg_max,
3831 MLX5_CAP_GEN(dev->mdev, log_max_msg));
3834 if (attr_mask & IB_QP_DEST_QPN)
3835 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
3837 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
3838 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
3840 if (attr_mask & IB_QP_PKEY_INDEX)
3841 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
3843 /* todo implement counter_index functionality */
3845 if (is_sqp(ibqp->qp_type))
3846 MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
3848 if (attr_mask & IB_QP_PORT)
3849 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
3851 if (attr_mask & IB_QP_AV) {
3852 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
3853 attr_mask & IB_QP_PORT ? attr->port_num :
3855 attr_mask, 0, attr, false);
3860 if (attr_mask & IB_QP_TIMEOUT)
3861 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
3863 if (attr_mask & IB_QP_ALT_PATH) {
3864 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
3866 attr_mask | IB_QP_PKEY_INDEX |
3873 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3874 &send_cq, &recv_cq);
3876 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3878 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
3880 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
3882 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
3884 if (attr_mask & IB_QP_RNR_RETRY)
3885 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
3887 if (attr_mask & IB_QP_RETRY_CNT)
3888 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
3890 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
3891 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
3893 if (attr_mask & IB_QP_SQ_PSN)
3894 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
3896 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
3897 MLX5_SET(qpc, qpc, log_rra_max,
3898 ilog2(attr->max_dest_rd_atomic));
3900 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3901 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
3906 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3907 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
3909 if (attr_mask & IB_QP_RQ_PSN)
3910 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
3912 if (attr_mask & IB_QP_QKEY)
3913 MLX5_SET(qpc, qpc, q_key, attr->qkey);
3915 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3916 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
3918 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3919 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3922 /* Underlay port should be used - index 0 function per port */
3923 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
3927 set_id = ibqp->counter->id;
3929 set_id = mlx5_ib_get_counters_id(dev, port_num);
3930 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3933 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3934 MLX5_SET(qpc, qpc, rlky, 1);
3936 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3937 MLX5_SET(qpc, qpc, deth_sqpn, 1);
3939 mlx5_cur = to_mlx5_state(cur_state);
3940 mlx5_new = to_mlx5_state(new_state);
3942 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3943 !optab[mlx5_cur][mlx5_new]) {
3948 op = optab[mlx5_cur][mlx5_new];
3949 optpar |= ib_mask_to_mlx5_opt(attr_mask);
3950 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3952 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3953 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
3954 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3956 raw_qp_param.operation = op;
3957 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3958 raw_qp_param.rq_q_ctr_id = set_id;
3959 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3962 if (attr_mask & IB_QP_PORT)
3963 raw_qp_param.port = attr->port_num;
3965 if (attr_mask & IB_QP_RATE_LIMIT) {
3966 raw_qp_param.rl.rate = attr->rate_limit;
3968 if (ucmd->burst_info.max_burst_sz) {
3969 if (attr->rate_limit &&
3970 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3971 raw_qp_param.rl.max_burst_sz =
3972 ucmd->burst_info.max_burst_sz;
3979 if (ucmd->burst_info.typical_pkt_sz) {
3980 if (attr->rate_limit &&
3981 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3982 raw_qp_param.rl.typical_pkt_sz =
3983 ucmd->burst_info.typical_pkt_sz;
3990 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3993 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3996 /* For the kernel flows, the resp will stay zero */
3998 MLX5_CAP_GEN(dev->mdev, ece_support) ?
3999 ucmd->ece_options : 0;
4000 resp->response_length = sizeof(*resp);
4002 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp,
4003 &resp->ece_options);
4009 qp->state = new_state;
4011 if (attr_mask & IB_QP_ACCESS_FLAGS)
4012 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
4013 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4014 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
4015 if (attr_mask & IB_QP_PORT)
4016 qp->port = attr->port_num;
4017 if (attr_mask & IB_QP_ALT_PATH)
4018 qp->trans_qp.alt_port = attr->alt_port_num;
4021 * If we moved a kernel QP to RESET, clean up all old CQ
4022 * entries and reinitialize the QP.
4024 if (new_state == IB_QPS_RESET &&
4025 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
4026 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
4027 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
4028 if (send_cq != recv_cq)
4029 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
4035 qp->sq.cur_post = 0;
4037 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
4038 qp->sq.last_poll = 0;
4039 qp->db.db[MLX5_RCV_DBR] = 0;
4040 qp->db.db[MLX5_SND_DBR] = 0;
4043 if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
4044 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
4046 qp->counter_pending = 0;
4054 static inline bool is_valid_mask(int mask, int req, int opt)
4056 if ((mask & req) != req)
4059 if (mask & ~(req | opt))
4065 /* check valid transition for driver QP types
4066 * for now the only QP type that this function supports is DCI
4068 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
4069 enum ib_qp_attr_mask attr_mask)
4071 int req = IB_QP_STATE;
4074 if (new_state == IB_QPS_RESET) {
4075 return is_valid_mask(attr_mask, req, opt);
4076 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4077 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
4078 return is_valid_mask(attr_mask, req, opt);
4079 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4080 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
4081 return is_valid_mask(attr_mask, req, opt);
4082 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4083 req |= IB_QP_PATH_MTU;
4084 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
4085 return is_valid_mask(attr_mask, req, opt);
4086 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4087 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
4088 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
4089 opt = IB_QP_MIN_RNR_TIMER;
4090 return is_valid_mask(attr_mask, req, opt);
4091 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
4092 opt = IB_QP_MIN_RNR_TIMER;
4093 return is_valid_mask(attr_mask, req, opt);
4094 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
4095 return is_valid_mask(attr_mask, req, opt);
4100 /* mlx5_ib_modify_dct: modify a DCT QP
4101 * valid transitions are:
4102 * RESET to INIT: must set access_flags, pkey_index and port
4103 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
4104 * mtu, gid_index and hop_limit
4105 * Other transitions and attributes are illegal
4107 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4108 int attr_mask, struct mlx5_ib_modify_qp *ucmd,
4109 struct ib_udata *udata)
4111 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4112 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4113 enum ib_qp_state cur_state, new_state;
4115 int required = IB_QP_STATE;
4118 if (!(attr_mask & IB_QP_STATE))
4121 cur_state = qp->state;
4122 new_state = attr->qp_state;
4124 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
4125 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options)
4127 * DCT doesn't initialize QP till modify command is executed,
4128 * so we need to overwrite previously set ECE field if user
4129 * provided any value except zero, which means not set/not
4132 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
4134 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4137 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4138 if (!is_valid_mask(attr_mask, required, 0))
4141 if (attr->port_num == 0 ||
4142 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
4143 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4144 attr->port_num, dev->num_ports);
4147 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4148 MLX5_SET(dctc, dctc, rre, 1);
4149 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4150 MLX5_SET(dctc, dctc, rwe, 1);
4151 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
4154 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4155 if (atomic_mode < 0)
4158 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
4159 MLX5_SET(dctc, dctc, rae, 1);
4161 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
4162 MLX5_SET(dctc, dctc, port, attr->port_num);
4164 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4165 MLX5_SET(dctc, dctc, counter_set_id, set_id);
4166 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4167 struct mlx5_ib_modify_qp_resp resp = {};
4168 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {};
4169 u32 min_resp_len = offsetofend(typeof(resp), dctn);
4171 if (udata->outlen < min_resp_len)
4174 * If we don't have enough space for the ECE options,
4175 * simply indicate it with resp.response_length.
4177 resp.response_length = (udata->outlen < sizeof(resp)) ?
4181 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4182 if (!is_valid_mask(attr_mask, required, 0))
4184 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4185 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4186 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4187 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4188 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4189 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4191 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
4192 MLX5_ST_SZ_BYTES(create_dct_in), out,
4196 resp.dctn = qp->dct.mdct.mqp.qpn;
4197 if (MLX5_CAP_GEN(dev->mdev, ece_support))
4198 resp.ece_options = MLX5_GET(create_dct_out, out, ece);
4199 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4201 mlx5_core_destroy_dct(dev, &qp->dct.mdct);
4205 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4209 qp->state = IB_QPS_ERR;
4211 qp->state = new_state;
4215 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4216 int attr_mask, struct ib_udata *udata)
4218 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4219 struct mlx5_ib_modify_qp_resp resp = {};
4220 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4221 struct mlx5_ib_modify_qp ucmd = {};
4222 enum ib_qp_type qp_type;
4223 enum ib_qp_state cur_state, new_state;
4227 if (ibqp->rwq_ind_tbl)
4230 if (udata && udata->inlen) {
4231 if (udata->inlen < offsetofend(typeof(ucmd), ece_options))
4234 if (udata->inlen > sizeof(ucmd) &&
4235 !ib_is_udata_cleared(udata, sizeof(ucmd),
4236 udata->inlen - sizeof(ucmd)))
4239 if (ib_copy_from_udata(&ucmd, udata,
4240 min(udata->inlen, sizeof(ucmd))))
4243 if (ucmd.comp_mask ||
4244 memchr_inv(&ucmd.burst_info.reserved, 0,
4245 sizeof(ucmd.burst_info.reserved)))
4250 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4251 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4253 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4256 if (qp_type == MLX5_IB_QPT_DCT)
4257 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata);
4259 mutex_lock(&qp->mutex);
4261 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4262 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4264 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4265 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4268 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4269 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4270 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4274 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4275 qp_type != MLX5_IB_QPT_DCI &&
4276 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4278 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4279 cur_state, new_state, ibqp->qp_type, attr_mask);
4281 } else if (qp_type == MLX5_IB_QPT_DCI &&
4282 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4283 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4284 cur_state, new_state, qp_type, attr_mask);
4288 if ((attr_mask & IB_QP_PORT) &&
4289 (attr->port_num == 0 ||
4290 attr->port_num > dev->num_ports)) {
4291 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4292 attr->port_num, dev->num_ports);
4296 if (attr_mask & IB_QP_PKEY_INDEX) {
4297 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4298 if (attr->pkey_index >=
4299 dev->mdev->port_caps[port - 1].pkey_table_len) {
4300 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4306 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4307 attr->max_rd_atomic >
4308 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4309 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4310 attr->max_rd_atomic);
4314 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4315 attr->max_dest_rd_atomic >
4316 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4317 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4318 attr->max_dest_rd_atomic);
4322 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4327 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4328 new_state, &ucmd, &resp, udata);
4330 /* resp.response_length is set in ECE supported flows only */
4331 if (!err && resp.response_length &&
4332 udata->outlen >= resp.response_length)
4333 /* Return -EFAULT to the user and expect him to destroy QP. */
4334 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4337 mutex_unlock(&qp->mutex);
4341 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4343 switch (mlx5_state) {
4344 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4345 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4346 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4347 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4348 case MLX5_QP_STATE_SQ_DRAINING:
4349 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4350 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4351 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4356 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4358 switch (mlx5_mig_state) {
4359 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4360 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4361 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4366 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4367 struct rdma_ah_attr *ah_attr, void *path)
4369 int port = MLX5_GET(ads, path, vhca_port_num);
4372 memset(ah_attr, 0, sizeof(*ah_attr));
4374 if (!port || port > ibdev->num_ports)
4377 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port);
4379 rdma_ah_set_port_num(ah_attr, port);
4380 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl));
4382 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid));
4383 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid));
4385 static_rate = MLX5_GET(ads, path, stat_rate);
4386 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0);
4387 if (MLX5_GET(ads, path, grh) ||
4388 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
4389 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label),
4390 MLX5_GET(ads, path, src_addr_index),
4391 MLX5_GET(ads, path, hop_limit),
4392 MLX5_GET(ads, path, tclass));
4393 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip));
4397 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4398 struct mlx5_ib_sq *sq,
4403 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4406 sq->state = *sq_state;
4412 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4413 struct mlx5_ib_rq *rq,
4421 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4422 out = kvzalloc(inlen, GFP_KERNEL);
4426 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4430 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4431 *rq_state = MLX5_GET(rqc, rqc, state);
4432 rq->state = *rq_state;
4439 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4440 struct mlx5_ib_qp *qp, u8 *qp_state)
4442 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4443 [MLX5_RQC_STATE_RST] = {
4444 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4445 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4446 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4447 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4449 [MLX5_RQC_STATE_RDY] = {
4450 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4451 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4452 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4453 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4455 [MLX5_RQC_STATE_ERR] = {
4456 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4457 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4458 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4459 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4461 [MLX5_RQ_STATE_NA] = {
4462 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4463 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4464 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4465 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4469 *qp_state = sqrq_trans[rq_state][sq_state];
4471 if (*qp_state == MLX5_QP_STATE_BAD) {
4472 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4473 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4474 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4478 if (*qp_state == MLX5_QP_STATE)
4479 *qp_state = qp->state;
4484 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4485 struct mlx5_ib_qp *qp,
4486 u8 *raw_packet_qp_state)
4488 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4489 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4490 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4492 u8 sq_state = MLX5_SQ_STATE_NA;
4493 u8 rq_state = MLX5_RQ_STATE_NA;
4495 if (qp->sq.wqe_cnt) {
4496 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4501 if (qp->rq.wqe_cnt) {
4502 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4507 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4508 raw_packet_qp_state);
4511 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4512 struct ib_qp_attr *qp_attr)
4514 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4515 void *qpc, *pri_path, *alt_path;
4519 outb = kzalloc(outlen, GFP_KERNEL);
4523 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
4527 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc);
4529 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state));
4530 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING)
4531 qp_attr->sq_draining = 1;
4533 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu);
4534 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state));
4535 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key);
4536 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn);
4537 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn);
4538 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn);
4540 if (MLX5_GET(qpc, qpc, rre))
4541 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ;
4542 if (MLX5_GET(qpc, qpc, rwe))
4543 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE;
4544 if (MLX5_GET(qpc, qpc, rae))
4545 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4547 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max);
4548 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max);
4549 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak);
4550 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count);
4551 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry);
4553 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
4554 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
4556 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4557 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path);
4558 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path);
4559 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index);
4560 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num);
4563 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index);
4564 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num);
4565 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout);
4566 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout);
4573 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4574 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4575 struct ib_qp_init_attr *qp_init_attr)
4577 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4579 u32 access_flags = 0;
4580 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4583 int supported_mask = IB_QP_STATE |
4584 IB_QP_ACCESS_FLAGS |
4586 IB_QP_MIN_RNR_TIMER |
4591 if (qp_attr_mask & ~supported_mask)
4593 if (mqp->state != IB_QPS_RTR)
4596 out = kzalloc(outlen, GFP_KERNEL);
4600 err = mlx5_core_dct_query(dev, dct, out, outlen);
4604 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4606 if (qp_attr_mask & IB_QP_STATE)
4607 qp_attr->qp_state = IB_QPS_RTR;
4609 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4610 if (MLX5_GET(dctc, dctc, rre))
4611 access_flags |= IB_ACCESS_REMOTE_READ;
4612 if (MLX5_GET(dctc, dctc, rwe))
4613 access_flags |= IB_ACCESS_REMOTE_WRITE;
4614 if (MLX5_GET(dctc, dctc, rae))
4615 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4616 qp_attr->qp_access_flags = access_flags;
4619 if (qp_attr_mask & IB_QP_PORT)
4620 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4621 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4622 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4623 if (qp_attr_mask & IB_QP_AV) {
4624 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4625 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4626 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4627 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4629 if (qp_attr_mask & IB_QP_PATH_MTU)
4630 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4631 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4632 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4638 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4639 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4641 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4642 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4644 u8 raw_packet_qp_state;
4646 if (ibqp->rwq_ind_tbl)
4649 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4650 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4653 /* Not all of output fields are applicable, make sure to zero them */
4654 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4655 memset(qp_attr, 0, sizeof(*qp_attr));
4657 if (unlikely(qp->type == MLX5_IB_QPT_DCT))
4658 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4659 qp_attr_mask, qp_init_attr);
4661 mutex_lock(&qp->mutex);
4663 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4664 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4665 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4668 qp->state = raw_packet_qp_state;
4669 qp_attr->port_num = 1;
4671 err = query_qp_attr(dev, qp, qp_attr);
4676 qp_attr->qp_state = qp->state;
4677 qp_attr->cur_qp_state = qp_attr->qp_state;
4678 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4679 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4681 if (!ibqp->uobject) {
4682 qp_attr->cap.max_send_wr = qp->sq.max_post;
4683 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4684 qp_init_attr->qp_context = ibqp->qp_context;
4686 qp_attr->cap.max_send_wr = 0;
4687 qp_attr->cap.max_send_sge = 0;
4690 qp_init_attr->qp_type = ibqp->qp_type;
4691 qp_init_attr->recv_cq = ibqp->recv_cq;
4692 qp_init_attr->send_cq = ibqp->send_cq;
4693 qp_init_attr->srq = ibqp->srq;
4694 qp_attr->cap.max_inline_data = qp->max_inline_data;
4696 qp_init_attr->cap = qp_attr->cap;
4698 qp_init_attr->create_flags = qp->flags;
4700 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4701 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4704 mutex_unlock(&qp->mutex);
4708 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4709 struct ib_udata *udata)
4711 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4712 struct mlx5_ib_xrcd *xrcd;
4715 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4716 return ERR_PTR(-ENOSYS);
4718 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4720 return ERR_PTR(-ENOMEM);
4722 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
4725 return ERR_PTR(-ENOMEM);
4728 return &xrcd->ibxrcd;
4731 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
4733 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4734 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4737 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
4739 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4745 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4747 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4748 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4749 struct ib_event event;
4751 if (rwq->ibwq.event_handler) {
4752 event.device = rwq->ibwq.device;
4753 event.element.wq = &rwq->ibwq;
4755 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4756 event.event = IB_EVENT_WQ_FATAL;
4759 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4763 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4767 static int set_delay_drop(struct mlx5_ib_dev *dev)
4771 mutex_lock(&dev->delay_drop.lock);
4772 if (dev->delay_drop.activate)
4775 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
4779 dev->delay_drop.activate = true;
4781 mutex_unlock(&dev->delay_drop.lock);
4784 atomic_inc(&dev->delay_drop.rqs_cnt);
4788 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4789 struct ib_wq_init_attr *init_attr)
4791 struct mlx5_ib_dev *dev;
4792 int has_net_offloads;
4800 dev = to_mdev(pd->device);
4802 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4803 in = kvzalloc(inlen, GFP_KERNEL);
4807 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
4808 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4809 MLX5_SET(rqc, rqc, mem_rq_type,
4810 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4811 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4812 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4813 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4814 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4815 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4816 MLX5_SET(wq, wq, wq_type,
4817 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4818 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4819 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4820 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4821 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4825 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4828 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4829 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4831 * In Firmware number of strides in each WQE is:
4832 * "512 * 2^single_wqe_log_num_of_strides"
4833 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
4834 * accepted as 0 to 9
4836 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
4837 2, 3, 4, 5, 6, 7, 8, 9 };
4838 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4839 MLX5_SET(wq, wq, log_wqe_stride_size,
4840 rwq->single_stride_log_num_of_bytes -
4841 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4842 MLX5_SET(wq, wq, log_wqe_num_of_strides,
4843 fw_map[rwq->log_num_strides -
4844 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
4846 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4847 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4848 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4849 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4850 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4851 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4852 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4853 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4854 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4855 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4860 MLX5_SET(rqc, rqc, vsd, 1);
4862 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4863 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4864 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4868 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4870 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4871 if (!(dev->ib_dev.attrs.raw_packet_caps &
4872 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4873 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4877 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4879 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4880 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4881 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
4882 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4883 err = set_delay_drop(dev);
4885 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4887 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
4889 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4897 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4898 struct ib_wq_init_attr *wq_init_attr,
4899 struct mlx5_ib_create_wq *ucmd,
4900 struct mlx5_ib_rwq *rwq)
4902 /* Sanity check RQ size before proceeding */
4903 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4906 if (!ucmd->rq_wqe_count)
4909 rwq->wqe_count = ucmd->rq_wqe_count;
4910 rwq->wqe_shift = ucmd->rq_wqe_shift;
4911 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
4914 rwq->log_rq_stride = rwq->wqe_shift;
4915 rwq->log_rq_size = ilog2(rwq->wqe_count);
4919 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
4921 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4922 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4925 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
4926 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4932 static int prepare_user_rq(struct ib_pd *pd,
4933 struct ib_wq_init_attr *init_attr,
4934 struct ib_udata *udata,
4935 struct mlx5_ib_rwq *rwq)
4937 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4938 struct mlx5_ib_create_wq ucmd = {};
4940 size_t required_cmd_sz;
4942 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4943 + sizeof(ucmd.single_stride_log_num_of_bytes);
4944 if (udata->inlen < required_cmd_sz) {
4945 mlx5_ib_dbg(dev, "invalid inlen\n");
4949 if (udata->inlen > sizeof(ucmd) &&
4950 !ib_is_udata_cleared(udata, sizeof(ucmd),
4951 udata->inlen - sizeof(ucmd))) {
4952 mlx5_ib_dbg(dev, "inlen is not supported\n");
4956 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4957 mlx5_ib_dbg(dev, "copy failed\n");
4961 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4962 mlx5_ib_dbg(dev, "invalid comp mask\n");
4964 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4965 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4966 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4969 if ((ucmd.single_stride_log_num_of_bytes <
4970 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4971 (ucmd.single_stride_log_num_of_bytes >
4972 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4973 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4974 ucmd.single_stride_log_num_of_bytes,
4975 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4976 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4979 if (!log_of_strides_valid(dev,
4980 ucmd.single_wqe_log_num_of_strides)) {
4983 "Invalid log num strides (%u. Range is %u - %u)\n",
4984 ucmd.single_wqe_log_num_of_strides,
4985 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
4986 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
4987 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4988 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4991 rwq->single_stride_log_num_of_bytes =
4992 ucmd.single_stride_log_num_of_bytes;
4993 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4994 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4995 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4998 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5000 mlx5_ib_dbg(dev, "err %d\n", err);
5004 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
5006 mlx5_ib_dbg(dev, "err %d\n", err);
5010 rwq->user_index = ucmd.user_index;
5014 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5015 struct ib_wq_init_attr *init_attr,
5016 struct ib_udata *udata)
5018 struct mlx5_ib_dev *dev;
5019 struct mlx5_ib_rwq *rwq;
5020 struct mlx5_ib_create_wq_resp resp = {};
5021 size_t min_resp_len;
5025 return ERR_PTR(-ENOSYS);
5027 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5028 if (udata->outlen && udata->outlen < min_resp_len)
5029 return ERR_PTR(-EINVAL);
5031 if (!capable(CAP_SYS_RAWIO) &&
5032 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5033 return ERR_PTR(-EPERM);
5035 dev = to_mdev(pd->device);
5036 switch (init_attr->wq_type) {
5038 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5040 return ERR_PTR(-ENOMEM);
5041 err = prepare_user_rq(pd, init_attr, udata, rwq);
5044 err = create_rq(rwq, pd, init_attr);
5049 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5050 init_attr->wq_type);
5051 return ERR_PTR(-EINVAL);
5054 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5055 rwq->ibwq.state = IB_WQS_RESET;
5056 if (udata->outlen) {
5057 resp.response_length = offsetof(typeof(resp), response_length) +
5058 sizeof(resp.response_length);
5059 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5064 rwq->core_qp.event = mlx5_ib_wq_event;
5065 rwq->ibwq.event_handler = init_attr->event_handler;
5069 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5071 destroy_user_rq(dev, pd, rwq, udata);
5074 return ERR_PTR(err);
5077 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
5079 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5080 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5082 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5083 destroy_user_rq(dev, wq->pd, rwq, udata);
5087 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5088 struct ib_rwq_ind_table_init_attr *init_attr,
5089 struct ib_udata *udata)
5091 struct mlx5_ib_dev *dev = to_mdev(device);
5092 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5093 int sz = 1 << init_attr->log_ind_tbl_size;
5094 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5095 size_t min_resp_len;
5102 if (udata->inlen > 0 &&
5103 !ib_is_udata_cleared(udata, 0,
5105 return ERR_PTR(-EOPNOTSUPP);
5107 if (init_attr->log_ind_tbl_size >
5108 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5109 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5110 init_attr->log_ind_tbl_size,
5111 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5112 return ERR_PTR(-EINVAL);
5115 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5116 if (udata->outlen && udata->outlen < min_resp_len)
5117 return ERR_PTR(-EINVAL);
5119 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5121 return ERR_PTR(-ENOMEM);
5123 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5124 in = kvzalloc(inlen, GFP_KERNEL);
5130 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5132 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5133 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5135 for (i = 0; i < sz; i++)
5136 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5138 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5139 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5141 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5147 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5148 if (udata->outlen) {
5149 resp.response_length = offsetof(typeof(resp), response_length) +
5150 sizeof(resp.response_length);
5151 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5156 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5159 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5162 return ERR_PTR(err);
5165 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5167 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5168 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5170 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5176 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5177 u32 wq_attr_mask, struct ib_udata *udata)
5179 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5180 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5181 struct mlx5_ib_modify_wq ucmd = {};
5182 size_t required_cmd_sz;
5190 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5191 if (udata->inlen < required_cmd_sz)
5194 if (udata->inlen > sizeof(ucmd) &&
5195 !ib_is_udata_cleared(udata, sizeof(ucmd),
5196 udata->inlen - sizeof(ucmd)))
5199 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5202 if (ucmd.comp_mask || ucmd.reserved)
5205 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5206 in = kvzalloc(inlen, GFP_KERNEL);
5210 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5212 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5213 wq_attr->curr_wq_state : wq->state;
5214 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5215 wq_attr->wq_state : curr_wq_state;
5216 if (curr_wq_state == IB_WQS_ERR)
5217 curr_wq_state = MLX5_RQC_STATE_ERR;
5218 if (wq_state == IB_WQS_ERR)
5219 wq_state = MLX5_RQC_STATE_ERR;
5220 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5221 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5222 MLX5_SET(rqc, rqc, state, wq_state);
5224 if (wq_attr_mask & IB_WQ_FLAGS) {
5225 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5226 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5227 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5228 mlx5_ib_dbg(dev, "VLAN offloads are not "
5233 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5234 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5235 MLX5_SET(rqc, rqc, vsd,
5236 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5239 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5240 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5246 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5249 set_id = mlx5_ib_get_counters_id(dev, 0);
5250 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5251 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5252 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5253 MLX5_SET(rqc, rqc, counter_set_id, set_id);
5257 "Receive WQ counters are not supported on current FW\n");
5260 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
5262 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5269 struct mlx5_ib_drain_cqe {
5271 struct completion done;
5274 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5276 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5277 struct mlx5_ib_drain_cqe,
5280 complete(&cqe->done);
5283 /* This function returns only once the drained WR was completed */
5284 static void handle_drain_completion(struct ib_cq *cq,
5285 struct mlx5_ib_drain_cqe *sdrain,
5286 struct mlx5_ib_dev *dev)
5288 struct mlx5_core_dev *mdev = dev->mdev;
5290 if (cq->poll_ctx == IB_POLL_DIRECT) {
5291 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5292 ib_process_cq_direct(cq, -1);
5296 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5297 struct mlx5_ib_cq *mcq = to_mcq(cq);
5298 bool triggered = false;
5299 unsigned long flags;
5301 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5302 /* Make sure that the CQ handler won't run if wasn't run yet */
5303 if (!mcq->mcq.reset_notify_added)
5304 mcq->mcq.reset_notify_added = 1;
5307 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5310 /* Wait for any scheduled/running task to be ended */
5311 switch (cq->poll_ctx) {
5312 case IB_POLL_SOFTIRQ:
5313 irq_poll_disable(&cq->iop);
5314 irq_poll_enable(&cq->iop);
5316 case IB_POLL_WORKQUEUE:
5317 cancel_work_sync(&cq->work);
5324 /* Run the CQ handler - this makes sure that the drain WR will
5325 * be processed if wasn't processed yet.
5327 mcq->mcq.comp(&mcq->mcq, NULL);
5330 wait_for_completion(&sdrain->done);
5333 void mlx5_ib_drain_sq(struct ib_qp *qp)
5335 struct ib_cq *cq = qp->send_cq;
5336 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5337 struct mlx5_ib_drain_cqe sdrain;
5338 const struct ib_send_wr *bad_swr;
5339 struct ib_rdma_wr swr = {
5342 { .wr_cqe = &sdrain.cqe, },
5343 .opcode = IB_WR_RDMA_WRITE,
5347 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5348 struct mlx5_core_dev *mdev = dev->mdev;
5350 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5351 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5352 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5356 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5357 init_completion(&sdrain.done);
5359 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr);
5361 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5365 handle_drain_completion(cq, &sdrain, dev);
5368 void mlx5_ib_drain_rq(struct ib_qp *qp)
5370 struct ib_cq *cq = qp->recv_cq;
5371 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5372 struct mlx5_ib_drain_cqe rdrain;
5373 struct ib_recv_wr rwr = {};
5374 const struct ib_recv_wr *bad_rwr;
5376 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5377 struct mlx5_core_dev *mdev = dev->mdev;
5379 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5380 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5381 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5385 rwr.wr_cqe = &rdrain.cqe;
5386 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5387 init_completion(&rdrain.done);
5389 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr);
5391 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5395 handle_drain_completion(cq, &rdrain, dev);
5399 * Bind a qp to a counter. If @counter is NULL then bind the qp to
5400 * the default counter
5402 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
5404 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5405 struct mlx5_ib_qp *mqp = to_mqp(qp);
5408 mutex_lock(&mqp->mutex);
5409 if (mqp->state == IB_QPS_RESET) {
5410 qp->counter = counter;
5414 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
5419 if (mqp->state == IB_QPS_RTS) {
5420 err = __mlx5_ib_qp_set_counter(qp, counter);
5422 qp->counter = counter;
5427 mqp->counter_pending = 1;
5428 qp->counter = counter;
5431 mutex_unlock(&mqp->mutex);