drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <rdma/rdma_counter.h>
  38 #include <linux/mlx5/fs.h>
  39 #include "mlx5_ib.h"
  40 #include "ib_rep.h"
  41 #include "cmd.h"
  42 #include "qp.h"
  43 #include "wr.h"
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum raw_qp_set_mask_map {
  57         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  58         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  59 };
  60
  61 struct mlx5_modify_raw_qp_param {
  62         u16 operation;
  63
  64         u32 set_mask; /* raw_qp_set_mask_map */
  65
  66         struct mlx5_rate_limit rl;
  67
  68         u8 rq_q_ctr_id;
  69         u16 port;
  70 };
  71
  72 static void get_cqs(enum ib_qp_type qp_type,
  73                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  74                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  75
  76 static int is_qp0(enum ib_qp_type qp_type)
  77 {
  78         return qp_type == IB_QPT_SMI;
  79 }
  80
  81 static int is_sqp(enum ib_qp_type qp_type)
  82 {
  83         return is_qp0(qp_type) || is_qp1(qp_type);
  84 }
  85
  86 /**
  87  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
  88  * to kernel buffer
  89  *
  90  * @umem: User space memory where the WQ is
  91  * @buffer: buffer to copy to
  92  * @buflen: buffer length
  93  * @wqe_index: index of WQE to copy from
  94  * @wq_offset: offset to start of WQ
  95  * @wq_wqe_cnt: number of WQEs in WQ
  96  * @wq_wqe_shift: log2 of WQE size
  97  * @bcnt: number of bytes to copy
  98  * @bytes_copied: number of bytes to copy (return value)
  99  *
 100  * Copies from start of WQE bcnt or less bytes.
 101  * Does not gurantee to copy the entire WQE.
 102  *
 103  * Return: zero on success, or an error code.
 104  */
 105 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
 106                                         size_t buflen, int wqe_index,
 107                                         int wq_offset, int wq_wqe_cnt,
 108                                         int wq_wqe_shift, int bcnt,
 109                                         size_t *bytes_copied)
 110 {
 111         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 112         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 113         size_t copy_length;
 114         int ret;
 115
 116         /* don't copy more than requested, more than buffer length or
 117          * beyond WQ end
 118          */
 119         copy_length = min_t(u32, buflen, wq_end - offset);
 120         copy_length = min_t(u32, copy_length, bcnt);
 121
 122         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 123         if (ret)
 124                 return ret;
 125
 126         if (!ret && bytes_copied)
 127                 *bytes_copied = copy_length;
 128
 129         return 0;
 130 }
 131
 132 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 133                                       void *buffer, size_t buflen, size_t *bc)
 134 {
 135         struct mlx5_wqe_ctrl_seg *ctrl;
 136         size_t bytes_copied = 0;
 137         size_t wqe_length;
 138         void *p;
 139         int ds;
 140
 141         wqe_index = wqe_index & qp->sq.fbc.sz_m1;
 142
 143         /* read the control segment first */
 144         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 145         ctrl = p;
 146         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 147         wqe_length = ds * MLX5_WQE_DS_UNITS;
 148
 149         /* read rest of WQE if it spreads over more than one stride */
 150         while (bytes_copied < wqe_length) {
 151                 size_t copy_length =
 152                         min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
 153
 154                 if (!copy_length)
 155                         break;
 156
 157                 memcpy(buffer + bytes_copied, p, copy_length);
 158                 bytes_copied += copy_length;
 159
 160                 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
 161                 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
 162         }
 163         *bc = bytes_copied;
 164         return 0;
 165 }
 166
 167 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
 168                                     void *buffer, size_t buflen, size_t *bc)
 169 {
 170         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 171         struct ib_umem *umem = base->ubuffer.umem;
 172         struct mlx5_ib_wq *wq = &qp->sq;
 173         struct mlx5_wqe_ctrl_seg *ctrl;
 174         size_t bytes_copied;
 175         size_t bytes_copied2;
 176         size_t wqe_length;
 177         int ret;
 178         int ds;
 179
 180         /* at first read as much as possible */
 181         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 182                                            wq->offset, wq->wqe_cnt,
 183                                            wq->wqe_shift, buflen,
 184                                            &bytes_copied);
 185         if (ret)
 186                 return ret;
 187
 188         /* we need at least control segment size to proceed */
 189         if (bytes_copied < sizeof(*ctrl))
 190                 return -EINVAL;
 191
 192         ctrl = buffer;
 193         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 194         wqe_length = ds * MLX5_WQE_DS_UNITS;
 195
 196         /* if we copied enough then we are done */
 197         if (bytes_copied >= wqe_length) {
 198                 *bc = bytes_copied;
 199                 return 0;
 200         }
 201
 202         /* otherwise this a wrapped around wqe
 203          * so read the remaining bytes starting
 204          * from  wqe_index 0
 205          */
 206         ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
 207                                            buflen - bytes_copied, 0, wq->offset,
 208                                            wq->wqe_cnt, wq->wqe_shift,
 209                                            wqe_length - bytes_copied,
 210                                            &bytes_copied2);
 211
 212         if (ret)
 213                 return ret;
 214         *bc = bytes_copied + bytes_copied2;
 215         return 0;
 216 }
 217
 218 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 219                         size_t buflen, size_t *bc)
 220 {
 221         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 222         struct ib_umem *umem = base->ubuffer.umem;
 223
 224         if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
 225                 return -EINVAL;
 226
 227         if (!umem)
 228                 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
 229                                                   buflen, bc);
 230
 231         return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
 232 }
 233
 234 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
 235                                     void *buffer, size_t buflen, size_t *bc)
 236 {
 237         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 238         struct ib_umem *umem = base->ubuffer.umem;
 239         struct mlx5_ib_wq *wq = &qp->rq;
 240         size_t bytes_copied;
 241         int ret;
 242
 243         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
 244                                            wq->offset, wq->wqe_cnt,
 245                                            wq->wqe_shift, buflen,
 246                                            &bytes_copied);
 247
 248         if (ret)
 249                 return ret;
 250         *bc = bytes_copied;
 251         return 0;
 252 }
 253
 254 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
 255                         size_t buflen, size_t *bc)
 256 {
 257         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 258         struct ib_umem *umem = base->ubuffer.umem;
 259         struct mlx5_ib_wq *wq = &qp->rq;
 260         size_t wqe_size = 1 << wq->wqe_shift;
 261
 262         if (buflen < wqe_size)
 263                 return -EINVAL;
 264
 265         if (!umem)
 266                 return -EOPNOTSUPP;
 267
 268         return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
 269 }
 270
 271 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
 272                                      void *buffer, size_t buflen, size_t *bc)
 273 {
 274         struct ib_umem *umem = srq->umem;
 275         size_t bytes_copied;
 276         int ret;
 277
 278         ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
 279                                            srq->msrq.max, srq->msrq.wqe_shift,
 280                                            buflen, &bytes_copied);
 281
 282         if (ret)
 283                 return ret;
 284         *bc = bytes_copied;
 285         return 0;
 286 }
 287
 288 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
 289                          size_t buflen, size_t *bc)
 290 {
 291         struct ib_umem *umem = srq->umem;
 292         size_t wqe_size = 1 << srq->msrq.wqe_shift;
 293
 294         if (buflen < wqe_size)
 295                 return -EINVAL;
 296
 297         if (!umem)
 298                 return -EOPNOTSUPP;
 299
 300         return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
 301 }
 302
 303 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 304 {
 305         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 306         struct ib_event event;
 307
 308         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 309                 /* This event is only valid for trans_qps */
 310                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 311         }
 312
 313         if (ibqp->event_handler) {
 314                 event.device     = ibqp->device;
 315                 event.element.qp = ibqp;
 316                 switch (type) {
 317                 case MLX5_EVENT_TYPE_PATH_MIG:
 318                         event.event = IB_EVENT_PATH_MIG;
 319                         break;
 320                 case MLX5_EVENT_TYPE_COMM_EST:
 321                         event.event = IB_EVENT_COMM_EST;
 322                         break;
 323                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 324                         event.event = IB_EVENT_SQ_DRAINED;
 325                         break;
 326                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 327                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 328                         break;
 329                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 330                         event.event = IB_EVENT_QP_FATAL;
 331                         break;
 332                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 333                         event.event = IB_EVENT_PATH_MIG_ERR;
 334                         break;
 335                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 336                         event.event = IB_EVENT_QP_REQ_ERR;
 337                         break;
 338                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 339                         event.event = IB_EVENT_QP_ACCESS_ERR;
 340                         break;
 341                 default:
 342                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 343                         return;
 344                 }
 345
 346                 ibqp->event_handler(&event, ibqp->qp_context);
 347         }
 348 }
 349
 350 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 351                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 352 {
 353         int wqe_size;
 354         int wq_size;
 355
 356         /* Sanity check RQ size before proceeding */
 357         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 358                 return -EINVAL;
 359
 360         if (!has_rq) {
 361                 qp->rq.max_gs = 0;
 362                 qp->rq.wqe_cnt = 0;
 363                 qp->rq.wqe_shift = 0;
 364                 cap->max_recv_wr = 0;
 365                 cap->max_recv_sge = 0;
 366         } else {
 367                 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
 368
 369                 if (ucmd) {
 370                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 371                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 372                                 return -EINVAL;
 373                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 374                         if ((1 << qp->rq.wqe_shift) /
 375                                     sizeof(struct mlx5_wqe_data_seg) <
 376                             wq_sig)
 377                                 return -EINVAL;
 378                         qp->rq.max_gs =
 379                                 (1 << qp->rq.wqe_shift) /
 380                                         sizeof(struct mlx5_wqe_data_seg) -
 381                                 wq_sig;
 382                         qp->rq.max_post = qp->rq.wqe_cnt;
 383                 } else {
 384                         wqe_size =
 385                                 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
 386                                          0;
 387                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 388                         wqe_size = roundup_pow_of_two(wqe_size);
 389                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 390                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 391                         qp->rq.wqe_cnt = wq_size / wqe_size;
 392                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 393                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 394                                             wqe_size,
 395                                             MLX5_CAP_GEN(dev->mdev,
 396                                                          max_wqe_sz_rq));
 397                                 return -EINVAL;
 398                         }
 399                         qp->rq.wqe_shift = ilog2(wqe_size);
 400                         qp->rq.max_gs =
 401                                 (1 << qp->rq.wqe_shift) /
 402                                         sizeof(struct mlx5_wqe_data_seg) -
 403                                 wq_sig;
 404                         qp->rq.max_post = qp->rq.wqe_cnt;
 405                 }
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int sq_overhead(struct ib_qp_init_attr *attr)
 412 {
 413         int size = 0;
 414
 415         switch (attr->qp_type) {
 416         case IB_QPT_XRC_INI:
 417                 size += sizeof(struct mlx5_wqe_xrc_seg);
 418                 /* fall through */
 419         case IB_QPT_RC:
 420                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 421                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 422                             sizeof(struct mlx5_wqe_raddr_seg),
 423                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 424                             sizeof(struct mlx5_mkey_seg) +
 425                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 426                             MLX5_IB_UMR_OCTOWORD);
 427                 break;
 428
 429         case IB_QPT_XRC_TGT:
 430                 return 0;
 431
 432         case IB_QPT_UC:
 433                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 434                         max(sizeof(struct mlx5_wqe_raddr_seg),
 435                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 436                             sizeof(struct mlx5_mkey_seg));
 437                 break;
 438
 439         case IB_QPT_UD:
 440                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 441                         size += sizeof(struct mlx5_wqe_eth_pad) +
 442                                 sizeof(struct mlx5_wqe_eth_seg);
 443                 /* fall through */
 444         case IB_QPT_SMI:
 445         case MLX5_IB_QPT_HW_GSI:
 446                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 447                         sizeof(struct mlx5_wqe_datagram_seg);
 448                 break;
 449
 450         case MLX5_IB_QPT_REG_UMR:
 451                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 452                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 453                         sizeof(struct mlx5_mkey_seg);
 454                 break;
 455
 456         default:
 457                 return -EINVAL;
 458         }
 459
 460         return size;
 461 }
 462
 463 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 464 {
 465         int inl_size = 0;
 466         int size;
 467
 468         size = sq_overhead(attr);
 469         if (size < 0)
 470                 return size;
 471
 472         if (attr->cap.max_inline_data) {
 473                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 474                         attr->cap.max_inline_data;
 475         }
 476
 477         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 478         if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
 479             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 480                 return MLX5_SIG_WQE_SIZE;
 481         else
 482                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 483 }
 484
 485 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 486 {
 487         int max_sge;
 488
 489         if (attr->qp_type == IB_QPT_RC)
 490                 max_sge = (min_t(int, wqe_size, 512) -
 491                            sizeof(struct mlx5_wqe_ctrl_seg) -
 492                            sizeof(struct mlx5_wqe_raddr_seg)) /
 493                         sizeof(struct mlx5_wqe_data_seg);
 494         else if (attr->qp_type == IB_QPT_XRC_INI)
 495                 max_sge = (min_t(int, wqe_size, 512) -
 496                            sizeof(struct mlx5_wqe_ctrl_seg) -
 497                            sizeof(struct mlx5_wqe_xrc_seg) -
 498                            sizeof(struct mlx5_wqe_raddr_seg)) /
 499                         sizeof(struct mlx5_wqe_data_seg);
 500         else
 501                 max_sge = (wqe_size - sq_overhead(attr)) /
 502                         sizeof(struct mlx5_wqe_data_seg);
 503
 504         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 505                      sizeof(struct mlx5_wqe_data_seg));
 506 }
 507
 508 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 509                         struct mlx5_ib_qp *qp)
 510 {
 511         int wqe_size;
 512         int wq_size;
 513
 514         if (!attr->cap.max_send_wr)
 515                 return 0;
 516
 517         wqe_size = calc_send_wqe(attr);
 518         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 519         if (wqe_size < 0)
 520                 return wqe_size;
 521
 522         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 523                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 524                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 525                 return -EINVAL;
 526         }
 527
 528         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 529                               sizeof(struct mlx5_wqe_inline_seg);
 530         attr->cap.max_inline_data = qp->max_inline_data;
 531
 532         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 533         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 534         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 535                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 536                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 537                             qp->sq.wqe_cnt,
 538                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 539                 return -ENOMEM;
 540         }
 541         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 542         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 543         if (qp->sq.max_gs < attr->cap.max_send_sge)
 544                 return -ENOMEM;
 545
 546         attr->cap.max_send_sge = qp->sq.max_gs;
 547         qp->sq.max_post = wq_size / wqe_size;
 548         attr->cap.max_send_wr = qp->sq.max_post;
 549
 550         return wq_size;
 551 }
 552
 553 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 554                             struct mlx5_ib_qp *qp,
 555                             struct mlx5_ib_create_qp *ucmd,
 556                             struct mlx5_ib_qp_base *base,
 557                             struct ib_qp_init_attr *attr)
 558 {
 559         int desc_sz = 1 << qp->sq.wqe_shift;
 560
 561         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 562                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 563                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 564                 return -EINVAL;
 565         }
 566
 567         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 568                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 569                              ucmd->sq_wqe_count);
 570                 return -EINVAL;
 571         }
 572
 573         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 574
 575         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 576                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 577                              qp->sq.wqe_cnt,
 578                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 579                 return -EINVAL;
 580         }
 581
 582         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 583             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
 584                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 585                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 586         } else {
 587                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 588                                          (qp->sq.wqe_cnt << 6);
 589         }
 590
 591         return 0;
 592 }
 593
 594 static int qp_has_rq(struct ib_qp_init_attr *attr)
 595 {
 596         if (attr->qp_type == IB_QPT_XRC_INI ||
 597             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 598             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 599             !attr->cap.max_recv_wr)
 600                 return 0;
 601
 602         return 1;
 603 }
 604
 605 enum {
 606         /* this is the first blue flame register in the array of bfregs assigned
 607          * to a processes. Since we do not use it for blue flame but rather
 608          * regular 64 bit doorbells, we do not need a lock for maintaiing
 609          * "odd/even" order
 610          */
 611         NUM_NON_BLUE_FLAME_BFREGS = 1,
 612 };
 613
 614 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 615 {
 616         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 617 }
 618
 619 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 620                          struct mlx5_bfreg_info *bfregi)
 621 {
 622         int n;
 623
 624         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 625             NUM_NON_BLUE_FLAME_BFREGS;
 626
 627         return n >= 0 ? n : 0;
 628 }
 629
 630 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 631                            struct mlx5_bfreg_info *bfregi)
 632 {
 633         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 634 }
 635
 636 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 637                           struct mlx5_bfreg_info *bfregi)
 638 {
 639         int med;
 640
 641         med = num_med_bfreg(dev, bfregi);
 642         return ++med;
 643 }
 644
 645 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 646                                   struct mlx5_bfreg_info *bfregi)
 647 {
 648         int i;
 649
 650         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 651                 if (!bfregi->count[i]) {
 652                         bfregi->count[i]++;
 653                         return i;
 654                 }
 655         }
 656
 657         return -ENOMEM;
 658 }
 659
 660 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 661                                  struct mlx5_bfreg_info *bfregi)
 662 {
 663         int minidx = first_med_bfreg(dev, bfregi);
 664         int i;
 665
 666         if (minidx < 0)
 667                 return minidx;
 668
 669         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 670                 if (bfregi->count[i] < bfregi->count[minidx])
 671                         minidx = i;
 672                 if (!bfregi->count[minidx])
 673                         break;
 674         }
 675
 676         bfregi->count[minidx]++;
 677         return minidx;
 678 }
 679
 680 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 681                        struct mlx5_bfreg_info *bfregi)
 682 {
 683         int bfregn = -ENOMEM;
 684
 685         if (bfregi->lib_uar_dyn)
 686                 return -EINVAL;
 687
 688         mutex_lock(&bfregi->lock);
 689         if (bfregi->ver >= 2) {
 690                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 691                 if (bfregn < 0)
 692                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 693         }
 694
 695         if (bfregn < 0) {
 696                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 697                 bfregn = 0;
 698                 bfregi->count[bfregn]++;
 699         }
 700         mutex_unlock(&bfregi->lock);
 701
 702         return bfregn;
 703 }
 704
 705 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 706 {
 707         mutex_lock(&bfregi->lock);
 708         bfregi->count[bfregn]--;
 709         mutex_unlock(&bfregi->lock);
 710 }
 711
 712 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 713 {
 714         switch (state) {
 715         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 716         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 717         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 718         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 719         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 720         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 721         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 722         default:                return -1;
 723         }
 724 }
 725
 726 static int to_mlx5_st(enum ib_qp_type type)
 727 {
 728         switch (type) {
 729         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 730         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 731         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 732         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 733         case IB_QPT_XRC_INI:
 734         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 735         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 736         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 737         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 738         case IB_QPT_RAW_PACKET:         return MLX5_QP_ST_RAW_ETHERTYPE;
 739         default:                return -EINVAL;
 740         }
 741 }
 742
 743 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 744                              struct mlx5_ib_cq *recv_cq);
 745 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 746                                struct mlx5_ib_cq *recv_cq);
 747
 748 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 749                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 750                         bool dyn_bfreg)
 751 {
 752         unsigned int bfregs_per_sys_page;
 753         u32 index_of_sys_page;
 754         u32 offset;
 755
 756         if (bfregi->lib_uar_dyn)
 757                 return -EINVAL;
 758
 759         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 760                                 MLX5_NON_FP_BFREGS_PER_UAR;
 761         index_of_sys_page = bfregn / bfregs_per_sys_page;
 762
 763         if (dyn_bfreg) {
 764                 index_of_sys_page += bfregi->num_static_sys_pages;
 765
 766                 if (index_of_sys_page >= bfregi->num_sys_pages)
 767                         return -EINVAL;
 768
 769                 if (bfregn > bfregi->num_dyn_bfregs ||
 770                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 771                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 772                         return -EINVAL;
 773                 }
 774         }
 775
 776         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 777         return bfregi->sys_pages[index_of_sys_page] + offset;
 778 }
 779
 780 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 781                             unsigned long addr, size_t size,
 782                             struct ib_umem **umem, int *npages, int *page_shift,
 783                             int *ncont, u32 *offset)
 784 {
 785         int err;
 786
 787         *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
 788         if (IS_ERR(*umem)) {
 789                 mlx5_ib_dbg(dev, "umem_get failed\n");
 790                 return PTR_ERR(*umem);
 791         }
 792
 793         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 794
 795         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 796         if (err) {
 797                 mlx5_ib_warn(dev, "bad offset\n");
 798                 goto err_umem;
 799         }
 800
 801         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 802                     addr, size, *npages, *page_shift, *ncont, *offset);
 803
 804         return 0;
 805
 806 err_umem:
 807         ib_umem_release(*umem);
 808         *umem = NULL;
 809
 810         return err;
 811 }
 812
 813 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 814                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 815 {
 816         struct mlx5_ib_ucontext *context =
 817                 rdma_udata_to_drv_context(
 818                         udata,
 819                         struct mlx5_ib_ucontext,
 820                         ibucontext);
 821
 822         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 823                 atomic_dec(&dev->delay_drop.rqs_cnt);
 824
 825         mlx5_ib_db_unmap_user(context, &rwq->db);
 826         ib_umem_release(rwq->umem);
 827 }
 828
 829 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 830                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 831                           struct mlx5_ib_create_wq *ucmd)
 832 {
 833         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 834                 udata, struct mlx5_ib_ucontext, ibucontext);
 835         int page_shift = 0;
 836         int npages;
 837         u32 offset = 0;
 838         int ncont = 0;
 839         int err;
 840
 841         if (!ucmd->buf_addr)
 842                 return -EINVAL;
 843
 844         rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
 845         if (IS_ERR(rwq->umem)) {
 846                 mlx5_ib_dbg(dev, "umem_get failed\n");
 847                 err = PTR_ERR(rwq->umem);
 848                 return err;
 849         }
 850
 851         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 852                            &ncont, NULL);
 853         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 854                                      &rwq->rq_page_offset);
 855         if (err) {
 856                 mlx5_ib_warn(dev, "bad offset\n");
 857                 goto err_umem;
 858         }
 859
 860         rwq->rq_num_pas = ncont;
 861         rwq->page_shift = page_shift;
 862         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 863         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 864
 865         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 866                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 867                     npages, page_shift, ncont, offset);
 868
 869         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 870         if (err) {
 871                 mlx5_ib_dbg(dev, "map failed\n");
 872                 goto err_umem;
 873         }
 874
 875         return 0;
 876
 877 err_umem:
 878         ib_umem_release(rwq->umem);
 879         return err;
 880 }
 881
 882 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 883                          struct mlx5_bfreg_info *bfregi, int bfregn)
 884 {
 885         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 886                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 887 }
 888
 889 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 890                            struct mlx5_ib_qp *qp, struct ib_udata *udata,
 891                            struct ib_qp_init_attr *attr, u32 **in,
 892                            struct mlx5_ib_create_qp_resp *resp, int *inlen,
 893                            struct mlx5_ib_qp_base *base,
 894                            struct mlx5_ib_create_qp *ucmd)
 895 {
 896         struct mlx5_ib_ucontext *context;
 897         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 898         int page_shift = 0;
 899         int uar_index = 0;
 900         int npages;
 901         u32 offset = 0;
 902         int bfregn;
 903         int ncont = 0;
 904         __be64 *pas;
 905         void *qpc;
 906         int err;
 907         u16 uid;
 908         u32 uar_flags;
 909
 910         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 911                                             ibucontext);
 912         uar_flags = qp->flags_en &
 913                     (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
 914         switch (uar_flags) {
 915         case MLX5_QP_FLAG_UAR_PAGE_INDEX:
 916                 uar_index = ucmd->bfreg_index;
 917                 bfregn = MLX5_IB_INVALID_BFREG;
 918                 break;
 919         case MLX5_QP_FLAG_BFREG_INDEX:
 920                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 921                                                 ucmd->bfreg_index, true);
 922                 if (uar_index < 0)
 923                         return uar_index;
 924                 bfregn = MLX5_IB_INVALID_BFREG;
 925                 break;
 926         case 0:
 927                 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
 928                         return -EINVAL;
 929                 bfregn = alloc_bfreg(dev, &context->bfregi);
 930                 if (bfregn < 0)
 931                         return bfregn;
 932                 break;
 933         default:
 934                 return -EINVAL;
 935         }
 936
 937         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 938         if (bfregn != MLX5_IB_INVALID_BFREG)
 939                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 940                                                 false);
 941
 942         qp->rq.offset = 0;
 943         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 944         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 945
 946         err = set_user_buf_size(dev, qp, ucmd, base, attr);
 947         if (err)
 948                 goto err_bfreg;
 949
 950         if (ucmd->buf_addr && ubuffer->buf_size) {
 951                 ubuffer->buf_addr = ucmd->buf_addr;
 952                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 953                                        ubuffer->buf_size, &ubuffer->umem,
 954                                        &npages, &page_shift, &ncont, &offset);
 955                 if (err)
 956                         goto err_bfreg;
 957         } else {
 958                 ubuffer->umem = NULL;
 959         }
 960
 961         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 962                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 963         *in = kvzalloc(*inlen, GFP_KERNEL);
 964         if (!*in) {
 965                 err = -ENOMEM;
 966                 goto err_umem;
 967         }
 968
 969         uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 970         MLX5_SET(create_qp_in, *in, uid, uid);
 971         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 972         if (ubuffer->umem)
 973                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 974
 975         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 976
 977         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 978         MLX5_SET(qpc, qpc, page_offset, offset);
 979
 980         MLX5_SET(qpc, qpc, uar_page, uar_index);
 981         if (bfregn != MLX5_IB_INVALID_BFREG)
 982                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 983         else
 984                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 985         qp->bfregn = bfregn;
 986
 987         err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
 988         if (err) {
 989                 mlx5_ib_dbg(dev, "map failed\n");
 990                 goto err_free;
 991         }
 992
 993         return 0;
 994
 995 err_free:
 996         kvfree(*in);
 997
 998 err_umem:
 999         ib_umem_release(ubuffer->umem);
1000
1001 err_bfreg:
1002         if (bfregn != MLX5_IB_INVALID_BFREG)
1003                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1004         return err;
1005 }
1006
1007 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1008                        struct mlx5_ib_qp_base *base, struct ib_udata *udata)
1009 {
1010         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1011                 udata, struct mlx5_ib_ucontext, ibucontext);
1012
1013         if (udata) {
1014                 /* User QP */
1015                 mlx5_ib_db_unmap_user(context, &qp->db);
1016                 ib_umem_release(base->ubuffer.umem);
1017
1018                 /*
1019                  * Free only the BFREGs which are handled by the kernel.
1020                  * BFREGs of UARs allocated dynamically are handled by user.
1021                  */
1022                 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1023                         mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1024                 return;
1025         }
1026
1027         /* Kernel QP */
1028         kvfree(qp->sq.wqe_head);
1029         kvfree(qp->sq.w_list);
1030         kvfree(qp->sq.wrid);
1031         kvfree(qp->sq.wr_data);
1032         kvfree(qp->rq.wrid);
1033         if (qp->db.db)
1034                 mlx5_db_free(dev->mdev, &qp->db);
1035         if (qp->buf.frags)
1036                 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1037 }
1038
1039 static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1040                              struct ib_qp_init_attr *init_attr,
1041                              struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1042                              struct mlx5_ib_qp_base *base)
1043 {
1044         int uar_index;
1045         void *qpc;
1046         int err;
1047
1048         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1049                 qp->bf.bfreg = &dev->fp_bfreg;
1050         else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
1051                 qp->bf.bfreg = &dev->wc_bfreg;
1052         else
1053                 qp->bf.bfreg = &dev->bfreg;
1054
1055         /* We need to divide by two since each register is comprised of
1056          * two buffers of identical size, namely odd and even
1057          */
1058         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1059         uar_index = qp->bf.bfreg->index;
1060
1061         err = calc_sq_size(dev, init_attr, qp);
1062         if (err < 0) {
1063                 mlx5_ib_dbg(dev, "err %d\n", err);
1064                 return err;
1065         }
1066
1067         qp->rq.offset = 0;
1068         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1069         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1070
1071         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1072                                        &qp->buf, dev->mdev->priv.numa_node);
1073         if (err) {
1074                 mlx5_ib_dbg(dev, "err %d\n", err);
1075                 return err;
1076         }
1077
1078         if (qp->rq.wqe_cnt)
1079                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1080                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1081
1082         if (qp->sq.wqe_cnt) {
1083                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1084                                         MLX5_SEND_WQE_BB;
1085                 mlx5_init_fbc_offset(qp->buf.frags +
1086                                      (qp->sq.offset / PAGE_SIZE),
1087                                      ilog2(MLX5_SEND_WQE_BB),
1088                                      ilog2(qp->sq.wqe_cnt),
1089                                      sq_strides_offset, &qp->sq.fbc);
1090
1091                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1092         }
1093
1094         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1095                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1096         *in = kvzalloc(*inlen, GFP_KERNEL);
1097         if (!*in) {
1098                 err = -ENOMEM;
1099                 goto err_buf;
1100         }
1101
1102         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1103         MLX5_SET(qpc, qpc, uar_page, uar_index);
1104         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1105
1106         /* Set "fast registration enabled" for all kernel QPs */
1107         MLX5_SET(qpc, qpc, fre, 1);
1108         MLX5_SET(qpc, qpc, rlky, 1);
1109
1110         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
1111                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1112
1113         mlx5_fill_page_frag_array(&qp->buf,
1114                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1115                                                          *in, pas));
1116
1117         err = mlx5_db_alloc(dev->mdev, &qp->db);
1118         if (err) {
1119                 mlx5_ib_dbg(dev, "err %d\n", err);
1120                 goto err_free;
1121         }
1122
1123         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1124                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1125         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1126                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1127         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1128                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1129         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1130                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1131         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1132                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1133
1134         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1135             !qp->sq.w_list || !qp->sq.wqe_head) {
1136                 err = -ENOMEM;
1137                 goto err_wrid;
1138         }
1139
1140         return 0;
1141
1142 err_wrid:
1143         kvfree(qp->sq.wqe_head);
1144         kvfree(qp->sq.w_list);
1145         kvfree(qp->sq.wrid);
1146         kvfree(qp->sq.wr_data);
1147         kvfree(qp->rq.wrid);
1148         mlx5_db_free(dev->mdev, &qp->db);
1149
1150 err_free:
1151         kvfree(*in);
1152
1153 err_buf:
1154         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1155         return err;
1156 }
1157
1158 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1159 {
1160         if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1161             (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
1162                 return MLX5_SRQ_RQ;
1163         else if (!qp->has_rq)
1164                 return MLX5_ZERO_LEN_RQ;
1165
1166         return MLX5_NON_ZERO_RQ;
1167 }
1168
1169 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1170                                     struct mlx5_ib_qp *qp,
1171                                     struct mlx5_ib_sq *sq, u32 tdn,
1172                                     struct ib_pd *pd)
1173 {
1174         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1175         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1176
1177         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1178         MLX5_SET(tisc, tisc, transport_domain, tdn);
1179         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1180                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1181
1182         return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1183 }
1184
1185 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1186                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1187 {
1188         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1189 }
1190
1191 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1192 {
1193         if (sq->flow_rule)
1194                 mlx5_del_flow_rules(sq->flow_rule);
1195         sq->flow_rule = NULL;
1196 }
1197
1198 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1199                                    struct ib_udata *udata,
1200                                    struct mlx5_ib_sq *sq, void *qpin,
1201                                    struct ib_pd *pd)
1202 {
1203         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1204         __be64 *pas;
1205         void *in;
1206         void *sqc;
1207         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1208         void *wq;
1209         int inlen;
1210         int err;
1211         int page_shift = 0;
1212         int npages;
1213         int ncont = 0;
1214         u32 offset = 0;
1215
1216         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1217                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1218                                &offset);
1219         if (err)
1220                 return err;
1221
1222         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1223         in = kvzalloc(inlen, GFP_KERNEL);
1224         if (!in) {
1225                 err = -ENOMEM;
1226                 goto err_umem;
1227         }
1228
1229         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1230         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1231         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1232         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1233                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1234         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1235         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1236         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1237         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1238         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1239         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1240             MLX5_CAP_ETH(dev->mdev, swp))
1241                 MLX5_SET(sqc, sqc, allow_swp, 1);
1242
1243         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1244         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1245         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1246         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1247         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1248         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1249         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1250         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1251         MLX5_SET(wq, wq, page_offset, offset);
1252
1253         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1254         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1255
1256         err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1257
1258         kvfree(in);
1259
1260         if (err)
1261                 goto err_umem;
1262
1263         return 0;
1264
1265 err_umem:
1266         ib_umem_release(sq->ubuffer.umem);
1267         sq->ubuffer.umem = NULL;
1268
1269         return err;
1270 }
1271
1272 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1273                                      struct mlx5_ib_sq *sq)
1274 {
1275         destroy_flow_rule_vport_sq(sq);
1276         mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1277         ib_umem_release(sq->ubuffer.umem);
1278 }
1279
1280 static size_t get_rq_pas_size(void *qpc)
1281 {
1282         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1283         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1284         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1285         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1286         u32 po_quanta     = 1 << (log_page_size - 6);
1287         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1288         u32 page_size     = 1 << log_page_size;
1289         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1290         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1291
1292         return rq_num_pas * sizeof(u64);
1293 }
1294
1295 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1296                                    struct mlx5_ib_rq *rq, void *qpin,
1297                                    size_t qpinlen, struct ib_pd *pd)
1298 {
1299         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1300         __be64 *pas;
1301         __be64 *qp_pas;
1302         void *in;
1303         void *rqc;
1304         void *wq;
1305         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1306         size_t rq_pas_size = get_rq_pas_size(qpc);
1307         size_t inlen;
1308         int err;
1309
1310         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1311                 return -EINVAL;
1312
1313         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1314         in = kvzalloc(inlen, GFP_KERNEL);
1315         if (!in)
1316                 return -ENOMEM;
1317
1318         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1319         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1320         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1321                 MLX5_SET(rqc, rqc, vsd, 1);
1322         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1323         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1324         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1325         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1326         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1327
1328         if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
1329                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1330
1331         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1332         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1333         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1334                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1335         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1336         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1337         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1338         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1339         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1340         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1341
1342         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1343         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1344         memcpy(pas, qp_pas, rq_pas_size);
1345
1346         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1347
1348         kvfree(in);
1349
1350         return err;
1351 }
1352
1353 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1354                                      struct mlx5_ib_rq *rq)
1355 {
1356         mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1357 }
1358
1359 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1360                                       struct mlx5_ib_rq *rq,
1361                                       u32 qp_flags_en,
1362                                       struct ib_pd *pd)
1363 {
1364         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1365                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1366                 mlx5_ib_disable_lb(dev, false, true);
1367         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1368 }
1369
1370 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1371                                     struct mlx5_ib_rq *rq, u32 tdn,
1372                                     u32 *qp_flags_en, struct ib_pd *pd,
1373                                     u32 *out)
1374 {
1375         u8 lb_flag = 0;
1376         u32 *in;
1377         void *tirc;
1378         int inlen;
1379         int err;
1380
1381         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1382         in = kvzalloc(inlen, GFP_KERNEL);
1383         if (!in)
1384                 return -ENOMEM;
1385
1386         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1387         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1388         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1389         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1390         MLX5_SET(tirc, tirc, transport_domain, tdn);
1391         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1392                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1393
1394         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1395                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1396
1397         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1398                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1399
1400         if (dev->is_rep) {
1401                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1402                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1403         }
1404
1405         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1406         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1407         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1408         rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1409         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1410                 err = mlx5_ib_enable_lb(dev, false, true);
1411
1412                 if (err)
1413                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1414         }
1415         kvfree(in);
1416
1417         return err;
1418 }
1419
1420 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1421                                 u32 *in, size_t inlen,
1422                                 struct ib_pd *pd,
1423                                 struct ib_udata *udata,
1424                                 struct mlx5_ib_create_qp_resp *resp)
1425 {
1426         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1427         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1428         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1429         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1430                 udata, struct mlx5_ib_ucontext, ibucontext);
1431         int err;
1432         u32 tdn = mucontext->tdn;
1433         u16 uid = to_mpd(pd)->uid;
1434         u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1435
1436         if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt)
1437                 return -EINVAL;
1438         if (qp->sq.wqe_cnt) {
1439                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1440                 if (err)
1441                         return err;
1442
1443                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1444                 if (err)
1445                         goto err_destroy_tis;
1446
1447                 if (uid) {
1448                         resp->tisn = sq->tisn;
1449                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1450                         resp->sqn = sq->base.mqp.qpn;
1451                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1452                 }
1453
1454                 sq->base.container_mibqp = qp;
1455                 sq->base.mqp.event = mlx5_ib_qp_event;
1456         }
1457
1458         if (qp->rq.wqe_cnt) {
1459                 rq->base.container_mibqp = qp;
1460
1461                 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
1462                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1463                 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
1464                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1465                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1466                 if (err)
1467                         goto err_destroy_sq;
1468
1469                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1470                                                out);
1471                 if (err)
1472                         goto err_destroy_rq;
1473
1474                 if (uid) {
1475                         resp->rqn = rq->base.mqp.qpn;
1476                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1477                         resp->tirn = rq->tirn;
1478                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1479                         if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1480                                 resp->tir_icm_addr = MLX5_GET(
1481                                         create_tir_out, out, icm_address_31_0);
1482                                 resp->tir_icm_addr |=
1483                                         (u64)MLX5_GET(create_tir_out, out,
1484                                                       icm_address_39_32)
1485                                         << 32;
1486                                 resp->tir_icm_addr |=
1487                                         (u64)MLX5_GET(create_tir_out, out,
1488                                                       icm_address_63_40)
1489                                         << 40;
1490                                 resp->comp_mask |=
1491                                         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1492                         }
1493                 }
1494         }
1495
1496         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1497                                                      rq->base.mqp.qpn;
1498         return 0;
1499
1500 err_destroy_rq:
1501         destroy_raw_packet_qp_rq(dev, rq);
1502 err_destroy_sq:
1503         if (!qp->sq.wqe_cnt)
1504                 return err;
1505         destroy_raw_packet_qp_sq(dev, sq);
1506 err_destroy_tis:
1507         destroy_raw_packet_qp_tis(dev, sq, pd);
1508
1509         return err;
1510 }
1511
1512 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1513                                   struct mlx5_ib_qp *qp)
1514 {
1515         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1516         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1517         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1518
1519         if (qp->rq.wqe_cnt) {
1520                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1521                 destroy_raw_packet_qp_rq(dev, rq);
1522         }
1523
1524         if (qp->sq.wqe_cnt) {
1525                 destroy_raw_packet_qp_sq(dev, sq);
1526                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1527         }
1528 }
1529
1530 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1531                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1532 {
1533         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1534         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1535
1536         sq->sq = &qp->sq;
1537         rq->rq = &qp->rq;
1538         sq->doorbell = &qp->db;
1539         rq->doorbell = &qp->db;
1540 }
1541
1542 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1543 {
1544         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1545                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1546                 mlx5_ib_disable_lb(dev, false, true);
1547         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1548                              to_mpd(qp->ibqp.pd)->uid);
1549 }
1550
1551 struct mlx5_create_qp_params {
1552         struct ib_udata *udata;
1553         size_t inlen;
1554         size_t outlen;
1555         size_t ucmd_size;
1556         void *ucmd;
1557         u8 is_rss_raw : 1;
1558         struct ib_qp_init_attr *attr;
1559         u32 uidx;
1560         struct mlx5_ib_create_qp_resp resp;
1561 };
1562
1563 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1564                                  struct mlx5_ib_qp *qp,
1565                                  struct mlx5_create_qp_params *params)
1566 {
1567         struct ib_qp_init_attr *init_attr = params->attr;
1568         struct mlx5_ib_create_qp_rss *ucmd = params->ucmd;
1569         struct ib_udata *udata = params->udata;
1570         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1571                 udata, struct mlx5_ib_ucontext, ibucontext);
1572         int inlen;
1573         int outlen;
1574         int err;
1575         u32 *in;
1576         u32 *out;
1577         void *tirc;
1578         void *hfso;
1579         u32 selected_fields = 0;
1580         u32 outer_l4;
1581         u32 tdn = mucontext->tdn;
1582         u8 lb_flag = 0;
1583
1584         if (ucmd->comp_mask) {
1585                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1586                 return -EOPNOTSUPP;
1587         }
1588
1589         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1590             !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1591                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1592                 return -EOPNOTSUPP;
1593         }
1594
1595         if (dev->is_rep)
1596                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1597
1598         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1599                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1600
1601         if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1602                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1603
1604         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1605         outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1606         in = kvzalloc(inlen + outlen, GFP_KERNEL);
1607         if (!in)
1608                 return -ENOMEM;
1609
1610         out = in + MLX5_ST_SZ_DW(create_tir_in);
1611         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1612         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1613         MLX5_SET(tirc, tirc, disp_type,
1614                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1615         MLX5_SET(tirc, tirc, indirect_table,
1616                  init_attr->rwq_ind_tbl->ind_tbl_num);
1617         MLX5_SET(tirc, tirc, transport_domain, tdn);
1618
1619         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1620
1621         if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1622                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1623
1624         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1625
1626         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1627                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1628         else
1629                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1630
1631         switch (ucmd->rx_hash_function) {
1632         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1633         {
1634                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1635                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1636
1637                 if (len != ucmd->rx_key_len) {
1638                         err = -EINVAL;
1639                         goto err;
1640                 }
1641
1642                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1643                 memcpy(rss_key, ucmd->rx_hash_key, len);
1644                 break;
1645         }
1646         default:
1647                 err = -EOPNOTSUPP;
1648                 goto err;
1649         }
1650
1651         if (!ucmd->rx_hash_fields_mask) {
1652                 /* special case when this TIR serves as steering entry without hashing */
1653                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1654                         goto create_tir;
1655                 err = -EINVAL;
1656                 goto err;
1657         }
1658
1659         if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1660              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1661              ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1662              (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1663                 err = -EINVAL;
1664                 goto err;
1665         }
1666
1667         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1668         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1669             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1670                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1671                          MLX5_L3_PROT_TYPE_IPV4);
1672         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1673                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1674                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1675                          MLX5_L3_PROT_TYPE_IPV6);
1676
1677         outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1678                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1679                            << 0 |
1680                    ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1681                     (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1682                            << 1 |
1683                    (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1684
1685         /* Check that only one l4 protocol is set */
1686         if (outer_l4 & (outer_l4 - 1)) {
1687                 err = -EINVAL;
1688                 goto err;
1689         }
1690
1691         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1692         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1693             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1694                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1695                          MLX5_L4_PROT_TYPE_TCP);
1696         else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1697                  (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1698                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1699                          MLX5_L4_PROT_TYPE_UDP);
1700
1701         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1702             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1703                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1704
1705         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1706             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1707                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1708
1709         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1710             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1711                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1712
1713         if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1714             (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1715                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1716
1717         if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1718                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1719
1720         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1721
1722 create_tir:
1723         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1724         err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1725
1726         qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1727         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1728                 err = mlx5_ib_enable_lb(dev, false, true);
1729
1730                 if (err)
1731                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1732                                              to_mpd(pd)->uid);
1733         }
1734
1735         if (err)
1736                 goto err;
1737
1738         if (mucontext->devx_uid) {
1739                 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1740                 params->resp.tirn = qp->rss_qp.tirn;
1741                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1742                         params->resp.tir_icm_addr =
1743                                 MLX5_GET(create_tir_out, out, icm_address_31_0);
1744                         params->resp.tir_icm_addr |=
1745                                 (u64)MLX5_GET(create_tir_out, out,
1746                                               icm_address_39_32)
1747                                 << 32;
1748                         params->resp.tir_icm_addr |=
1749                                 (u64)MLX5_GET(create_tir_out, out,
1750                                               icm_address_63_40)
1751                                 << 40;
1752                         params->resp.comp_mask |=
1753                                 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1754                 }
1755         }
1756
1757         kvfree(in);
1758         /* qpn is reserved for that QP */
1759         qp->trans_qp.base.mqp.qpn = 0;
1760         qp->is_rss = true;
1761         return 0;
1762
1763 err:
1764         kvfree(in);
1765         return err;
1766 }
1767
1768 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1769                                          struct ib_qp_init_attr *init_attr,
1770                                          struct mlx5_ib_create_qp *ucmd,
1771                                          void *qpc)
1772 {
1773         int scqe_sz;
1774         bool allow_scat_cqe = false;
1775
1776         if (ucmd)
1777                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1778
1779         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1780                 return;
1781
1782         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1783         if (scqe_sz == 128) {
1784                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1785                 return;
1786         }
1787
1788         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1789             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1790                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1791 }
1792
1793 static int atomic_size_to_mode(int size_mask)
1794 {
1795         /* driver does not support atomic_size > 256B
1796          * and does not know how to translate bigger sizes
1797          */
1798         int supported_size_mask = size_mask & 0x1ff;
1799         int log_max_size;
1800
1801         if (!supported_size_mask)
1802                 return -EOPNOTSUPP;
1803
1804         log_max_size = __fls(supported_size_mask);
1805
1806         if (log_max_size > 3)
1807                 return log_max_size;
1808
1809         return MLX5_ATOMIC_MODE_8B;
1810 }
1811
1812 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1813                            enum ib_qp_type qp_type)
1814 {
1815         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1816         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1817         int atomic_mode = -EOPNOTSUPP;
1818         int atomic_size_mask;
1819
1820         if (!atomic)
1821                 return -EOPNOTSUPP;
1822
1823         if (qp_type == MLX5_IB_QPT_DCT)
1824                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1825         else
1826                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1827
1828         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1829             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1830                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1831
1832         if (atomic_mode <= 0 &&
1833             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1834              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1835                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1836
1837         return atomic_mode;
1838 }
1839
1840 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1841                              struct mlx5_create_qp_params *params)
1842 {
1843         struct mlx5_ib_create_qp *ucmd = params->ucmd;
1844         struct ib_qp_init_attr *attr = params->attr;
1845         u32 uidx = params->uidx;
1846         struct mlx5_ib_resources *devr = &dev->devr;
1847         u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1848         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1849         struct mlx5_core_dev *mdev = dev->mdev;
1850         struct mlx5_ib_qp_base *base;
1851         unsigned long flags;
1852         void *qpc;
1853         u32 *in;
1854         int err;
1855
1856         mutex_init(&qp->mutex);
1857
1858         if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1859                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1860
1861         in = kvzalloc(inlen, GFP_KERNEL);
1862         if (!in)
1863                 return -ENOMEM;
1864
1865         if (MLX5_CAP_GEN(mdev, ece_support) && ucmd)
1866                 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
1867         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1868
1869         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1870         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1871         MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1872
1873         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1874                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1875         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1876                 MLX5_SET(qpc, qpc, cd_master, 1);
1877         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1878                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1879         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1880                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1881
1882         MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1883         MLX5_SET(qpc, qpc, no_sq, 1);
1884         MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1885         MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1886         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1887         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1888         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1889
1890         /* 0xffffff means we ask to work with cqe version 0 */
1891         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1892                 MLX5_SET(qpc, qpc, user_index, uidx);
1893
1894         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1895                 MLX5_SET(qpc, qpc, end_padding_mode,
1896                          MLX5_WQ_END_PAD_MODE_ALIGN);
1897                 /* Special case to clean flag */
1898                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1899         }
1900
1901         base = &qp->trans_qp.base;
1902         err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
1903         kvfree(in);
1904         if (err)
1905                 return err;
1906
1907         base->container_mibqp = qp;
1908         base->mqp.event = mlx5_ib_qp_event;
1909         if (MLX5_CAP_GEN(mdev, ece_support))
1910                 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
1911
1912         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1913         list_add_tail(&qp->qps_list, &dev->qp_list);
1914         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1915
1916         qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn;
1917         return 0;
1918 }
1919
1920 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1921                           struct mlx5_ib_qp *qp,
1922                           struct mlx5_create_qp_params *params)
1923 {
1924         struct ib_qp_init_attr *init_attr = params->attr;
1925         struct mlx5_ib_create_qp *ucmd = params->ucmd;
1926         u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1927         struct ib_udata *udata = params->udata;
1928         u32 uidx = params->uidx;
1929         struct mlx5_ib_resources *devr = &dev->devr;
1930         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1931         struct mlx5_core_dev *mdev = dev->mdev;
1932         struct mlx5_ib_cq *send_cq;
1933         struct mlx5_ib_cq *recv_cq;
1934         unsigned long flags;
1935         struct mlx5_ib_qp_base *base;
1936         int mlx5_st;
1937         void *qpc;
1938         u32 *in;
1939         int err;
1940
1941         mutex_init(&qp->mutex);
1942         spin_lock_init(&qp->sq.lock);
1943         spin_lock_init(&qp->rq.lock);
1944
1945         mlx5_st = to_mlx5_st(qp->type);
1946         if (mlx5_st < 0)
1947                 return -EINVAL;
1948
1949         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1950                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1951
1952         if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1953                 qp->underlay_qpn = init_attr->source_qpn;
1954
1955         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1956                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
1957                &qp->raw_packet_qp.rq.base :
1958                &qp->trans_qp.base;
1959
1960         qp->has_rq = qp_has_rq(init_attr);
1961         err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
1962         if (err) {
1963                 mlx5_ib_dbg(dev, "err %d\n", err);
1964                 return err;
1965         }
1966
1967         if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1968             ucmd->rq_wqe_count != qp->rq.wqe_cnt)
1969                 return -EINVAL;
1970
1971         if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1972                 return -EINVAL;
1973
1974         err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, &params->resp,
1975                               &inlen, base, ucmd);
1976         if (err)
1977                 return err;
1978
1979         if (is_sqp(init_attr->qp_type))
1980                 qp->port = init_attr->port_num;
1981
1982         if (MLX5_CAP_GEN(mdev, ece_support))
1983                 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
1984         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1985
1986         MLX5_SET(qpc, qpc, st, mlx5_st);
1987         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1988         MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
1989
1990         if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
1991                 MLX5_SET(qpc, qpc, wq_signature, 1);
1992
1993         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1994                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1995
1996         if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1997                 MLX5_SET(qpc, qpc, cd_master, 1);
1998         if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1999                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2000         if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
2001                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2002         if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
2003                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2004         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2005             (init_attr->qp_type == IB_QPT_RC ||
2006              init_attr->qp_type == IB_QPT_UC)) {
2007                 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
2008
2009                 MLX5_SET(qpc, qpc, cs_res,
2010                          rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2011                                           MLX5_RES_SCAT_DATA32_CQE);
2012         }
2013         if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2014             (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
2015                 configure_requester_scat_cqe(dev, init_attr, ucmd, qpc);
2016
2017         if (qp->rq.wqe_cnt) {
2018                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2019                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2020         }
2021
2022         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2023
2024         if (qp->sq.wqe_cnt) {
2025                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2026         } else {
2027                 MLX5_SET(qpc, qpc, no_sq, 1);
2028                 if (init_attr->srq &&
2029                     init_attr->srq->srq_type == IB_SRQT_TM)
2030                         MLX5_SET(qpc, qpc, offload_type,
2031                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2032         }
2033
2034         /* Set default resources */
2035         switch (init_attr->qp_type) {
2036         case IB_QPT_XRC_INI:
2037                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2038                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2039                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2040                 break;
2041         default:
2042                 if (init_attr->srq) {
2043                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2044                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2045                 } else {
2046                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2047                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2048                 }
2049         }
2050
2051         if (init_attr->send_cq)
2052                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2053
2054         if (init_attr->recv_cq)
2055                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2056
2057         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2058
2059         /* 0xffffff means we ask to work with cqe version 0 */
2060         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2061                 MLX5_SET(qpc, qpc, user_index, uidx);
2062
2063         if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2064             init_attr->qp_type != IB_QPT_RAW_PACKET) {
2065                 MLX5_SET(qpc, qpc, end_padding_mode,
2066                          MLX5_WQ_END_PAD_MODE_ALIGN);
2067                 /* Special case to clean flag */
2068                 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
2069         }
2070
2071         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2072             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2073                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
2074                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2075                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2076                                            &params->resp);
2077         } else
2078                 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2079
2080         kvfree(in);
2081         if (err)
2082                 goto err_create;
2083
2084         base->container_mibqp = qp;
2085         base->mqp.event = mlx5_ib_qp_event;
2086         if (MLX5_CAP_GEN(mdev, ece_support))
2087                 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
2088
2089         get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
2090                 &send_cq, &recv_cq);
2091         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2092         mlx5_ib_lock_cqs(send_cq, recv_cq);
2093         /* Maintain device to QPs access, needed for further handling via reset
2094          * flow
2095          */
2096         list_add_tail(&qp->qps_list, &dev->qp_list);
2097         /* Maintain CQ to QPs access, needed for further handling via reset flow
2098          */
2099         if (send_cq)
2100                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2101         if (recv_cq)
2102                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2103         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2104         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2105
2106         return 0;
2107
2108 err_create:
2109         destroy_qp(dev, qp, base, udata);
2110         return err;
2111 }
2112
2113 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2114                             struct mlx5_ib_qp *qp,
2115                             struct mlx5_create_qp_params *params)
2116 {
2117         struct ib_qp_init_attr *attr = params->attr;
2118         u32 uidx = params->uidx;
2119         struct mlx5_ib_resources *devr = &dev->devr;
2120         u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
2121         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2122         struct mlx5_core_dev *mdev = dev->mdev;
2123         struct mlx5_ib_cq *send_cq;
2124         struct mlx5_ib_cq *recv_cq;
2125         unsigned long flags;
2126         struct mlx5_ib_qp_base *base;
2127         int mlx5_st;
2128         void *qpc;
2129         u32 *in;
2130         int err;
2131
2132         mutex_init(&qp->mutex);
2133         spin_lock_init(&qp->sq.lock);
2134         spin_lock_init(&qp->rq.lock);
2135
2136         mlx5_st = to_mlx5_st(qp->type);
2137         if (mlx5_st < 0)
2138                 return -EINVAL;
2139
2140         if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2141                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2142
2143         base = &qp->trans_qp.base;
2144
2145         qp->has_rq = qp_has_rq(attr);
2146         err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2147         if (err) {
2148                 mlx5_ib_dbg(dev, "err %d\n", err);
2149                 return err;
2150         }
2151
2152         err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2153         if (err)
2154                 return err;
2155
2156         if (is_sqp(attr->qp_type))
2157                 qp->port = attr->port_num;
2158
2159         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2160
2161         MLX5_SET(qpc, qpc, st, mlx5_st);
2162         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2163
2164         if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2165                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2166         else
2167                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2168
2169
2170         if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2171                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2172
2173         if (qp->rq.wqe_cnt) {
2174                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2175                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2176         }
2177
2178         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2179
2180         if (qp->sq.wqe_cnt)
2181                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2182         else
2183                 MLX5_SET(qpc, qpc, no_sq, 1);
2184
2185         if (attr->srq) {
2186                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2187                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2188                          to_msrq(attr->srq)->msrq.srqn);
2189         } else {
2190                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2191                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2192                          to_msrq(devr->s1)->msrq.srqn);
2193         }
2194
2195         if (attr->send_cq)
2196                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2197
2198         if (attr->recv_cq)
2199                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2200
2201         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2202
2203         /* 0xffffff means we ask to work with cqe version 0 */
2204         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2205                 MLX5_SET(qpc, qpc, user_index, uidx);
2206
2207         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2208         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2209                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2210
2211         err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2212         kvfree(in);
2213         if (err)
2214                 goto err_create;
2215
2216         base->container_mibqp = qp;
2217         base->mqp.event = mlx5_ib_qp_event;
2218
2219         get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2220                 &send_cq, &recv_cq);
2221         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2222         mlx5_ib_lock_cqs(send_cq, recv_cq);
2223         /* Maintain device to QPs access, needed for further handling via reset
2224          * flow
2225          */
2226         list_add_tail(&qp->qps_list, &dev->qp_list);
2227         /* Maintain CQ to QPs access, needed for further handling via reset flow
2228          */
2229         if (send_cq)
2230                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2231         if (recv_cq)
2232                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2233         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2234         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2235
2236         return 0;
2237
2238 err_create:
2239         destroy_qp(dev, qp, base, NULL);
2240         return err;
2241 }
2242
2243 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2244         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2245 {
2246         if (send_cq) {
2247                 if (recv_cq) {
2248                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2249                                 spin_lock(&send_cq->lock);
2250                                 spin_lock_nested(&recv_cq->lock,
2251                                                  SINGLE_DEPTH_NESTING);
2252                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2253                                 spin_lock(&send_cq->lock);
2254                                 __acquire(&recv_cq->lock);
2255                         } else {
2256                                 spin_lock(&recv_cq->lock);
2257                                 spin_lock_nested(&send_cq->lock,
2258                                                  SINGLE_DEPTH_NESTING);
2259                         }
2260                 } else {
2261                         spin_lock(&send_cq->lock);
2262                         __acquire(&recv_cq->lock);
2263                 }
2264         } else if (recv_cq) {
2265                 spin_lock(&recv_cq->lock);
2266                 __acquire(&send_cq->lock);
2267         } else {
2268                 __acquire(&send_cq->lock);
2269                 __acquire(&recv_cq->lock);
2270         }
2271 }
2272
2273 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2274         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2275 {
2276         if (send_cq) {
2277                 if (recv_cq) {
2278                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2279                                 spin_unlock(&recv_cq->lock);
2280                                 spin_unlock(&send_cq->lock);
2281                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2282                                 __release(&recv_cq->lock);
2283                                 spin_unlock(&send_cq->lock);
2284                         } else {
2285                                 spin_unlock(&send_cq->lock);
2286                                 spin_unlock(&recv_cq->lock);
2287                         }
2288                 } else {
2289                         __release(&recv_cq->lock);
2290                         spin_unlock(&send_cq->lock);
2291                 }
2292         } else if (recv_cq) {
2293                 __release(&send_cq->lock);
2294                 spin_unlock(&recv_cq->lock);
2295         } else {
2296                 __release(&recv_cq->lock);
2297                 __release(&send_cq->lock);
2298         }
2299 }
2300
2301 static void get_cqs(enum ib_qp_type qp_type,
2302                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2303                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2304 {
2305         switch (qp_type) {
2306         case IB_QPT_XRC_TGT:
2307                 *send_cq = NULL;
2308                 *recv_cq = NULL;
2309                 break;
2310         case MLX5_IB_QPT_REG_UMR:
2311         case IB_QPT_XRC_INI:
2312                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2313                 *recv_cq = NULL;
2314                 break;
2315
2316         case IB_QPT_SMI:
2317         case MLX5_IB_QPT_HW_GSI:
2318         case IB_QPT_RC:
2319         case IB_QPT_UC:
2320         case IB_QPT_UD:
2321         case IB_QPT_RAW_PACKET:
2322                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2323                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2324                 break;
2325         default:
2326                 *send_cq = NULL;
2327                 *recv_cq = NULL;
2328                 break;
2329         }
2330 }
2331
2332 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2333                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2334                                 u8 lag_tx_affinity);
2335
2336 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2337                               struct ib_udata *udata)
2338 {
2339         struct mlx5_ib_cq *send_cq, *recv_cq;
2340         struct mlx5_ib_qp_base *base;
2341         unsigned long flags;
2342         int err;
2343
2344         if (qp->is_rss) {
2345                 destroy_rss_raw_qp_tir(dev, qp);
2346                 return;
2347         }
2348
2349         base = (qp->type == IB_QPT_RAW_PACKET ||
2350                 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2351                        &qp->raw_packet_qp.rq.base :
2352                        &qp->trans_qp.base;
2353
2354         if (qp->state != IB_QPS_RESET) {
2355                 if (qp->type != IB_QPT_RAW_PACKET &&
2356                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
2357                         err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2358                                                   NULL, &base->mqp, NULL);
2359                 } else {
2360                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2361                                 .operation = MLX5_CMD_OP_2RST_QP
2362                         };
2363
2364                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2365                 }
2366                 if (err)
2367                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2368                                      base->mqp.qpn);
2369         }
2370
2371         get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq,
2372                 &recv_cq);
2373
2374         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2375         mlx5_ib_lock_cqs(send_cq, recv_cq);
2376         /* del from lists under both locks above to protect reset flow paths */
2377         list_del(&qp->qps_list);
2378         if (send_cq)
2379                 list_del(&qp->cq_send_list);
2380
2381         if (recv_cq)
2382                 list_del(&qp->cq_recv_list);
2383
2384         if (!udata) {
2385                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2386                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2387                 if (send_cq != recv_cq)
2388                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2389                                            NULL);
2390         }
2391         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2392         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2393
2394         if (qp->type == IB_QPT_RAW_PACKET ||
2395             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2396                 destroy_raw_packet_qp(dev, qp);
2397         } else {
2398                 err = mlx5_core_destroy_qp(dev, &base->mqp);
2399                 if (err)
2400                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2401                                      base->mqp.qpn);
2402         }
2403
2404         destroy_qp(dev, qp, base, udata);
2405 }
2406
2407 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2408                       struct mlx5_ib_qp *qp,
2409                       struct mlx5_create_qp_params *params)
2410 {
2411         struct ib_qp_init_attr *attr = params->attr;
2412         struct mlx5_ib_create_qp *ucmd = params->ucmd;
2413         u32 uidx = params->uidx;
2414         void *dctc;
2415
2416         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2417         if (!qp->dct.in)
2418                 return -ENOMEM;
2419
2420         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2421         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2422         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2423         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2424         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2425         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2426         MLX5_SET(dctc, dctc, user_index, uidx);
2427         if (MLX5_CAP_GEN(dev->mdev, ece_support))
2428                 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
2429
2430         if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
2431                 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2432
2433                 if (rcqe_sz == 128)
2434                         MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2435         }
2436
2437         qp->state = IB_QPS_RESET;
2438
2439         return 0;
2440 }
2441
2442 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2443                          enum ib_qp_type *type)
2444 {
2445         if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2446                 goto out;
2447
2448         switch (attr->qp_type) {
2449         case IB_QPT_XRC_TGT:
2450         case IB_QPT_XRC_INI:
2451                 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2452                         goto out;
2453                 fallthrough;
2454         case IB_QPT_RC:
2455         case IB_QPT_UC:
2456         case IB_QPT_SMI:
2457         case MLX5_IB_QPT_HW_GSI:
2458         case IB_QPT_DRIVER:
2459         case IB_QPT_GSI:
2460                 if (dev->profile == &raw_eth_profile)
2461                         goto out;
2462         case IB_QPT_RAW_PACKET:
2463         case IB_QPT_UD:
2464         case MLX5_IB_QPT_REG_UMR:
2465                 break;
2466         default:
2467                 goto out;
2468         }
2469
2470         *type = attr->qp_type;
2471         return 0;
2472
2473 out:
2474         mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2475         return -EOPNOTSUPP;
2476 }
2477
2478 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2479                             struct ib_qp_init_attr *attr,
2480                             struct ib_udata *udata)
2481 {
2482         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2483                 udata, struct mlx5_ib_ucontext, ibucontext);
2484
2485         if (!udata) {
2486                 /* Kernel create_qp callers */
2487                 if (attr->rwq_ind_tbl)
2488                         return -EOPNOTSUPP;
2489
2490                 switch (attr->qp_type) {
2491                 case IB_QPT_RAW_PACKET:
2492                 case IB_QPT_DRIVER:
2493                         return -EOPNOTSUPP;
2494                 default:
2495                         return 0;
2496                 }
2497         }
2498
2499         /* Userspace create_qp callers */
2500         if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2501                 mlx5_ib_dbg(dev,
2502                         "Raw Packet QP is only supported for CQE version > 0\n");
2503                 return -EINVAL;
2504         }
2505
2506         if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2507                 mlx5_ib_dbg(dev,
2508                             "Wrong QP type %d for the RWQ indirect table\n",
2509                             attr->qp_type);
2510                 return -EINVAL;
2511         }
2512
2513         switch (attr->qp_type) {
2514         case IB_QPT_SMI:
2515         case MLX5_IB_QPT_HW_GSI:
2516         case MLX5_IB_QPT_REG_UMR:
2517         case IB_QPT_GSI:
2518                 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2519                             attr->qp_type);
2520                 return -EINVAL;
2521         default:
2522                 break;
2523         }
2524
2525         /*
2526          * We don't need to see this warning, it means that kernel code
2527          * missing ib_pd. Placed here to catch developer's mistakes.
2528          */
2529         WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2530                   "There is a missing PD pointer assignment\n");
2531         return 0;
2532 }
2533
2534 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2535                                 bool cond, struct mlx5_ib_qp *qp)
2536 {
2537         if (!(*flags & flag))
2538                 return;
2539
2540         if (cond) {
2541                 qp->flags_en |= flag;
2542                 *flags &= ~flag;
2543                 return;
2544         }
2545
2546         if (flag == MLX5_QP_FLAG_SCATTER_CQE) {
2547                 /*
2548                  * We don't return error if this flag was provided,
2549                  * and mlx5 doesn't have right capability.
2550                  */
2551                 *flags &= ~MLX5_QP_FLAG_SCATTER_CQE;
2552                 return;
2553         }
2554         mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2555 }
2556
2557 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2558                                 void *ucmd, struct ib_qp_init_attr *attr)
2559 {
2560         struct mlx5_core_dev *mdev = dev->mdev;
2561         bool cond;
2562         int flags;
2563
2564         if (attr->rwq_ind_tbl)
2565                 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2566         else
2567                 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
2568
2569         switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2570         case MLX5_QP_FLAG_TYPE_DCI:
2571                 qp->type = MLX5_IB_QPT_DCI;
2572                 break;
2573         case MLX5_QP_FLAG_TYPE_DCT:
2574                 qp->type = MLX5_IB_QPT_DCT;
2575                 break;
2576         default:
2577                 if (qp->type != IB_QPT_DRIVER)
2578                         break;
2579                 /*
2580                  * It is IB_QPT_DRIVER and or no subtype or
2581                  * wrong subtype were provided.
2582                  */
2583                 return -EINVAL;
2584         }
2585
2586         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2587         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2588
2589         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2590         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2591                             MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2592
2593         if (qp->type == IB_QPT_RAW_PACKET) {
2594                 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2595                        MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2596                        MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2597                 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2598                                     cond, qp);
2599                 process_vendor_flag(dev, &flags,
2600                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2601                                     qp);
2602                 process_vendor_flag(dev, &flags,
2603                                     MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2604                                     qp);
2605         }
2606
2607         if (qp->type == IB_QPT_RC)
2608                 process_vendor_flag(dev, &flags,
2609                                     MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2610                                     MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2611
2612         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2613         process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2614
2615         cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2616                                 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2617                                 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC);
2618         if (attr->rwq_ind_tbl && cond) {
2619                 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n",
2620                             cond);
2621                 return -EINVAL;
2622         }
2623
2624         if (flags)
2625                 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2626
2627         return (flags) ? -EINVAL : 0;
2628         }
2629
2630 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2631                                 bool cond, struct mlx5_ib_qp *qp)
2632 {
2633         if (!(*flags & flag))
2634                 return;
2635
2636         if (cond) {
2637                 qp->flags |= flag;
2638                 *flags &= ~flag;
2639                 return;
2640         }
2641
2642         if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2643                 /*
2644                  * Special case, if condition didn't meet, it won't be error,
2645                  * just different in-kernel flow.
2646                  */
2647                 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2648                 return;
2649         }
2650         mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2651 }
2652
2653 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2654                                 struct ib_qp_init_attr *attr)
2655 {
2656         enum ib_qp_type qp_type = qp->type;
2657         struct mlx5_core_dev *mdev = dev->mdev;
2658         int create_flags = attr->create_flags;
2659         bool cond;
2660
2661         if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile)
2662                 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST)
2663                         return -EINVAL;
2664
2665         if (qp_type == MLX5_IB_QPT_DCT)
2666                 return (create_flags) ? -EINVAL : 0;
2667
2668         if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2669                 return (create_flags) ? -EINVAL : 0;
2670
2671         process_create_flag(dev, &create_flags,
2672                             IB_QP_CREATE_INTEGRITY_EN,
2673                             MLX5_CAP_GEN(mdev, sho), qp);
2674         process_create_flag(dev, &create_flags,
2675                             IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2676                             MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2677         process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2678                             MLX5_CAP_GEN(mdev, cd), qp);
2679         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2680                             MLX5_CAP_GEN(mdev, cd), qp);
2681         process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2682                             MLX5_CAP_GEN(mdev, cd), qp);
2683
2684         if (qp_type == IB_QPT_UD) {
2685                 process_create_flag(dev, &create_flags,
2686                                     IB_QP_CREATE_IPOIB_UD_LSO,
2687                                     MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2688                                     qp);
2689                 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2690                 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2691                                     cond, qp);
2692         }
2693
2694         if (qp_type == IB_QPT_RAW_PACKET) {
2695                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2696                        MLX5_CAP_ETH(mdev, scatter_fcs);
2697                 process_create_flag(dev, &create_flags,
2698                                     IB_QP_CREATE_SCATTER_FCS, cond, qp);
2699
2700                 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2701                        MLX5_CAP_ETH(mdev, vlan_cap);
2702                 process_create_flag(dev, &create_flags,
2703                                     IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2704         }
2705
2706         process_create_flag(dev, &create_flags,
2707                             IB_QP_CREATE_PCI_WRITE_END_PADDING,
2708                             MLX5_CAP_GEN(mdev, end_pad), qp);
2709
2710         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2711                             qp_type != MLX5_IB_QPT_REG_UMR, qp);
2712         process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2713                             true, qp);
2714
2715         if (create_flags)
2716                 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2717                             create_flags);
2718
2719         return (create_flags) ? -EINVAL : 0;
2720 }
2721
2722 static int process_udata_size(struct mlx5_ib_dev *dev,
2723                               struct mlx5_create_qp_params *params)
2724 {
2725         size_t ucmd = sizeof(struct mlx5_ib_create_qp);
2726         struct ib_udata *udata = params->udata;
2727         size_t outlen = udata->outlen;
2728         size_t inlen = udata->inlen;
2729
2730         params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp));
2731         params->ucmd_size = ucmd;
2732         if (!params->is_rss_raw) {
2733                 /* User has old rdma-core, which doesn't support ECE */
2734                 size_t min_inlen =
2735                         offsetof(struct mlx5_ib_create_qp, ece_options);
2736
2737                 /*
2738                  * We will check in check_ucmd_data() that user
2739                  * cleared everything after inlen.
2740                  */
2741                 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd);
2742                 goto out;
2743         }
2744
2745         /* RSS RAW QP */
2746         if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
2747                 return -EINVAL;
2748
2749         if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index))
2750                 return -EINVAL;
2751
2752         ucmd = sizeof(struct mlx5_ib_create_qp_rss);
2753         params->ucmd_size = ucmd;
2754         if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
2755                 return -EINVAL;
2756
2757         params->inlen = min(ucmd, inlen);
2758 out:
2759         if (!params->inlen)
2760                 mlx5_ib_dbg(dev, "udata is too small\n");
2761
2762         return (params->inlen) ? 0 : -EINVAL;
2763 }
2764
2765 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2766                      struct mlx5_ib_qp *qp,
2767                      struct mlx5_create_qp_params *params)
2768 {
2769         int err;
2770
2771         if (params->is_rss_raw) {
2772                 err = create_rss_raw_qp_tir(dev, pd, qp, params);
2773                 goto out;
2774         }
2775
2776         if (qp->type == MLX5_IB_QPT_DCT) {
2777                 err = create_dct(dev, pd, qp, params);
2778                 goto out;
2779         }
2780
2781         if (qp->type == IB_QPT_XRC_TGT) {
2782                 err = create_xrc_tgt_qp(dev, qp, params);
2783                 goto out;
2784         }
2785
2786         if (params->udata)
2787                 err = create_user_qp(dev, pd, qp, params);
2788         else
2789                 err = create_kernel_qp(dev, pd, qp, params);
2790
2791 out:
2792         if (err) {
2793                 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type);
2794                 return err;
2795         }
2796
2797         if (is_qp0(qp->type))
2798                 qp->ibqp.qp_num = 0;
2799         else if (is_qp1(qp->type))
2800                 qp->ibqp.qp_num = 1;
2801         else
2802                 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2803
2804         mlx5_ib_dbg(dev,
2805                 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n",
2806                 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2807                 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn :
2808                                         -1,
2809                 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn :
2810                                         -1,
2811                 params->resp.ece_options);
2812
2813         return 0;
2814 }
2815
2816 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2817                          struct ib_qp_init_attr *attr)
2818 {
2819         int ret = 0;
2820
2821         switch (qp->type) {
2822         case MLX5_IB_QPT_DCT:
2823                 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2824                 break;
2825         case MLX5_IB_QPT_DCI:
2826                 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2827                               -EINVAL :
2828                               0;
2829                 break;
2830         case IB_QPT_RAW_PACKET:
2831                 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2832                 break;
2833         default:
2834                 break;
2835         }
2836
2837         if (ret)
2838                 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2839
2840         return ret;
2841 }
2842
2843 static int get_qp_uidx(struct mlx5_ib_qp *qp,
2844                        struct mlx5_create_qp_params *params)
2845 {
2846         struct mlx5_ib_create_qp *ucmd = params->ucmd;
2847         struct ib_udata *udata = params->udata;
2848         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2849                 udata, struct mlx5_ib_ucontext, ibucontext);
2850
2851         if (params->is_rss_raw)
2852                 return 0;
2853
2854         return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &params->uidx);
2855 }
2856
2857 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2858 {
2859         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2860
2861         if (mqp->state == IB_QPS_RTR) {
2862                 int err;
2863
2864                 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2865                 if (err) {
2866                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2867                         return err;
2868                 }
2869         }
2870
2871         kfree(mqp->dct.in);
2872         kfree(mqp);
2873         return 0;
2874 }
2875
2876 static int check_ucmd_data(struct mlx5_ib_dev *dev,
2877                            struct mlx5_create_qp_params *params)
2878 {
2879         struct ib_udata *udata = params->udata;
2880         size_t size, last;
2881         int ret;
2882
2883         if (params->is_rss_raw)
2884                 /*
2885                  * These QPs don't have "reserved" field in their
2886                  * create_qp input struct, so their data is always valid.
2887                  */
2888                 last = sizeof(struct mlx5_ib_create_qp_rss);
2889         else
2890                 last = offsetof(struct mlx5_ib_create_qp, reserved);
2891
2892         if (udata->inlen <= last)
2893                 return 0;
2894
2895         /*
2896          * User provides different create_qp structures based on the
2897          * flow and we need to know if he cleared memory after our
2898          * struct create_qp ends.
2899          */
2900         size = udata->inlen - last;
2901         ret = ib_is_udata_cleared(params->udata, last, size);
2902         if (!ret)
2903                 mlx5_ib_dbg(
2904                         dev,
2905                         "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n",
2906                         udata->inlen, params->ucmd_size, last, size);
2907         return ret ? 0 : -EINVAL;
2908 }
2909
2910 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr,
2911                                 struct ib_udata *udata)
2912 {
2913         struct mlx5_create_qp_params params = {};
2914         struct mlx5_ib_dev *dev;
2915         struct mlx5_ib_qp *qp;
2916         enum ib_qp_type type;
2917         int err;
2918
2919         dev = pd ? to_mdev(pd->device) :
2920                    to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device);
2921
2922         err = check_qp_type(dev, attr, &type);
2923         if (err)
2924                 return ERR_PTR(err);
2925
2926         err = check_valid_flow(dev, pd, attr, udata);
2927         if (err)
2928                 return ERR_PTR(err);
2929
2930         if (attr->qp_type == IB_QPT_GSI)
2931                 return mlx5_ib_gsi_create_qp(pd, attr);
2932
2933         params.udata = udata;
2934         params.uidx = MLX5_IB_DEFAULT_UIDX;
2935         params.attr = attr;
2936         params.is_rss_raw = !!attr->rwq_ind_tbl;
2937
2938         if (udata) {
2939                 err = process_udata_size(dev, &params);
2940                 if (err)
2941                         return ERR_PTR(err);
2942
2943                 err = check_ucmd_data(dev, &params);
2944                 if (err)
2945                         return ERR_PTR(err);
2946
2947                 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL);
2948                 if (!params.ucmd)
2949                         return ERR_PTR(-ENOMEM);
2950
2951                 err = ib_copy_from_udata(params.ucmd, udata, params.inlen);
2952                 if (err)
2953                         goto free_ucmd;
2954         }
2955
2956         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2957         if (!qp) {
2958                 err = -ENOMEM;
2959                 goto free_ucmd;
2960         }
2961
2962         qp->type = type;
2963         if (udata) {
2964                 err = process_vendor_flags(dev, qp, params.ucmd, attr);
2965                 if (err)
2966                         goto free_qp;
2967
2968                 err = get_qp_uidx(qp, &params);
2969                 if (err)
2970                         goto free_qp;
2971         }
2972         err = process_create_flags(dev, qp, attr);
2973         if (err)
2974                 goto free_qp;
2975
2976         err = check_qp_attr(dev, qp, attr);
2977         if (err)
2978                 goto free_qp;
2979
2980         err = create_qp(dev, pd, qp, &params);
2981         if (err)
2982                 goto free_qp;
2983
2984         kfree(params.ucmd);
2985         params.ucmd = NULL;
2986
2987         if (udata)
2988                 /*
2989                  * It is safe to copy response for all user create QP flows,
2990                  * including MLX5_IB_QPT_DCT, which doesn't need it.
2991                  * In that case, resp will be filled with zeros.
2992                  */
2993                 err = ib_copy_to_udata(udata, &params.resp, params.outlen);
2994         if (err)
2995                 goto destroy_qp;
2996
2997         return &qp->ibqp;
2998
2999 destroy_qp:
3000         if (qp->type == MLX5_IB_QPT_DCT) {
3001                 mlx5_ib_destroy_dct(qp);
3002         } else {
3003                 /*
3004                  * The two lines below are temp solution till QP allocation
3005                  * will be moved to be under IB/core responsiblity.
3006                  */
3007                 qp->ibqp.send_cq = attr->send_cq;
3008                 qp->ibqp.recv_cq = attr->recv_cq;
3009                 destroy_qp_common(dev, qp, udata);
3010         }
3011
3012         qp = NULL;
3013 free_qp:
3014         kfree(qp);
3015 free_ucmd:
3016         kfree(params.ucmd);
3017         return ERR_PTR(err);
3018 }
3019
3020 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
3021 {
3022         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3023         struct mlx5_ib_qp *mqp = to_mqp(qp);
3024
3025         if (unlikely(qp->qp_type == IB_QPT_GSI))
3026                 return mlx5_ib_gsi_destroy_qp(qp);
3027
3028         if (mqp->type == MLX5_IB_QPT_DCT)
3029                 return mlx5_ib_destroy_dct(mqp);
3030
3031         destroy_qp_common(dev, mqp, udata);
3032
3033         kfree(mqp);
3034
3035         return 0;
3036 }
3037
3038 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
3039                                 const struct ib_qp_attr *attr, int attr_mask,
3040                                 void *qpc)
3041 {
3042         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
3043         u8 dest_rd_atomic;
3044         u32 access_flags;
3045
3046         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3047                 dest_rd_atomic = attr->max_dest_rd_atomic;
3048         else
3049                 dest_rd_atomic = qp->trans_qp.resp_depth;
3050
3051         if (attr_mask & IB_QP_ACCESS_FLAGS)
3052                 access_flags = attr->qp_access_flags;
3053         else
3054                 access_flags = qp->trans_qp.atomic_rd_en;
3055
3056         if (!dest_rd_atomic)
3057                 access_flags &= IB_ACCESS_REMOTE_WRITE;
3058
3059         MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
3060
3061         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3062                 int atomic_mode;
3063
3064                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3065                 if (atomic_mode < 0)
3066                         return -EOPNOTSUPP;
3067
3068                 MLX5_SET(qpc, qpc, rae, 1);
3069                 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
3070         }
3071
3072         MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3073         return 0;
3074 }
3075
3076 enum {
3077         MLX5_PATH_FLAG_FL       = 1 << 0,
3078         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
3079         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
3080 };
3081
3082 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3083 {
3084         if (rate == IB_RATE_PORT_CURRENT)
3085                 return 0;
3086
3087         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
3088                 return -EINVAL;
3089
3090         while (rate != IB_RATE_PORT_CURRENT &&
3091                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
3092                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
3093                 --rate;
3094
3095         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
3096 }
3097
3098 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
3099                                       struct mlx5_ib_sq *sq, u8 sl,
3100                                       struct ib_pd *pd)
3101 {
3102         void *in;
3103         void *tisc;
3104         int inlen;
3105         int err;
3106
3107         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3108         in = kvzalloc(inlen, GFP_KERNEL);
3109         if (!in)
3110                 return -ENOMEM;
3111
3112         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
3113         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3114
3115         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3116         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3117
3118         err = mlx5_core_modify_tis(dev, sq->tisn, in);
3119
3120         kvfree(in);
3121
3122         return err;
3123 }
3124
3125 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
3126                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
3127                                          struct ib_pd *pd)
3128 {
3129         void *in;
3130         void *tisc;
3131         int inlen;
3132         int err;
3133
3134         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3135         in = kvzalloc(inlen, GFP_KERNEL);
3136         if (!in)
3137                 return -ENOMEM;
3138
3139         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
3140         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3141
3142         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3143         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3144
3145         err = mlx5_core_modify_tis(dev, sq->tisn, in);
3146
3147         kvfree(in);
3148
3149         return err;
3150 }
3151
3152 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
3153                                     u32 lqpn, u32 rqpn)
3154
3155 {
3156         u32 fl = ah->grh.flow_label;
3157
3158         if (!fl)
3159                 fl = rdma_calc_flow_label(lqpn, rqpn);
3160
3161         MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
3162 }
3163
3164 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3165                          const struct rdma_ah_attr *ah, void *path, u8 port,
3166                          int attr_mask, u32 path_flags,
3167                          const struct ib_qp_attr *attr, bool alt)
3168 {
3169         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
3170         int err;
3171         enum ib_gid_type gid_type;
3172         u8 ah_flags = rdma_ah_get_ah_flags(ah);
3173         u8 sl = rdma_ah_get_sl(ah);
3174
3175         if (attr_mask & IB_QP_PKEY_INDEX)
3176                 MLX5_SET(ads, path, pkey_index,
3177                          alt ? attr->alt_pkey_index : attr->pkey_index);
3178
3179         if (ah_flags & IB_AH_GRH) {
3180                 if (grh->sgid_index >=
3181                     dev->mdev->port_caps[port - 1].gid_table_len) {
3182                         pr_err("sgid_index (%u) too large. max is %d\n",
3183                                grh->sgid_index,
3184                                dev->mdev->port_caps[port - 1].gid_table_len);
3185                         return -EINVAL;
3186                 }
3187         }
3188
3189         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
3190                 if (!(ah_flags & IB_AH_GRH))
3191                         return -EINVAL;
3192
3193                 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
3194                                 ah->roce.dmac);
3195                 if ((qp->ibqp.qp_type == IB_QPT_RC ||
3196                      qp->ibqp.qp_type == IB_QPT_UC ||
3197                      qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3198                      qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
3199                     (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) &&
3200                     (attr_mask & IB_QP_DEST_QPN))
3201                         mlx5_set_path_udp_sport(path, ah,
3202                                                 qp->ibqp.qp_num,
3203                                                 attr->dest_qp_num);
3204                 MLX5_SET(ads, path, eth_prio, sl & 0x7);
3205                 gid_type = ah->grh.sgid_attr->gid_type;
3206                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3207                         MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
3208         } else {
3209                 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
3210                 MLX5_SET(ads, path, free_ar,
3211                          !!(path_flags & MLX5_PATH_FLAG_FREE_AR));
3212                 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
3213                 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
3214                 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
3215                 MLX5_SET(ads, path, sl, sl);
3216         }
3217
3218         if (ah_flags & IB_AH_GRH) {
3219                 MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
3220                 MLX5_SET(ads, path, hop_limit, grh->hop_limit);
3221                 MLX5_SET(ads, path, tclass, grh->traffic_class);
3222                 MLX5_SET(ads, path, flow_label, grh->flow_label);
3223                 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
3224                        sizeof(grh->dgid.raw));
3225         }
3226
3227         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3228         if (err < 0)
3229                 return err;
3230         MLX5_SET(ads, path, stat_rate, err);
3231         MLX5_SET(ads, path, vhca_port_num, port);
3232
3233         if (attr_mask & IB_QP_TIMEOUT)
3234                 MLX5_SET(ads, path, ack_timeout,
3235                          alt ? attr->alt_timeout : attr->timeout);
3236
3237         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3238                 return modify_raw_packet_eth_prio(dev->mdev,
3239                                                   &qp->raw_packet_qp.sq,
3240                                                   sl & 0xf, qp->ibqp.pd);
3241
3242         return 0;
3243 }
3244
3245 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3246         [MLX5_QP_STATE_INIT] = {
3247                 [MLX5_QP_STATE_INIT] = {
3248                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3249                                           MLX5_QP_OPTPAR_RAE            |
3250                                           MLX5_QP_OPTPAR_RWE            |
3251                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3252                                           MLX5_QP_OPTPAR_PRI_PORT       |
3253                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3254                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3255                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3256                                           MLX5_QP_OPTPAR_PRI_PORT       |
3257                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3258                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3259                                           MLX5_QP_OPTPAR_Q_KEY          |
3260                                           MLX5_QP_OPTPAR_PRI_PORT,
3261                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3262                                           MLX5_QP_OPTPAR_RAE            |
3263                                           MLX5_QP_OPTPAR_RWE            |
3264                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3265                                           MLX5_QP_OPTPAR_PRI_PORT       |
3266                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3267                 },
3268                 [MLX5_QP_STATE_RTR] = {
3269                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3270                                           MLX5_QP_OPTPAR_RRE            |
3271                                           MLX5_QP_OPTPAR_RAE            |
3272                                           MLX5_QP_OPTPAR_RWE            |
3273                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3274                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3275                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3276                                           MLX5_QP_OPTPAR_RWE            |
3277                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3278                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3279                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3280                                           MLX5_QP_OPTPAR_Q_KEY,
3281                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
3282                                            MLX5_QP_OPTPAR_Q_KEY,
3283                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3284                                           MLX5_QP_OPTPAR_RRE            |
3285                                           MLX5_QP_OPTPAR_RAE            |
3286                                           MLX5_QP_OPTPAR_RWE            |
3287                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3288                                           MLX5_QP_OPTPAR_LAG_TX_AFF,
3289                 },
3290         },
3291         [MLX5_QP_STATE_RTR] = {
3292                 [MLX5_QP_STATE_RTS] = {
3293                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3294                                           MLX5_QP_OPTPAR_RRE            |
3295                                           MLX5_QP_OPTPAR_RAE            |
3296                                           MLX5_QP_OPTPAR_RWE            |
3297                                           MLX5_QP_OPTPAR_PM_STATE       |
3298                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3299                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3300                                           MLX5_QP_OPTPAR_RWE            |
3301                                           MLX5_QP_OPTPAR_PM_STATE,
3302                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3303                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3304                                           MLX5_QP_OPTPAR_RRE            |
3305                                           MLX5_QP_OPTPAR_RAE            |
3306                                           MLX5_QP_OPTPAR_RWE            |
3307                                           MLX5_QP_OPTPAR_PM_STATE       |
3308                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3309                 },
3310         },
3311         [MLX5_QP_STATE_RTS] = {
3312                 [MLX5_QP_STATE_RTS] = {
3313                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3314                                           MLX5_QP_OPTPAR_RAE            |
3315                                           MLX5_QP_OPTPAR_RWE            |
3316                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3317                                           MLX5_QP_OPTPAR_PM_STATE       |
3318                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3319                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3320                                           MLX5_QP_OPTPAR_PM_STATE       |
3321                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3322                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3323                                           MLX5_QP_OPTPAR_SRQN           |
3324                                           MLX5_QP_OPTPAR_CQN_RCV,
3325                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3326                                           MLX5_QP_OPTPAR_RAE            |
3327                                           MLX5_QP_OPTPAR_RWE            |
3328                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3329                                           MLX5_QP_OPTPAR_PM_STATE       |
3330                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3331                 },
3332         },
3333         [MLX5_QP_STATE_SQER] = {
3334                 [MLX5_QP_STATE_RTS] = {
3335                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3336                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3337                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3338                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3339                                            MLX5_QP_OPTPAR_RWE           |
3340                                            MLX5_QP_OPTPAR_RAE           |
3341                                            MLX5_QP_OPTPAR_RRE,
3342                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
3343                                            MLX5_QP_OPTPAR_RWE           |
3344                                            MLX5_QP_OPTPAR_RAE           |
3345                                            MLX5_QP_OPTPAR_RRE,
3346                 },
3347         },
3348 };
3349
3350 static int ib_nr_to_mlx5_nr(int ib_mask)
3351 {
3352         switch (ib_mask) {
3353         case IB_QP_STATE:
3354                 return 0;
3355         case IB_QP_CUR_STATE:
3356                 return 0;
3357         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3358                 return 0;
3359         case IB_QP_ACCESS_FLAGS:
3360                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3361                         MLX5_QP_OPTPAR_RAE;
3362         case IB_QP_PKEY_INDEX:
3363                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3364         case IB_QP_PORT:
3365                 return MLX5_QP_OPTPAR_PRI_PORT;
3366         case IB_QP_QKEY:
3367                 return MLX5_QP_OPTPAR_Q_KEY;
3368         case IB_QP_AV:
3369                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3370                         MLX5_QP_OPTPAR_PRI_PORT;
3371         case IB_QP_PATH_MTU:
3372                 return 0;
3373         case IB_QP_TIMEOUT:
3374                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3375         case IB_QP_RETRY_CNT:
3376                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3377         case IB_QP_RNR_RETRY:
3378                 return MLX5_QP_OPTPAR_RNR_RETRY;
3379         case IB_QP_RQ_PSN:
3380                 return 0;
3381         case IB_QP_MAX_QP_RD_ATOMIC:
3382                 return MLX5_QP_OPTPAR_SRA_MAX;
3383         case IB_QP_ALT_PATH:
3384                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3385         case IB_QP_MIN_RNR_TIMER:
3386                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3387         case IB_QP_SQ_PSN:
3388                 return 0;
3389         case IB_QP_MAX_DEST_RD_ATOMIC:
3390                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3391                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3392         case IB_QP_PATH_MIG_STATE:
3393                 return MLX5_QP_OPTPAR_PM_STATE;
3394         case IB_QP_CAP:
3395                 return 0;
3396         case IB_QP_DEST_QPN:
3397                 return 0;
3398         }
3399         return 0;
3400 }
3401
3402 static int ib_mask_to_mlx5_opt(int ib_mask)
3403 {
3404         int result = 0;
3405         int i;
3406
3407         for (i = 0; i < 8 * sizeof(int); i++) {
3408                 if ((1 << i) & ib_mask)
3409                         result |= ib_nr_to_mlx5_nr(1 << i);
3410         }
3411
3412         return result;
3413 }
3414
3415 static int modify_raw_packet_qp_rq(
3416         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3417         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3418 {
3419         void *in;
3420         void *rqc;
3421         int inlen;
3422         int err;
3423
3424         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3425         in = kvzalloc(inlen, GFP_KERNEL);
3426         if (!in)
3427                 return -ENOMEM;
3428
3429         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3430         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3431
3432         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3433         MLX5_SET(rqc, rqc, state, new_state);
3434
3435         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3436                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3437                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3438                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3439                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3440                 } else
3441                         dev_info_once(
3442                                 &dev->ib_dev.dev,
3443                                 "RAW PACKET QP counters are not supported on current FW\n");
3444         }
3445
3446         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3447         if (err)
3448                 goto out;
3449
3450         rq->state = new_state;
3451
3452 out:
3453         kvfree(in);
3454         return err;
3455 }
3456
3457 static int modify_raw_packet_qp_sq(
3458         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3459         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3460 {
3461         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3462         struct mlx5_rate_limit old_rl = ibqp->rl;
3463         struct mlx5_rate_limit new_rl = old_rl;
3464         bool new_rate_added = false;
3465         u16 rl_index = 0;
3466         void *in;
3467         void *sqc;
3468         int inlen;
3469         int err;
3470
3471         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3472         in = kvzalloc(inlen, GFP_KERNEL);
3473         if (!in)
3474                 return -ENOMEM;
3475
3476         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3477         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3478
3479         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3480         MLX5_SET(sqc, sqc, state, new_state);
3481
3482         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3483                 if (new_state != MLX5_SQC_STATE_RDY)
3484                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3485                                 __func__);
3486                 else
3487                         new_rl = raw_qp_param->rl;
3488         }
3489
3490         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3491                 if (new_rl.rate) {
3492                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3493                         if (err) {
3494                                 pr_err("Failed configuring rate limit(err %d): \
3495                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3496                                        err, new_rl.rate, new_rl.max_burst_sz,
3497                                        new_rl.typical_pkt_sz);
3498
3499                                 goto out;
3500                         }
3501                         new_rate_added = true;
3502                 }
3503
3504                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3505                 /* index 0 means no limit */
3506                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3507         }
3508
3509         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3510         if (err) {
3511                 /* Remove new rate from table if failed */
3512                 if (new_rate_added)
3513                         mlx5_rl_remove_rate(dev, &new_rl);
3514                 goto out;
3515         }
3516
3517         /* Only remove the old rate after new rate was set */
3518         if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3519             (new_state != MLX5_SQC_STATE_RDY)) {
3520                 mlx5_rl_remove_rate(dev, &old_rl);
3521                 if (new_state != MLX5_SQC_STATE_RDY)
3522                         memset(&new_rl, 0, sizeof(new_rl));
3523         }
3524
3525         ibqp->rl = new_rl;
3526         sq->state = new_state;
3527
3528 out:
3529         kvfree(in);
3530         return err;
3531 }
3532
3533 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3534                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3535                                 u8 tx_affinity)
3536 {
3537         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3538         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3539         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3540         int modify_rq = !!qp->rq.wqe_cnt;
3541         int modify_sq = !!qp->sq.wqe_cnt;
3542         int rq_state;
3543         int sq_state;
3544         int err;
3545
3546         switch (raw_qp_param->operation) {
3547         case MLX5_CMD_OP_RST2INIT_QP:
3548                 rq_state = MLX5_RQC_STATE_RDY;
3549                 sq_state = MLX5_SQC_STATE_RDY;
3550                 break;
3551         case MLX5_CMD_OP_2ERR_QP:
3552                 rq_state = MLX5_RQC_STATE_ERR;
3553                 sq_state = MLX5_SQC_STATE_ERR;
3554                 break;
3555         case MLX5_CMD_OP_2RST_QP:
3556                 rq_state = MLX5_RQC_STATE_RST;
3557                 sq_state = MLX5_SQC_STATE_RST;
3558                 break;
3559         case MLX5_CMD_OP_RTR2RTS_QP:
3560         case MLX5_CMD_OP_RTS2RTS_QP:
3561                 if (raw_qp_param->set_mask ==
3562                     MLX5_RAW_QP_RATE_LIMIT) {
3563                         modify_rq = 0;
3564                         sq_state = sq->state;
3565                 } else {
3566                         return raw_qp_param->set_mask ? -EINVAL : 0;
3567                 }
3568                 break;
3569         case MLX5_CMD_OP_INIT2INIT_QP:
3570         case MLX5_CMD_OP_INIT2RTR_QP:
3571                 if (raw_qp_param->set_mask)
3572                         return -EINVAL;
3573                 else
3574                         return 0;
3575         default:
3576                 WARN_ON(1);
3577                 return -EINVAL;
3578         }
3579
3580         if (modify_rq) {
3581                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3582                                                qp->ibqp.pd);
3583                 if (err)
3584                         return err;
3585         }
3586
3587         if (modify_sq) {
3588                 struct mlx5_flow_handle *flow_rule;
3589
3590                 if (tx_affinity) {
3591                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3592                                                             tx_affinity,
3593                                                             qp->ibqp.pd);
3594                         if (err)
3595                                 return err;
3596                 }
3597
3598                 flow_rule = create_flow_rule_vport_sq(dev, sq,
3599                                                       raw_qp_param->port);
3600                 if (IS_ERR(flow_rule))
3601                         return PTR_ERR(flow_rule);
3602
3603                 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3604                                               raw_qp_param, qp->ibqp.pd);
3605                 if (err) {
3606                         if (flow_rule)
3607                                 mlx5_del_flow_rules(flow_rule);
3608                         return err;
3609                 }
3610
3611                 if (flow_rule) {
3612                         destroy_flow_rule_vport_sq(sq);
3613                         sq->flow_rule = flow_rule;
3614                 }
3615
3616                 return err;
3617         }
3618
3619         return 0;
3620 }
3621
3622 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev,
3623                                        struct ib_udata *udata)
3624 {
3625         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3626                 udata, struct mlx5_ib_ucontext, ibucontext);
3627         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3628         atomic_t *tx_port_affinity;
3629
3630         if (ucontext)
3631                 tx_port_affinity = &ucontext->tx_port_affinity;
3632         else
3633                 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity;
3634
3635         return (unsigned int)atomic_add_return(1, tx_port_affinity) %
3636                 MLX5_MAX_PORTS + 1;
3637 }
3638
3639 static bool qp_supports_affinity(struct ib_qp *qp)
3640 {
3641         if ((qp->qp_type == IB_QPT_RC) ||
3642             (qp->qp_type == IB_QPT_UD) ||
3643             (qp->qp_type == IB_QPT_UC) ||
3644             (qp->qp_type == IB_QPT_RAW_PACKET) ||
3645             (qp->qp_type == IB_QPT_XRC_INI) ||
3646             (qp->qp_type == IB_QPT_XRC_TGT))
3647                 return true;
3648         return false;
3649 }
3650
3651 static unsigned int get_tx_affinity(struct ib_qp *qp,
3652                                     const struct ib_qp_attr *attr,
3653                                     int attr_mask, u8 init,
3654                                     struct ib_udata *udata)
3655 {
3656         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3657                 udata, struct mlx5_ib_ucontext, ibucontext);
3658         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3659         struct mlx5_ib_qp *mqp = to_mqp(qp);
3660         struct mlx5_ib_qp_base *qp_base;
3661         unsigned int tx_affinity;
3662
3663         if (!(mlx5_ib_lag_should_assign_affinity(dev) &&
3664               qp_supports_affinity(qp)))
3665                 return 0;
3666
3667         if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3668                 tx_affinity = mqp->gsi_lag_port;
3669         else if (init)
3670                 tx_affinity = get_tx_affinity_rr(dev, udata);
3671         else if ((attr_mask & IB_QP_AV) && attr->xmit_slave)
3672                 tx_affinity =
3673                         mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3674         else
3675                 return 0;
3676
3677         qp_base = &mqp->trans_qp.base;
3678         if (ucontext)
3679                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3680                             tx_affinity, qp_base->mqp.qpn, ucontext);
3681         else
3682                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3683                             tx_affinity, qp_base->mqp.qpn);
3684         return tx_affinity;
3685 }
3686
3687 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3688                                     struct rdma_counter *counter)
3689 {
3690         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3691         u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {};
3692         struct mlx5_ib_qp *mqp = to_mqp(qp);
3693         struct mlx5_ib_qp_base *base;
3694         u32 set_id;
3695         u32 *qpc;
3696
3697         if (counter)
3698                 set_id = counter->id;
3699         else
3700                 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3701
3702         base = &mqp->trans_qp.base;
3703         MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
3704         MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);
3705         MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid);
3706         MLX5_SET(rts2rts_qp_in, in, opt_param_mask,
3707                  MLX5_QP_OPTPAR_COUNTER_SET_ID);
3708
3709         qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc);
3710         MLX5_SET(qpc, qpc, counter_set_id, set_id);
3711         return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
3712 }
3713
3714 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3715                                const struct ib_qp_attr *attr, int attr_mask,
3716                                enum ib_qp_state cur_state,
3717                                enum ib_qp_state new_state,
3718                                const struct mlx5_ib_modify_qp *ucmd,
3719                                struct mlx5_ib_modify_qp_resp *resp,
3720                                struct ib_udata *udata)
3721 {
3722         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3723                 [MLX5_QP_STATE_RST] = {
3724                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3725                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3726                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3727                 },
3728                 [MLX5_QP_STATE_INIT]  = {
3729                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3730                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3731                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3732                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3733                 },
3734                 [MLX5_QP_STATE_RTR]   = {
3735                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3736                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3737                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3738                 },
3739                 [MLX5_QP_STATE_RTS]   = {
3740                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3741                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3742                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3743                 },
3744                 [MLX5_QP_STATE_SQD] = {
3745                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3746                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3747                 },
3748                 [MLX5_QP_STATE_SQER] = {
3749                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3750                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3751                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3752                 },
3753                 [MLX5_QP_STATE_ERR] = {
3754                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3755                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3756                 }
3757         };
3758
3759         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3760         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3761         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3762         struct mlx5_ib_cq *send_cq, *recv_cq;
3763         struct mlx5_ib_pd *pd;
3764         enum mlx5_qp_state mlx5_cur, mlx5_new;
3765         void *qpc, *pri_path, *alt_path;
3766         enum mlx5_qp_optpar optpar = 0;
3767         u32 set_id = 0;
3768         int mlx5_st;
3769         int err;
3770         u16 op;
3771         u8 tx_affinity = 0;
3772
3773         mlx5_st = to_mlx5_st(qp->type);
3774         if (mlx5_st < 0)
3775                 return -EINVAL;
3776
3777         qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
3778         if (!qpc)
3779                 return -ENOMEM;
3780
3781         pd = to_mpd(qp->ibqp.pd);
3782         MLX5_SET(qpc, qpc, st, mlx5_st);
3783
3784         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3785                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3786         } else {
3787                 switch (attr->path_mig_state) {
3788                 case IB_MIG_MIGRATED:
3789                         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3790                         break;
3791                 case IB_MIG_REARM:
3792                         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
3793                         break;
3794                 case IB_MIG_ARMED:
3795                         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
3796                         break;
3797                 }
3798         }
3799
3800         tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
3801                                       cur_state == IB_QPS_RESET &&
3802                                       new_state == IB_QPS_INIT, udata);
3803
3804         MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
3805         if (tx_affinity && new_state == IB_QPS_RTR &&
3806             MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3807                 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
3808
3809         if (is_sqp(ibqp->qp_type)) {
3810                 MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
3811                 MLX5_SET(qpc, qpc, log_msg_max, 8);
3812         } else if ((ibqp->qp_type == IB_QPT_UD &&
3813                     !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
3814                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3815                 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
3816                 MLX5_SET(qpc, qpc, log_msg_max, 12);
3817         } else if (attr_mask & IB_QP_PATH_MTU) {
3818                 if (attr->path_mtu < IB_MTU_256 ||
3819                     attr->path_mtu > IB_MTU_4096) {
3820                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3821                         err = -EINVAL;
3822                         goto out;
3823                 }
3824                 MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
3825                 MLX5_SET(qpc, qpc, log_msg_max,
3826                          MLX5_CAP_GEN(dev->mdev, log_max_msg));
3827         }
3828
3829         if (attr_mask & IB_QP_DEST_QPN)
3830                 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
3831
3832         pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
3833         alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
3834
3835         if (attr_mask & IB_QP_PKEY_INDEX)
3836                 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
3837
3838         /* todo implement counter_index functionality */
3839
3840         if (is_sqp(ibqp->qp_type))
3841                 MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
3842
3843         if (attr_mask & IB_QP_PORT)
3844                 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
3845
3846         if (attr_mask & IB_QP_AV) {
3847                 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
3848                                     attr_mask & IB_QP_PORT ? attr->port_num :
3849                                                              qp->port,
3850                                     attr_mask, 0, attr, false);
3851                 if (err)
3852                         goto out;
3853         }
3854
3855         if (attr_mask & IB_QP_TIMEOUT)
3856                 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
3857
3858         if (attr_mask & IB_QP_ALT_PATH) {
3859                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
3860                                     attr->alt_port_num,
3861                                     attr_mask | IB_QP_PKEY_INDEX |
3862                                             IB_QP_TIMEOUT,
3863                                     0, attr, true);
3864                 if (err)
3865                         goto out;
3866         }
3867
3868         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3869                 &send_cq, &recv_cq);
3870
3871         MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3872         if (send_cq)
3873                 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
3874         if (recv_cq)
3875                 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
3876
3877         MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
3878
3879         if (attr_mask & IB_QP_RNR_RETRY)
3880                 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
3881
3882         if (attr_mask & IB_QP_RETRY_CNT)
3883                 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
3884
3885         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
3886                 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
3887
3888         if (attr_mask & IB_QP_SQ_PSN)
3889                 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
3890
3891         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
3892                 MLX5_SET(qpc, qpc, log_rra_max,
3893                          ilog2(attr->max_dest_rd_atomic));
3894
3895         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3896                 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
3897                 if (err)
3898                         goto out;
3899         }
3900
3901         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3902                 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
3903
3904         if (attr_mask & IB_QP_RQ_PSN)
3905                 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
3906
3907         if (attr_mask & IB_QP_QKEY)
3908                 MLX5_SET(qpc, qpc, q_key, attr->qkey);
3909
3910         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3911                 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
3912
3913         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3914                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3915                                qp->port) - 1;
3916
3917                 /* Underlay port should be used - index 0 function per port */
3918                 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
3919                         port_num = 0;
3920
3921                 if (ibqp->counter)
3922                         set_id = ibqp->counter->id;
3923                 else
3924                         set_id = mlx5_ib_get_counters_id(dev, port_num);
3925                 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3926         }
3927
3928         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3929                 MLX5_SET(qpc, qpc, rlky, 1);
3930
3931         if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3932                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
3933
3934         mlx5_cur = to_mlx5_state(cur_state);
3935         mlx5_new = to_mlx5_state(new_state);
3936
3937         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3938             !optab[mlx5_cur][mlx5_new]) {
3939                 err = -EINVAL;
3940                 goto out;
3941         }
3942
3943         op = optab[mlx5_cur][mlx5_new];
3944         optpar |= ib_mask_to_mlx5_opt(attr_mask);
3945         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3946
3947         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3948             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
3949                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3950
3951                 raw_qp_param.operation = op;
3952                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3953                         raw_qp_param.rq_q_ctr_id = set_id;
3954                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3955                 }
3956
3957                 if (attr_mask & IB_QP_PORT)
3958                         raw_qp_param.port = attr->port_num;
3959
3960                 if (attr_mask & IB_QP_RATE_LIMIT) {
3961                         raw_qp_param.rl.rate = attr->rate_limit;
3962
3963                         if (ucmd->burst_info.max_burst_sz) {
3964                                 if (attr->rate_limit &&
3965                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3966                                         raw_qp_param.rl.max_burst_sz =
3967                                                 ucmd->burst_info.max_burst_sz;
3968                                 } else {
3969                                         err = -EINVAL;
3970                                         goto out;
3971                                 }
3972                         }
3973
3974                         if (ucmd->burst_info.typical_pkt_sz) {
3975                                 if (attr->rate_limit &&
3976                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3977                                         raw_qp_param.rl.typical_pkt_sz =
3978                                                 ucmd->burst_info.typical_pkt_sz;
3979                                 } else {
3980                                         err = -EINVAL;
3981                                         goto out;
3982                                 }
3983                         }
3984
3985                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3986                 }
3987
3988                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3989         } else {
3990                 if (udata) {
3991                         /* For the kernel flows, the resp will stay zero */
3992                         resp->ece_options =
3993                                 MLX5_CAP_GEN(dev->mdev, ece_support) ?
3994                                         ucmd->ece_options : 0;
3995                         resp->response_length = sizeof(*resp);
3996                 }
3997                 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp,
3998                                           &resp->ece_options);
3999         }
4000
4001         if (err)
4002                 goto out;
4003
4004         qp->state = new_state;
4005
4006         if (attr_mask & IB_QP_ACCESS_FLAGS)
4007                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
4008         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4009                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
4010         if (attr_mask & IB_QP_PORT)
4011                 qp->port = attr->port_num;
4012         if (attr_mask & IB_QP_ALT_PATH)
4013                 qp->trans_qp.alt_port = attr->alt_port_num;
4014
4015         /*
4016          * If we moved a kernel QP to RESET, clean up all old CQ
4017          * entries and reinitialize the QP.
4018          */
4019         if (new_state == IB_QPS_RESET &&
4020             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
4021                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
4022                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
4023                 if (send_cq != recv_cq)
4024                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
4025
4026                 qp->rq.head = 0;
4027                 qp->rq.tail = 0;
4028                 qp->sq.head = 0;
4029                 qp->sq.tail = 0;
4030                 qp->sq.cur_post = 0;
4031                 if (qp->sq.wqe_cnt)
4032                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
4033                 qp->sq.last_poll = 0;
4034                 qp->db.db[MLX5_RCV_DBR] = 0;
4035                 qp->db.db[MLX5_SND_DBR] = 0;
4036         }
4037
4038         if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
4039                 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
4040                 if (!err)
4041                         qp->counter_pending = 0;
4042         }
4043
4044 out:
4045         kfree(qpc);
4046         return err;
4047 }
4048
4049 static inline bool is_valid_mask(int mask, int req, int opt)
4050 {
4051         if ((mask & req) != req)
4052                 return false;
4053
4054         if (mask & ~(req | opt))
4055                 return false;
4056
4057         return true;
4058 }
4059
4060 /* check valid transition for driver QP types
4061  * for now the only QP type that this function supports is DCI
4062  */
4063 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
4064                                 enum ib_qp_attr_mask attr_mask)
4065 {
4066         int req = IB_QP_STATE;
4067         int opt = 0;
4068
4069         if (new_state == IB_QPS_RESET) {
4070                 return is_valid_mask(attr_mask, req, opt);
4071         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4072                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
4073                 return is_valid_mask(attr_mask, req, opt);
4074         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4075                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
4076                 return is_valid_mask(attr_mask, req, opt);
4077         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4078                 req |= IB_QP_PATH_MTU;
4079                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
4080                 return is_valid_mask(attr_mask, req, opt);
4081         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4082                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
4083                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
4084                 opt = IB_QP_MIN_RNR_TIMER;
4085                 return is_valid_mask(attr_mask, req, opt);
4086         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
4087                 opt = IB_QP_MIN_RNR_TIMER;
4088                 return is_valid_mask(attr_mask, req, opt);
4089         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
4090                 return is_valid_mask(attr_mask, req, opt);
4091         }
4092         return false;
4093 }
4094
4095 /* mlx5_ib_modify_dct: modify a DCT QP
4096  * valid transitions are:
4097  * RESET to INIT: must set access_flags, pkey_index and port
4098  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
4099  *                         mtu, gid_index and hop_limit
4100  * Other transitions and attributes are illegal
4101  */
4102 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4103                               int attr_mask, struct mlx5_ib_modify_qp *ucmd,
4104                               struct ib_udata *udata)
4105 {
4106         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4107         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4108         enum ib_qp_state cur_state, new_state;
4109         int err = 0;
4110         int required = IB_QP_STATE;
4111         void *dctc;
4112
4113         if (!(attr_mask & IB_QP_STATE))
4114                 return -EINVAL;
4115
4116         cur_state = qp->state;
4117         new_state = attr->qp_state;
4118
4119         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
4120         if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options)
4121                 /*
4122                  * DCT doesn't initialize QP till modify command is executed,
4123                  * so we need to overwrite previously set ECE field if user
4124                  * provided any value except zero, which means not set/not
4125                  * valid.
4126                  */
4127                 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
4128
4129         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4130                 u16 set_id;
4131
4132                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4133                 if (!is_valid_mask(attr_mask, required, 0))
4134                         return -EINVAL;
4135
4136                 if (attr->port_num == 0 ||
4137                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
4138                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4139                                     attr->port_num, dev->num_ports);
4140                         return -EINVAL;
4141                 }
4142                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4143                         MLX5_SET(dctc, dctc, rre, 1);
4144                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4145                         MLX5_SET(dctc, dctc, rwe, 1);
4146                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
4147                         int atomic_mode;
4148
4149                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4150                         if (atomic_mode < 0)
4151                                 return -EOPNOTSUPP;
4152
4153                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
4154                         MLX5_SET(dctc, dctc, rae, 1);
4155                 }
4156                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
4157                 MLX5_SET(dctc, dctc, port, attr->port_num);
4158
4159                 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4160                 MLX5_SET(dctc, dctc, counter_set_id, set_id);
4161         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4162                 struct mlx5_ib_modify_qp_resp resp = {};
4163                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {};
4164                 u32 min_resp_len = offsetofend(typeof(resp), dctn);
4165
4166                 if (udata->outlen < min_resp_len)
4167                         return -EINVAL;
4168                 /*
4169                  * If we don't have enough space for the ECE options,
4170                  * simply indicate it with resp.response_length.
4171                  */
4172                 resp.response_length = (udata->outlen < sizeof(resp)) ?
4173                                                min_resp_len :
4174                                                sizeof(resp);
4175
4176                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4177                 if (!is_valid_mask(attr_mask, required, 0))
4178                         return -EINVAL;
4179                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4180                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4181                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4182                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4183                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4184                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4185
4186                 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
4187                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
4188                                            sizeof(out));
4189                 if (err)
4190                         return err;
4191                 resp.dctn = qp->dct.mdct.mqp.qpn;
4192                 if (MLX5_CAP_GEN(dev->mdev, ece_support))
4193                         resp.ece_options = MLX5_GET(create_dct_out, out, ece);
4194                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4195                 if (err) {
4196                         mlx5_core_destroy_dct(dev, &qp->dct.mdct);
4197                         return err;
4198                 }
4199         } else {
4200                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4201                 return -EINVAL;
4202         }
4203         if (err)
4204                 qp->state = IB_QPS_ERR;
4205         else
4206                 qp->state = new_state;
4207         return err;
4208 }
4209
4210 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4211                       int attr_mask, struct ib_udata *udata)
4212 {
4213         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4214         struct mlx5_ib_modify_qp_resp resp = {};
4215         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4216         struct mlx5_ib_modify_qp ucmd = {};
4217         enum ib_qp_type qp_type;
4218         enum ib_qp_state cur_state, new_state;
4219         int err = -EINVAL;
4220         int port;
4221
4222         if (ibqp->rwq_ind_tbl)
4223                 return -ENOSYS;
4224
4225         if (udata && udata->inlen) {
4226                 if (udata->inlen < offsetofend(typeof(ucmd), ece_options))
4227                         return -EINVAL;
4228
4229                 if (udata->inlen > sizeof(ucmd) &&
4230                     !ib_is_udata_cleared(udata, sizeof(ucmd),
4231                                          udata->inlen - sizeof(ucmd)))
4232                         return -EOPNOTSUPP;
4233
4234                 if (ib_copy_from_udata(&ucmd, udata,
4235                                        min(udata->inlen, sizeof(ucmd))))
4236                         return -EFAULT;
4237
4238                 if (ucmd.comp_mask ||
4239                     memchr_inv(&ucmd.burst_info.reserved, 0,
4240                                sizeof(ucmd.burst_info.reserved)))
4241                         return -EOPNOTSUPP;
4242
4243         }
4244
4245         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4246                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4247
4248         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4249                                                                     qp->type;
4250
4251         if (qp_type == MLX5_IB_QPT_DCT)
4252                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata);
4253
4254         mutex_lock(&qp->mutex);
4255
4256         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4257         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4258
4259         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4260                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4261         }
4262
4263         if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4264                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4265                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4266                                     attr_mask);
4267                         goto out;
4268                 }
4269         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4270                    qp_type != MLX5_IB_QPT_DCI &&
4271                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4272                                        attr_mask)) {
4273                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4274                             cur_state, new_state, ibqp->qp_type, attr_mask);
4275                 goto out;
4276         } else if (qp_type == MLX5_IB_QPT_DCI &&
4277                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4278                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4279                             cur_state, new_state, qp_type, attr_mask);
4280                 goto out;
4281         }
4282
4283         if ((attr_mask & IB_QP_PORT) &&
4284             (attr->port_num == 0 ||
4285              attr->port_num > dev->num_ports)) {
4286                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4287                             attr->port_num, dev->num_ports);
4288                 goto out;
4289         }
4290
4291         if (attr_mask & IB_QP_PKEY_INDEX) {
4292                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4293                 if (attr->pkey_index >=
4294                     dev->mdev->port_caps[port - 1].pkey_table_len) {
4295                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4296                                     attr->pkey_index);
4297                         goto out;
4298                 }
4299         }
4300
4301         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4302             attr->max_rd_atomic >
4303             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4304                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4305                             attr->max_rd_atomic);
4306                 goto out;
4307         }
4308
4309         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4310             attr->max_dest_rd_atomic >
4311             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4312                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4313                             attr->max_dest_rd_atomic);
4314                 goto out;
4315         }
4316
4317         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4318                 err = 0;
4319                 goto out;
4320         }
4321
4322         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4323                                   new_state, &ucmd, &resp, udata);
4324
4325         /* resp.response_length is set in ECE supported flows only */
4326         if (!err && resp.response_length &&
4327             udata->outlen >= resp.response_length)
4328                 /* Return -EFAULT to the user and expect him to destroy QP. */
4329                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4330
4331 out:
4332         mutex_unlock(&qp->mutex);
4333         return err;
4334 }
4335
4336 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4337 {
4338         switch (mlx5_state) {
4339         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4340         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4341         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4342         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4343         case MLX5_QP_STATE_SQ_DRAINING:
4344         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4345         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4346         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4347         default:                     return -1;
4348         }
4349 }
4350
4351 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4352 {
4353         switch (mlx5_mig_state) {
4354         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4355         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4356         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4357         default: return -1;
4358         }
4359 }
4360
4361 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4362                             struct rdma_ah_attr *ah_attr, void *path)
4363 {
4364         int port = MLX5_GET(ads, path, vhca_port_num);
4365         int static_rate;
4366
4367         memset(ah_attr, 0, sizeof(*ah_attr));
4368
4369         if (!port || port > ibdev->num_ports)
4370                 return;
4371
4372         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port);
4373
4374         rdma_ah_set_port_num(ah_attr, port);
4375         rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl));
4376
4377         rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid));
4378         rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid));
4379
4380         static_rate = MLX5_GET(ads, path, stat_rate);
4381         rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0);
4382         if (MLX5_GET(ads, path, grh) ||
4383             ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
4384                 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label),
4385                                 MLX5_GET(ads, path, src_addr_index),
4386                                 MLX5_GET(ads, path, hop_limit),
4387                                 MLX5_GET(ads, path, tclass));
4388                 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip));
4389         }
4390 }
4391
4392 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4393                                         struct mlx5_ib_sq *sq,
4394                                         u8 *sq_state)
4395 {
4396         int err;
4397
4398         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4399         if (err)
4400                 goto out;
4401         sq->state = *sq_state;
4402
4403 out:
4404         return err;
4405 }
4406
4407 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4408                                         struct mlx5_ib_rq *rq,
4409                                         u8 *rq_state)
4410 {
4411         void *out;
4412         void *rqc;
4413         int inlen;
4414         int err;
4415
4416         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4417         out = kvzalloc(inlen, GFP_KERNEL);
4418         if (!out)
4419                 return -ENOMEM;
4420
4421         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4422         if (err)
4423                 goto out;
4424
4425         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4426         *rq_state = MLX5_GET(rqc, rqc, state);
4427         rq->state = *rq_state;
4428
4429 out:
4430         kvfree(out);
4431         return err;
4432 }
4433
4434 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4435                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4436 {
4437         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4438                 [MLX5_RQC_STATE_RST] = {
4439                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4440                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4441                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4442                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4443                 },
4444                 [MLX5_RQC_STATE_RDY] = {
4445                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4446                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4447                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4448                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4449                 },
4450                 [MLX5_RQC_STATE_ERR] = {
4451                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4452                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4453                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4454                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4455                 },
4456                 [MLX5_RQ_STATE_NA] = {
4457                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4458                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4459                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4460                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4461                 },
4462         };
4463
4464         *qp_state = sqrq_trans[rq_state][sq_state];
4465
4466         if (*qp_state == MLX5_QP_STATE_BAD) {
4467                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4468                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4469                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4470                 return -EINVAL;
4471         }
4472
4473         if (*qp_state == MLX5_QP_STATE)
4474                 *qp_state = qp->state;
4475
4476         return 0;
4477 }
4478
4479 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4480                                      struct mlx5_ib_qp *qp,
4481                                      u8 *raw_packet_qp_state)
4482 {
4483         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4484         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4485         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4486         int err;
4487         u8 sq_state = MLX5_SQ_STATE_NA;
4488         u8 rq_state = MLX5_RQ_STATE_NA;
4489
4490         if (qp->sq.wqe_cnt) {
4491                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4492                 if (err)
4493                         return err;
4494         }
4495
4496         if (qp->rq.wqe_cnt) {
4497                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4498                 if (err)
4499                         return err;
4500         }
4501
4502         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4503                                       raw_packet_qp_state);
4504 }
4505
4506 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4507                          struct ib_qp_attr *qp_attr)
4508 {
4509         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4510         void *qpc, *pri_path, *alt_path;
4511         u32 *outb;
4512         int err;
4513
4514         outb = kzalloc(outlen, GFP_KERNEL);
4515         if (!outb)
4516                 return -ENOMEM;
4517
4518         err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
4519         if (err)
4520                 goto out;
4521
4522         qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc);
4523
4524         qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state));
4525         if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING)
4526                 qp_attr->sq_draining = 1;
4527
4528         qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu);
4529         qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state));
4530         qp_attr->qkey = MLX5_GET(qpc, qpc, q_key);
4531         qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn);
4532         qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn);
4533         qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn);
4534
4535         if (MLX5_GET(qpc, qpc, rre))
4536                 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ;
4537         if (MLX5_GET(qpc, qpc, rwe))
4538                 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE;
4539         if (MLX5_GET(qpc, qpc, rae))
4540                 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4541
4542         qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max);
4543         qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max);
4544         qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak);
4545         qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count);
4546         qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry);
4547
4548         pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
4549         alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
4550
4551         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4552                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path);
4553                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path);
4554                 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index);
4555                 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num);
4556         }
4557
4558         qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index);
4559         qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num);
4560         qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout);
4561         qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout);
4562
4563 out:
4564         kfree(outb);
4565         return err;
4566 }
4567
4568 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4569                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4570                                 struct ib_qp_init_attr *qp_init_attr)
4571 {
4572         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
4573         u32 *out;
4574         u32 access_flags = 0;
4575         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4576         void *dctc;
4577         int err;
4578         int supported_mask = IB_QP_STATE |
4579                              IB_QP_ACCESS_FLAGS |
4580                              IB_QP_PORT |
4581                              IB_QP_MIN_RNR_TIMER |
4582                              IB_QP_AV |
4583                              IB_QP_PATH_MTU |
4584                              IB_QP_PKEY_INDEX;
4585
4586         if (qp_attr_mask & ~supported_mask)
4587                 return -EINVAL;
4588         if (mqp->state != IB_QPS_RTR)
4589                 return -EINVAL;
4590
4591         out = kzalloc(outlen, GFP_KERNEL);
4592         if (!out)
4593                 return -ENOMEM;
4594
4595         err = mlx5_core_dct_query(dev, dct, out, outlen);
4596         if (err)
4597                 goto out;
4598
4599         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4600
4601         if (qp_attr_mask & IB_QP_STATE)
4602                 qp_attr->qp_state = IB_QPS_RTR;
4603
4604         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4605                 if (MLX5_GET(dctc, dctc, rre))
4606                         access_flags |= IB_ACCESS_REMOTE_READ;
4607                 if (MLX5_GET(dctc, dctc, rwe))
4608                         access_flags |= IB_ACCESS_REMOTE_WRITE;
4609                 if (MLX5_GET(dctc, dctc, rae))
4610                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4611                 qp_attr->qp_access_flags = access_flags;
4612         }
4613
4614         if (qp_attr_mask & IB_QP_PORT)
4615                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4616         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4617                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4618         if (qp_attr_mask & IB_QP_AV) {
4619                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4620                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4621                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4622                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4623         }
4624         if (qp_attr_mask & IB_QP_PATH_MTU)
4625                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4626         if (qp_attr_mask & IB_QP_PKEY_INDEX)
4627                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4628 out:
4629         kfree(out);
4630         return err;
4631 }
4632
4633 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4634                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4635 {
4636         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4637         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4638         int err = 0;
4639         u8 raw_packet_qp_state;
4640
4641         if (ibqp->rwq_ind_tbl)
4642                 return -ENOSYS;
4643
4644         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4645                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4646                                             qp_init_attr);
4647
4648         /* Not all of output fields are applicable, make sure to zero them */
4649         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4650         memset(qp_attr, 0, sizeof(*qp_attr));
4651
4652         if (unlikely(qp->type == MLX5_IB_QPT_DCT))
4653                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4654                                             qp_attr_mask, qp_init_attr);
4655
4656         mutex_lock(&qp->mutex);
4657
4658         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4659             qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4660                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4661                 if (err)
4662                         goto out;
4663                 qp->state = raw_packet_qp_state;
4664                 qp_attr->port_num = 1;
4665         } else {
4666                 err = query_qp_attr(dev, qp, qp_attr);
4667                 if (err)
4668                         goto out;
4669         }
4670
4671         qp_attr->qp_state            = qp->state;
4672         qp_attr->cur_qp_state        = qp_attr->qp_state;
4673         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4674         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4675
4676         if (!ibqp->uobject) {
4677                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4678                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4679                 qp_init_attr->qp_context = ibqp->qp_context;
4680         } else {
4681                 qp_attr->cap.max_send_wr  = 0;
4682                 qp_attr->cap.max_send_sge = 0;
4683         }
4684
4685         qp_init_attr->qp_type = ibqp->qp_type;
4686         qp_init_attr->recv_cq = ibqp->recv_cq;
4687         qp_init_attr->send_cq = ibqp->send_cq;
4688         qp_init_attr->srq = ibqp->srq;
4689         qp_attr->cap.max_inline_data = qp->max_inline_data;
4690
4691         qp_init_attr->cap            = qp_attr->cap;
4692
4693         qp_init_attr->create_flags = qp->flags;
4694
4695         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4696                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4697
4698 out:
4699         mutex_unlock(&qp->mutex);
4700         return err;
4701 }
4702
4703 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4704                                    struct ib_udata *udata)
4705 {
4706         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4707         struct mlx5_ib_xrcd *xrcd;
4708         int err;
4709
4710         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4711                 return ERR_PTR(-ENOSYS);
4712
4713         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4714         if (!xrcd)
4715                 return ERR_PTR(-ENOMEM);
4716
4717         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
4718         if (err) {
4719                 kfree(xrcd);
4720                 return ERR_PTR(-ENOMEM);
4721         }
4722
4723         return &xrcd->ibxrcd;
4724 }
4725
4726 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
4727 {
4728         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4729         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4730         int err;
4731
4732         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
4733         if (err)
4734                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4735
4736         kfree(xrcd);
4737         return 0;
4738 }
4739
4740 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4741 {
4742         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4743         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4744         struct ib_event event;
4745
4746         if (rwq->ibwq.event_handler) {
4747                 event.device     = rwq->ibwq.device;
4748                 event.element.wq = &rwq->ibwq;
4749                 switch (type) {
4750                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4751                         event.event = IB_EVENT_WQ_FATAL;
4752                         break;
4753                 default:
4754                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4755                         return;
4756                 }
4757
4758                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4759         }
4760 }
4761
4762 static int set_delay_drop(struct mlx5_ib_dev *dev)
4763 {
4764         int err = 0;
4765
4766         mutex_lock(&dev->delay_drop.lock);
4767         if (dev->delay_drop.activate)
4768                 goto out;
4769
4770         err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
4771         if (err)
4772                 goto out;
4773
4774         dev->delay_drop.activate = true;
4775 out:
4776         mutex_unlock(&dev->delay_drop.lock);
4777
4778         if (!err)
4779                 atomic_inc(&dev->delay_drop.rqs_cnt);
4780         return err;
4781 }
4782
4783 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4784                       struct ib_wq_init_attr *init_attr)
4785 {
4786         struct mlx5_ib_dev *dev;
4787         int has_net_offloads;
4788         __be64 *rq_pas0;
4789         void *in;
4790         void *rqc;
4791         void *wq;
4792         int inlen;
4793         int err;
4794
4795         dev = to_mdev(pd->device);
4796
4797         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4798         in = kvzalloc(inlen, GFP_KERNEL);
4799         if (!in)
4800                 return -ENOMEM;
4801
4802         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
4803         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4804         MLX5_SET(rqc,  rqc, mem_rq_type,
4805                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4806         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4807         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4808         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4809         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4810         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4811         MLX5_SET(wq, wq, wq_type,
4812                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4813                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4814         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4815                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4816                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4817                         err = -EOPNOTSUPP;
4818                         goto out;
4819                 } else {
4820                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4821                 }
4822         }
4823         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4824         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4825                 /*
4826                  * In Firmware number of strides in each WQE is:
4827                  *   "512 * 2^single_wqe_log_num_of_strides"
4828                  * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
4829                  * accepted as 0 to 9
4830                  */
4831                 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
4832                                              2,  3,  4,  5,  6,  7,  8, 9 };
4833                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4834                 MLX5_SET(wq, wq, log_wqe_stride_size,
4835                          rwq->single_stride_log_num_of_bytes -
4836                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4837                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
4838                          fw_map[rwq->log_num_strides -
4839                                 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
4840         }
4841         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4842         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4843         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4844         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4845         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4846         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4847         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4848         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4849                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4850                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4851                         err = -EOPNOTSUPP;
4852                         goto out;
4853                 }
4854         } else {
4855                 MLX5_SET(rqc, rqc, vsd, 1);
4856         }
4857         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4858                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4859                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4860                         err = -EOPNOTSUPP;
4861                         goto out;
4862                 }
4863                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4864         }
4865         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4866                 if (!(dev->ib_dev.attrs.raw_packet_caps &
4867                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
4868                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4869                         err = -EOPNOTSUPP;
4870                         goto out;
4871                 }
4872                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4873         }
4874         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4875         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4876         err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
4877         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4878                 err = set_delay_drop(dev);
4879                 if (err) {
4880                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4881                                      err);
4882                         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
4883                 } else {
4884                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4885                 }
4886         }
4887 out:
4888         kvfree(in);
4889         return err;
4890 }
4891
4892 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4893                             struct ib_wq_init_attr *wq_init_attr,
4894                             struct mlx5_ib_create_wq *ucmd,
4895                             struct mlx5_ib_rwq *rwq)
4896 {
4897         /* Sanity check RQ size before proceeding */
4898         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4899                 return -EINVAL;
4900
4901         if (!ucmd->rq_wqe_count)
4902                 return -EINVAL;
4903
4904         rwq->wqe_count = ucmd->rq_wqe_count;
4905         rwq->wqe_shift = ucmd->rq_wqe_shift;
4906         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
4907                 return -EINVAL;
4908
4909         rwq->log_rq_stride = rwq->wqe_shift;
4910         rwq->log_rq_size = ilog2(rwq->wqe_count);
4911         return 0;
4912 }
4913
4914 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
4915 {
4916         if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4917             (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4918                 return false;
4919
4920         if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
4921             (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4922                 return false;
4923
4924         return true;
4925 }
4926
4927 static int prepare_user_rq(struct ib_pd *pd,
4928                            struct ib_wq_init_attr *init_attr,
4929                            struct ib_udata *udata,
4930                            struct mlx5_ib_rwq *rwq)
4931 {
4932         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4933         struct mlx5_ib_create_wq ucmd = {};
4934         int err;
4935         size_t required_cmd_sz;
4936
4937         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4938                 + sizeof(ucmd.single_stride_log_num_of_bytes);
4939         if (udata->inlen < required_cmd_sz) {
4940                 mlx5_ib_dbg(dev, "invalid inlen\n");
4941                 return -EINVAL;
4942         }
4943
4944         if (udata->inlen > sizeof(ucmd) &&
4945             !ib_is_udata_cleared(udata, sizeof(ucmd),
4946                                  udata->inlen - sizeof(ucmd))) {
4947                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4948                 return -EOPNOTSUPP;
4949         }
4950
4951         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4952                 mlx5_ib_dbg(dev, "copy failed\n");
4953                 return -EFAULT;
4954         }
4955
4956         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4957                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4958                 return -EOPNOTSUPP;
4959         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4960                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4961                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4962                         return -EOPNOTSUPP;
4963                 }
4964                 if ((ucmd.single_stride_log_num_of_bytes <
4965                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4966                     (ucmd.single_stride_log_num_of_bytes >
4967                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4968                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4969                                     ucmd.single_stride_log_num_of_bytes,
4970                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4971                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4972                         return -EINVAL;
4973                 }
4974                 if (!log_of_strides_valid(dev,
4975                                           ucmd.single_wqe_log_num_of_strides)) {
4976                         mlx5_ib_dbg(
4977                                 dev,
4978                                 "Invalid log num strides (%u. Range is %u - %u)\n",
4979                                 ucmd.single_wqe_log_num_of_strides,
4980                                 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
4981                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
4982                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4983                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4984                         return -EINVAL;
4985                 }
4986                 rwq->single_stride_log_num_of_bytes =
4987                         ucmd.single_stride_log_num_of_bytes;
4988                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4989                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4990                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4991         }
4992
4993         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4994         if (err) {
4995                 mlx5_ib_dbg(dev, "err %d\n", err);
4996                 return err;
4997         }
4998
4999         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
5000         if (err) {
5001                 mlx5_ib_dbg(dev, "err %d\n", err);
5002                 return err;
5003         }
5004
5005         rwq->user_index = ucmd.user_index;
5006         return 0;
5007 }
5008
5009 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5010                                 struct ib_wq_init_attr *init_attr,
5011                                 struct ib_udata *udata)
5012 {
5013         struct mlx5_ib_dev *dev;
5014         struct mlx5_ib_rwq *rwq;
5015         struct mlx5_ib_create_wq_resp resp = {};
5016         size_t min_resp_len;
5017         int err;
5018
5019         if (!udata)
5020                 return ERR_PTR(-ENOSYS);
5021
5022         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5023         if (udata->outlen && udata->outlen < min_resp_len)
5024                 return ERR_PTR(-EINVAL);
5025
5026         if (!capable(CAP_SYS_RAWIO) &&
5027             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5028                 return ERR_PTR(-EPERM);
5029
5030         dev = to_mdev(pd->device);
5031         switch (init_attr->wq_type) {
5032         case IB_WQT_RQ:
5033                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5034                 if (!rwq)
5035                         return ERR_PTR(-ENOMEM);
5036                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5037                 if (err)
5038                         goto err;
5039                 err = create_rq(rwq, pd, init_attr);
5040                 if (err)
5041                         goto err_user_rq;
5042                 break;
5043         default:
5044                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5045                             init_attr->wq_type);
5046                 return ERR_PTR(-EINVAL);
5047         }
5048
5049         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5050         rwq->ibwq.state = IB_WQS_RESET;
5051         if (udata->outlen) {
5052                 resp.response_length = offsetof(typeof(resp), response_length) +
5053                                 sizeof(resp.response_length);
5054                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5055                 if (err)
5056                         goto err_copy;
5057         }
5058
5059         rwq->core_qp.event = mlx5_ib_wq_event;
5060         rwq->ibwq.event_handler = init_attr->event_handler;
5061         return &rwq->ibwq;
5062
5063 err_copy:
5064         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5065 err_user_rq:
5066         destroy_user_rq(dev, pd, rwq, udata);
5067 err:
5068         kfree(rwq);
5069         return ERR_PTR(err);
5070 }
5071
5072 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
5073 {
5074         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5075         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5076
5077         mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5078         destroy_user_rq(dev, wq->pd, rwq, udata);
5079         kfree(rwq);
5080 }
5081
5082 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5083                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5084                                                       struct ib_udata *udata)
5085 {
5086         struct mlx5_ib_dev *dev = to_mdev(device);
5087         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5088         int sz = 1 << init_attr->log_ind_tbl_size;
5089         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5090         size_t min_resp_len;
5091         int inlen;
5092         int err;
5093         int i;
5094         u32 *in;
5095         void *rqtc;
5096
5097         if (udata->inlen > 0 &&
5098             !ib_is_udata_cleared(udata, 0,
5099                                  udata->inlen))
5100                 return ERR_PTR(-EOPNOTSUPP);
5101
5102         if (init_attr->log_ind_tbl_size >
5103             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5104                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5105                             init_attr->log_ind_tbl_size,
5106                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5107                 return ERR_PTR(-EINVAL);
5108         }
5109
5110         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5111         if (udata->outlen && udata->outlen < min_resp_len)
5112                 return ERR_PTR(-EINVAL);
5113
5114         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5115         if (!rwq_ind_tbl)
5116                 return ERR_PTR(-ENOMEM);
5117
5118         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5119         in = kvzalloc(inlen, GFP_KERNEL);
5120         if (!in) {
5121                 err = -ENOMEM;
5122                 goto err;
5123         }
5124
5125         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5126
5127         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5128         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5129
5130         for (i = 0; i < sz; i++)
5131                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5132
5133         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5134         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5135
5136         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5137         kvfree(in);
5138
5139         if (err)
5140                 goto err;
5141
5142         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5143         if (udata->outlen) {
5144                 resp.response_length = offsetof(typeof(resp), response_length) +
5145                                         sizeof(resp.response_length);
5146                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5147                 if (err)
5148                         goto err_copy;
5149         }
5150
5151         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5152
5153 err_copy:
5154         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5155 err:
5156         kfree(rwq_ind_tbl);
5157         return ERR_PTR(err);
5158 }
5159
5160 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5161 {
5162         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5163         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5164
5165         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5166
5167         kfree(rwq_ind_tbl);
5168         return 0;
5169 }
5170
5171 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5172                       u32 wq_attr_mask, struct ib_udata *udata)
5173 {
5174         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5175         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5176         struct mlx5_ib_modify_wq ucmd = {};
5177         size_t required_cmd_sz;
5178         int curr_wq_state;
5179         int wq_state;
5180         int inlen;
5181         int err;
5182         void *rqc;
5183         void *in;
5184
5185         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5186         if (udata->inlen < required_cmd_sz)
5187                 return -EINVAL;
5188
5189         if (udata->inlen > sizeof(ucmd) &&
5190             !ib_is_udata_cleared(udata, sizeof(ucmd),
5191                                  udata->inlen - sizeof(ucmd)))
5192                 return -EOPNOTSUPP;
5193
5194         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5195                 return -EFAULT;
5196
5197         if (ucmd.comp_mask || ucmd.reserved)
5198                 return -EOPNOTSUPP;
5199
5200         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5201         in = kvzalloc(inlen, GFP_KERNEL);
5202         if (!in)
5203                 return -ENOMEM;
5204
5205         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5206
5207         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5208                 wq_attr->curr_wq_state : wq->state;
5209         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5210                 wq_attr->wq_state : curr_wq_state;
5211         if (curr_wq_state == IB_WQS_ERR)
5212                 curr_wq_state = MLX5_RQC_STATE_ERR;
5213         if (wq_state == IB_WQS_ERR)
5214                 wq_state = MLX5_RQC_STATE_ERR;
5215         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5216         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5217         MLX5_SET(rqc, rqc, state, wq_state);
5218
5219         if (wq_attr_mask & IB_WQ_FLAGS) {
5220                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5221                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5222                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5223                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
5224                                             "supported\n");
5225                                 err = -EOPNOTSUPP;
5226                                 goto out;
5227                         }
5228                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5229                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5230                         MLX5_SET(rqc, rqc, vsd,
5231                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5232                 }
5233
5234                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5235                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5236                         err = -EOPNOTSUPP;
5237                         goto out;
5238                 }
5239         }
5240
5241         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5242                 u16 set_id;
5243
5244                 set_id = mlx5_ib_get_counters_id(dev, 0);
5245                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5246                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5247                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5248                         MLX5_SET(rqc, rqc, counter_set_id, set_id);
5249                 } else
5250                         dev_info_once(
5251                                 &dev->ib_dev.dev,
5252                                 "Receive WQ counters are not supported on current FW\n");
5253         }
5254
5255         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
5256         if (!err)
5257                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5258
5259 out:
5260         kvfree(in);
5261         return err;
5262 }
5263
5264 struct mlx5_ib_drain_cqe {
5265         struct ib_cqe cqe;
5266         struct completion done;
5267 };
5268
5269 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5270 {
5271         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5272                                                      struct mlx5_ib_drain_cqe,
5273                                                      cqe);
5274
5275         complete(&cqe->done);
5276 }
5277
5278 /* This function returns only once the drained WR was completed */
5279 static void handle_drain_completion(struct ib_cq *cq,
5280                                     struct mlx5_ib_drain_cqe *sdrain,
5281                                     struct mlx5_ib_dev *dev)
5282 {
5283         struct mlx5_core_dev *mdev = dev->mdev;
5284
5285         if (cq->poll_ctx == IB_POLL_DIRECT) {
5286                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5287                         ib_process_cq_direct(cq, -1);
5288                 return;
5289         }
5290
5291         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5292                 struct mlx5_ib_cq *mcq = to_mcq(cq);
5293                 bool triggered = false;
5294                 unsigned long flags;
5295
5296                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5297                 /* Make sure that the CQ handler won't run if wasn't run yet */
5298                 if (!mcq->mcq.reset_notify_added)
5299                         mcq->mcq.reset_notify_added = 1;
5300                 else
5301                         triggered = true;
5302                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5303
5304                 if (triggered) {
5305                         /* Wait for any scheduled/running task to be ended */
5306                         switch (cq->poll_ctx) {
5307                         case IB_POLL_SOFTIRQ:
5308                                 irq_poll_disable(&cq->iop);
5309                                 irq_poll_enable(&cq->iop);
5310                                 break;
5311                         case IB_POLL_WORKQUEUE:
5312                                 cancel_work_sync(&cq->work);
5313                                 break;
5314                         default:
5315                                 WARN_ON_ONCE(1);
5316                         }
5317                 }
5318
5319                 /* Run the CQ handler - this makes sure that the drain WR will
5320                  * be processed if wasn't processed yet.
5321                  */
5322                 mcq->mcq.comp(&mcq->mcq, NULL);
5323         }
5324
5325         wait_for_completion(&sdrain->done);
5326 }
5327
5328 void mlx5_ib_drain_sq(struct ib_qp *qp)
5329 {
5330         struct ib_cq *cq = qp->send_cq;
5331         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5332         struct mlx5_ib_drain_cqe sdrain;
5333         const struct ib_send_wr *bad_swr;
5334         struct ib_rdma_wr swr = {
5335                 .wr = {
5336                         .next = NULL,
5337                         { .wr_cqe       = &sdrain.cqe, },
5338                         .opcode = IB_WR_RDMA_WRITE,
5339                 },
5340         };
5341         int ret;
5342         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5343         struct mlx5_core_dev *mdev = dev->mdev;
5344
5345         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5346         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5347                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5348                 return;
5349         }
5350
5351         sdrain.cqe.done = mlx5_ib_drain_qp_done;
5352         init_completion(&sdrain.done);
5353
5354         ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr);
5355         if (ret) {
5356                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5357                 return;
5358         }
5359
5360         handle_drain_completion(cq, &sdrain, dev);
5361 }
5362
5363 void mlx5_ib_drain_rq(struct ib_qp *qp)
5364 {
5365         struct ib_cq *cq = qp->recv_cq;
5366         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5367         struct mlx5_ib_drain_cqe rdrain;
5368         struct ib_recv_wr rwr = {};
5369         const struct ib_recv_wr *bad_rwr;
5370         int ret;
5371         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5372         struct mlx5_core_dev *mdev = dev->mdev;
5373
5374         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5375         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5376                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5377                 return;
5378         }
5379
5380         rwr.wr_cqe = &rdrain.cqe;
5381         rdrain.cqe.done = mlx5_ib_drain_qp_done;
5382         init_completion(&rdrain.done);
5383
5384         ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr);
5385         if (ret) {
5386                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5387                 return;
5388         }
5389
5390         handle_drain_completion(cq, &rdrain, dev);
5391 }
5392
5393 /**
5394  * Bind a qp to a counter. If @counter is NULL then bind the qp to
5395  * the default counter
5396  */
5397 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
5398 {
5399         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5400         struct mlx5_ib_qp *mqp = to_mqp(qp);
5401         int err = 0;
5402
5403         mutex_lock(&mqp->mutex);
5404         if (mqp->state == IB_QPS_RESET) {
5405                 qp->counter = counter;
5406                 goto out;
5407         }
5408
5409         if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
5410                 err = -EOPNOTSUPP;
5411                 goto out;
5412         }
5413
5414         if (mqp->state == IB_QPS_RTS) {
5415                 err = __mlx5_ib_qp_set_counter(qp, counter);
5416                 if (!err)
5417                         qp->counter = counter;
5418
5419                 goto out;
5420         }
5421
5422         mqp->counter_pending = 1;
5423         qp->counter = counter;
5424
5425 out:
5426         mutex_unlock(&mqp->mutex);
5427         return err;
5428 }