drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include "mlx5_ib.h"
  36 #include "user.h"
  37
  38 /* not supported currently */
  39 static int wq_signature;
  40
  41 enum {
  42         MLX5_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  48         MLX5_IB_LINK_TYPE_IB            = 0,
  49         MLX5_IB_LINK_TYPE_ETH           = 1
  50 };
  51
  52 enum {
  53         MLX5_IB_SQ_STRIDE       = 6,
  54         MLX5_IB_CACHE_LINE_SIZE = 64,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  60         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  61         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  62         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  63         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  64         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  65         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  66         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  67         [IB_WR_FAST_REG_MR]                     = MLX5_OPCODE_UMR,
  68         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  69         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  70         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  71 };
  72
  73 struct umr_wr {
  74         u64                             virt_addr;
  75         struct ib_pd                   *pd;
  76         unsigned int                    page_shift;
  77         unsigned int                    npages;
  78         u32                             length;
  79         int                             access_flags;
  80         u32                             mkey;
  81 };
  82
  83 static int is_qp0(enum ib_qp_type qp_type)
  84 {
  85         return qp_type == IB_QPT_SMI;
  86 }
  87
  88 static int is_qp1(enum ib_qp_type qp_type)
  89 {
  90         return qp_type == IB_QPT_GSI;
  91 }
  92
  93 static int is_sqp(enum ib_qp_type qp_type)
  94 {
  95         return is_qp0(qp_type) || is_qp1(qp_type);
  96 }
  97
  98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  99 {
 100         return mlx5_buf_offset(&qp->buf, offset);
 101 }
 102
 103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 104 {
 105         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 106 }
 107
 108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 109 {
 110         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 111 }
 112
 113 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 114 {
 115         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 116         struct ib_event event;
 117
 118         if (type == MLX5_EVENT_TYPE_PATH_MIG)
 119                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 120
 121         if (ibqp->event_handler) {
 122                 event.device     = ibqp->device;
 123                 event.element.qp = ibqp;
 124                 switch (type) {
 125                 case MLX5_EVENT_TYPE_PATH_MIG:
 126                         event.event = IB_EVENT_PATH_MIG;
 127                         break;
 128                 case MLX5_EVENT_TYPE_COMM_EST:
 129                         event.event = IB_EVENT_COMM_EST;
 130                         break;
 131                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 132                         event.event = IB_EVENT_SQ_DRAINED;
 133                         break;
 134                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 135                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 136                         break;
 137                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 138                         event.event = IB_EVENT_QP_FATAL;
 139                         break;
 140                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 141                         event.event = IB_EVENT_PATH_MIG_ERR;
 142                         break;
 143                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 144                         event.event = IB_EVENT_QP_REQ_ERR;
 145                         break;
 146                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 147                         event.event = IB_EVENT_QP_ACCESS_ERR;
 148                         break;
 149                 default:
 150                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 151                         return;
 152                 }
 153
 154                 ibqp->event_handler(&event, ibqp->qp_context);
 155         }
 156 }
 157
 158 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 159                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 160 {
 161         struct mlx5_general_caps *gen;
 162         int wqe_size;
 163         int wq_size;
 164
 165         gen = &dev->mdev->caps.gen;
 166         /* Sanity check RQ size before proceeding */
 167         if (cap->max_recv_wr  > gen->max_wqes)
 168                 return -EINVAL;
 169
 170         if (!has_rq) {
 171                 qp->rq.max_gs = 0;
 172                 qp->rq.wqe_cnt = 0;
 173                 qp->rq.wqe_shift = 0;
 174         } else {
 175                 if (ucmd) {
 176                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 177                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 178                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 179                         qp->rq.max_post = qp->rq.wqe_cnt;
 180                 } else {
 181                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 182                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 183                         wqe_size = roundup_pow_of_two(wqe_size);
 184                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 185                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 186                         qp->rq.wqe_cnt = wq_size / wqe_size;
 187                         if (wqe_size > gen->max_rq_desc_sz) {
 188                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 189                                             wqe_size,
 190                                             gen->max_rq_desc_sz);
 191                                 return -EINVAL;
 192                         }
 193                         qp->rq.wqe_shift = ilog2(wqe_size);
 194                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 195                         qp->rq.max_post = qp->rq.wqe_cnt;
 196                 }
 197         }
 198
 199         return 0;
 200 }
 201
 202 static int sq_overhead(enum ib_qp_type qp_type)
 203 {
 204         int size = 0;
 205
 206         switch (qp_type) {
 207         case IB_QPT_XRC_INI:
 208                 size += sizeof(struct mlx5_wqe_xrc_seg);
 209                 /* fall through */
 210         case IB_QPT_RC:
 211                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 212                         sizeof(struct mlx5_wqe_atomic_seg) +
 213                         sizeof(struct mlx5_wqe_raddr_seg);
 214                 break;
 215
 216         case IB_QPT_XRC_TGT:
 217                 return 0;
 218
 219         case IB_QPT_UC:
 220                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 221                         sizeof(struct mlx5_wqe_raddr_seg) +
 222                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 223                         sizeof(struct mlx5_mkey_seg);
 224                 break;
 225
 226         case IB_QPT_UD:
 227         case IB_QPT_SMI:
 228         case IB_QPT_GSI:
 229                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 230                         sizeof(struct mlx5_wqe_datagram_seg);
 231                 break;
 232
 233         case MLX5_IB_QPT_REG_UMR:
 234                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 235                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 236                         sizeof(struct mlx5_mkey_seg);
 237                 break;
 238
 239         default:
 240                 return -EINVAL;
 241         }
 242
 243         return size;
 244 }
 245
 246 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 247 {
 248         int inl_size = 0;
 249         int size;
 250
 251         size = sq_overhead(attr->qp_type);
 252         if (size < 0)
 253                 return size;
 254
 255         if (attr->cap.max_inline_data) {
 256                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 257                         attr->cap.max_inline_data;
 258         }
 259
 260         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 261         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 262             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 263                         return MLX5_SIG_WQE_SIZE;
 264         else
 265                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 266 }
 267
 268 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 269                         struct mlx5_ib_qp *qp)
 270 {
 271         struct mlx5_general_caps *gen;
 272         int wqe_size;
 273         int wq_size;
 274
 275         gen = &dev->mdev->caps.gen;
 276         if (!attr->cap.max_send_wr)
 277                 return 0;
 278
 279         wqe_size = calc_send_wqe(attr);
 280         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 281         if (wqe_size < 0)
 282                 return wqe_size;
 283
 284         if (wqe_size > gen->max_sq_desc_sz) {
 285                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 286                             wqe_size, gen->max_sq_desc_sz);
 287                 return -EINVAL;
 288         }
 289
 290         qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
 291                 sizeof(struct mlx5_wqe_inline_seg);
 292         attr->cap.max_inline_data = qp->max_inline_data;
 293
 294         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 295                 qp->signature_en = true;
 296
 297         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 298         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 299         if (qp->sq.wqe_cnt > gen->max_wqes) {
 300                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 301                             qp->sq.wqe_cnt, gen->max_wqes);
 302                 return -ENOMEM;
 303         }
 304         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 305         qp->sq.max_gs = attr->cap.max_send_sge;
 306         qp->sq.max_post = wq_size / wqe_size;
 307         attr->cap.max_send_wr = qp->sq.max_post;
 308
 309         return wq_size;
 310 }
 311
 312 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 313                             struct mlx5_ib_qp *qp,
 314                             struct mlx5_ib_create_qp *ucmd)
 315 {
 316         struct mlx5_general_caps *gen;
 317         int desc_sz = 1 << qp->sq.wqe_shift;
 318
 319         gen = &dev->mdev->caps.gen;
 320         if (desc_sz > gen->max_sq_desc_sz) {
 321                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 322                              desc_sz, gen->max_sq_desc_sz);
 323                 return -EINVAL;
 324         }
 325
 326         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 327                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 328                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 329                 return -EINVAL;
 330         }
 331
 332         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 333
 334         if (qp->sq.wqe_cnt > gen->max_wqes) {
 335                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 336                              qp->sq.wqe_cnt, gen->max_wqes);
 337                 return -EINVAL;
 338         }
 339
 340         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 341                 (qp->sq.wqe_cnt << 6);
 342
 343         return 0;
 344 }
 345
 346 static int qp_has_rq(struct ib_qp_init_attr *attr)
 347 {
 348         if (attr->qp_type == IB_QPT_XRC_INI ||
 349             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 350             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 351             !attr->cap.max_recv_wr)
 352                 return 0;
 353
 354         return 1;
 355 }
 356
 357 static int first_med_uuar(void)
 358 {
 359         return 1;
 360 }
 361
 362 static int next_uuar(int n)
 363 {
 364         n++;
 365
 366         while (((n % 4) & 2))
 367                 n++;
 368
 369         return n;
 370 }
 371
 372 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 373 {
 374         int n;
 375
 376         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 377                 uuari->num_low_latency_uuars - 1;
 378
 379         return n >= 0 ? n : 0;
 380 }
 381
 382 static int max_uuari(struct mlx5_uuar_info *uuari)
 383 {
 384         return uuari->num_uars * 4;
 385 }
 386
 387 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 388 {
 389         int med;
 390         int i;
 391         int t;
 392
 393         med = num_med_uuar(uuari);
 394         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 395                 t++;
 396                 if (t == med)
 397                         return next_uuar(i);
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 404 {
 405         int i;
 406
 407         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 408                 if (!test_bit(i, uuari->bitmap)) {
 409                         set_bit(i, uuari->bitmap);
 410                         uuari->count[i]++;
 411                         return i;
 412                 }
 413         }
 414
 415         return -ENOMEM;
 416 }
 417
 418 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 419 {
 420         int minidx = first_med_uuar();
 421         int i;
 422
 423         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 424                 if (uuari->count[i] < uuari->count[minidx])
 425                         minidx = i;
 426         }
 427
 428         uuari->count[minidx]++;
 429         return minidx;
 430 }
 431
 432 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 433                       enum mlx5_ib_latency_class lat)
 434 {
 435         int uuarn = -EINVAL;
 436
 437         mutex_lock(&uuari->lock);
 438         switch (lat) {
 439         case MLX5_IB_LATENCY_CLASS_LOW:
 440                 uuarn = 0;
 441                 uuari->count[uuarn]++;
 442                 break;
 443
 444         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 445                 if (uuari->ver < 2)
 446                         uuarn = -ENOMEM;
 447                 else
 448                         uuarn = alloc_med_class_uuar(uuari);
 449                 break;
 450
 451         case MLX5_IB_LATENCY_CLASS_HIGH:
 452                 if (uuari->ver < 2)
 453                         uuarn = -ENOMEM;
 454                 else
 455                         uuarn = alloc_high_class_uuar(uuari);
 456                 break;
 457
 458         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 459                 uuarn = 2;
 460                 break;
 461         }
 462         mutex_unlock(&uuari->lock);
 463
 464         return uuarn;
 465 }
 466
 467 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 468 {
 469         clear_bit(uuarn, uuari->bitmap);
 470         --uuari->count[uuarn];
 471 }
 472
 473 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 474 {
 475         clear_bit(uuarn, uuari->bitmap);
 476         --uuari->count[uuarn];
 477 }
 478
 479 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 480 {
 481         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 482         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 483
 484         mutex_lock(&uuari->lock);
 485         if (uuarn == 0) {
 486                 --uuari->count[uuarn];
 487                 goto out;
 488         }
 489
 490         if (uuarn < high_uuar) {
 491                 free_med_class_uuar(uuari, uuarn);
 492                 goto out;
 493         }
 494
 495         free_high_class_uuar(uuari, uuarn);
 496
 497 out:
 498         mutex_unlock(&uuari->lock);
 499 }
 500
 501 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 502 {
 503         switch (state) {
 504         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 505         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 506         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 507         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 508         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 509         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 510         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 511         default:                return -1;
 512         }
 513 }
 514
 515 static int to_mlx5_st(enum ib_qp_type type)
 516 {
 517         switch (type) {
 518         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 519         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 520         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 521         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 522         case IB_QPT_XRC_INI:
 523         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 524         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 525         case IB_QPT_GSI:                return MLX5_QP_ST_QP1;
 526         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 527         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 528         case IB_QPT_RAW_PACKET:
 529         case IB_QPT_MAX:
 530         default:                return -EINVAL;
 531         }
 532 }
 533
 534 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 535 {
 536         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 537 }
 538
 539 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 540                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 541                           struct mlx5_create_qp_mbox_in **in,
 542                           struct mlx5_ib_create_qp_resp *resp, int *inlen)
 543 {
 544         struct mlx5_ib_ucontext *context;
 545         struct mlx5_ib_create_qp ucmd;
 546         int page_shift = 0;
 547         int uar_index;
 548         int npages;
 549         u32 offset = 0;
 550         int uuarn;
 551         int ncont = 0;
 552         int err;
 553
 554         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 555         if (err) {
 556                 mlx5_ib_dbg(dev, "copy failed\n");
 557                 return err;
 558         }
 559
 560         context = to_mucontext(pd->uobject->context);
 561         /*
 562          * TBD: should come from the verbs when we have the API
 563          */
 564         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 565         if (uuarn < 0) {
 566                 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 567                 mlx5_ib_dbg(dev, "reverting to medium latency\n");
 568                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 569                 if (uuarn < 0) {
 570                         mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 571                         mlx5_ib_dbg(dev, "reverting to high latency\n");
 572                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 573                         if (uuarn < 0) {
 574                                 mlx5_ib_warn(dev, "uuar allocation failed\n");
 575                                 return uuarn;
 576                         }
 577                 }
 578         }
 579
 580         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 581         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 582
 583         qp->rq.offset = 0;
 584         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 585         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 586
 587         err = set_user_buf_size(dev, qp, &ucmd);
 588         if (err)
 589                 goto err_uuar;
 590
 591         if (ucmd.buf_addr && qp->buf_size) {
 592                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 593                                        qp->buf_size, 0, 0);
 594                 if (IS_ERR(qp->umem)) {
 595                         mlx5_ib_dbg(dev, "umem_get failed\n");
 596                         err = PTR_ERR(qp->umem);
 597                         goto err_uuar;
 598                 }
 599         } else {
 600                 qp->umem = NULL;
 601         }
 602
 603         if (qp->umem) {
 604                 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
 605                                    &ncont, NULL);
 606                 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
 607                 if (err) {
 608                         mlx5_ib_warn(dev, "bad offset\n");
 609                         goto err_umem;
 610                 }
 611                 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
 612                             ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
 613         }
 614
 615         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
 616         *in = mlx5_vzalloc(*inlen);
 617         if (!*in) {
 618                 err = -ENOMEM;
 619                 goto err_umem;
 620         }
 621         if (qp->umem)
 622                 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
 623         (*in)->ctx.log_pg_sz_remote_qpn =
 624                 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 625         (*in)->ctx.params2 = cpu_to_be32(offset << 6);
 626
 627         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 628         resp->uuar_index = uuarn;
 629         qp->uuarn = uuarn;
 630
 631         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 632         if (err) {
 633                 mlx5_ib_dbg(dev, "map failed\n");
 634                 goto err_free;
 635         }
 636
 637         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 638         if (err) {
 639                 mlx5_ib_dbg(dev, "copy failed\n");
 640                 goto err_unmap;
 641         }
 642         qp->create_type = MLX5_QP_USER;
 643
 644         return 0;
 645
 646 err_unmap:
 647         mlx5_ib_db_unmap_user(context, &qp->db);
 648
 649 err_free:
 650         mlx5_vfree(*in);
 651
 652 err_umem:
 653         if (qp->umem)
 654                 ib_umem_release(qp->umem);
 655
 656 err_uuar:
 657         free_uuar(&context->uuari, uuarn);
 658         return err;
 659 }
 660
 661 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
 662 {
 663         struct mlx5_ib_ucontext *context;
 664
 665         context = to_mucontext(pd->uobject->context);
 666         mlx5_ib_db_unmap_user(context, &qp->db);
 667         if (qp->umem)
 668                 ib_umem_release(qp->umem);
 669         free_uuar(&context->uuari, qp->uuarn);
 670 }
 671
 672 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 673                             struct ib_qp_init_attr *init_attr,
 674                             struct mlx5_ib_qp *qp,
 675                             struct mlx5_create_qp_mbox_in **in, int *inlen)
 676 {
 677         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 678         struct mlx5_uuar_info *uuari;
 679         int uar_index;
 680         int uuarn;
 681         int err;
 682
 683         uuari = &dev->mdev->priv.uuari;
 684         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
 685                 return -EINVAL;
 686
 687         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 688                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 689
 690         uuarn = alloc_uuar(uuari, lc);
 691         if (uuarn < 0) {
 692                 mlx5_ib_dbg(dev, "\n");
 693                 return -ENOMEM;
 694         }
 695
 696         qp->bf = &uuari->bfs[uuarn];
 697         uar_index = qp->bf->uar->index;
 698
 699         err = calc_sq_size(dev, init_attr, qp);
 700         if (err < 0) {
 701                 mlx5_ib_dbg(dev, "err %d\n", err);
 702                 goto err_uuar;
 703         }
 704
 705         qp->rq.offset = 0;
 706         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 707         qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 708
 709         err = mlx5_buf_alloc(dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf);
 710         if (err) {
 711                 mlx5_ib_dbg(dev, "err %d\n", err);
 712                 goto err_uuar;
 713         }
 714
 715         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 716         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
 717         *in = mlx5_vzalloc(*inlen);
 718         if (!*in) {
 719                 err = -ENOMEM;
 720                 goto err_buf;
 721         }
 722         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 723         (*in)->ctx.log_pg_sz_remote_qpn =
 724                 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 725         /* Set "fast registration enabled" for all kernel QPs */
 726         (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
 727         (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
 728
 729         mlx5_fill_page_array(&qp->buf, (*in)->pas);
 730
 731         err = mlx5_db_alloc(dev->mdev, &qp->db);
 732         if (err) {
 733                 mlx5_ib_dbg(dev, "err %d\n", err);
 734                 goto err_free;
 735         }
 736
 737         qp->db.db[0] = 0;
 738         qp->db.db[1] = 0;
 739
 740         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 741         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 742         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 743         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 744         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 745
 746         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 747             !qp->sq.w_list || !qp->sq.wqe_head) {
 748                 err = -ENOMEM;
 749                 goto err_wrid;
 750         }
 751         qp->create_type = MLX5_QP_KERNEL;
 752
 753         return 0;
 754
 755 err_wrid:
 756         mlx5_db_free(dev->mdev, &qp->db);
 757         kfree(qp->sq.wqe_head);
 758         kfree(qp->sq.w_list);
 759         kfree(qp->sq.wrid);
 760         kfree(qp->sq.wr_data);
 761         kfree(qp->rq.wrid);
 762
 763 err_free:
 764         mlx5_vfree(*in);
 765
 766 err_buf:
 767         mlx5_buf_free(dev->mdev, &qp->buf);
 768
 769 err_uuar:
 770         free_uuar(&dev->mdev->priv.uuari, uuarn);
 771         return err;
 772 }
 773
 774 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 775 {
 776         mlx5_db_free(dev->mdev, &qp->db);
 777         kfree(qp->sq.wqe_head);
 778         kfree(qp->sq.w_list);
 779         kfree(qp->sq.wrid);
 780         kfree(qp->sq.wr_data);
 781         kfree(qp->rq.wrid);
 782         mlx5_buf_free(dev->mdev, &qp->buf);
 783         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 784 }
 785
 786 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 787 {
 788         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 789             (attr->qp_type == IB_QPT_XRC_INI))
 790                 return cpu_to_be32(MLX5_SRQ_RQ);
 791         else if (!qp->has_rq)
 792                 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
 793         else
 794                 return cpu_to_be32(MLX5_NON_ZERO_RQ);
 795 }
 796
 797 static int is_connected(enum ib_qp_type qp_type)
 798 {
 799         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
 800                 return 1;
 801
 802         return 0;
 803 }
 804
 805 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 806                             struct ib_qp_init_attr *init_attr,
 807                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
 808 {
 809         struct mlx5_ib_resources *devr = &dev->devr;
 810         struct mlx5_ib_create_qp_resp resp;
 811         struct mlx5_create_qp_mbox_in *in;
 812         struct mlx5_general_caps *gen;
 813         struct mlx5_ib_create_qp ucmd;
 814         int inlen = sizeof(*in);
 815         int err;
 816
 817         gen = &dev->mdev->caps.gen;
 818         mutex_init(&qp->mutex);
 819         spin_lock_init(&qp->sq.lock);
 820         spin_lock_init(&qp->rq.lock);
 821
 822         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
 823                 if (!(gen->flags & MLX5_DEV_CAP_FLAG_BLOCK_MCAST)) {
 824                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
 825                         return -EINVAL;
 826                 } else {
 827                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 828                 }
 829         }
 830
 831         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 832                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
 833
 834         if (pd && pd->uobject) {
 835                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
 836                         mlx5_ib_dbg(dev, "copy failed\n");
 837                         return -EFAULT;
 838                 }
 839
 840                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
 841                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
 842         } else {
 843                 qp->wq_sig = !!wq_signature;
 844         }
 845
 846         qp->has_rq = qp_has_rq(init_attr);
 847         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
 848                           qp, (pd && pd->uobject) ? &ucmd : NULL);
 849         if (err) {
 850                 mlx5_ib_dbg(dev, "err %d\n", err);
 851                 return err;
 852         }
 853
 854         if (pd) {
 855                 if (pd->uobject) {
 856                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
 857                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
 858                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
 859                                 mlx5_ib_dbg(dev, "invalid rq params\n");
 860                                 return -EINVAL;
 861                         }
 862                         if (ucmd.sq_wqe_count > gen->max_wqes) {
 863                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
 864                                             ucmd.sq_wqe_count, gen->max_wqes);
 865                                 return -EINVAL;
 866                         }
 867                         err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
 868                         if (err)
 869                                 mlx5_ib_dbg(dev, "err %d\n", err);
 870                 } else {
 871                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
 872                         if (err)
 873                                 mlx5_ib_dbg(dev, "err %d\n", err);
 874                         else
 875                                 qp->pa_lkey = to_mpd(pd)->pa_lkey;
 876                 }
 877
 878                 if (err)
 879                         return err;
 880         } else {
 881                 in = mlx5_vzalloc(sizeof(*in));
 882                 if (!in)
 883                         return -ENOMEM;
 884
 885                 qp->create_type = MLX5_QP_EMPTY;
 886         }
 887
 888         if (is_sqp(init_attr->qp_type))
 889                 qp->port = init_attr->port_num;
 890
 891         in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
 892                                     MLX5_QP_PM_MIGRATED << 11);
 893
 894         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
 895                 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
 896         else
 897                 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
 898
 899         if (qp->wq_sig)
 900                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
 901
 902         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
 903                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
 904
 905         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
 906                 int rcqe_sz;
 907                 int scqe_sz;
 908
 909                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
 910                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
 911
 912                 if (rcqe_sz == 128)
 913                         in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
 914                 else
 915                         in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
 916
 917                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
 918                         if (scqe_sz == 128)
 919                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
 920                         else
 921                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
 922                 }
 923         }
 924
 925         if (qp->rq.wqe_cnt) {
 926                 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
 927                 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
 928         }
 929
 930         in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
 931
 932         if (qp->sq.wqe_cnt)
 933                 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
 934         else
 935                 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
 936
 937         /* Set default resources */
 938         switch (init_attr->qp_type) {
 939         case IB_QPT_XRC_TGT:
 940                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 941                 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 942                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 943                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
 944                 break;
 945         case IB_QPT_XRC_INI:
 946                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 947                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
 948                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 949                 break;
 950         default:
 951                 if (init_attr->srq) {
 952                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
 953                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
 954                 } else {
 955                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
 956                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 957                 }
 958         }
 959
 960         if (init_attr->send_cq)
 961                 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
 962
 963         if (init_attr->recv_cq)
 964                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
 965
 966         in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
 967
 968         err = mlx5_core_create_qp(dev->mdev, &qp->mqp, in, inlen);
 969         if (err) {
 970                 mlx5_ib_dbg(dev, "create qp failed\n");
 971                 goto err_create;
 972         }
 973
 974         mlx5_vfree(in);
 975         /* Hardware wants QPN written in big-endian order (after
 976          * shifting) for send doorbell.  Precompute this value to save
 977          * a little bit when posting sends.
 978          */
 979         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 980
 981         qp->mqp.event = mlx5_ib_qp_event;
 982
 983         return 0;
 984
 985 err_create:
 986         if (qp->create_type == MLX5_QP_USER)
 987                 destroy_qp_user(pd, qp);
 988         else if (qp->create_type == MLX5_QP_KERNEL)
 989                 destroy_qp_kernel(dev, qp);
 990
 991         mlx5_vfree(in);
 992         return err;
 993 }
 994
 995 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
 996         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 997 {
 998         if (send_cq) {
 999                 if (recv_cq) {
1000                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1001                                 spin_lock_irq(&send_cq->lock);
1002                                 spin_lock_nested(&recv_cq->lock,
1003                                                  SINGLE_DEPTH_NESTING);
1004                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1005                                 spin_lock_irq(&send_cq->lock);
1006                                 __acquire(&recv_cq->lock);
1007                         } else {
1008                                 spin_lock_irq(&recv_cq->lock);
1009                                 spin_lock_nested(&send_cq->lock,
1010                                                  SINGLE_DEPTH_NESTING);
1011                         }
1012                 } else {
1013                         spin_lock_irq(&send_cq->lock);
1014                 }
1015         } else if (recv_cq) {
1016                 spin_lock_irq(&recv_cq->lock);
1017         }
1018 }
1019
1020 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1021         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1022 {
1023         if (send_cq) {
1024                 if (recv_cq) {
1025                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1026                                 spin_unlock(&recv_cq->lock);
1027                                 spin_unlock_irq(&send_cq->lock);
1028                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1029                                 __release(&recv_cq->lock);
1030                                 spin_unlock_irq(&send_cq->lock);
1031                         } else {
1032                                 spin_unlock(&send_cq->lock);
1033                                 spin_unlock_irq(&recv_cq->lock);
1034                         }
1035                 } else {
1036                         spin_unlock_irq(&send_cq->lock);
1037                 }
1038         } else if (recv_cq) {
1039                 spin_unlock_irq(&recv_cq->lock);
1040         }
1041 }
1042
1043 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1044 {
1045         return to_mpd(qp->ibqp.pd);
1046 }
1047
1048 static void get_cqs(struct mlx5_ib_qp *qp,
1049                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1050 {
1051         switch (qp->ibqp.qp_type) {
1052         case IB_QPT_XRC_TGT:
1053                 *send_cq = NULL;
1054                 *recv_cq = NULL;
1055                 break;
1056         case MLX5_IB_QPT_REG_UMR:
1057         case IB_QPT_XRC_INI:
1058                 *send_cq = to_mcq(qp->ibqp.send_cq);
1059                 *recv_cq = NULL;
1060                 break;
1061
1062         case IB_QPT_SMI:
1063         case IB_QPT_GSI:
1064         case IB_QPT_RC:
1065         case IB_QPT_UC:
1066         case IB_QPT_UD:
1067         case IB_QPT_RAW_IPV6:
1068         case IB_QPT_RAW_ETHERTYPE:
1069                 *send_cq = to_mcq(qp->ibqp.send_cq);
1070                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1071                 break;
1072
1073         case IB_QPT_RAW_PACKET:
1074         case IB_QPT_MAX:
1075         default:
1076                 *send_cq = NULL;
1077                 *recv_cq = NULL;
1078                 break;
1079         }
1080 }
1081
1082 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1083 {
1084         struct mlx5_ib_cq *send_cq, *recv_cq;
1085         struct mlx5_modify_qp_mbox_in *in;
1086         int err;
1087
1088         in = kzalloc(sizeof(*in), GFP_KERNEL);
1089         if (!in)
1090                 return;
1091         if (qp->state != IB_QPS_RESET)
1092                 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state),
1093                                         MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp))
1094                         mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1095                                      qp->mqp.qpn);
1096
1097         get_cqs(qp, &send_cq, &recv_cq);
1098
1099         if (qp->create_type == MLX5_QP_KERNEL) {
1100                 mlx5_ib_lock_cqs(send_cq, recv_cq);
1101                 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1102                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1103                 if (send_cq != recv_cq)
1104                         __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1105                 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1106         }
1107
1108         err = mlx5_core_destroy_qp(dev->mdev, &qp->mqp);
1109         if (err)
1110                 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1111         kfree(in);
1112
1113
1114         if (qp->create_type == MLX5_QP_KERNEL)
1115                 destroy_qp_kernel(dev, qp);
1116         else if (qp->create_type == MLX5_QP_USER)
1117                 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1118 }
1119
1120 static const char *ib_qp_type_str(enum ib_qp_type type)
1121 {
1122         switch (type) {
1123         case IB_QPT_SMI:
1124                 return "IB_QPT_SMI";
1125         case IB_QPT_GSI:
1126                 return "IB_QPT_GSI";
1127         case IB_QPT_RC:
1128                 return "IB_QPT_RC";
1129         case IB_QPT_UC:
1130                 return "IB_QPT_UC";
1131         case IB_QPT_UD:
1132                 return "IB_QPT_UD";
1133         case IB_QPT_RAW_IPV6:
1134                 return "IB_QPT_RAW_IPV6";
1135         case IB_QPT_RAW_ETHERTYPE:
1136                 return "IB_QPT_RAW_ETHERTYPE";
1137         case IB_QPT_XRC_INI:
1138                 return "IB_QPT_XRC_INI";
1139         case IB_QPT_XRC_TGT:
1140                 return "IB_QPT_XRC_TGT";
1141         case IB_QPT_RAW_PACKET:
1142                 return "IB_QPT_RAW_PACKET";
1143         case MLX5_IB_QPT_REG_UMR:
1144                 return "MLX5_IB_QPT_REG_UMR";
1145         case IB_QPT_MAX:
1146         default:
1147                 return "Invalid QP type";
1148         }
1149 }
1150
1151 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1152                                 struct ib_qp_init_attr *init_attr,
1153                                 struct ib_udata *udata)
1154 {
1155         struct mlx5_general_caps *gen;
1156         struct mlx5_ib_dev *dev;
1157         struct mlx5_ib_qp *qp;
1158         u16 xrcdn = 0;
1159         int err;
1160
1161         if (pd) {
1162                 dev = to_mdev(pd->device);
1163         } else {
1164                 /* being cautious here */
1165                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1166                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1167                         pr_warn("%s: no PD for transport %s\n", __func__,
1168                                 ib_qp_type_str(init_attr->qp_type));
1169                         return ERR_PTR(-EINVAL);
1170                 }
1171                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1172         }
1173         gen = &dev->mdev->caps.gen;
1174
1175         switch (init_attr->qp_type) {
1176         case IB_QPT_XRC_TGT:
1177         case IB_QPT_XRC_INI:
1178                 if (!(gen->flags & MLX5_DEV_CAP_FLAG_XRC)) {
1179                         mlx5_ib_dbg(dev, "XRC not supported\n");
1180                         return ERR_PTR(-ENOSYS);
1181                 }
1182                 init_attr->recv_cq = NULL;
1183                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1184                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1185                         init_attr->send_cq = NULL;
1186                 }
1187
1188                 /* fall through */
1189         case IB_QPT_RC:
1190         case IB_QPT_UC:
1191         case IB_QPT_UD:
1192         case IB_QPT_SMI:
1193         case IB_QPT_GSI:
1194         case MLX5_IB_QPT_REG_UMR:
1195                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1196                 if (!qp)
1197                         return ERR_PTR(-ENOMEM);
1198
1199                 err = create_qp_common(dev, pd, init_attr, udata, qp);
1200                 if (err) {
1201                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
1202                         kfree(qp);
1203                         return ERR_PTR(err);
1204                 }
1205
1206                 if (is_qp0(init_attr->qp_type))
1207                         qp->ibqp.qp_num = 0;
1208                 else if (is_qp1(init_attr->qp_type))
1209                         qp->ibqp.qp_num = 1;
1210                 else
1211                         qp->ibqp.qp_num = qp->mqp.qpn;
1212
1213                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1214                             qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1215                             to_mcq(init_attr->send_cq)->mcq.cqn);
1216
1217                 qp->xrcdn = xrcdn;
1218
1219                 break;
1220
1221         case IB_QPT_RAW_IPV6:
1222         case IB_QPT_RAW_ETHERTYPE:
1223         case IB_QPT_RAW_PACKET:
1224         case IB_QPT_MAX:
1225         default:
1226                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1227                             init_attr->qp_type);
1228                 /* Don't support raw QPs */
1229                 return ERR_PTR(-EINVAL);
1230         }
1231
1232         return &qp->ibqp;
1233 }
1234
1235 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1236 {
1237         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1238         struct mlx5_ib_qp *mqp = to_mqp(qp);
1239
1240         destroy_qp_common(dev, mqp);
1241
1242         kfree(mqp);
1243
1244         return 0;
1245 }
1246
1247 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1248                                    int attr_mask)
1249 {
1250         u32 hw_access_flags = 0;
1251         u8 dest_rd_atomic;
1252         u32 access_flags;
1253
1254         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1255                 dest_rd_atomic = attr->max_dest_rd_atomic;
1256         else
1257                 dest_rd_atomic = qp->resp_depth;
1258
1259         if (attr_mask & IB_QP_ACCESS_FLAGS)
1260                 access_flags = attr->qp_access_flags;
1261         else
1262                 access_flags = qp->atomic_rd_en;
1263
1264         if (!dest_rd_atomic)
1265                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1266
1267         if (access_flags & IB_ACCESS_REMOTE_READ)
1268                 hw_access_flags |= MLX5_QP_BIT_RRE;
1269         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1270                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1271         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1272                 hw_access_flags |= MLX5_QP_BIT_RWE;
1273
1274         return cpu_to_be32(hw_access_flags);
1275 }
1276
1277 enum {
1278         MLX5_PATH_FLAG_FL       = 1 << 0,
1279         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
1280         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
1281 };
1282
1283 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1284 {
1285         struct mlx5_general_caps *gen;
1286
1287         gen = &dev->mdev->caps.gen;
1288         if (rate == IB_RATE_PORT_CURRENT) {
1289                 return 0;
1290         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1291                 return -EINVAL;
1292         } else {
1293                 while (rate != IB_RATE_2_5_GBPS &&
1294                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1295                          gen->stat_rate_support))
1296                         --rate;
1297         }
1298
1299         return rate + MLX5_STAT_RATE_OFFSET;
1300 }
1301
1302 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1303                          struct mlx5_qp_path *path, u8 port, int attr_mask,
1304                          u32 path_flags, const struct ib_qp_attr *attr)
1305 {
1306         struct mlx5_general_caps *gen;
1307         int err;
1308
1309         gen = &dev->mdev->caps.gen;
1310         path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1311         path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1312
1313         if (attr_mask & IB_QP_PKEY_INDEX)
1314                 path->pkey_index = attr->pkey_index;
1315
1316         path->grh_mlid  = ah->src_path_bits & 0x7f;
1317         path->rlid      = cpu_to_be16(ah->dlid);
1318
1319         if (ah->ah_flags & IB_AH_GRH) {
1320                 if (ah->grh.sgid_index >= gen->port[port - 1].gid_table_len) {
1321                         pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n",
1322                                ah->grh.sgid_index, gen->port[port - 1].gid_table_len);
1323                         return -EINVAL;
1324                 }
1325                 path->grh_mlid |= 1 << 7;
1326                 path->mgid_index = ah->grh.sgid_index;
1327                 path->hop_limit  = ah->grh.hop_limit;
1328                 path->tclass_flowlabel =
1329                         cpu_to_be32((ah->grh.traffic_class << 20) |
1330                                     (ah->grh.flow_label));
1331                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1332         }
1333
1334         err = ib_rate_to_mlx5(dev, ah->static_rate);
1335         if (err < 0)
1336                 return err;
1337         path->static_rate = err;
1338         path->port = port;
1339
1340         if (attr_mask & IB_QP_TIMEOUT)
1341                 path->ackto_lt = attr->timeout << 3;
1342
1343         path->sl = ah->sl & 0xf;
1344
1345         return 0;
1346 }
1347
1348 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1349         [MLX5_QP_STATE_INIT] = {
1350                 [MLX5_QP_STATE_INIT] = {
1351                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1352                                           MLX5_QP_OPTPAR_RAE            |
1353                                           MLX5_QP_OPTPAR_RWE            |
1354                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1355                                           MLX5_QP_OPTPAR_PRI_PORT,
1356                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1357                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1358                                           MLX5_QP_OPTPAR_PRI_PORT,
1359                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1360                                           MLX5_QP_OPTPAR_Q_KEY          |
1361                                           MLX5_QP_OPTPAR_PRI_PORT,
1362                 },
1363                 [MLX5_QP_STATE_RTR] = {
1364                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1365                                           MLX5_QP_OPTPAR_RRE            |
1366                                           MLX5_QP_OPTPAR_RAE            |
1367                                           MLX5_QP_OPTPAR_RWE            |
1368                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1369                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1370                                           MLX5_QP_OPTPAR_RWE            |
1371                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1372                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1373                                           MLX5_QP_OPTPAR_Q_KEY,
1374                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
1375                                            MLX5_QP_OPTPAR_Q_KEY,
1376                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1377                                           MLX5_QP_OPTPAR_RRE            |
1378                                           MLX5_QP_OPTPAR_RAE            |
1379                                           MLX5_QP_OPTPAR_RWE            |
1380                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1381                 },
1382         },
1383         [MLX5_QP_STATE_RTR] = {
1384                 [MLX5_QP_STATE_RTS] = {
1385                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1386                                           MLX5_QP_OPTPAR_RRE            |
1387                                           MLX5_QP_OPTPAR_RAE            |
1388                                           MLX5_QP_OPTPAR_RWE            |
1389                                           MLX5_QP_OPTPAR_PM_STATE       |
1390                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
1391                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1392                                           MLX5_QP_OPTPAR_RWE            |
1393                                           MLX5_QP_OPTPAR_PM_STATE,
1394                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1395                 },
1396         },
1397         [MLX5_QP_STATE_RTS] = {
1398                 [MLX5_QP_STATE_RTS] = {
1399                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1400                                           MLX5_QP_OPTPAR_RAE            |
1401                                           MLX5_QP_OPTPAR_RWE            |
1402                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
1403                                           MLX5_QP_OPTPAR_PM_STATE       |
1404                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1405                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1406                                           MLX5_QP_OPTPAR_PM_STATE       |
1407                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1408                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
1409                                           MLX5_QP_OPTPAR_SRQN           |
1410                                           MLX5_QP_OPTPAR_CQN_RCV,
1411                 },
1412         },
1413         [MLX5_QP_STATE_SQER] = {
1414                 [MLX5_QP_STATE_RTS] = {
1415                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
1416                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1417                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
1418                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
1419                                            MLX5_QP_OPTPAR_RWE           |
1420                                            MLX5_QP_OPTPAR_RAE           |
1421                                            MLX5_QP_OPTPAR_RRE,
1422                 },
1423         },
1424 };
1425
1426 static int ib_nr_to_mlx5_nr(int ib_mask)
1427 {
1428         switch (ib_mask) {
1429         case IB_QP_STATE:
1430                 return 0;
1431         case IB_QP_CUR_STATE:
1432                 return 0;
1433         case IB_QP_EN_SQD_ASYNC_NOTIFY:
1434                 return 0;
1435         case IB_QP_ACCESS_FLAGS:
1436                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1437                         MLX5_QP_OPTPAR_RAE;
1438         case IB_QP_PKEY_INDEX:
1439                 return MLX5_QP_OPTPAR_PKEY_INDEX;
1440         case IB_QP_PORT:
1441                 return MLX5_QP_OPTPAR_PRI_PORT;
1442         case IB_QP_QKEY:
1443                 return MLX5_QP_OPTPAR_Q_KEY;
1444         case IB_QP_AV:
1445                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1446                         MLX5_QP_OPTPAR_PRI_PORT;
1447         case IB_QP_PATH_MTU:
1448                 return 0;
1449         case IB_QP_TIMEOUT:
1450                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1451         case IB_QP_RETRY_CNT:
1452                 return MLX5_QP_OPTPAR_RETRY_COUNT;
1453         case IB_QP_RNR_RETRY:
1454                 return MLX5_QP_OPTPAR_RNR_RETRY;
1455         case IB_QP_RQ_PSN:
1456                 return 0;
1457         case IB_QP_MAX_QP_RD_ATOMIC:
1458                 return MLX5_QP_OPTPAR_SRA_MAX;
1459         case IB_QP_ALT_PATH:
1460                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1461         case IB_QP_MIN_RNR_TIMER:
1462                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1463         case IB_QP_SQ_PSN:
1464                 return 0;
1465         case IB_QP_MAX_DEST_RD_ATOMIC:
1466                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1467                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1468         case IB_QP_PATH_MIG_STATE:
1469                 return MLX5_QP_OPTPAR_PM_STATE;
1470         case IB_QP_CAP:
1471                 return 0;
1472         case IB_QP_DEST_QPN:
1473                 return 0;
1474         }
1475         return 0;
1476 }
1477
1478 static int ib_mask_to_mlx5_opt(int ib_mask)
1479 {
1480         int result = 0;
1481         int i;
1482
1483         for (i = 0; i < 8 * sizeof(int); i++) {
1484                 if ((1 << i) & ib_mask)
1485                         result |= ib_nr_to_mlx5_nr(1 << i);
1486         }
1487
1488         return result;
1489 }
1490
1491 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1492                                const struct ib_qp_attr *attr, int attr_mask,
1493                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1494 {
1495         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1496         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1497         struct mlx5_ib_cq *send_cq, *recv_cq;
1498         struct mlx5_qp_context *context;
1499         struct mlx5_general_caps *gen;
1500         struct mlx5_modify_qp_mbox_in *in;
1501         struct mlx5_ib_pd *pd;
1502         enum mlx5_qp_state mlx5_cur, mlx5_new;
1503         enum mlx5_qp_optpar optpar;
1504         int sqd_event;
1505         int mlx5_st;
1506         int err;
1507
1508         gen = &dev->mdev->caps.gen;
1509         in = kzalloc(sizeof(*in), GFP_KERNEL);
1510         if (!in)
1511                 return -ENOMEM;
1512
1513         context = &in->ctx;
1514         err = to_mlx5_st(ibqp->qp_type);
1515         if (err < 0)
1516                 goto out;
1517
1518         context->flags = cpu_to_be32(err << 16);
1519
1520         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1521                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1522         } else {
1523                 switch (attr->path_mig_state) {
1524                 case IB_MIG_MIGRATED:
1525                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1526                         break;
1527                 case IB_MIG_REARM:
1528                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1529                         break;
1530                 case IB_MIG_ARMED:
1531                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1532                         break;
1533                 }
1534         }
1535
1536         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1537                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1538         } else if (ibqp->qp_type == IB_QPT_UD ||
1539                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1540                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1541         } else if (attr_mask & IB_QP_PATH_MTU) {
1542                 if (attr->path_mtu < IB_MTU_256 ||
1543                     attr->path_mtu > IB_MTU_4096) {
1544                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1545                         err = -EINVAL;
1546                         goto out;
1547                 }
1548                 context->mtu_msgmax = (attr->path_mtu << 5) | gen->log_max_msg;
1549         }
1550
1551         if (attr_mask & IB_QP_DEST_QPN)
1552                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1553
1554         if (attr_mask & IB_QP_PKEY_INDEX)
1555                 context->pri_path.pkey_index = attr->pkey_index;
1556
1557         /* todo implement counter_index functionality */
1558
1559         if (is_sqp(ibqp->qp_type))
1560                 context->pri_path.port = qp->port;
1561
1562         if (attr_mask & IB_QP_PORT)
1563                 context->pri_path.port = attr->port_num;
1564
1565         if (attr_mask & IB_QP_AV) {
1566                 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1567                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1568                                     attr_mask, 0, attr);
1569                 if (err)
1570                         goto out;
1571         }
1572
1573         if (attr_mask & IB_QP_TIMEOUT)
1574                 context->pri_path.ackto_lt |= attr->timeout << 3;
1575
1576         if (attr_mask & IB_QP_ALT_PATH) {
1577                 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1578                                     attr->alt_port_num, attr_mask, 0, attr);
1579                 if (err)
1580                         goto out;
1581         }
1582
1583         pd = get_pd(qp);
1584         get_cqs(qp, &send_cq, &recv_cq);
1585
1586         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1587         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1588         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1589         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1590
1591         if (attr_mask & IB_QP_RNR_RETRY)
1592                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1593
1594         if (attr_mask & IB_QP_RETRY_CNT)
1595                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1596
1597         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1598                 if (attr->max_rd_atomic)
1599                         context->params1 |=
1600                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1601         }
1602
1603         if (attr_mask & IB_QP_SQ_PSN)
1604                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1605
1606         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1607                 if (attr->max_dest_rd_atomic)
1608                         context->params2 |=
1609                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1610         }
1611
1612         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1613                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1614
1615         if (attr_mask & IB_QP_MIN_RNR_TIMER)
1616                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1617
1618         if (attr_mask & IB_QP_RQ_PSN)
1619                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1620
1621         if (attr_mask & IB_QP_QKEY)
1622                 context->qkey = cpu_to_be32(attr->qkey);
1623
1624         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1625                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1626
1627         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1628             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1629                 sqd_event = 1;
1630         else
1631                 sqd_event = 0;
1632
1633         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1634                 context->sq_crq_size |= cpu_to_be16(1 << 4);
1635
1636
1637         mlx5_cur = to_mlx5_state(cur_state);
1638         mlx5_new = to_mlx5_state(new_state);
1639         mlx5_st = to_mlx5_st(ibqp->qp_type);
1640         if (mlx5_st < 0)
1641                 goto out;
1642
1643         optpar = ib_mask_to_mlx5_opt(attr_mask);
1644         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1645         in->optparam = cpu_to_be32(optpar);
1646         err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state),
1647                                   to_mlx5_state(new_state), in, sqd_event,
1648                                   &qp->mqp);
1649         if (err)
1650                 goto out;
1651
1652         qp->state = new_state;
1653
1654         if (attr_mask & IB_QP_ACCESS_FLAGS)
1655                 qp->atomic_rd_en = attr->qp_access_flags;
1656         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1657                 qp->resp_depth = attr->max_dest_rd_atomic;
1658         if (attr_mask & IB_QP_PORT)
1659                 qp->port = attr->port_num;
1660         if (attr_mask & IB_QP_ALT_PATH)
1661                 qp->alt_port = attr->alt_port_num;
1662
1663         /*
1664          * If we moved a kernel QP to RESET, clean up all old CQ
1665          * entries and reinitialize the QP.
1666          */
1667         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1668                 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1669                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1670                 if (send_cq != recv_cq)
1671                         mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1672
1673                 qp->rq.head = 0;
1674                 qp->rq.tail = 0;
1675                 qp->sq.head = 0;
1676                 qp->sq.tail = 0;
1677                 qp->sq.cur_post = 0;
1678                 qp->sq.last_poll = 0;
1679                 qp->db.db[MLX5_RCV_DBR] = 0;
1680                 qp->db.db[MLX5_SND_DBR] = 0;
1681         }
1682
1683 out:
1684         kfree(in);
1685         return err;
1686 }
1687
1688 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1689                       int attr_mask, struct ib_udata *udata)
1690 {
1691         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1692         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1693         enum ib_qp_state cur_state, new_state;
1694         struct mlx5_general_caps *gen;
1695         int err = -EINVAL;
1696         int port;
1697
1698         gen = &dev->mdev->caps.gen;
1699         mutex_lock(&qp->mutex);
1700
1701         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1702         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1703
1704         if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1705             !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
1706                                 IB_LINK_LAYER_UNSPECIFIED))
1707                 goto out;
1708
1709         if ((attr_mask & IB_QP_PORT) &&
1710             (attr->port_num == 0 || attr->port_num > gen->num_ports))
1711                 goto out;
1712
1713         if (attr_mask & IB_QP_PKEY_INDEX) {
1714                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1715                 if (attr->pkey_index >= gen->port[port - 1].pkey_table_len)
1716                         goto out;
1717         }
1718
1719         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1720             attr->max_rd_atomic > (1 << gen->log_max_ra_res_qp))
1721                 goto out;
1722
1723         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1724             attr->max_dest_rd_atomic > (1 << gen->log_max_ra_req_qp))
1725                 goto out;
1726
1727         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1728                 err = 0;
1729                 goto out;
1730         }
1731
1732         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1733
1734 out:
1735         mutex_unlock(&qp->mutex);
1736         return err;
1737 }
1738
1739 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1740 {
1741         struct mlx5_ib_cq *cq;
1742         unsigned cur;
1743
1744         cur = wq->head - wq->tail;
1745         if (likely(cur + nreq < wq->max_post))
1746                 return 0;
1747
1748         cq = to_mcq(ib_cq);
1749         spin_lock(&cq->lock);
1750         cur = wq->head - wq->tail;
1751         spin_unlock(&cq->lock);
1752
1753         return cur + nreq >= wq->max_post;
1754 }
1755
1756 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1757                                           u64 remote_addr, u32 rkey)
1758 {
1759         rseg->raddr    = cpu_to_be64(remote_addr);
1760         rseg->rkey     = cpu_to_be32(rkey);
1761         rseg->reserved = 0;
1762 }
1763
1764 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1765                              struct ib_send_wr *wr)
1766 {
1767         memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1768         dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1769         dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1770 }
1771
1772 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1773 {
1774         dseg->byte_count = cpu_to_be32(sg->length);
1775         dseg->lkey       = cpu_to_be32(sg->lkey);
1776         dseg->addr       = cpu_to_be64(sg->addr);
1777 }
1778
1779 static __be16 get_klm_octo(int npages)
1780 {
1781         return cpu_to_be16(ALIGN(npages, 8) / 2);
1782 }
1783
1784 static __be64 frwr_mkey_mask(void)
1785 {
1786         u64 result;
1787
1788         result = MLX5_MKEY_MASK_LEN             |
1789                 MLX5_MKEY_MASK_PAGE_SIZE        |
1790                 MLX5_MKEY_MASK_START_ADDR       |
1791                 MLX5_MKEY_MASK_EN_RINVAL        |
1792                 MLX5_MKEY_MASK_KEY              |
1793                 MLX5_MKEY_MASK_LR               |
1794                 MLX5_MKEY_MASK_LW               |
1795                 MLX5_MKEY_MASK_RR               |
1796                 MLX5_MKEY_MASK_RW               |
1797                 MLX5_MKEY_MASK_A                |
1798                 MLX5_MKEY_MASK_SMALL_FENCE      |
1799                 MLX5_MKEY_MASK_FREE;
1800
1801         return cpu_to_be64(result);
1802 }
1803
1804 static __be64 sig_mkey_mask(void)
1805 {
1806         u64 result;
1807
1808         result = MLX5_MKEY_MASK_LEN             |
1809                 MLX5_MKEY_MASK_PAGE_SIZE        |
1810                 MLX5_MKEY_MASK_START_ADDR       |
1811                 MLX5_MKEY_MASK_EN_SIGERR        |
1812                 MLX5_MKEY_MASK_EN_RINVAL        |
1813                 MLX5_MKEY_MASK_KEY              |
1814                 MLX5_MKEY_MASK_LR               |
1815                 MLX5_MKEY_MASK_LW               |
1816                 MLX5_MKEY_MASK_RR               |
1817                 MLX5_MKEY_MASK_RW               |
1818                 MLX5_MKEY_MASK_SMALL_FENCE      |
1819                 MLX5_MKEY_MASK_FREE             |
1820                 MLX5_MKEY_MASK_BSF_EN;
1821
1822         return cpu_to_be64(result);
1823 }
1824
1825 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1826                                  struct ib_send_wr *wr, int li)
1827 {
1828         memset(umr, 0, sizeof(*umr));
1829
1830         if (li) {
1831                 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1832                 umr->flags = 1 << 7;
1833                 return;
1834         }
1835
1836         umr->flags = (1 << 5); /* fail if not free */
1837         umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1838         umr->mkey_mask = frwr_mkey_mask();
1839 }
1840
1841 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1842                                 struct ib_send_wr *wr)
1843 {
1844         struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg;
1845         u64 mask;
1846
1847         memset(umr, 0, sizeof(*umr));
1848
1849         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1850                 umr->flags = 1 << 5; /* fail if not free */
1851                 umr->klm_octowords = get_klm_octo(umrwr->npages);
1852                 mask =  MLX5_MKEY_MASK_LEN              |
1853                         MLX5_MKEY_MASK_PAGE_SIZE        |
1854                         MLX5_MKEY_MASK_START_ADDR       |
1855                         MLX5_MKEY_MASK_PD               |
1856                         MLX5_MKEY_MASK_LR               |
1857                         MLX5_MKEY_MASK_LW               |
1858                         MLX5_MKEY_MASK_KEY              |
1859                         MLX5_MKEY_MASK_RR               |
1860                         MLX5_MKEY_MASK_RW               |
1861                         MLX5_MKEY_MASK_A                |
1862                         MLX5_MKEY_MASK_FREE;
1863                 umr->mkey_mask = cpu_to_be64(mask);
1864         } else {
1865                 umr->flags = 2 << 5; /* fail if free */
1866                 mask = MLX5_MKEY_MASK_FREE;
1867                 umr->mkey_mask = cpu_to_be64(mask);
1868         }
1869
1870         if (!wr->num_sge)
1871                 umr->flags |= (1 << 7); /* inline */
1872 }
1873
1874 static u8 get_umr_flags(int acc)
1875 {
1876         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
1877                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
1878                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
1879                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
1880                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
1881 }
1882
1883 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1884                              int li, int *writ)
1885 {
1886         memset(seg, 0, sizeof(*seg));
1887         if (li) {
1888                 seg->status = 1 << 6;
1889                 return;
1890         }
1891
1892         seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags) |
1893                      MLX5_ACCESS_MODE_MTT;
1894         *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
1895         seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
1896         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
1897         seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1898         seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1899         seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
1900         seg->log2_page_size = wr->wr.fast_reg.page_shift;
1901 }
1902
1903 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
1904 {
1905         memset(seg, 0, sizeof(*seg));
1906         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
1907                 seg->status = 1 << 6;
1908                 return;
1909         }
1910
1911         seg->flags = convert_access(wr->wr.fast_reg.access_flags);
1912         seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn);
1913         seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1914         seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1915         seg->log2_page_size = wr->wr.fast_reg.page_shift;
1916         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
1917                                        mlx5_mkey_variant(wr->wr.fast_reg.rkey));
1918 }
1919
1920 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
1921                            struct ib_send_wr *wr,
1922                            struct mlx5_core_dev *mdev,
1923                            struct mlx5_ib_pd *pd,
1924                            int writ)
1925 {
1926         struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1927         u64 *page_list = wr->wr.fast_reg.page_list->page_list;
1928         u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
1929         int i;
1930
1931         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
1932                 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
1933         dseg->addr = cpu_to_be64(mfrpl->map);
1934         dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
1935         dseg->lkey = cpu_to_be32(pd->pa_lkey);
1936 }
1937
1938 static __be32 send_ieth(struct ib_send_wr *wr)
1939 {
1940         switch (wr->opcode) {
1941         case IB_WR_SEND_WITH_IMM:
1942         case IB_WR_RDMA_WRITE_WITH_IMM:
1943                 return wr->ex.imm_data;
1944
1945         case IB_WR_SEND_WITH_INV:
1946                 return cpu_to_be32(wr->ex.invalidate_rkey);
1947
1948         default:
1949                 return 0;
1950         }
1951 }
1952
1953 static u8 calc_sig(void *wqe, int size)
1954 {
1955         u8 *p = wqe;
1956         u8 res = 0;
1957         int i;
1958
1959         for (i = 0; i < size; i++)
1960                 res ^= p[i];
1961
1962         return ~res;
1963 }
1964
1965 static u8 wq_sig(void *wqe)
1966 {
1967         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
1968 }
1969
1970 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
1971                             void *wqe, int *sz)
1972 {
1973         struct mlx5_wqe_inline_seg *seg;
1974         void *qend = qp->sq.qend;
1975         void *addr;
1976         int inl = 0;
1977         int copy;
1978         int len;
1979         int i;
1980
1981         seg = wqe;
1982         wqe += sizeof(*seg);
1983         for (i = 0; i < wr->num_sge; i++) {
1984                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
1985                 len  = wr->sg_list[i].length;
1986                 inl += len;
1987
1988                 if (unlikely(inl > qp->max_inline_data))
1989                         return -ENOMEM;
1990
1991                 if (unlikely(wqe + len > qend)) {
1992                         copy = qend - wqe;
1993                         memcpy(wqe, addr, copy);
1994                         addr += copy;
1995                         len -= copy;
1996                         wqe = mlx5_get_send_wqe(qp, 0);
1997                 }
1998                 memcpy(wqe, addr, len);
1999                 wqe += len;
2000         }
2001
2002         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2003
2004         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2005
2006         return 0;
2007 }
2008
2009 static u16 prot_field_size(enum ib_signature_type type)
2010 {
2011         switch (type) {
2012         case IB_SIG_TYPE_T10_DIF:
2013                 return MLX5_DIF_SIZE;
2014         default:
2015                 return 0;
2016         }
2017 }
2018
2019 static u8 bs_selector(int block_size)
2020 {
2021         switch (block_size) {
2022         case 512:           return 0x1;
2023         case 520:           return 0x2;
2024         case 4096:          return 0x3;
2025         case 4160:          return 0x4;
2026         case 1073741824:    return 0x5;
2027         default:            return 0;
2028         }
2029 }
2030
2031 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2032                               struct mlx5_bsf_inl *inl)
2033 {
2034         /* Valid inline section and allow BSF refresh */
2035         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2036                                        MLX5_BSF_REFRESH_DIF);
2037         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2038         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
2039         /* repeating block */
2040         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2041         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2042                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
2043
2044         if (domain->sig.dif.ref_remap)
2045                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
2046
2047         if (domain->sig.dif.app_escape) {
2048                 if (domain->sig.dif.ref_escape)
2049                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2050                 else
2051                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
2052         }
2053
2054         inl->dif_app_bitmask_check =
2055                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
2056 }
2057
2058 static int mlx5_set_bsf(struct ib_mr *sig_mr,
2059                         struct ib_sig_attrs *sig_attrs,
2060                         struct mlx5_bsf *bsf, u32 data_size)
2061 {
2062         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2063         struct mlx5_bsf_basic *basic = &bsf->basic;
2064         struct ib_sig_domain *mem = &sig_attrs->mem;
2065         struct ib_sig_domain *wire = &sig_attrs->wire;
2066
2067         memset(bsf, 0, sizeof(*bsf));
2068
2069         /* Basic + Extended + Inline */
2070         basic->bsf_size_sbs = 1 << 7;
2071         /* Input domain check byte mask */
2072         basic->check_byte_mask = sig_attrs->check_mask;
2073         basic->raw_data_size = cpu_to_be32(data_size);
2074
2075         /* Memory domain */
2076         switch (sig_attrs->mem.sig_type) {
2077         case IB_SIG_TYPE_NONE:
2078                 break;
2079         case IB_SIG_TYPE_T10_DIF:
2080                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2081                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2082                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2083                 break;
2084         default:
2085                 return -EINVAL;
2086         }
2087
2088         /* Wire domain */
2089         switch (sig_attrs->wire.sig_type) {
2090         case IB_SIG_TYPE_NONE:
2091                 break;
2092         case IB_SIG_TYPE_T10_DIF:
2093                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
2094                     mem->sig_type == wire->sig_type) {
2095                         /* Same block structure */
2096                         basic->bsf_size_sbs |= 1 << 4;
2097                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
2098                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
2099                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
2100                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
2101                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
2102                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
2103                 } else
2104                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2105
2106                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
2107                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
2108                 break;
2109         default:
2110                 return -EINVAL;
2111         }
2112
2113         return 0;
2114 }
2115
2116 static int set_sig_data_segment(struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
2117                                 void **seg, int *size)
2118 {
2119         struct ib_sig_attrs *sig_attrs = wr->wr.sig_handover.sig_attrs;
2120         struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr;
2121         struct mlx5_bsf *bsf;
2122         u32 data_len = wr->sg_list->length;
2123         u32 data_key = wr->sg_list->lkey;
2124         u64 data_va = wr->sg_list->addr;
2125         int ret;
2126         int wqe_size;
2127
2128         if (!wr->wr.sig_handover.prot ||
2129             (data_key == wr->wr.sig_handover.prot->lkey &&
2130              data_va == wr->wr.sig_handover.prot->addr &&
2131              data_len == wr->wr.sig_handover.prot->length)) {
2132                 /**
2133                  * Source domain doesn't contain signature information
2134                  * or data and protection are interleaved in memory.
2135                  * So need construct:
2136                  *                  ------------------
2137                  *                 |     data_klm     |
2138                  *                  ------------------
2139                  *                 |       BSF        |
2140                  *                  ------------------
2141                  **/
2142                 struct mlx5_klm *data_klm = *seg;
2143
2144                 data_klm->bcount = cpu_to_be32(data_len);
2145                 data_klm->key = cpu_to_be32(data_key);
2146                 data_klm->va = cpu_to_be64(data_va);
2147                 wqe_size = ALIGN(sizeof(*data_klm), 64);
2148         } else {
2149                 /**
2150                  * Source domain contains signature information
2151                  * So need construct a strided block format:
2152                  *               ---------------------------
2153                  *              |     stride_block_ctrl     |
2154                  *               ---------------------------
2155                  *              |          data_klm         |
2156                  *               ---------------------------
2157                  *              |          prot_klm         |
2158                  *               ---------------------------
2159                  *              |             BSF           |
2160                  *               ---------------------------
2161                  **/
2162                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2163                 struct mlx5_stride_block_entry *data_sentry;
2164                 struct mlx5_stride_block_entry *prot_sentry;
2165                 u32 prot_key = wr->wr.sig_handover.prot->lkey;
2166                 u64 prot_va = wr->wr.sig_handover.prot->addr;
2167                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2168                 int prot_size;
2169
2170                 sblock_ctrl = *seg;
2171                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2172                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2173
2174                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2175                 if (!prot_size) {
2176                         pr_err("Bad block size given: %u\n", block_size);
2177                         return -EINVAL;
2178                 }
2179                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
2180                                                             prot_size);
2181                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
2182                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
2183                 sblock_ctrl->num_entries = cpu_to_be16(2);
2184
2185                 data_sentry->bcount = cpu_to_be16(block_size);
2186                 data_sentry->key = cpu_to_be32(data_key);
2187                 data_sentry->va = cpu_to_be64(data_va);
2188                 data_sentry->stride = cpu_to_be16(block_size);
2189
2190                 prot_sentry->bcount = cpu_to_be16(prot_size);
2191                 prot_sentry->key = cpu_to_be32(prot_key);
2192                 prot_sentry->va = cpu_to_be64(prot_va);
2193                 prot_sentry->stride = cpu_to_be16(prot_size);
2194
2195                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
2196                                  sizeof(*prot_sentry), 64);
2197         }
2198
2199         *seg += wqe_size;
2200         *size += wqe_size / 16;
2201         if (unlikely((*seg == qp->sq.qend)))
2202                 *seg = mlx5_get_send_wqe(qp, 0);
2203
2204         bsf = *seg;
2205         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
2206         if (ret)
2207                 return -EINVAL;
2208
2209         *seg += sizeof(*bsf);
2210         *size += sizeof(*bsf) / 16;
2211         if (unlikely((*seg == qp->sq.qend)))
2212                 *seg = mlx5_get_send_wqe(qp, 0);
2213
2214         return 0;
2215 }
2216
2217 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
2218                                  struct ib_send_wr *wr, u32 nelements,
2219                                  u32 length, u32 pdn)
2220 {
2221         struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr;
2222         u32 sig_key = sig_mr->rkey;
2223         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
2224
2225         memset(seg, 0, sizeof(*seg));
2226
2227         seg->flags = get_umr_flags(wr->wr.sig_handover.access_flags) |
2228                                    MLX5_ACCESS_MODE_KLM;
2229         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
2230         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
2231                                     MLX5_MKEY_BSF_EN | pdn);
2232         seg->len = cpu_to_be64(length);
2233         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
2234         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
2235 }
2236
2237 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2238                                 struct ib_send_wr *wr, u32 nelements)
2239 {
2240         memset(umr, 0, sizeof(*umr));
2241
2242         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
2243         umr->klm_octowords = get_klm_octo(nelements);
2244         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
2245         umr->mkey_mask = sig_mkey_mask();
2246 }
2247
2248
2249 static int set_sig_umr_wr(struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
2250                           void **seg, int *size)
2251 {
2252         struct mlx5_ib_mr *sig_mr = to_mmr(wr->wr.sig_handover.sig_mr);
2253         u32 pdn = get_pd(qp)->pdn;
2254         u32 klm_oct_size;
2255         int region_len, ret;
2256
2257         if (unlikely(wr->num_sge != 1) ||
2258             unlikely(wr->wr.sig_handover.access_flags &
2259                      IB_ACCESS_REMOTE_ATOMIC) ||
2260             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
2261             unlikely(!sig_mr->sig->sig_status_checked))
2262                 return -EINVAL;
2263
2264         /* length of the protected region, data + protection */
2265         region_len = wr->sg_list->length;
2266         if (wr->wr.sig_handover.prot &&
2267             (wr->wr.sig_handover.prot->lkey != wr->sg_list->lkey  ||
2268              wr->wr.sig_handover.prot->addr != wr->sg_list->addr  ||
2269              wr->wr.sig_handover.prot->length != wr->sg_list->length))
2270                 region_len += wr->wr.sig_handover.prot->length;
2271
2272         /**
2273          * KLM octoword size - if protection was provided
2274          * then we use strided block format (3 octowords),
2275          * else we use single KLM (1 octoword)
2276          **/
2277         klm_oct_size = wr->wr.sig_handover.prot ? 3 : 1;
2278
2279         set_sig_umr_segment(*seg, wr, klm_oct_size);
2280         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2281         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2282         if (unlikely((*seg == qp->sq.qend)))
2283                 *seg = mlx5_get_send_wqe(qp, 0);
2284
2285         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
2286         *seg += sizeof(struct mlx5_mkey_seg);
2287         *size += sizeof(struct mlx5_mkey_seg) / 16;
2288         if (unlikely((*seg == qp->sq.qend)))
2289                 *seg = mlx5_get_send_wqe(qp, 0);
2290
2291         ret = set_sig_data_segment(wr, qp, seg, size);
2292         if (ret)
2293                 return ret;
2294
2295         sig_mr->sig->sig_status_checked = false;
2296         return 0;
2297 }
2298
2299 static int set_psv_wr(struct ib_sig_domain *domain,
2300                       u32 psv_idx, void **seg, int *size)
2301 {
2302         struct mlx5_seg_set_psv *psv_seg = *seg;
2303
2304         memset(psv_seg, 0, sizeof(*psv_seg));
2305         psv_seg->psv_num = cpu_to_be32(psv_idx);
2306         switch (domain->sig_type) {
2307         case IB_SIG_TYPE_NONE:
2308                 break;
2309         case IB_SIG_TYPE_T10_DIF:
2310                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
2311                                                      domain->sig.dif.app_tag);
2312                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
2313                 break;
2314         default:
2315                 pr_err("Bad signature type given.\n");
2316                 return 1;
2317         }
2318
2319         *seg += sizeof(*psv_seg);
2320         *size += sizeof(*psv_seg) / 16;
2321
2322         return 0;
2323 }
2324
2325 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
2326                           struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
2327 {
2328         int writ = 0;
2329         int li;
2330
2331         li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
2332         if (unlikely(wr->send_flags & IB_SEND_INLINE))
2333                 return -EINVAL;
2334
2335         set_frwr_umr_segment(*seg, wr, li);
2336         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2337         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2338         if (unlikely((*seg == qp->sq.qend)))
2339                 *seg = mlx5_get_send_wqe(qp, 0);
2340         set_mkey_segment(*seg, wr, li, &writ);
2341         *seg += sizeof(struct mlx5_mkey_seg);
2342         *size += sizeof(struct mlx5_mkey_seg) / 16;
2343         if (unlikely((*seg == qp->sq.qend)))
2344                 *seg = mlx5_get_send_wqe(qp, 0);
2345         if (!li) {
2346                 if (unlikely(wr->wr.fast_reg.page_list_len >
2347                              wr->wr.fast_reg.page_list->max_page_list_len))
2348                         return  -ENOMEM;
2349
2350                 set_frwr_pages(*seg, wr, mdev, pd, writ);
2351                 *seg += sizeof(struct mlx5_wqe_data_seg);
2352                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
2353         }
2354         return 0;
2355 }
2356
2357 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
2358 {
2359         __be32 *p = NULL;
2360         int tidx = idx;
2361         int i, j;
2362
2363         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
2364         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
2365                 if ((i & 0xf) == 0) {
2366                         void *buf = mlx5_get_send_wqe(qp, tidx);
2367                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
2368                         p = buf;
2369                         j = 0;
2370                 }
2371                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
2372                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
2373                          be32_to_cpu(p[j + 3]));
2374         }
2375 }
2376
2377 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2378                          unsigned bytecnt, struct mlx5_ib_qp *qp)
2379 {
2380         while (bytecnt > 0) {
2381                 __iowrite64_copy(dst++, src++, 8);
2382                 __iowrite64_copy(dst++, src++, 8);
2383                 __iowrite64_copy(dst++, src++, 8);
2384                 __iowrite64_copy(dst++, src++, 8);
2385                 __iowrite64_copy(dst++, src++, 8);
2386                 __iowrite64_copy(dst++, src++, 8);
2387                 __iowrite64_copy(dst++, src++, 8);
2388                 __iowrite64_copy(dst++, src++, 8);
2389                 bytecnt -= 64;
2390                 if (unlikely(src == qp->sq.qend))
2391                         src = mlx5_get_send_wqe(qp, 0);
2392         }
2393 }
2394
2395 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2396 {
2397         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2398                      wr->send_flags & IB_SEND_FENCE))
2399                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2400
2401         if (unlikely(fence)) {
2402                 if (wr->send_flags & IB_SEND_FENCE)
2403                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2404                 else
2405                         return fence;
2406
2407         } else {
2408                 return 0;
2409         }
2410 }
2411
2412 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
2413                      struct mlx5_wqe_ctrl_seg **ctrl,
2414                      struct ib_send_wr *wr, int *idx,
2415                      int *size, int nreq)
2416 {
2417         int err = 0;
2418
2419         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2420                 err = -ENOMEM;
2421                 return err;
2422         }
2423
2424         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2425         *seg = mlx5_get_send_wqe(qp, *idx);
2426         *ctrl = *seg;
2427         *(uint32_t *)(*seg + 8) = 0;
2428         (*ctrl)->imm = send_ieth(wr);
2429         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
2430                 (wr->send_flags & IB_SEND_SIGNALED ?
2431                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2432                 (wr->send_flags & IB_SEND_SOLICITED ?
2433                  MLX5_WQE_CTRL_SOLICITED : 0);
2434
2435         *seg += sizeof(**ctrl);
2436         *size = sizeof(**ctrl) / 16;
2437
2438         return err;
2439 }
2440
2441 static void finish_wqe(struct mlx5_ib_qp *qp,
2442                        struct mlx5_wqe_ctrl_seg *ctrl,
2443                        u8 size, unsigned idx, u64 wr_id,
2444                        int nreq, u8 fence, u8 next_fence,
2445                        u32 mlx5_opcode)
2446 {
2447         u8 opmod = 0;
2448
2449         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2450                                              mlx5_opcode | ((u32)opmod << 24));
2451         ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2452         ctrl->fm_ce_se |= fence;
2453         qp->fm_cache = next_fence;
2454         if (unlikely(qp->wq_sig))
2455                 ctrl->signature = wq_sig(ctrl);
2456
2457         qp->sq.wrid[idx] = wr_id;
2458         qp->sq.w_list[idx].opcode = mlx5_opcode;
2459         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2460         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2461         qp->sq.w_list[idx].next = qp->sq.cur_post;
2462 }
2463
2464
2465 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2466                       struct ib_send_wr **bad_wr)
2467 {
2468         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
2469         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2470         struct mlx5_core_dev *mdev = dev->mdev;
2471         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2472         struct mlx5_ib_mr *mr;
2473         struct mlx5_wqe_data_seg *dpseg;
2474         struct mlx5_wqe_xrc_seg *xrc;
2475         struct mlx5_bf *bf = qp->bf;
2476         int uninitialized_var(size);
2477         void *qend = qp->sq.qend;
2478         unsigned long flags;
2479         unsigned idx;
2480         int err = 0;
2481         int inl = 0;
2482         int num_sge;
2483         void *seg;
2484         int nreq;
2485         int i;
2486         u8 next_fence = 0;
2487         u8 fence;
2488
2489         spin_lock_irqsave(&qp->sq.lock, flags);
2490
2491         for (nreq = 0; wr; nreq++, wr = wr->next) {
2492                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
2493                         mlx5_ib_warn(dev, "\n");
2494                         err = -EINVAL;
2495                         *bad_wr = wr;
2496                         goto out;
2497                 }
2498
2499                 fence = qp->fm_cache;
2500                 num_sge = wr->num_sge;
2501                 if (unlikely(num_sge > qp->sq.max_gs)) {
2502                         mlx5_ib_warn(dev, "\n");
2503                         err = -ENOMEM;
2504                         *bad_wr = wr;
2505                         goto out;
2506                 }
2507
2508                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
2509                 if (err) {
2510                         mlx5_ib_warn(dev, "\n");
2511                         err = -ENOMEM;
2512                         *bad_wr = wr;
2513                         goto out;
2514                 }
2515
2516                 switch (ibqp->qp_type) {
2517                 case IB_QPT_XRC_INI:
2518                         xrc = seg;
2519                         xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2520                         seg += sizeof(*xrc);
2521                         size += sizeof(*xrc) / 16;
2522                         /* fall through */
2523                 case IB_QPT_RC:
2524                         switch (wr->opcode) {
2525                         case IB_WR_RDMA_READ:
2526                         case IB_WR_RDMA_WRITE:
2527                         case IB_WR_RDMA_WRITE_WITH_IMM:
2528                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2529                                               wr->wr.rdma.rkey);
2530                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
2531                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2532                                 break;
2533
2534                         case IB_WR_ATOMIC_CMP_AND_SWP:
2535                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2536                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2537                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2538                                 err = -ENOSYS;
2539                                 *bad_wr = wr;
2540                                 goto out;
2541
2542                         case IB_WR_LOCAL_INV:
2543                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2544                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2545                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2546                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2547                                 if (err) {
2548                                         mlx5_ib_warn(dev, "\n");
2549                                         *bad_wr = wr;
2550                                         goto out;
2551                                 }
2552                                 num_sge = 0;
2553                                 break;
2554
2555                         case IB_WR_FAST_REG_MR:
2556                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2557                                 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2558                                 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2559                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2560                                 if (err) {
2561                                         mlx5_ib_warn(dev, "\n");
2562                                         *bad_wr = wr;
2563                                         goto out;
2564                                 }
2565                                 num_sge = 0;
2566                                 break;
2567
2568                         case IB_WR_REG_SIG_MR:
2569                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
2570                                 mr = to_mmr(wr->wr.sig_handover.sig_mr);
2571
2572                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
2573                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
2574                                 if (err) {
2575                                         mlx5_ib_warn(dev, "\n");
2576                                         *bad_wr = wr;
2577                                         goto out;
2578                                 }
2579
2580                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2581                                            nreq, get_fence(fence, wr),
2582                                            next_fence, MLX5_OPCODE_UMR);
2583                                 /*
2584                                  * SET_PSV WQEs are not signaled and solicited
2585                                  * on error
2586                                  */
2587                                 wr->send_flags &= ~IB_SEND_SIGNALED;
2588                                 wr->send_flags |= IB_SEND_SOLICITED;
2589                                 err = begin_wqe(qp, &seg, &ctrl, wr,
2590                                                 &idx, &size, nreq);
2591                                 if (err) {
2592                                         mlx5_ib_warn(dev, "\n");
2593                                         err = -ENOMEM;
2594                                         *bad_wr = wr;
2595                                         goto out;
2596                                 }
2597
2598                                 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->mem,
2599                                                  mr->sig->psv_memory.psv_idx, &seg,
2600                                                  &size);
2601                                 if (err) {
2602                                         mlx5_ib_warn(dev, "\n");
2603                                         *bad_wr = wr;
2604                                         goto out;
2605                                 }
2606
2607                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2608                                            nreq, get_fence(fence, wr),
2609                                            next_fence, MLX5_OPCODE_SET_PSV);
2610                                 err = begin_wqe(qp, &seg, &ctrl, wr,
2611                                                 &idx, &size, nreq);
2612                                 if (err) {
2613                                         mlx5_ib_warn(dev, "\n");
2614                                         err = -ENOMEM;
2615                                         *bad_wr = wr;
2616                                         goto out;
2617                                 }
2618
2619                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2620                                 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->wire,
2621                                                  mr->sig->psv_wire.psv_idx, &seg,
2622                                                  &size);
2623                                 if (err) {
2624                                         mlx5_ib_warn(dev, "\n");
2625                                         *bad_wr = wr;
2626                                         goto out;
2627                                 }
2628
2629                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2630                                            nreq, get_fence(fence, wr),
2631                                            next_fence, MLX5_OPCODE_SET_PSV);
2632                                 num_sge = 0;
2633                                 goto skip_psv;
2634
2635                         default:
2636                                 break;
2637                         }
2638                         break;
2639
2640                 case IB_QPT_UC:
2641                         switch (wr->opcode) {
2642                         case IB_WR_RDMA_WRITE:
2643                         case IB_WR_RDMA_WRITE_WITH_IMM:
2644                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2645                                               wr->wr.rdma.rkey);
2646                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
2647                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2648                                 break;
2649
2650                         default:
2651                                 break;
2652                         }
2653                         break;
2654
2655                 case IB_QPT_UD:
2656                 case IB_QPT_SMI:
2657                 case IB_QPT_GSI:
2658                         set_datagram_seg(seg, wr);
2659                         seg += sizeof(struct mlx5_wqe_datagram_seg);
2660                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2661                         if (unlikely((seg == qend)))
2662                                 seg = mlx5_get_send_wqe(qp, 0);
2663                         break;
2664
2665                 case MLX5_IB_QPT_REG_UMR:
2666                         if (wr->opcode != MLX5_IB_WR_UMR) {
2667                                 err = -EINVAL;
2668                                 mlx5_ib_warn(dev, "bad opcode\n");
2669                                 goto out;
2670                         }
2671                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2672                         ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2673                         set_reg_umr_segment(seg, wr);
2674                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2675                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2676                         if (unlikely((seg == qend)))
2677                                 seg = mlx5_get_send_wqe(qp, 0);
2678                         set_reg_mkey_segment(seg, wr);
2679                         seg += sizeof(struct mlx5_mkey_seg);
2680                         size += sizeof(struct mlx5_mkey_seg) / 16;
2681                         if (unlikely((seg == qend)))
2682                                 seg = mlx5_get_send_wqe(qp, 0);
2683                         break;
2684
2685                 default:
2686                         break;
2687                 }
2688
2689                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2690                         int uninitialized_var(sz);
2691
2692                         err = set_data_inl_seg(qp, wr, seg, &sz);
2693                         if (unlikely(err)) {
2694                                 mlx5_ib_warn(dev, "\n");
2695                                 *bad_wr = wr;
2696                                 goto out;
2697                         }
2698                         inl = 1;
2699                         size += sz;
2700                 } else {
2701                         dpseg = seg;
2702                         for (i = 0; i < num_sge; i++) {
2703                                 if (unlikely(dpseg == qend)) {
2704                                         seg = mlx5_get_send_wqe(qp, 0);
2705                                         dpseg = seg;
2706                                 }
2707                                 if (likely(wr->sg_list[i].length)) {
2708                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
2709                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
2710                                         dpseg++;
2711                                 }
2712                         }
2713                 }
2714
2715                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
2716                            get_fence(fence, wr), next_fence,
2717                            mlx5_ib_opcode[wr->opcode]);
2718 skip_psv:
2719                 if (0)
2720                         dump_wqe(qp, idx, size);
2721         }
2722
2723 out:
2724         if (likely(nreq)) {
2725                 qp->sq.head += nreq;
2726
2727                 /* Make sure that descriptors are written before
2728                  * updating doorbell record and ringing the doorbell
2729                  */
2730                 wmb();
2731
2732                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2733
2734                 /* Make sure doorbell record is visible to the HCA before
2735                  * we hit doorbell */
2736                 wmb();
2737
2738                 if (bf->need_lock)
2739                         spin_lock(&bf->lock);
2740
2741                 /* TBD enable WC */
2742                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2743                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2744                         /* wc_wmb(); */
2745                 } else {
2746                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2747                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2748                         /* Make sure doorbells don't leak out of SQ spinlock
2749                          * and reach the HCA out of order.
2750                          */
2751                         mmiowb();
2752                 }
2753                 bf->offset ^= bf->buf_size;
2754                 if (bf->need_lock)
2755                         spin_unlock(&bf->lock);
2756         }
2757
2758         spin_unlock_irqrestore(&qp->sq.lock, flags);
2759
2760         return err;
2761 }
2762
2763 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2764 {
2765         sig->signature = calc_sig(sig, size);
2766 }
2767
2768 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2769                       struct ib_recv_wr **bad_wr)
2770 {
2771         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2772         struct mlx5_wqe_data_seg *scat;
2773         struct mlx5_rwqe_sig *sig;
2774         unsigned long flags;
2775         int err = 0;
2776         int nreq;
2777         int ind;
2778         int i;
2779
2780         spin_lock_irqsave(&qp->rq.lock, flags);
2781
2782         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2783
2784         for (nreq = 0; wr; nreq++, wr = wr->next) {
2785                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2786                         err = -ENOMEM;
2787                         *bad_wr = wr;
2788                         goto out;
2789                 }
2790
2791                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2792                         err = -EINVAL;
2793                         *bad_wr = wr;
2794                         goto out;
2795                 }
2796
2797                 scat = get_recv_wqe(qp, ind);
2798                 if (qp->wq_sig)
2799                         scat++;
2800
2801                 for (i = 0; i < wr->num_sge; i++)
2802                         set_data_ptr_seg(scat + i, wr->sg_list + i);
2803
2804                 if (i < qp->rq.max_gs) {
2805                         scat[i].byte_count = 0;
2806                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
2807                         scat[i].addr       = 0;
2808                 }
2809
2810                 if (qp->wq_sig) {
2811                         sig = (struct mlx5_rwqe_sig *)scat;
2812                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2813                 }
2814
2815                 qp->rq.wrid[ind] = wr->wr_id;
2816
2817                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2818         }
2819
2820 out:
2821         if (likely(nreq)) {
2822                 qp->rq.head += nreq;
2823
2824                 /* Make sure that descriptors are written before
2825                  * doorbell record.
2826                  */
2827                 wmb();
2828
2829                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2830         }
2831
2832         spin_unlock_irqrestore(&qp->rq.lock, flags);
2833
2834         return err;
2835 }
2836
2837 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2838 {
2839         switch (mlx5_state) {
2840         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
2841         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
2842         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
2843         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
2844         case MLX5_QP_STATE_SQ_DRAINING:
2845         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
2846         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
2847         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
2848         default:                     return -1;
2849         }
2850 }
2851
2852 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2853 {
2854         switch (mlx5_mig_state) {
2855         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
2856         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
2857         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2858         default: return -1;
2859         }
2860 }
2861
2862 static int to_ib_qp_access_flags(int mlx5_flags)
2863 {
2864         int ib_flags = 0;
2865
2866         if (mlx5_flags & MLX5_QP_BIT_RRE)
2867                 ib_flags |= IB_ACCESS_REMOTE_READ;
2868         if (mlx5_flags & MLX5_QP_BIT_RWE)
2869                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2870         if (mlx5_flags & MLX5_QP_BIT_RAE)
2871                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2872
2873         return ib_flags;
2874 }
2875
2876 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2877                                 struct mlx5_qp_path *path)
2878 {
2879         struct mlx5_core_dev *dev = ibdev->mdev;
2880
2881         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
2882         ib_ah_attr->port_num      = path->port;
2883
2884         if (ib_ah_attr->port_num == 0 ||
2885             ib_ah_attr->port_num > dev->caps.gen.num_ports)
2886                 return;
2887
2888         ib_ah_attr->sl = path->sl & 0xf;
2889
2890         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2891         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
2892         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2893         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
2894         if (ib_ah_attr->ah_flags) {
2895                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2896                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2897                 ib_ah_attr->grh.traffic_class =
2898                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2899                 ib_ah_attr->grh.flow_label =
2900                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2901                 memcpy(ib_ah_attr->grh.dgid.raw,
2902                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
2903         }
2904 }
2905
2906 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2907                      struct ib_qp_init_attr *qp_init_attr)
2908 {
2909         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2910         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2911         struct mlx5_query_qp_mbox_out *outb;
2912         struct mlx5_qp_context *context;
2913         int mlx5_state;
2914         int err = 0;
2915
2916         mutex_lock(&qp->mutex);
2917         outb = kzalloc(sizeof(*outb), GFP_KERNEL);
2918         if (!outb) {
2919                 err = -ENOMEM;
2920                 goto out;
2921         }
2922         context = &outb->ctx;
2923         err = mlx5_core_qp_query(dev->mdev, &qp->mqp, outb, sizeof(*outb));
2924         if (err)
2925                 goto out_free;
2926
2927         mlx5_state = be32_to_cpu(context->flags) >> 28;
2928
2929         qp->state                    = to_ib_qp_state(mlx5_state);
2930         qp_attr->qp_state            = qp->state;
2931         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
2932         qp_attr->path_mig_state      =
2933                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
2934         qp_attr->qkey                = be32_to_cpu(context->qkey);
2935         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
2936         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
2937         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
2938         qp_attr->qp_access_flags     =
2939                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
2940
2941         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2942                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
2943                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
2944                 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
2945                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2946         }
2947
2948         qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
2949         qp_attr->port_num = context->pri_path.port;
2950
2951         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2952         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
2953
2954         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
2955
2956         qp_attr->max_dest_rd_atomic =
2957                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
2958         qp_attr->min_rnr_timer      =
2959                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
2960         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
2961         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
2962         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
2963         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
2964         qp_attr->cur_qp_state        = qp_attr->qp_state;
2965         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2966         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2967
2968         if (!ibqp->uobject) {
2969                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2970                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2971         } else {
2972                 qp_attr->cap.max_send_wr  = 0;
2973                 qp_attr->cap.max_send_sge = 0;
2974         }
2975
2976         /* We don't support inline sends for kernel QPs (yet), and we
2977          * don't know what userspace's value should be.
2978          */
2979         qp_attr->cap.max_inline_data = 0;
2980
2981         qp_init_attr->cap            = qp_attr->cap;
2982
2983         qp_init_attr->create_flags = 0;
2984         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2985                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2986
2987         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
2988                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2989
2990 out_free:
2991         kfree(outb);
2992
2993 out:
2994         mutex_unlock(&qp->mutex);
2995         return err;
2996 }
2997
2998 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
2999                                           struct ib_ucontext *context,
3000                                           struct ib_udata *udata)
3001 {
3002         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3003         struct mlx5_general_caps *gen;
3004         struct mlx5_ib_xrcd *xrcd;
3005         int err;
3006
3007         gen = &dev->mdev->caps.gen;
3008         if (!(gen->flags & MLX5_DEV_CAP_FLAG_XRC))
3009                 return ERR_PTR(-ENOSYS);
3010
3011         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
3012         if (!xrcd)
3013                 return ERR_PTR(-ENOMEM);
3014
3015         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
3016         if (err) {
3017                 kfree(xrcd);
3018                 return ERR_PTR(-ENOMEM);
3019         }
3020
3021         return &xrcd->ibxrcd;
3022 }
3023
3024 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
3025 {
3026         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
3027         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
3028         int err;
3029
3030         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
3031         if (err) {
3032                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
3033                 return err;
3034         }
3035
3036         kfree(xrcd);
3037
3038         return 0;
3039 }