2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_smi.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/fs.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/types.h>
46 #include <linux/mlx5/transobj.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/mlx5-abi.h>
49 #include <rdma/uverbs_ioctl.h>
50 #include <rdma/mlx5_user_ioctl_cmds.h>
51 #include <rdma/mlx5_user_ioctl_verbs.h>
55 #define mlx5_ib_dbg(_dev, format, arg...) \
56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
57 __LINE__, current->pid, ##arg)
59 #define mlx5_ib_err(_dev, format, arg...) \
60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
61 __LINE__, current->pid, ##arg)
63 #define mlx5_ib_warn(_dev, format, arg...) \
64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
65 __LINE__, current->pid, ##arg)
67 #define MLX5_IB_DEFAULT_UIDX 0xffffff
68 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
70 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
73 MLX5_IB_MMAP_OFFSET_START = 9,
74 MLX5_IB_MMAP_OFFSET_END = 255,
78 MLX5_IB_MMAP_CMD_SHIFT = 8,
79 MLX5_IB_MMAP_CMD_MASK = 0xff,
83 MLX5_RES_SCAT_DATA32_CQE = 0x1,
84 MLX5_RES_SCAT_DATA64_CQE = 0x2,
85 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
86 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
89 enum mlx5_ib_mad_ifc_flags {
90 MLX5_MAD_IFC_IGNORE_MKEY = 1,
91 MLX5_MAD_IFC_IGNORE_BKEY = 2,
92 MLX5_MAD_IFC_NET_VIEW = 4,
96 MLX5_CROSS_CHANNEL_BFREG = 0,
105 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
110 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
111 MLX5_IB_INVALID_BFREG = BIT(31),
115 MLX5_MAX_MEMIC_PAGES = 0x100,
116 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
120 MLX5_MEMIC_BASE_ALIGN = 6,
121 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
124 enum mlx5_ib_mmap_type {
125 MLX5_IB_MMAP_TYPE_MEMIC = 1,
126 MLX5_IB_MMAP_TYPE_VAR = 2,
127 MLX5_IB_MMAP_TYPE_UAR_WC = 3,
128 MLX5_IB_MMAP_TYPE_UAR_NC = 4,
131 struct mlx5_bfreg_info {
133 int num_low_latency_bfregs;
137 * protect bfreg allocation data structs
144 u32 num_static_sys_pages;
145 u32 total_num_bfregs;
149 struct mlx5_ib_ucontext {
150 struct ib_ucontext ibucontext;
151 struct list_head db_page_list;
153 /* protect doorbell record alloc/free
155 struct mutex db_page_mutex;
156 struct mlx5_bfreg_info bfregi;
158 /* Transport Domain number */
163 /* For RoCE LAG TX affinity */
164 atomic_t tx_port_affinity;
167 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
169 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
179 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
180 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
181 MLX5_IB_FLOW_ACTION_DECAP,
184 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
185 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
186 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
187 #error "Invalid number of bypass priorities"
189 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
191 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
192 #define MLX5_IB_NUM_SNIFFER_FTS 2
193 #define MLX5_IB_NUM_EGRESS_FTS 1
194 struct mlx5_ib_flow_prio {
195 struct mlx5_flow_table *flow_table;
196 unsigned int refcount;
199 struct mlx5_ib_flow_handler {
200 struct list_head list;
201 struct ib_flow ibflow;
202 struct mlx5_ib_flow_prio *prio;
203 struct mlx5_flow_handle *rule;
204 struct ib_counters *ibcounters;
205 struct mlx5_ib_dev *dev;
206 struct mlx5_ib_flow_matcher *flow_matcher;
209 struct mlx5_ib_flow_matcher {
210 struct mlx5_ib_match_params matcher_mask;
212 enum mlx5_ib_flow_type flow_type;
213 enum mlx5_flow_namespace_type ns_type;
215 struct mlx5_core_dev *mdev;
217 u8 match_criteria_enable;
222 struct mlx5_core_dev *mdev;
225 struct mlx5_ib_flow_db {
226 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
227 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
228 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
229 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
230 struct mlx5_ib_flow_prio fdb;
231 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
232 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT];
233 struct mlx5_flow_table *lag_demux_ft;
234 /* Protect flow steering bypass flow tables
235 * when add/del flow rules.
236 * only single add/removal of flow steering rule could be done
242 /* Use macros here so that don't have to duplicate
243 * enum ib_send_flags and enum ib_qp_type for low-level driver
246 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
247 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
248 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
249 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
250 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
251 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
253 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
255 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
256 * creates the actual hardware QP.
258 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
259 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
260 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
261 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
263 #define MLX5_IB_UMR_OCTOWORD 16
264 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
266 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
267 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
268 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
269 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
270 #define MLX5_IB_UPD_XLT_PD BIT(4)
271 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
272 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
274 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
276 * These flags are intended for internal use by the mlx5_ib driver, and they
277 * rely on the range reserved for that use in the ib_qp_create_flags enum.
279 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START
280 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1)
287 enum mlx5_ib_rq_flags {
288 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
289 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
293 struct mlx5_frag_buf_ctrl fbc;
296 struct wr_list *w_list;
300 /* serialize post to the work queue
315 enum mlx5_ib_wq_flags {
316 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
317 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
320 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
321 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
322 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
323 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
324 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
328 struct mlx5_core_qp core_qp;
335 u32 two_byte_shift_en;
336 u32 single_stride_log_num_of_bytes;
337 struct ib_umem *umem;
339 unsigned int page_shift;
345 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
348 struct mlx5_ib_rwq_ind_table {
349 struct ib_rwq_ind_table ib_rwq_ind_tbl;
354 struct mlx5_ib_ubuffer {
355 struct ib_umem *umem;
360 struct mlx5_ib_qp_base {
361 struct mlx5_ib_qp *container_mibqp;
362 struct mlx5_core_qp mqp;
363 struct mlx5_ib_ubuffer ubuffer;
366 struct mlx5_ib_qp_trans {
367 struct mlx5_ib_qp_base base;
374 struct mlx5_ib_rss_qp {
379 struct mlx5_ib_qp_base base;
380 struct mlx5_ib_wq *rq;
381 struct mlx5_ib_ubuffer ubuffer;
382 struct mlx5_db *doorbell;
389 struct mlx5_ib_qp_base base;
390 struct mlx5_ib_wq *sq;
391 struct mlx5_ib_ubuffer ubuffer;
392 struct mlx5_db *doorbell;
393 struct mlx5_flow_handle *flow_rule;
398 struct mlx5_ib_raw_packet_qp {
399 struct mlx5_ib_sq sq;
400 struct mlx5_ib_rq rq;
405 unsigned long offset;
406 struct mlx5_sq_bfreg *bfreg;
410 struct mlx5_core_dct mdct;
417 struct mlx5_ib_qp_trans trans_qp;
418 struct mlx5_ib_raw_packet_qp raw_packet_qp;
419 struct mlx5_ib_rss_qp rss_qp;
420 struct mlx5_ib_dct dct;
422 struct mlx5_frag_buf buf;
425 struct mlx5_ib_wq rq;
429 struct mlx5_ib_wq sq;
431 /* serialize qp state modifications
434 /* cached variant of create_flags from struct ib_qp_init_attr */
443 /* only for user space QPs. For kernel
444 * we have it from the bf object
448 struct list_head qps_list;
449 struct list_head cq_recv_list;
450 struct list_head cq_send_list;
451 struct mlx5_rate_limit rl;
455 * IB/core doesn't store low-level QP types, so
456 * store both MLX and IBTA types in the field below.
457 * IB_QPT_DRIVER will be break to DCI/DCT subtypes.
459 enum ib_qp_type type;
460 /* A flag to indicate if there's a new counter is configured
461 * but not take effective
467 struct mlx5_ib_cq_buf {
468 struct mlx5_frag_buf_ctrl fbc;
469 struct mlx5_frag_buf frag_buf;
470 struct ib_umem *umem;
476 struct ib_send_wr wr;
480 unsigned int page_shift;
481 unsigned int xlt_size;
485 u8 ignore_free_state:1;
488 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
490 return container_of(wr, struct mlx5_umr_wr, wr);
493 struct mlx5_shared_mr_info {
495 struct ib_umem *umem;
498 enum mlx5_ib_cq_pr_flags {
499 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
504 struct mlx5_core_cq mcq;
505 struct mlx5_ib_cq_buf buf;
508 /* serialize access to the CQ
514 struct mutex resize_mutex;
515 struct mlx5_ib_cq_buf *resize_buf;
516 struct ib_umem *resize_umem;
518 struct list_head list_send_qp;
519 struct list_head list_recv_qp;
521 struct list_head wc_list;
522 enum ib_cq_notify_flags notify_flags;
523 struct work_struct notify_work;
524 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
529 struct list_head list;
534 struct mlx5_core_srq msrq;
535 struct mlx5_frag_buf buf;
537 struct mlx5_frag_buf_ctrl fbc;
539 /* protect SRQ hanlding
545 struct ib_umem *umem;
546 /* serialize arming a SRQ
552 struct mlx5_ib_xrcd {
553 struct ib_xrcd ibxrcd;
557 enum mlx5_ib_mtt_access_flags {
558 MLX5_IB_MTT_READ = (1 << 0),
559 MLX5_IB_MTT_WRITE = (1 << 1),
562 struct mlx5_user_mmap_entry {
563 struct rdma_user_mmap_entry rdma_entry;
571 phys_addr_t dev_addr;
578 /* other dm types specific params should be added here */
580 struct mlx5_user_mmap_entry mentry;
583 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
585 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
586 IB_ACCESS_REMOTE_WRITE |\
587 IB_ACCESS_REMOTE_READ |\
588 IB_ACCESS_REMOTE_ATOMIC |\
591 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
592 IB_ACCESS_REMOTE_WRITE |\
593 IB_ACCESS_REMOTE_READ |\
596 #define mlx5_update_odp_stats(mr, counter_name, value) \
597 atomic64_add(value, &((mr)->odp_stats.counter_name))
610 struct mlx5_core_mkey mmkey;
611 struct ib_umem *umem;
612 struct mlx5_shared_mr_info *smr_info;
613 struct list_head list;
615 struct mlx5_cache_ent *cache_ent;
617 struct mlx5_ib_dev *dev;
618 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
619 struct mlx5_core_sig_ctx *sig;
621 int access_flags; /* Needed for rereg MR */
623 struct mlx5_ib_mr *parent;
624 /* Needed for IB_MR_TYPE_INTEGRITY */
625 struct mlx5_ib_mr *pi_mr;
626 struct mlx5_ib_mr *klm_mr;
627 struct mlx5_ib_mr *mtt_mr;
631 /* For ODP and implicit */
632 atomic_t num_deferred_work;
633 wait_queue_head_t q_deferred_work;
634 struct xarray implicit_children;
637 struct list_head elm;
638 struct work_struct work;
640 struct ib_odp_counters odp_stats;
641 bool is_odp_implicit;
643 struct mlx5_async_work cb_work;
646 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
648 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
654 struct mlx5_core_mkey mmkey;
658 struct mlx5_ib_devx_mr {
659 struct mlx5_core_mkey mmkey;
663 struct mlx5_ib_umr_context {
665 enum ib_wc_status status;
666 struct completion done;
673 /* control access to UMR QP
675 struct semaphore sem;
678 struct mlx5_cache_ent {
679 struct list_head head;
680 /* sync access to the cahce entry
692 u8 fill_to_high_water:1;
695 * - available_mrs is the length of list head, ie the number of MRs
696 * available for immediate allocation.
697 * - total_mrs is available_mrs plus all in use MRs that could be
698 * returned to the cache.
699 * - limit is the low water mark for available_mrs, 2* limit is the
701 * - pending is the number of MRs currently being created
711 struct mlx5_ib_dev *dev;
712 struct work_struct work;
713 struct delayed_work dwork;
716 struct mlx5_mr_cache {
717 struct workqueue_struct *wq;
718 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
720 unsigned long last_add;
723 struct mlx5_ib_gsi_qp;
725 struct mlx5_ib_port_resources {
726 struct mlx5_ib_resources *devr;
727 struct mlx5_ib_gsi_qp *gsi;
728 struct work_struct pkey_change_work;
731 struct mlx5_ib_resources {
738 struct mlx5_ib_port_resources ports[2];
739 /* Protects changes to the port resources */
743 struct mlx5_ib_counters {
747 u32 num_cong_counters;
748 u32 num_ext_ppcnt_counters;
752 struct mlx5_ib_multiport_info;
754 struct mlx5_ib_multiport {
755 struct mlx5_ib_multiport_info *mpi;
756 /* To be held when accessing the multiport info */
761 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
764 rwlock_t netdev_lock;
765 struct net_device *netdev;
766 struct notifier_block nb;
767 atomic_t tx_port_affinity;
768 enum ib_port_state last_port_state;
769 struct mlx5_ib_dev *dev;
773 struct mlx5_ib_port {
774 struct mlx5_ib_counters cnts;
775 struct mlx5_ib_multiport mp;
776 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
777 struct mlx5_roce roce;
778 struct mlx5_eswitch_rep *rep;
781 struct mlx5_ib_dbg_param {
783 struct mlx5_ib_dev *dev;
784 struct dentry *dentry;
788 enum mlx5_ib_dbg_cc_types {
789 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
790 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
791 MLX5_IB_DBG_CC_RP_TIME_RESET,
792 MLX5_IB_DBG_CC_RP_BYTE_RESET,
793 MLX5_IB_DBG_CC_RP_THRESHOLD,
794 MLX5_IB_DBG_CC_RP_AI_RATE,
795 MLX5_IB_DBG_CC_RP_MAX_RATE,
796 MLX5_IB_DBG_CC_RP_HAI_RATE,
797 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
798 MLX5_IB_DBG_CC_RP_MIN_RATE,
799 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
800 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
801 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
802 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
803 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
804 MLX5_IB_DBG_CC_RP_GD,
805 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
806 MLX5_IB_DBG_CC_NP_CNP_DSCP,
807 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
808 MLX5_IB_DBG_CC_NP_CNP_PRIO,
812 struct mlx5_ib_dbg_cc_params {
814 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
818 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
821 struct mlx5_ib_delay_drop {
822 struct mlx5_ib_dev *dev;
823 struct work_struct delay_drop_work;
824 /* serialize setting of delay drop */
830 struct dentry *dir_debugfs;
833 enum mlx5_ib_stages {
835 MLX5_IB_STAGE_FLOW_DB,
837 MLX5_IB_STAGE_NON_DEFAULT_CB,
841 MLX5_IB_STAGE_DEVICE_RESOURCES,
842 MLX5_IB_STAGE_DEVICE_NOTIFIER,
844 MLX5_IB_STAGE_COUNTERS,
845 MLX5_IB_STAGE_CONG_DEBUGFS,
848 MLX5_IB_STAGE_PRE_IB_REG_UMR,
849 MLX5_IB_STAGE_WHITELIST_UID,
850 MLX5_IB_STAGE_IB_REG,
851 MLX5_IB_STAGE_POST_IB_REG_UMR,
852 MLX5_IB_STAGE_DELAY_DROP,
853 MLX5_IB_STAGE_CLASS_ATTR,
857 struct mlx5_ib_stage {
858 int (*init)(struct mlx5_ib_dev *dev);
859 void (*cleanup)(struct mlx5_ib_dev *dev);
862 #define STAGE_CREATE(_stage, _init, _cleanup) \
863 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
865 struct mlx5_ib_profile {
866 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
869 struct mlx5_ib_multiport_info {
870 struct list_head list;
871 struct mlx5_ib_dev *ibdev;
872 struct mlx5_core_dev *mdev;
873 struct notifier_block mdev_events;
874 struct completion unref_comp;
881 struct mlx5_ib_flow_action {
882 struct ib_flow_action ib_action;
886 struct mlx5_accel_esp_xfrm *ctx;
889 struct mlx5_ib_dev *dev;
892 struct mlx5_modify_hdr *modify_hdr;
893 struct mlx5_pkt_reformat *pkt_reformat;
900 struct mlx5_core_dev *dev;
901 /* This lock is used to protect the access to the shared
902 * allocation map when concurrent requests by different
903 * processes are handled.
906 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
909 struct mlx5_read_counters_attr {
910 struct mlx5_fc *hw_cntrs_hndl;
915 enum mlx5_ib_counters_type {
916 MLX5_IB_COUNTERS_FLOW,
919 struct mlx5_ib_mcounters {
920 struct ib_counters ibcntrs;
921 enum mlx5_ib_counters_type type;
922 /* number of counters supported for this counters type */
924 struct mlx5_fc *hw_cntrs_hndl;
925 /* read function for this counters type */
926 int (*read_counters)(struct ib_device *ibdev,
927 struct mlx5_read_counters_attr *read_attr);
928 /* max index set as part of create_flow */
930 /* number of counters data entries (<description,index> pair) */
932 /* counters data array for descriptions and indexes */
933 struct mlx5_ib_flow_counters_desc *counters_data;
934 /* protects access to mcounters internal data */
935 struct mutex mcntrs_mutex;
938 static inline struct mlx5_ib_mcounters *
939 to_mcounters(struct ib_counters *ibcntrs)
941 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
944 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
946 struct mlx5_flow_act *action);
947 struct mlx5_ib_lb_state {
948 /* protect the user_td */
955 struct mlx5_ib_pf_eq {
956 struct notifier_block irq_nb;
957 struct mlx5_ib_dev *dev;
958 struct mlx5_eq *core;
959 struct work_struct work;
960 spinlock_t lock; /* Pagefaults spinlock */
961 struct workqueue_struct *wq;
965 struct mlx5_devx_event_table {
966 struct mlx5_nb devx_nb;
967 /* serialize updating the event_xa */
968 struct mutex event_xa_lock;
969 struct xarray event_xa;
972 struct mlx5_var_table {
973 /* serialize updating the bitmap */
974 struct mutex bitmap_lock;
975 unsigned long *bitmap;
978 u64 num_var_hw_entries;
982 struct ib_device ib_dev;
983 struct mlx5_core_dev *mdev;
984 struct notifier_block mdev_events;
986 /* serialize update of capability mask
988 struct mutex cap_mask_mutex;
994 struct umr_common umrc;
995 /* sync used page count stats
997 struct mlx5_ib_resources devr;
1000 struct mlx5_mr_cache cache;
1001 struct timer_list delay_timer;
1002 /* Prevents soft lock on massive reg MRs */
1003 struct mutex slow_path_mutex;
1004 struct ib_odp_caps odp_caps;
1006 struct mlx5_ib_pf_eq odp_pf_eq;
1009 * Sleepable RCU that prevents destruction of MRs while they are still
1010 * being used by a page fault handler.
1012 struct srcu_struct odp_srcu;
1013 struct xarray odp_mkeys;
1016 struct mlx5_ib_flow_db *flow_db;
1017 /* protect resources needed as part of reset flow */
1018 spinlock_t reset_flow_resource_lock;
1019 struct list_head qp_list;
1020 /* Array with num_ports elements */
1021 struct mlx5_ib_port *port;
1022 struct mlx5_sq_bfreg bfreg;
1023 struct mlx5_sq_bfreg wc_bfreg;
1024 struct mlx5_sq_bfreg fp_bfreg;
1025 struct mlx5_ib_delay_drop delay_drop;
1026 const struct mlx5_ib_profile *profile;
1028 struct mlx5_ib_lb_state lb;
1030 struct list_head ib_dev_list;
1033 u16 devx_whitelist_uid;
1034 struct mlx5_srq_table srq_table;
1035 struct mlx5_qp_table qp_table;
1036 struct mlx5_async_ctx async_ctx;
1037 struct mlx5_devx_event_table devx_event_table;
1038 struct mlx5_var_table var_table;
1040 struct xarray sig_mrs;
1043 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1045 return container_of(mcq, struct mlx5_ib_cq, mcq);
1048 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1050 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1053 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1055 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1058 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1060 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1061 udata, struct mlx5_ib_ucontext, ibucontext);
1063 return to_mdev(context->ibucontext.device);
1066 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1068 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1071 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1073 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1076 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1078 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1081 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
1083 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
1086 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1088 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1091 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1093 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1096 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1098 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1101 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1103 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1106 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1108 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1111 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1113 return container_of(msrq, struct mlx5_ib_srq, msrq);
1116 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
1118 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
1121 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1123 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1126 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1128 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1131 static inline struct mlx5_ib_flow_action *
1132 to_mflow_act(struct ib_flow_action *ibact)
1134 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1137 static inline struct mlx5_user_mmap_entry *
1138 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1140 return container_of(rdma_entry,
1141 struct mlx5_user_mmap_entry, rdma_entry);
1144 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context,
1145 struct ib_udata *udata, unsigned long virt,
1146 struct mlx5_db *db);
1147 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1148 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1149 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1150 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1151 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1152 struct ib_udata *udata);
1153 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1154 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags);
1155 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1156 struct ib_udata *udata);
1157 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1158 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1159 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1160 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1161 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1162 const struct ib_recv_wr **bad_wr);
1163 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1164 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1165 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1166 struct ib_qp_init_attr *init_attr,
1167 struct ib_udata *udata);
1168 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1169 int attr_mask, struct ib_udata *udata);
1170 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1171 struct ib_qp_init_attr *qp_init_attr);
1172 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1173 void mlx5_ib_drain_sq(struct ib_qp *qp);
1174 void mlx5_ib_drain_rq(struct ib_qp *qp);
1175 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1176 size_t buflen, size_t *bc);
1177 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1178 size_t buflen, size_t *bc);
1179 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1180 size_t buflen, size_t *bc);
1181 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1182 struct ib_udata *udata);
1183 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1184 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1185 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1186 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1187 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1188 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1189 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1190 u64 virt_addr, int access_flags,
1191 struct ib_udata *udata);
1192 int mlx5_ib_advise_mr(struct ib_pd *pd,
1193 enum ib_uverbs_advise_mr_advice advice,
1195 struct ib_sge *sg_list,
1197 struct uverbs_attr_bundle *attrs);
1198 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1199 struct ib_udata *udata);
1200 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1201 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1202 int page_shift, int flags);
1203 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1204 struct ib_udata *udata,
1206 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1207 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr);
1208 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1209 u64 length, u64 virt_addr, int access_flags,
1210 struct ib_pd *pd, struct ib_udata *udata);
1211 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1212 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1213 u32 max_num_sg, struct ib_udata *udata);
1214 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1216 u32 max_num_meta_sg);
1217 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1218 unsigned int *sg_offset);
1219 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1220 int data_sg_nents, unsigned int *data_sg_offset,
1221 struct scatterlist *meta_sg, int meta_sg_nents,
1222 unsigned int *meta_sg_offset);
1223 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1224 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1225 const struct ib_mad *in, struct ib_mad *out,
1226 size_t *out_mad_size, u16 *out_mad_pkey_index);
1227 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1228 struct ib_udata *udata);
1229 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1230 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1231 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1232 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1233 struct ib_smp *out_mad);
1234 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1235 __be64 *sys_image_guid);
1236 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1238 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1240 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1241 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1242 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1244 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1246 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1247 struct ib_port_attr *props);
1248 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1249 struct ib_port_attr *props);
1250 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1251 unsigned long max_page_shift,
1252 int *count, int *shift,
1253 int *ncont, int *order);
1254 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1255 int page_shift, size_t offset, size_t num_pages,
1256 __be64 *pas, int access_flags);
1257 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1258 int page_shift, __be64 *pas, int access_flags);
1259 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1260 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1261 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1262 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1264 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1265 unsigned int entry);
1266 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1267 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr);
1269 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1270 struct ib_mr_status *mr_status);
1271 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1272 struct ib_wq_init_attr *init_attr,
1273 struct ib_udata *udata);
1274 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1275 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1276 u32 wq_attr_mask, struct ib_udata *udata);
1277 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1278 struct ib_rwq_ind_table_init_attr *init_attr,
1279 struct ib_udata *udata);
1280 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1281 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1282 struct ib_ucontext *context,
1283 struct ib_dm_alloc_attr *attr,
1284 struct uverbs_attr_bundle *attrs);
1285 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs);
1286 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1287 struct ib_dm_mr_attr *attr,
1288 struct uverbs_attr_bundle *attrs);
1290 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1291 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1292 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1293 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1294 int __init mlx5_ib_odp_init(void);
1295 void mlx5_ib_odp_cleanup(void);
1296 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1297 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1298 struct mlx5_ib_mr *mr, int flags);
1300 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1301 enum ib_uverbs_advise_mr_advice advice,
1302 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1303 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1304 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1309 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1310 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
1311 static inline int mlx5_ib_odp_init(void) { return 0; }
1312 static inline void mlx5_ib_odp_cleanup(void) {}
1313 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1314 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1315 struct mlx5_ib_mr *mr, int flags) {}
1318 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1319 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1320 struct ib_sge *sg_list, u32 num_sge)
1324 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1326 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1328 /* Needed for rep profile */
1329 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1330 const struct mlx5_ib_profile *profile,
1332 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1333 const struct mlx5_ib_profile *profile);
1335 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1336 u8 port, struct ifla_vf_info *info);
1337 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1338 u8 port, int state);
1339 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1340 u8 port, struct ifla_vf_stats *stats);
1341 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port,
1342 struct ifla_vf_guid *node_guid,
1343 struct ifla_vf_guid *port_guid);
1344 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1345 u64 guid, int type);
1347 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
1348 const struct ib_gid_attr *attr);
1350 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1351 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1353 /* GSI QP helper functions */
1354 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1355 struct ib_qp_init_attr *init_attr);
1356 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1357 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1359 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1361 struct ib_qp_init_attr *qp_init_attr);
1362 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1363 const struct ib_send_wr **bad_wr);
1364 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1365 const struct ib_recv_wr **bad_wr);
1366 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1368 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1370 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1372 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1373 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1375 u8 *native_port_num);
1376 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1378 int mlx5_ib_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr);
1379 int mlx5_ib_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ibqp);
1380 int mlx5_ib_fill_stat_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr);
1382 extern const struct uapi_definition mlx5_ib_devx_defs[];
1383 extern const struct uapi_definition mlx5_ib_flow_defs[];
1384 extern const struct uapi_definition mlx5_ib_qos_defs[];
1386 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1387 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user);
1388 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid);
1389 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev);
1390 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev);
1391 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1392 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1393 struct mlx5_flow_context *flow_context,
1394 struct mlx5_flow_act *flow_act, u32 counter_id,
1395 void *cmd_in, int inlen, int dest_id, int dest_type);
1396 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1397 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 offset, u32 *counter_id);
1398 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction);
1401 mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1402 bool is_user) { return -EOPNOTSUPP; }
1403 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {}
1404 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {}
1405 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {}
1406 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1412 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction)
1417 static inline void init_query_mad(struct ib_smp *mad)
1419 mad->base_version = 1;
1420 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1421 mad->class_version = 1;
1422 mad->method = IB_MGMT_METHOD_GET;
1425 static inline u8 convert_access(int acc)
1427 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1428 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1429 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1430 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1431 MLX5_PERM_LOCAL_READ;
1434 static inline int is_qp1(enum ib_qp_type qp_type)
1436 return qp_type == MLX5_IB_QPT_HW_GSI;
1439 #define MLX5_MAX_UMR_SHIFT 16
1440 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1442 static inline u32 check_cq_create_flags(u32 flags)
1445 * It returns non-zero value for unsupported CQ
1446 * create flags, otherwise it returns zero.
1448 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1449 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1452 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1456 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1457 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1459 *user_index = cmd_uidx;
1461 *user_index = MLX5_IB_DEFAULT_UIDX;
1467 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1468 struct mlx5_ib_create_qp *ucmd,
1472 u8 cqe_version = ucontext->cqe_version;
1474 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1475 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1478 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1481 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1484 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1485 struct mlx5_ib_create_srq *ucmd,
1489 u8 cqe_version = ucontext->cqe_version;
1491 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1492 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1495 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1498 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1501 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1503 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1504 MLX5_UARS_IN_PAGE : 1;
1507 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1508 struct mlx5_bfreg_info *bfregi)
1510 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1513 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1514 void mlx5_ib_put_xlt_emergency_page(void);
1516 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1517 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1520 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter);
1521 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num);
1523 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev,
1524 bool do_modify_atomic, int access_flags)
1526 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1529 if (do_modify_atomic &&
1530 MLX5_CAP_GEN(dev->mdev, atomic) &&
1531 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
1534 if (access_flags & IB_ACCESS_RELAXED_ORDERING &&
1535 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) ||
1536 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)))
1542 int mlx5_ib_enable_driver(struct ib_device *dev);
1543 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1545 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev)
1547 return dev->lag_active ||
1548 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 &&
1549 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity));
1551 #endif /* MLX5_IB_H */