drivers/infiniband/hw/hns/hns_roce_main.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 #include <linux/acpi.h>
  34 #include <linux/of_platform.h>
  35 #include <linux/module.h>
  36 #include <linux/pci.h>
  37 #include <rdma/ib_addr.h>
  38 #include <rdma/ib_smi.h>
  39 #include <rdma/ib_user_verbs.h>
  40 #include <rdma/ib_cache.h>
  41 #include "hns_roce_common.h"
  42 #include "hns_roce_device.h"
  43 #include "hns_roce_hem.h"
  44
  45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port, u8 *addr)
  46 {
  47         u8 phy_port;
  48         u32 i;
  49
  50         if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
  51                 return 0;
  52
  53         if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
  54                 return 0;
  55
  56         for (i = 0; i < ETH_ALEN; i++)
  57                 hr_dev->dev_addr[port][i] = addr[i];
  58
  59         phy_port = hr_dev->iboe.phy_port[port];
  60         return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  61 }
  62
  63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
  64 {
  65         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  66         u32 port = attr->port_num - 1;
  67         int ret;
  68
  69         if (port >= hr_dev->caps.num_ports)
  70                 return -EINVAL;
  71
  72         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
  73
  74         return ret;
  75 }
  76
  77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  78 {
  79         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  80         u32 port = attr->port_num - 1;
  81         int ret;
  82
  83         if (port >= hr_dev->caps.num_ports)
  84                 return -EINVAL;
  85
  86         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, NULL, NULL);
  87
  88         return ret;
  89 }
  90
  91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
  92                            unsigned long event)
  93 {
  94         struct device *dev = hr_dev->dev;
  95         struct net_device *netdev;
  96         int ret = 0;
  97
  98         netdev = hr_dev->iboe.netdevs[port];
  99         if (!netdev) {
 100                 dev_err(dev, "Can't find netdev on port(%u)!\n", port);
 101                 return -ENODEV;
 102         }
 103
 104         switch (event) {
 105         case NETDEV_UP:
 106         case NETDEV_CHANGE:
 107         case NETDEV_REGISTER:
 108         case NETDEV_CHANGEADDR:
 109                 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
 110                 break;
 111         case NETDEV_DOWN:
 112                 /*
 113                  * In v1 engine, only support all ports closed together.
 114                  */
 115                 break;
 116         default:
 117                 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
 118                 break;
 119         }
 120
 121         return ret;
 122 }
 123
 124 static int hns_roce_netdev_event(struct notifier_block *self,
 125                                  unsigned long event, void *ptr)
 126 {
 127         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
 128         struct hns_roce_ib_iboe *iboe = NULL;
 129         struct hns_roce_dev *hr_dev = NULL;
 130         int ret;
 131         u32 port;
 132
 133         hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
 134         iboe = &hr_dev->iboe;
 135
 136         for (port = 0; port < hr_dev->caps.num_ports; port++) {
 137                 if (dev == iboe->netdevs[port]) {
 138                         ret = handle_en_event(hr_dev, port, event);
 139                         if (ret)
 140                                 return NOTIFY_DONE;
 141                         break;
 142                 }
 143         }
 144
 145         return NOTIFY_DONE;
 146 }
 147
 148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
 149 {
 150         int ret;
 151         u8 i;
 152
 153         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 154                 if (hr_dev->hw->set_mtu)
 155                         hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
 156                                             hr_dev->caps.max_mtu);
 157                 ret = hns_roce_set_mac(hr_dev, i,
 158                                        hr_dev->iboe.netdevs[i]->dev_addr);
 159                 if (ret)
 160                         return ret;
 161         }
 162
 163         return 0;
 164 }
 165
 166 static int hns_roce_query_device(struct ib_device *ib_dev,
 167                                  struct ib_device_attr *props,
 168                                  struct ib_udata *uhw)
 169 {
 170         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 171
 172         memset(props, 0, sizeof(*props));
 173
 174         props->fw_ver = hr_dev->caps.fw_ver;
 175         props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
 176         props->max_mr_size = (u64)(~(0ULL));
 177         props->page_size_cap = hr_dev->caps.page_size_cap;
 178         props->vendor_id = hr_dev->vendor_id;
 179         props->vendor_part_id = hr_dev->vendor_part_id;
 180         props->hw_ver = hr_dev->hw_rev;
 181         props->max_qp = hr_dev->caps.num_qps;
 182         props->max_qp_wr = hr_dev->caps.max_wqes;
 183         props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
 184                                   IB_DEVICE_RC_RNR_NAK_GEN;
 185         props->max_send_sge = hr_dev->caps.max_sq_sg;
 186         props->max_recv_sge = hr_dev->caps.max_rq_sg;
 187         props->max_sge_rd = 1;
 188         props->max_cq = hr_dev->caps.num_cqs;
 189         props->max_cqe = hr_dev->caps.max_cqes;
 190         props->max_mr = hr_dev->caps.num_mtpts;
 191         props->max_pd = hr_dev->caps.num_pds;
 192         props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
 193         props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
 194         props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
 195                             IB_ATOMIC_HCA : IB_ATOMIC_NONE;
 196         props->max_pkeys = 1;
 197         props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
 198         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 199                 props->max_srq = hr_dev->caps.num_srqs;
 200                 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
 201                 props->max_srq_sge = hr_dev->caps.max_srq_sges;
 202         }
 203
 204         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
 205             hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
 206                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 207                 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
 208         }
 209
 210         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 211                 props->device_cap_flags |= IB_DEVICE_XRC;
 212
 213         return 0;
 214 }
 215
 216 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
 217                                struct ib_port_attr *props)
 218 {
 219         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 220         struct device *dev = hr_dev->dev;
 221         struct net_device *net_dev;
 222         unsigned long flags;
 223         enum ib_mtu mtu;
 224         u32 port;
 225
 226         port = port_num - 1;
 227
 228         /* props being zeroed by the caller, avoid zeroing it here */
 229
 230         props->max_mtu = hr_dev->caps.max_mtu;
 231         props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
 232         props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 233                                 IB_PORT_VENDOR_CLASS_SUP |
 234                                 IB_PORT_BOOT_MGMT_SUP;
 235         props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
 236         props->pkey_tbl_len = 1;
 237         props->active_width = IB_WIDTH_4X;
 238         props->active_speed = 1;
 239
 240         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
 241
 242         net_dev = hr_dev->iboe.netdevs[port];
 243         if (!net_dev) {
 244                 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 245                 dev_err(dev, "Find netdev %u failed!\n", port);
 246                 return -EINVAL;
 247         }
 248
 249         mtu = iboe_get_mtu(net_dev->mtu);
 250         props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
 251         props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
 252                                IB_PORT_ACTIVE :
 253                                IB_PORT_DOWN;
 254         props->phys_state = props->state == IB_PORT_ACTIVE ?
 255                                     IB_PORT_PHYS_STATE_LINK_UP :
 256                                     IB_PORT_PHYS_STATE_DISABLED;
 257
 258         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 259
 260         return 0;
 261 }
 262
 263 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
 264                                                     u32 port_num)
 265 {
 266         return IB_LINK_LAYER_ETHERNET;
 267 }
 268
 269 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
 270                                u16 *pkey)
 271 {
 272         *pkey = PKEY_ID;
 273
 274         return 0;
 275 }
 276
 277 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
 278                                   struct ib_device_modify *props)
 279 {
 280         unsigned long flags;
 281
 282         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 283                 return -EOPNOTSUPP;
 284
 285         if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
 286                 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
 287                 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
 288                 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
 295                                    struct ib_udata *udata)
 296 {
 297         int ret;
 298         struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
 299         struct hns_roce_ib_alloc_ucontext_resp resp = {};
 300         struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
 301
 302         if (!hr_dev->active)
 303                 return -EAGAIN;
 304
 305         resp.qp_tab_size = hr_dev->caps.num_qps;
 306         resp.srq_tab_size = hr_dev->caps.num_srqs;
 307
 308         ret = hns_roce_uar_alloc(hr_dev, &context->uar);
 309         if (ret)
 310                 goto error_fail_uar_alloc;
 311
 312         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
 313             hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
 314                 INIT_LIST_HEAD(&context->page_list);
 315                 mutex_init(&context->page_mutex);
 316         }
 317
 318         resp.cqe_size = hr_dev->caps.cqe_sz;
 319
 320         ret = ib_copy_to_udata(udata, &resp,
 321                                min(udata->outlen, sizeof(resp)));
 322         if (ret)
 323                 goto error_fail_copy_to_udata;
 324
 325         return 0;
 326
 327 error_fail_copy_to_udata:
 328         ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
 329
 330 error_fail_uar_alloc:
 331         return ret;
 332 }
 333
 334 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
 335 {
 336         struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
 337         struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
 338
 339         ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
 340 }
 341
 342 static int hns_roce_mmap(struct ib_ucontext *context,
 343                          struct vm_area_struct *vma)
 344 {
 345         struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
 346
 347         switch (vma->vm_pgoff) {
 348         case 0:
 349                 return rdma_user_mmap_io(context, vma,
 350                                          to_hr_ucontext(context)->uar.pfn,
 351                                          PAGE_SIZE,
 352                                          pgprot_noncached(vma->vm_page_prot),
 353                                          NULL);
 354
 355         /* vm_pgoff: 1 -- TPTR */
 356         case 1:
 357                 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
 358                         return -EINVAL;
 359                 /*
 360                  * FIXME: using io_remap_pfn_range on the dma address returned
 361                  * by dma_alloc_coherent is totally wrong.
 362                  */
 363                 return rdma_user_mmap_io(context, vma,
 364                                          hr_dev->tptr_dma_addr >> PAGE_SHIFT,
 365                                          hr_dev->tptr_size,
 366                                          vma->vm_page_prot,
 367                                          NULL);
 368
 369         default:
 370                 return -EINVAL;
 371         }
 372 }
 373
 374 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
 375                                    struct ib_port_immutable *immutable)
 376 {
 377         struct ib_port_attr attr;
 378         int ret;
 379
 380         ret = ib_query_port(ib_dev, port_num, &attr);
 381         if (ret)
 382                 return ret;
 383
 384         immutable->pkey_tbl_len = attr.pkey_tbl_len;
 385         immutable->gid_tbl_len = attr.gid_tbl_len;
 386
 387         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 388         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 389         if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
 390                 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
 391
 392         return 0;
 393 }
 394
 395 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
 396 {
 397 }
 398
 399 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
 400 {
 401         u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
 402         unsigned int major, minor, sub_minor;
 403
 404         major = upper_32_bits(fw_ver);
 405         minor = high_16_bits(lower_32_bits(fw_ver));
 406         sub_minor = low_16_bits(fw_ver);
 407
 408         snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
 409                  sub_minor);
 410 }
 411
 412 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
 413 {
 414         struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
 415
 416         hr_dev->active = false;
 417         unregister_netdevice_notifier(&iboe->nb);
 418         ib_unregister_device(&hr_dev->ib_dev);
 419 }
 420
 421 static const struct ib_device_ops hns_roce_dev_ops = {
 422         .owner = THIS_MODULE,
 423         .driver_id = RDMA_DRIVER_HNS,
 424         .uverbs_abi_ver = 1,
 425         .uverbs_no_driver_id_binding = 1,
 426
 427         .get_dev_fw_str = hns_roce_get_fw_ver,
 428         .add_gid = hns_roce_add_gid,
 429         .alloc_pd = hns_roce_alloc_pd,
 430         .alloc_ucontext = hns_roce_alloc_ucontext,
 431         .create_ah = hns_roce_create_ah,
 432         .create_user_ah = hns_roce_create_ah,
 433         .create_cq = hns_roce_create_cq,
 434         .create_qp = hns_roce_create_qp,
 435         .dealloc_pd = hns_roce_dealloc_pd,
 436         .dealloc_ucontext = hns_roce_dealloc_ucontext,
 437         .del_gid = hns_roce_del_gid,
 438         .dereg_mr = hns_roce_dereg_mr,
 439         .destroy_ah = hns_roce_destroy_ah,
 440         .destroy_cq = hns_roce_destroy_cq,
 441         .disassociate_ucontext = hns_roce_disassociate_ucontext,
 442         .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
 443         .get_dma_mr = hns_roce_get_dma_mr,
 444         .get_link_layer = hns_roce_get_link_layer,
 445         .get_port_immutable = hns_roce_port_immutable,
 446         .mmap = hns_roce_mmap,
 447         .modify_device = hns_roce_modify_device,
 448         .modify_qp = hns_roce_modify_qp,
 449         .query_ah = hns_roce_query_ah,
 450         .query_device = hns_roce_query_device,
 451         .query_pkey = hns_roce_query_pkey,
 452         .query_port = hns_roce_query_port,
 453         .reg_user_mr = hns_roce_reg_user_mr,
 454
 455         INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
 456         INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
 457         INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
 458         INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
 459         INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
 460 };
 461
 462 static const struct ib_device_ops hns_roce_dev_mr_ops = {
 463         .rereg_user_mr = hns_roce_rereg_user_mr,
 464 };
 465
 466 static const struct ib_device_ops hns_roce_dev_mw_ops = {
 467         .alloc_mw = hns_roce_alloc_mw,
 468         .dealloc_mw = hns_roce_dealloc_mw,
 469
 470         INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
 471 };
 472
 473 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
 474         .alloc_mr = hns_roce_alloc_mr,
 475         .map_mr_sg = hns_roce_map_mr_sg,
 476 };
 477
 478 static const struct ib_device_ops hns_roce_dev_srq_ops = {
 479         .create_srq = hns_roce_create_srq,
 480         .destroy_srq = hns_roce_destroy_srq,
 481
 482         INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
 483 };
 484
 485 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
 486         .alloc_xrcd = hns_roce_alloc_xrcd,
 487         .dealloc_xrcd = hns_roce_dealloc_xrcd,
 488
 489         INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
 490 };
 491
 492 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
 493 {
 494         int ret;
 495         struct hns_roce_ib_iboe *iboe = NULL;
 496         struct ib_device *ib_dev = NULL;
 497         struct device *dev = hr_dev->dev;
 498         unsigned int i;
 499
 500         iboe = &hr_dev->iboe;
 501         spin_lock_init(&iboe->lock);
 502
 503         ib_dev = &hr_dev->ib_dev;
 504
 505         ib_dev->node_type = RDMA_NODE_IB_CA;
 506         ib_dev->dev.parent = dev;
 507
 508         ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
 509         ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
 510         ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
 511
 512         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
 513                 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
 514
 515         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
 516                 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
 517
 518         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
 519                 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
 520
 521         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 522                 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
 523                 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
 524         }
 525
 526         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 527                 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
 528
 529         ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
 530         ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
 531         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 532                 if (!hr_dev->iboe.netdevs[i])
 533                         continue;
 534
 535                 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
 536                                            i + 1);
 537                 if (ret)
 538                         return ret;
 539         }
 540         dma_set_max_seg_size(dev, UINT_MAX);
 541         ret = ib_register_device(ib_dev, "hns_%d", dev);
 542         if (ret) {
 543                 dev_err(dev, "ib_register_device failed!\n");
 544                 return ret;
 545         }
 546
 547         ret = hns_roce_setup_mtu_mac(hr_dev);
 548         if (ret) {
 549                 dev_err(dev, "setup_mtu_mac failed!\n");
 550                 goto error_failed_setup_mtu_mac;
 551         }
 552
 553         iboe->nb.notifier_call = hns_roce_netdev_event;
 554         ret = register_netdevice_notifier(&iboe->nb);
 555         if (ret) {
 556                 dev_err(dev, "register_netdevice_notifier failed!\n");
 557                 goto error_failed_setup_mtu_mac;
 558         }
 559
 560         hr_dev->active = true;
 561         return 0;
 562
 563 error_failed_setup_mtu_mac:
 564         ib_unregister_device(ib_dev);
 565
 566         return ret;
 567 }
 568
 569 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
 570 {
 571         struct device *dev = hr_dev->dev;
 572         int ret;
 573
 574         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
 575                                       HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
 576                                       hr_dev->caps.num_mtpts, 1);
 577         if (ret) {
 578                 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
 579                 return ret;
 580         }
 581
 582         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
 583                                       HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
 584                                       hr_dev->caps.num_qps, 1);
 585         if (ret) {
 586                 dev_err(dev, "Failed to init QP context memory, aborting.\n");
 587                 goto err_unmap_dmpt;
 588         }
 589
 590         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
 591                                       HEM_TYPE_IRRL,
 592                                       hr_dev->caps.irrl_entry_sz *
 593                                       hr_dev->caps.max_qp_init_rdma,
 594                                       hr_dev->caps.num_qps, 1);
 595         if (ret) {
 596                 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
 597                 goto err_unmap_qp;
 598         }
 599
 600         if (hr_dev->caps.trrl_entry_sz) {
 601                 ret = hns_roce_init_hem_table(hr_dev,
 602                                               &hr_dev->qp_table.trrl_table,
 603                                               HEM_TYPE_TRRL,
 604                                               hr_dev->caps.trrl_entry_sz *
 605                                               hr_dev->caps.max_qp_dest_rdma,
 606                                               hr_dev->caps.num_qps, 1);
 607                 if (ret) {
 608                         dev_err(dev,
 609                                 "Failed to init trrl_table memory, aborting.\n");
 610                         goto err_unmap_irrl;
 611                 }
 612         }
 613
 614         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
 615                                       HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
 616                                       hr_dev->caps.num_cqs, 1);
 617         if (ret) {
 618                 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
 619                 goto err_unmap_trrl;
 620         }
 621
 622         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 623                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
 624                                               HEM_TYPE_SRQC,
 625                                               hr_dev->caps.srqc_entry_sz,
 626                                               hr_dev->caps.num_srqs, 1);
 627                 if (ret) {
 628                         dev_err(dev,
 629                                 "Failed to init SRQ context memory, aborting.\n");
 630                         goto err_unmap_cq;
 631                 }
 632         }
 633
 634         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
 635                 ret = hns_roce_init_hem_table(hr_dev,
 636                                               &hr_dev->qp_table.sccc_table,
 637                                               HEM_TYPE_SCCC,
 638                                               hr_dev->caps.sccc_sz,
 639                                               hr_dev->caps.num_qps, 1);
 640                 if (ret) {
 641                         dev_err(dev,
 642                                 "Failed to init SCC context memory, aborting.\n");
 643                         goto err_unmap_srq;
 644                 }
 645         }
 646
 647         if (hr_dev->caps.qpc_timer_entry_sz) {
 648                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
 649                                               HEM_TYPE_QPC_TIMER,
 650                                               hr_dev->caps.qpc_timer_entry_sz,
 651                                               hr_dev->caps.num_qpc_timer, 1);
 652                 if (ret) {
 653                         dev_err(dev,
 654                                 "Failed to init QPC timer memory, aborting.\n");
 655                         goto err_unmap_ctx;
 656                 }
 657         }
 658
 659         if (hr_dev->caps.cqc_timer_entry_sz) {
 660                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
 661                                               HEM_TYPE_CQC_TIMER,
 662                                               hr_dev->caps.cqc_timer_entry_sz,
 663                                               hr_dev->caps.num_cqc_timer, 1);
 664                 if (ret) {
 665                         dev_err(dev,
 666                                 "Failed to init CQC timer memory, aborting.\n");
 667                         goto err_unmap_qpc_timer;
 668                 }
 669         }
 670
 671         if (hr_dev->caps.gmv_entry_sz) {
 672                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
 673                                               HEM_TYPE_GMV,
 674                                               hr_dev->caps.gmv_entry_sz,
 675                                               hr_dev->caps.gmv_entry_num, 1);
 676                 if (ret) {
 677                         dev_err(dev,
 678                                 "failed to init gmv table memory, ret = %d\n",
 679                                 ret);
 680                         goto err_unmap_cqc_timer;
 681                 }
 682         }
 683
 684         return 0;
 685
 686 err_unmap_cqc_timer:
 687         if (hr_dev->caps.cqc_timer_entry_sz)
 688                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
 689
 690 err_unmap_qpc_timer:
 691         if (hr_dev->caps.qpc_timer_entry_sz)
 692                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
 693
 694 err_unmap_ctx:
 695         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
 696                 hns_roce_cleanup_hem_table(hr_dev,
 697                                            &hr_dev->qp_table.sccc_table);
 698 err_unmap_srq:
 699         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
 700                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
 701
 702 err_unmap_cq:
 703         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
 704
 705 err_unmap_trrl:
 706         if (hr_dev->caps.trrl_entry_sz)
 707                 hns_roce_cleanup_hem_table(hr_dev,
 708                                            &hr_dev->qp_table.trrl_table);
 709
 710 err_unmap_irrl:
 711         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
 712
 713 err_unmap_qp:
 714         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
 715
 716 err_unmap_dmpt:
 717         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
 718
 719         return ret;
 720 }
 721
 722 /**
 723  * hns_roce_setup_hca - setup host channel adapter
 724  * @hr_dev: pointer to hns roce device
 725  * Return : int
 726  */
 727 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
 728 {
 729         struct device *dev = hr_dev->dev;
 730         int ret;
 731
 732         spin_lock_init(&hr_dev->sm_lock);
 733         spin_lock_init(&hr_dev->bt_cmd_lock);
 734
 735         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
 736             hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
 737                 INIT_LIST_HEAD(&hr_dev->pgdir_list);
 738                 mutex_init(&hr_dev->pgdir_mutex);
 739         }
 740
 741         hns_roce_init_uar_table(hr_dev);
 742
 743         ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
 744         if (ret) {
 745                 dev_err(dev, "Failed to allocate priv_uar.\n");
 746                 goto err_uar_table_free;
 747         }
 748
 749         ret = hns_roce_init_qp_table(hr_dev);
 750         if (ret) {
 751                 dev_err(dev, "Failed to init qp_table.\n");
 752                 goto err_uar_table_free;
 753         }
 754
 755         hns_roce_init_pd_table(hr_dev);
 756
 757         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
 758                 hns_roce_init_xrcd_table(hr_dev);
 759
 760         hns_roce_init_mr_table(hr_dev);
 761
 762         hns_roce_init_cq_table(hr_dev);
 763
 764         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 765                 hns_roce_init_srq_table(hr_dev);
 766         }
 767
 768         return 0;
 769
 770 err_uar_table_free:
 771         ida_destroy(&hr_dev->uar_ida.ida);
 772         return ret;
 773 }
 774
 775 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
 776 {
 777         struct hns_roce_cq *hr_cq = to_hr_cq(cq);
 778         unsigned long flags;
 779
 780         spin_lock_irqsave(&hr_cq->lock, flags);
 781         if (cq->comp_handler) {
 782                 if (!hr_cq->is_armed) {
 783                         hr_cq->is_armed = 1;
 784                         list_add_tail(&hr_cq->node, cq_list);
 785                 }
 786         }
 787         spin_unlock_irqrestore(&hr_cq->lock, flags);
 788 }
 789
 790 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
 791 {
 792         struct hns_roce_qp *hr_qp;
 793         struct hns_roce_cq *hr_cq;
 794         struct list_head cq_list;
 795         unsigned long flags_qp;
 796         unsigned long flags;
 797
 798         INIT_LIST_HEAD(&cq_list);
 799
 800         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
 801         list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
 802                 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
 803                 if (hr_qp->sq.tail != hr_qp->sq.head)
 804                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
 805                 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
 806
 807                 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
 808                 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
 809                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
 810                 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
 811         }
 812
 813         list_for_each_entry(hr_cq, &cq_list, node)
 814                 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
 815
 816         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
 817 }
 818
 819 int hns_roce_init(struct hns_roce_dev *hr_dev)
 820 {
 821         struct device *dev = hr_dev->dev;
 822         int ret;
 823
 824         if (hr_dev->hw->reset) {
 825                 ret = hr_dev->hw->reset(hr_dev, true);
 826                 if (ret) {
 827                         dev_err(dev, "Reset RoCE engine failed!\n");
 828                         return ret;
 829                 }
 830         }
 831         hr_dev->is_reset = false;
 832
 833         if (hr_dev->hw->cmq_init) {
 834                 ret = hr_dev->hw->cmq_init(hr_dev);
 835                 if (ret) {
 836                         dev_err(dev, "Init RoCE Command Queue failed!\n");
 837                         goto error_failed_cmq_init;
 838                 }
 839         }
 840
 841         ret = hr_dev->hw->hw_profile(hr_dev);
 842         if (ret) {
 843                 dev_err(dev, "Get RoCE engine profile failed!\n");
 844                 goto error_failed_cmd_init;
 845         }
 846
 847         ret = hns_roce_cmd_init(hr_dev);
 848         if (ret) {
 849                 dev_err(dev, "cmd init failed!\n");
 850                 goto error_failed_cmd_init;
 851         }
 852
 853         /* EQ depends on poll mode, event mode depends on EQ */
 854         ret = hr_dev->hw->init_eq(hr_dev);
 855         if (ret) {
 856                 dev_err(dev, "eq init failed!\n");
 857                 goto error_failed_eq_table;
 858         }
 859
 860         if (hr_dev->cmd_mod) {
 861                 ret = hns_roce_cmd_use_events(hr_dev);
 862                 if (ret)
 863                         dev_warn(dev,
 864                                  "Cmd event  mode failed, set back to poll!\n");
 865         }
 866
 867         ret = hns_roce_init_hem(hr_dev);
 868         if (ret) {
 869                 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
 870                 goto error_failed_init_hem;
 871         }
 872
 873         ret = hns_roce_setup_hca(hr_dev);
 874         if (ret) {
 875                 dev_err(dev, "setup hca failed!\n");
 876                 goto error_failed_setup_hca;
 877         }
 878
 879         if (hr_dev->hw->hw_init) {
 880                 ret = hr_dev->hw->hw_init(hr_dev);
 881                 if (ret) {
 882                         dev_err(dev, "hw_init failed!\n");
 883                         goto error_failed_engine_init;
 884                 }
 885         }
 886
 887         INIT_LIST_HEAD(&hr_dev->qp_list);
 888         spin_lock_init(&hr_dev->qp_list_lock);
 889         INIT_LIST_HEAD(&hr_dev->dip_list);
 890         spin_lock_init(&hr_dev->dip_list_lock);
 891
 892         ret = hns_roce_register_device(hr_dev);
 893         if (ret)
 894                 goto error_failed_register_device;
 895
 896         return 0;
 897
 898 error_failed_register_device:
 899         if (hr_dev->hw->hw_exit)
 900                 hr_dev->hw->hw_exit(hr_dev);
 901
 902 error_failed_engine_init:
 903         hns_roce_cleanup_bitmap(hr_dev);
 904
 905 error_failed_setup_hca:
 906         hns_roce_cleanup_hem(hr_dev);
 907
 908 error_failed_init_hem:
 909         if (hr_dev->cmd_mod)
 910                 hns_roce_cmd_use_polling(hr_dev);
 911         hr_dev->hw->cleanup_eq(hr_dev);
 912
 913 error_failed_eq_table:
 914         hns_roce_cmd_cleanup(hr_dev);
 915
 916 error_failed_cmd_init:
 917         if (hr_dev->hw->cmq_exit)
 918                 hr_dev->hw->cmq_exit(hr_dev);
 919
 920 error_failed_cmq_init:
 921         if (hr_dev->hw->reset) {
 922                 if (hr_dev->hw->reset(hr_dev, false))
 923                         dev_err(dev, "Dereset RoCE engine failed!\n");
 924         }
 925
 926         return ret;
 927 }
 928
 929 void hns_roce_exit(struct hns_roce_dev *hr_dev)
 930 {
 931         hns_roce_unregister_device(hr_dev);
 932
 933         if (hr_dev->hw->hw_exit)
 934                 hr_dev->hw->hw_exit(hr_dev);
 935         hns_roce_cleanup_bitmap(hr_dev);
 936         hns_roce_cleanup_hem(hr_dev);
 937
 938         if (hr_dev->cmd_mod)
 939                 hns_roce_cmd_use_polling(hr_dev);
 940
 941         hr_dev->hw->cleanup_eq(hr_dev);
 942         hns_roce_cmd_cleanup(hr_dev);
 943         if (hr_dev->hw->cmq_exit)
 944                 hr_dev->hw->cmq_exit(hr_dev);
 945         if (hr_dev->hw->reset)
 946                 hr_dev->hw->reset(hr_dev, false);
 947 }
 948
 949 MODULE_LICENSE("Dual BSD/GPL");
 950 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
 951 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
 952 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
 953 MODULE_DESCRIPTION("HNS RoCE Driver");