drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37
  38 #define DRV_NAME "hns_roce"
  39
  40 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  41
  42 #define MAC_ADDR_OCTET_NUM                      6
  43 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  44
  45 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
  46
  47 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  48
  49 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  50
  51 /* Hardware specification only for v1 engine */
  52 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  53 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  54
  55 /* Hardware specification only for v1 engine */
  56 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  57 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  58
  59 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  60 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  61         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  62 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  63 #define HNS_ROCE_MIN_CQE_CNT                    16
  64
  65 #define HNS_ROCE_MAX_IRQ_NUM                    128
  66
  67 #define EQ_ENABLE                               1
  68 #define EQ_DISABLE                              0
  69
  70 #define HNS_ROCE_CEQ                            0
  71 #define HNS_ROCE_AEQ                            1
  72
  73 #define HNS_ROCE_CEQ_ENTRY_SIZE                 0x4
  74 #define HNS_ROCE_AEQ_ENTRY_SIZE                 0x10
  75
  76 /* 4G/4K = 1M */
  77 #define HNS_ROCE_SL_SHIFT                       28
  78 #define HNS_ROCE_TCLASS_SHIFT                   20
  79 #define HNS_ROCE_FLOW_LABLE_MASK                0xfffff
  80
  81 #define HNS_ROCE_MAX_PORTS                      6
  82 #define HNS_ROCE_MAX_GID_NUM                    16
  83 #define HNS_ROCE_GID_SIZE                       16
  84
  85 #define HNS_ROCE_HOP_NUM_0                      0xff
  86
  87 #define BITMAP_NO_RR                            0
  88 #define BITMAP_RR                               1
  89
  90 #define MR_TYPE_MR                              0x00
  91 #define MR_TYPE_DMA                             0x03
  92
  93 #define PKEY_ID                                 0xffff
  94 #define GUID_LEN                                8
  95 #define NODE_DESC_SIZE                          64
  96 #define DB_REG_OFFSET                           0x1000
  97
  98 #define SERV_TYPE_RC                            0
  99 #define SERV_TYPE_RD                            1
 100 #define SERV_TYPE_UC                            2
 101 #define SERV_TYPE_UD                            3
 102
 103 /* Configure to HW for PAGE_SIZE larger than 4KB */
 104 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 105
 106 #define PAGES_SHIFT_8                           8
 107 #define PAGES_SHIFT_16                          16
 108 #define PAGES_SHIFT_24                          24
 109 #define PAGES_SHIFT_32                          32
 110
 111 enum {
 112         HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0,
 113 };
 114
 115 enum {
 116         HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0,
 117 };
 118
 119 enum hns_roce_qp_state {
 120         HNS_ROCE_QP_STATE_RST,
 121         HNS_ROCE_QP_STATE_INIT,
 122         HNS_ROCE_QP_STATE_RTR,
 123         HNS_ROCE_QP_STATE_RTS,
 124         HNS_ROCE_QP_STATE_SQD,
 125         HNS_ROCE_QP_STATE_ERR,
 126         HNS_ROCE_QP_NUM_STATE,
 127 };
 128
 129 enum hns_roce_event {
 130         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 131         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 132         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 133         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 134         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 135         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 136         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 137         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 138         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 139         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 140         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 141         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 142         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 143         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 144         /* 0x10 and 0x11 is unused in currently application case */
 145         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 146         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 147         HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
 148         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 149 };
 150
 151 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 152 enum {
 153         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 154         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 155         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 156         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 157         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 158         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 159         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 160 };
 161
 162 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 163 enum {
 164         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 165         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 166         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 167         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 168         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 169         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 170         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 171 };
 172
 173 /* DOORBELL overflow subtype */
 174 enum {
 175         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 176         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 177         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 178         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 179         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 180         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 181 };
 182
 183 enum {
 184         /* RQ&SRQ related operations */
 185         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 186         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 187 };
 188
 189 enum {
 190         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 191         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 192         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 193         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3)
 194 };
 195
 196 enum hns_roce_mtt_type {
 197         MTT_TYPE_WQE,
 198         MTT_TYPE_CQE,
 199 };
 200
 201 enum {
 202         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 203 };
 204
 205 #define HNS_ROCE_CMD_SUCCESS                    1
 206
 207 #define HNS_ROCE_PORT_DOWN                      0
 208 #define HNS_ROCE_PORT_UP                        1
 209
 210 #define HNS_ROCE_MTT_ENTRY_PER_SEG              8
 211
 212 #define PAGE_ADDR_SHIFT                         12
 213
 214 struct hns_roce_uar {
 215         u64             pfn;
 216         unsigned long   index;
 217         unsigned long   logic_idx;
 218 };
 219
 220 struct hns_roce_vma_data {
 221         struct list_head list;
 222         struct vm_area_struct *vma;
 223         struct mutex *vma_list_mutex;
 224 };
 225
 226 struct hns_roce_ucontext {
 227         struct ib_ucontext      ibucontext;
 228         struct hns_roce_uar     uar;
 229         struct list_head        page_list;
 230         struct mutex            page_mutex;
 231         struct list_head        vma_list;
 232         struct mutex            vma_list_mutex;
 233 };
 234
 235 struct hns_roce_pd {
 236         struct ib_pd            ibpd;
 237         unsigned long           pdn;
 238 };
 239
 240 struct hns_roce_bitmap {
 241         /* Bitmap Traversal last a bit which is 1 */
 242         unsigned long           last;
 243         unsigned long           top;
 244         unsigned long           max;
 245         unsigned long           reserved_top;
 246         unsigned long           mask;
 247         spinlock_t              lock;
 248         unsigned long           *table;
 249 };
 250
 251 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
 252 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
 253 /* Every bit repesent to a partner free/used status in bitmap */
 254 /*
 255  * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
 256  * Bit = 1 represent to idle and available; bit = 0: not available
 257  */
 258 struct hns_roce_buddy {
 259         /* Members point to every order level bitmap */
 260         unsigned long **bits;
 261         /* Represent to avail bits of the order level bitmap */
 262         u32            *num_free;
 263         int             max_order;
 264         spinlock_t      lock;
 265 };
 266
 267 /* For Hardware Entry Memory */
 268 struct hns_roce_hem_table {
 269         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 270         u32             type;
 271         /* HEM array elment num */
 272         unsigned long   num_hem;
 273         /* HEM entry record obj total num */
 274         unsigned long   num_obj;
 275         /*Single obj size */
 276         unsigned long   obj_size;
 277         unsigned long   table_chunk_size;
 278         int             lowmem;
 279         struct mutex    mutex;
 280         struct hns_roce_hem **hem;
 281         u64             **bt_l1;
 282         dma_addr_t      *bt_l1_dma_addr;
 283         u64             **bt_l0;
 284         dma_addr_t      *bt_l0_dma_addr;
 285 };
 286
 287 struct hns_roce_mtt {
 288         unsigned long           first_seg;
 289         int                     order;
 290         int                     page_shift;
 291         enum hns_roce_mtt_type  mtt_type;
 292 };
 293
 294 /* Only support 4K page size for mr register */
 295 #define MR_SIZE_4K 0
 296
 297 struct hns_roce_mr {
 298         struct ib_mr            ibmr;
 299         struct ib_umem          *umem;
 300         u64                     iova; /* MR's virtual orignal addr */
 301         u64                     size; /* Address range of MR */
 302         u32                     key; /* Key of MR */
 303         u32                     pd;   /* PD num of MR */
 304         u32                     access;/* Access permission of MR */
 305         int                     enabled; /* MR's active status */
 306         int                     type;   /* MR's register type */
 307         u64                     *pbl_buf;/* MR's PBL space */
 308         dma_addr_t              pbl_dma_addr;   /* MR's PBL space PA */
 309         u32                     pbl_size;/* PA number in the PBL */
 310         u64                     pbl_ba;/* page table address */
 311         u32                     l0_chunk_last_num;/* L0 last number */
 312         u32                     l1_chunk_last_num;/* L1 last number */
 313         u64                     **pbl_bt_l2;/* PBL BT L2 */
 314         u64                     **pbl_bt_l1;/* PBL BT L1 */
 315         u64                     *pbl_bt_l0;/* PBL BT L0 */
 316         dma_addr_t              *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
 317         dma_addr_t              *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
 318         dma_addr_t              pbl_l0_dma_addr;/* PBL BT L0 dma addr */
 319         u32                     pbl_ba_pg_sz;/* BT chunk page size */
 320         u32                     pbl_buf_pg_sz;/* buf chunk page size */
 321         u32                     pbl_hop_num;/* multi-hop number */
 322 };
 323
 324 struct hns_roce_mr_table {
 325         struct hns_roce_bitmap          mtpt_bitmap;
 326         struct hns_roce_buddy           mtt_buddy;
 327         struct hns_roce_hem_table       mtt_table;
 328         struct hns_roce_hem_table       mtpt_table;
 329         struct hns_roce_buddy           mtt_cqe_buddy;
 330         struct hns_roce_hem_table       mtt_cqe_table;
 331 };
 332
 333 struct hns_roce_wq {
 334         u64             *wrid;     /* Work request ID */
 335         spinlock_t      lock;
 336         int             wqe_cnt;  /* WQE num */
 337         u32             max_post;
 338         int             max_gs;
 339         int             offset;
 340         int             wqe_shift;/* WQE size */
 341         u32             head;
 342         u32             tail;
 343         void __iomem    *db_reg_l;
 344 };
 345
 346 struct hns_roce_sge {
 347         int             sge_cnt;  /* SGE num */
 348         int             offset;
 349         int             sge_shift;/* SGE size */
 350 };
 351
 352 struct hns_roce_buf_list {
 353         void            *buf;
 354         dma_addr_t      map;
 355 };
 356
 357 struct hns_roce_buf {
 358         struct hns_roce_buf_list        direct;
 359         struct hns_roce_buf_list        *page_list;
 360         int                             nbufs;
 361         u32                             npages;
 362         int                             page_shift;
 363 };
 364
 365 struct hns_roce_db_pgdir {
 366         struct list_head        list;
 367         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 368         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / 2);
 369         unsigned long           *bits[2];
 370         u32                     *page;
 371         dma_addr_t              db_dma;
 372 };
 373
 374 struct hns_roce_user_db_page {
 375         struct list_head        list;
 376         struct ib_umem          *umem;
 377         unsigned long           user_virt;
 378         refcount_t              refcount;
 379 };
 380
 381 struct hns_roce_db {
 382         u32             *db_record;
 383         union {
 384                 struct hns_roce_db_pgdir *pgdir;
 385                 struct hns_roce_user_db_page *user_page;
 386         } u;
 387         dma_addr_t      dma;
 388         int             index;
 389         int             order;
 390 };
 391
 392 struct hns_roce_cq_buf {
 393         struct hns_roce_buf hr_buf;
 394         struct hns_roce_mtt hr_mtt;
 395 };
 396
 397 struct hns_roce_cq {
 398         struct ib_cq                    ib_cq;
 399         struct hns_roce_cq_buf          hr_buf;
 400         struct hns_roce_db              db;
 401         u8                              db_en;
 402         spinlock_t                      lock;
 403         struct ib_umem                  *umem;
 404         void (*comp)(struct hns_roce_cq *cq);
 405         void (*event)(struct hns_roce_cq *cq, enum hns_roce_event event_type);
 406
 407         struct hns_roce_uar             *uar;
 408         u32                             cq_depth;
 409         u32                             cons_index;
 410         u32                             *set_ci_db;
 411         void __iomem                    *cq_db_l;
 412         u16                             *tptr_addr;
 413         int                             arm_sn;
 414         unsigned long                   cqn;
 415         u32                             vector;
 416         atomic_t                        refcount;
 417         struct completion               free;
 418 };
 419
 420 struct hns_roce_srq {
 421         struct ib_srq           ibsrq;
 422         int                     srqn;
 423 };
 424
 425 struct hns_roce_uar_table {
 426         struct hns_roce_bitmap bitmap;
 427 };
 428
 429 struct hns_roce_qp_table {
 430         struct hns_roce_bitmap          bitmap;
 431         spinlock_t                      lock;
 432         struct hns_roce_hem_table       qp_table;
 433         struct hns_roce_hem_table       irrl_table;
 434         struct hns_roce_hem_table       trrl_table;
 435 };
 436
 437 struct hns_roce_cq_table {
 438         struct hns_roce_bitmap          bitmap;
 439         spinlock_t                      lock;
 440         struct radix_tree_root          tree;
 441         struct hns_roce_hem_table       table;
 442 };
 443
 444 struct hns_roce_raq_table {
 445         struct hns_roce_buf_list        *e_raq_buf;
 446 };
 447
 448 struct hns_roce_av {
 449         __le32      port_pd;
 450         u8          gid_index;
 451         u8          stat_rate;
 452         u8          hop_limit;
 453         __le32      sl_tclass_flowlabel;
 454         u8          dgid[HNS_ROCE_GID_SIZE];
 455         u8          mac[6];
 456         __le16      vlan;
 457 };
 458
 459 struct hns_roce_ah {
 460         struct ib_ah            ibah;
 461         struct hns_roce_av      av;
 462 };
 463
 464 struct hns_roce_cmd_context {
 465         struct completion       done;
 466         int                     result;
 467         int                     next;
 468         u64                     out_param;
 469         u16                     token;
 470 };
 471
 472 struct hns_roce_cmdq {
 473         struct dma_pool         *pool;
 474         struct mutex            hcr_mutex;
 475         struct semaphore        poll_sem;
 476         /*
 477          * Event mode: cmd register mutex protection,
 478          * ensure to not exceed max_cmds and user use limit region
 479          */
 480         struct semaphore        event_sem;
 481         int                     max_cmds;
 482         spinlock_t              context_lock;
 483         int                     free_head;
 484         struct hns_roce_cmd_context *context;
 485         /*
 486          * Result of get integer part
 487          * which max_comds compute according a power of 2
 488          */
 489         u16                     token_mask;
 490         /*
 491          * Process whether use event mode, init default non-zero
 492          * After the event queue of cmd event ready,
 493          * can switch into event mode
 494          * close device, switch into poll mode(non event mode)
 495          */
 496         u8                      use_events;
 497         u8                      toggle;
 498 };
 499
 500 struct hns_roce_cmd_mailbox {
 501         void                   *buf;
 502         dma_addr_t              dma;
 503 };
 504
 505 struct hns_roce_dev;
 506
 507 struct hns_roce_rinl_sge {
 508         void                    *addr;
 509         u32                     len;
 510 };
 511
 512 struct hns_roce_rinl_wqe {
 513         struct hns_roce_rinl_sge *sg_list;
 514         u32                      sge_cnt;
 515 };
 516
 517 struct hns_roce_rinl_buf {
 518         struct hns_roce_rinl_wqe *wqe_list;
 519         u32                      wqe_cnt;
 520 };
 521
 522 struct hns_roce_qp {
 523         struct ib_qp            ibqp;
 524         struct hns_roce_buf     hr_buf;
 525         struct hns_roce_wq      rq;
 526         struct hns_roce_db      rdb;
 527         u8                      rdb_en;
 528         u32                     doorbell_qpn;
 529         __le32                  sq_signal_bits;
 530         u32                     sq_next_wqe;
 531         int                     sq_max_wqes_per_wr;
 532         int                     sq_spare_wqes;
 533         struct hns_roce_wq      sq;
 534
 535         struct ib_umem          *umem;
 536         struct hns_roce_mtt     mtt;
 537         u32                     buff_size;
 538         struct mutex            mutex;
 539         u8                      port;
 540         u8                      phy_port;
 541         u8                      sl;
 542         u8                      resp_depth;
 543         u8                      state;
 544         u32                     access_flags;
 545         u32                     atomic_rd_en;
 546         u32                     pkey_index;
 547         u32                     qkey;
 548         void                    (*event)(struct hns_roce_qp *qp,
 549                                          enum hns_roce_event event_type);
 550         unsigned long           qpn;
 551
 552         atomic_t                refcount;
 553         struct completion       free;
 554
 555         struct hns_roce_sge     sge;
 556         u32                     next_sge;
 557
 558         struct hns_roce_rinl_buf rq_inl_buf;
 559 };
 560
 561 struct hns_roce_sqp {
 562         struct hns_roce_qp      hr_qp;
 563 };
 564
 565 struct hns_roce_ib_iboe {
 566         spinlock_t              lock;
 567         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 568         struct notifier_block   nb;
 569         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 570 };
 571
 572 enum {
 573         HNS_ROCE_EQ_STAT_INVALID  = 0,
 574         HNS_ROCE_EQ_STAT_VALID    = 2,
 575 };
 576
 577 struct hns_roce_ceqe {
 578         u32                     comp;
 579 };
 580
 581 struct hns_roce_aeqe {
 582         __le32 asyn;
 583         union {
 584                 struct {
 585                         __le32 qp;
 586                         u32 rsv0;
 587                         u32 rsv1;
 588                 } qp_event;
 589
 590                 struct {
 591                         __le32 cq;
 592                         u32 rsv0;
 593                         u32 rsv1;
 594                 } cq_event;
 595
 596                 struct {
 597                         __le32 ceqe;
 598                         u32 rsv0;
 599                         u32 rsv1;
 600                 } ce_event;
 601
 602                 struct {
 603                         __le64  out_param;
 604                         __le16  token;
 605                         u8      status;
 606                         u8      rsv0;
 607                 } __packed cmd;
 608          } event;
 609 };
 610
 611 struct hns_roce_eq {
 612         struct hns_roce_dev             *hr_dev;
 613         void __iomem                    *doorbell;
 614
 615         int                             type_flag;/* Aeq:1 ceq:0 */
 616         int                             eqn;
 617         u32                             entries;
 618         int                             log_entries;
 619         int                             eqe_size;
 620         int                             irq;
 621         int                             log_page_size;
 622         int                             cons_index;
 623         struct hns_roce_buf_list        *buf_list;
 624         int                             over_ignore;
 625         int                             coalesce;
 626         int                             arm_st;
 627         u64                             eqe_ba;
 628         int                             eqe_ba_pg_sz;
 629         int                             eqe_buf_pg_sz;
 630         int                             hop_num;
 631         u64                             *bt_l0; /* Base address table for L0 */
 632         u64                             **bt_l1; /* Base address table for L1 */
 633         u64                             **buf;
 634         dma_addr_t                      l0_dma;
 635         dma_addr_t                      *l1_dma;
 636         dma_addr_t                      *buf_dma;
 637         u32                             l0_last_num; /* L0 last chunk num */
 638         u32                             l1_last_num; /* L1 last chunk num */
 639         int                             eq_max_cnt;
 640         int                             eq_period;
 641         int                             shift;
 642         dma_addr_t                      cur_eqe_ba;
 643         dma_addr_t                      nxt_eqe_ba;
 644 };
 645
 646 struct hns_roce_eq_table {
 647         struct hns_roce_eq      *eq;
 648         void __iomem            **eqc_base; /* only for hw v1 */
 649 };
 650
 651 struct hns_roce_caps {
 652         u8              num_ports;
 653         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 654         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 655         int             local_ca_ack_delay;
 656         int             num_uars;
 657         u32             phy_num_uars;
 658         u32             max_sq_sg;      /* 2 */
 659         u32             max_sq_inline;  /* 32 */
 660         u32             max_rq_sg;      /* 2 */
 661         int             num_qps;        /* 256k */
 662         u32             max_wqes;       /* 16k */
 663         u32             max_sq_desc_sz; /* 64 */
 664         u32             max_rq_desc_sz; /* 64 */
 665         u32             max_srq_desc_sz;
 666         int             max_qp_init_rdma;
 667         int             max_qp_dest_rdma;
 668         int             num_cqs;
 669         int             max_cqes;
 670         int             min_cqes;
 671         u32             min_wqes;
 672         int             reserved_cqs;
 673         int             num_aeq_vectors;        /* 1 */
 674         int             num_comp_vectors;
 675         int             num_other_vectors;
 676         int             num_mtpts;
 677         u32             num_mtt_segs;
 678         u32             num_cqe_segs;
 679         int             reserved_mrws;
 680         int             reserved_uars;
 681         int             num_pds;
 682         int             reserved_pds;
 683         u32             mtt_entry_sz;
 684         u32             cq_entry_sz;
 685         u32             page_size_cap;
 686         u32             reserved_lkey;
 687         int             mtpt_entry_sz;
 688         int             qpc_entry_sz;
 689         int             irrl_entry_sz;
 690         int             trrl_entry_sz;
 691         int             cqc_entry_sz;
 692         u32             pbl_ba_pg_sz;
 693         u32             pbl_buf_pg_sz;
 694         u32             pbl_hop_num;
 695         int             aeqe_depth;
 696         int             ceqe_depth;
 697         enum ib_mtu     max_mtu;
 698         u32             qpc_bt_num;
 699         u32             srqc_bt_num;
 700         u32             cqc_bt_num;
 701         u32             mpt_bt_num;
 702         u32             qpc_ba_pg_sz;
 703         u32             qpc_buf_pg_sz;
 704         u32             qpc_hop_num;
 705         u32             srqc_ba_pg_sz;
 706         u32             srqc_buf_pg_sz;
 707         u32             srqc_hop_num;
 708         u32             cqc_ba_pg_sz;
 709         u32             cqc_buf_pg_sz;
 710         u32             cqc_hop_num;
 711         u32             mpt_ba_pg_sz;
 712         u32             mpt_buf_pg_sz;
 713         u32             mpt_hop_num;
 714         u32             mtt_ba_pg_sz;
 715         u32             mtt_buf_pg_sz;
 716         u32             mtt_hop_num;
 717         u32             cqe_ba_pg_sz;
 718         u32             cqe_buf_pg_sz;
 719         u32             cqe_hop_num;
 720         u32             eqe_ba_pg_sz;
 721         u32             eqe_buf_pg_sz;
 722         u32             eqe_hop_num;
 723         u32             sl_num;
 724         u32             tsq_buf_pg_sz;
 725         u32             tpq_buf_pg_sz;
 726         u32             chunk_sz;       /* chunk size in non multihop mode*/
 727         u64             flags;
 728 };
 729
 730 struct hns_roce_hw {
 731         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 732         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 733         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 734         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 735         int (*hw_init)(struct hns_roce_dev *hr_dev);
 736         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 737         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 738                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 739                          u16 token, int event);
 740         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
 741         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 742                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 743         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 744         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 745                         enum ib_mtu mtu);
 746         int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
 747                           unsigned long mtpt_idx);
 748         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 749                                 struct hns_roce_mr *mr, int flags, u32 pdn,
 750                                 int mr_access_flags, u64 iova, u64 size,
 751                                 void *mb_buf);
 752         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 753                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 754                           dma_addr_t dma_handle, int nent, u32 vector);
 755         int (*set_hem)(struct hns_roce_dev *hr_dev,
 756                        struct hns_roce_hem_table *table, int obj, int step_idx);
 757         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 758                          struct hns_roce_hem_table *table, int obj,
 759                          int step_idx);
 760         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 761                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 762         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 763                          int attr_mask, enum ib_qp_state cur_state,
 764                          enum ib_qp_state new_state);
 765         int (*destroy_qp)(struct ib_qp *ibqp);
 766         int (*post_send)(struct ib_qp *ibqp, struct ib_send_wr *wr,
 767                          struct ib_send_wr **bad_wr);
 768         int (*post_recv)(struct ib_qp *qp, struct ib_recv_wr *recv_wr,
 769                          struct ib_recv_wr **bad_recv_wr);
 770         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 771         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 772         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
 773         int (*destroy_cq)(struct ib_cq *ibcq);
 774         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 775         int (*init_eq)(struct hns_roce_dev *hr_dev);
 776         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 777 };
 778
 779 struct hns_roce_dev {
 780         struct ib_device        ib_dev;
 781         struct platform_device  *pdev;
 782         struct pci_dev          *pci_dev;
 783         struct device           *dev;
 784         struct hns_roce_uar     priv_uar;
 785         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 786         spinlock_t              sm_lock;
 787         spinlock_t              bt_cmd_lock;
 788         bool                    active;
 789         bool                    is_reset;
 790         struct hns_roce_ib_iboe iboe;
 791
 792         struct list_head        pgdir_list;
 793         struct mutex            pgdir_mutex;
 794         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 795         u8 __iomem              *reg_base;
 796         struct hns_roce_caps    caps;
 797         struct radix_tree_root  qp_table_tree;
 798
 799         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM];
 800         u64                     sys_image_guid;
 801         u32                     vendor_id;
 802         u32                     vendor_part_id;
 803         u32                     hw_rev;
 804         void __iomem            *priv_addr;
 805
 806         struct hns_roce_cmdq    cmd;
 807         struct hns_roce_bitmap    pd_bitmap;
 808         struct hns_roce_uar_table uar_table;
 809         struct hns_roce_mr_table  mr_table;
 810         struct hns_roce_cq_table  cq_table;
 811         struct hns_roce_qp_table  qp_table;
 812         struct hns_roce_eq_table  eq_table;
 813
 814         int                     cmd_mod;
 815         int                     loop_idc;
 816         u32                     sdb_offset;
 817         u32                     odb_offset;
 818         dma_addr_t              tptr_dma_addr; /*only for hw v1*/
 819         u32                     tptr_size; /*only for hw v1*/
 820         const struct hns_roce_hw *hw;
 821         void                    *priv;
 822 };
 823
 824 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
 825 {
 826         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
 827 }
 828
 829 static inline struct hns_roce_ucontext
 830                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
 831 {
 832         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
 833 }
 834
 835 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
 836 {
 837         return container_of(ibpd, struct hns_roce_pd, ibpd);
 838 }
 839
 840 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
 841 {
 842         return container_of(ibah, struct hns_roce_ah, ibah);
 843 }
 844
 845 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
 846 {
 847         return container_of(ibmr, struct hns_roce_mr, ibmr);
 848 }
 849
 850 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
 851 {
 852         return container_of(ibqp, struct hns_roce_qp, ibqp);
 853 }
 854
 855 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
 856 {
 857         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
 858 }
 859
 860 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
 861 {
 862         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
 863 }
 864
 865 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
 866 {
 867         return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
 868 }
 869
 870 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
 871 {
 872         __raw_writeq(*(u64 *) val, dest);
 873 }
 874
 875 static inline struct hns_roce_qp
 876         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
 877 {
 878         return radix_tree_lookup(&hr_dev->qp_table_tree,
 879                                  qpn & (hr_dev->caps.num_qps - 1));
 880 }
 881
 882 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
 883 {
 884         u32 page_size = 1 << buf->page_shift;
 885
 886         if (buf->nbufs == 1)
 887                 return (char *)(buf->direct.buf) + offset;
 888         else
 889                 return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
 890                        (offset & (page_size - 1));
 891 }
 892
 893 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
 894 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
 895 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
 896 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
 897
 898 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
 899 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
 900 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
 901                         u64 out_param);
 902 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
 903 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
 904
 905 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
 906                       struct hns_roce_mtt *mtt);
 907 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
 908                           struct hns_roce_mtt *mtt);
 909 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
 910                            struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
 911
 912 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
 913 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
 914 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
 915 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
 916 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
 917
 918 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
 919 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
 920 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
 921 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
 922 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
 923
 924 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
 925 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
 926                          int rr);
 927 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
 928                          u32 reserved_bot, u32 resetrved_top);
 929 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
 930 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
 931 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
 932                                 int align, unsigned long *obj);
 933 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
 934                                 unsigned long obj, int cnt,
 935                                 int rr);
 936
 937 struct ib_ah *hns_roce_create_ah(struct ib_pd *pd,
 938                                  struct rdma_ah_attr *ah_attr,
 939                                  struct ib_udata *udata);
 940 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
 941 int hns_roce_destroy_ah(struct ib_ah *ah);
 942
 943 struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
 944                                 struct ib_ucontext *context,
 945                                 struct ib_udata *udata);
 946 int hns_roce_dealloc_pd(struct ib_pd *pd);
 947
 948 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
 949 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 950                                    u64 virt_addr, int access_flags,
 951                                    struct ib_udata *udata);
 952 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
 953                            u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
 954                            struct ib_udata *udata);
 955 int hns_roce_dereg_mr(struct ib_mr *ibmr);
 956 int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
 957                        struct hns_roce_cmd_mailbox *mailbox,
 958                        unsigned long mpt_index);
 959 unsigned long key_to_hw_index(u32 key);
 960
 961 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
 962                        struct hns_roce_buf *buf);
 963 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
 964                        struct hns_roce_buf *buf, u32 page_shift);
 965
 966 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
 967                                struct hns_roce_mtt *mtt, struct ib_umem *umem);
 968
 969 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
 970                                  struct ib_qp_init_attr *init_attr,
 971                                  struct ib_udata *udata);
 972 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 973                        int attr_mask, struct ib_udata *udata);
 974 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
 975 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
 976 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
 977 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
 978                           struct ib_cq *ib_cq);
 979 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
 980 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
 981                        struct hns_roce_cq *recv_cq);
 982 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
 983                          struct hns_roce_cq *recv_cq);
 984 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
 985 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
 986 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
 987                                int cnt);
 988 __be32 send_ieth(struct ib_send_wr *wr);
 989 int to_hr_qp_type(int qp_type);
 990
 991 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
 992                                     const struct ib_cq_init_attr *attr,
 993                                     struct ib_ucontext *context,
 994                                     struct ib_udata *udata);
 995
 996 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq);
 997 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
 998
 999 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1000                          struct hns_roce_db *db);
1001 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1002                             struct hns_roce_db *db);
1003 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1004                       int order);
1005 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1006
1007 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1008 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1009 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1010 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1011 int hns_roce_init(struct hns_roce_dev *hr_dev);
1012 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1013
1014 #endif /* _HNS_ROCE_DEVICE_H */