drivers/infiniband/hw/bnxt_re/ib_verbs.c

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: IB Verbs interpreter
  37  */
  38
  39 #include <linux/interrupt.h>
  40 #include <linux/types.h>
  41 #include <linux/pci.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/if_ether.h>
  44
  45 #include <rdma/ib_verbs.h>
  46 #include <rdma/ib_user_verbs.h>
  47 #include <rdma/ib_umem.h>
  48 #include <rdma/ib_addr.h>
  49 #include <rdma/ib_mad.h>
  50 #include <rdma/ib_cache.h>
  51 #include <rdma/uverbs_ioctl.h>
  52
  53 #include "bnxt_ulp.h"
  54
  55 #include "roce_hsi.h"
  56 #include "qplib_res.h"
  57 #include "qplib_sp.h"
  58 #include "qplib_fp.h"
  59 #include "qplib_rcfw.h"
  60
  61 #include "bnxt_re.h"
  62 #include "ib_verbs.h"
  63 #include <rdma/bnxt_re-abi.h>
  64
  65 static int __from_ib_access_flags(int iflags)
  66 {
  67         int qflags = 0;
  68
  69         if (iflags & IB_ACCESS_LOCAL_WRITE)
  70                 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
  71         if (iflags & IB_ACCESS_REMOTE_READ)
  72                 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
  73         if (iflags & IB_ACCESS_REMOTE_WRITE)
  74                 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
  75         if (iflags & IB_ACCESS_REMOTE_ATOMIC)
  76                 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
  77         if (iflags & IB_ACCESS_MW_BIND)
  78                 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
  79         if (iflags & IB_ZERO_BASED)
  80                 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
  81         if (iflags & IB_ACCESS_ON_DEMAND)
  82                 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
  83         return qflags;
  84 };
  85
  86 static enum ib_access_flags __to_ib_access_flags(int qflags)
  87 {
  88         enum ib_access_flags iflags = 0;
  89
  90         if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
  91                 iflags |= IB_ACCESS_LOCAL_WRITE;
  92         if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
  93                 iflags |= IB_ACCESS_REMOTE_WRITE;
  94         if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
  95                 iflags |= IB_ACCESS_REMOTE_READ;
  96         if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
  97                 iflags |= IB_ACCESS_REMOTE_ATOMIC;
  98         if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
  99                 iflags |= IB_ACCESS_MW_BIND;
 100         if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
 101                 iflags |= IB_ZERO_BASED;
 102         if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
 103                 iflags |= IB_ACCESS_ON_DEMAND;
 104         return iflags;
 105 };
 106
 107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
 108                              struct bnxt_qplib_sge *sg_list, int num)
 109 {
 110         int i, total = 0;
 111
 112         for (i = 0; i < num; i++) {
 113                 sg_list[i].addr = ib_sg_list[i].addr;
 114                 sg_list[i].lkey = ib_sg_list[i].lkey;
 115                 sg_list[i].size = ib_sg_list[i].length;
 116                 total += sg_list[i].size;
 117         }
 118         return total;
 119 }
 120
 121 /* Device */
 122 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num)
 123 {
 124         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 125         struct net_device *netdev = NULL;
 126
 127         rcu_read_lock();
 128         if (rdev)
 129                 netdev = rdev->netdev;
 130         if (netdev)
 131                 dev_hold(netdev);
 132
 133         rcu_read_unlock();
 134         return netdev;
 135 }
 136
 137 int bnxt_re_query_device(struct ib_device *ibdev,
 138                          struct ib_device_attr *ib_attr,
 139                          struct ib_udata *udata)
 140 {
 141         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 142         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
 143
 144         memset(ib_attr, 0, sizeof(*ib_attr));
 145         memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
 146                min(sizeof(dev_attr->fw_ver),
 147                    sizeof(ib_attr->fw_ver)));
 148         bnxt_qplib_get_guid(rdev->netdev->dev_addr,
 149                             (u8 *)&ib_attr->sys_image_guid);
 150         ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
 151         ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M;
 152
 153         ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
 154         ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
 155         ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
 156         ib_attr->max_qp = dev_attr->max_qp;
 157         ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
 158         ib_attr->device_cap_flags =
 159                                     IB_DEVICE_CURR_QP_STATE_MOD
 160                                     | IB_DEVICE_RC_RNR_NAK_GEN
 161                                     | IB_DEVICE_SHUTDOWN_PORT
 162                                     | IB_DEVICE_SYS_IMAGE_GUID
 163                                     | IB_DEVICE_LOCAL_DMA_LKEY
 164                                     | IB_DEVICE_RESIZE_MAX_WR
 165                                     | IB_DEVICE_PORT_ACTIVE_EVENT
 166                                     | IB_DEVICE_N_NOTIFY_CQ
 167                                     | IB_DEVICE_MEM_WINDOW
 168                                     | IB_DEVICE_MEM_WINDOW_TYPE_2B
 169                                     | IB_DEVICE_MEM_MGT_EXTENSIONS;
 170         ib_attr->max_send_sge = dev_attr->max_qp_sges;
 171         ib_attr->max_recv_sge = dev_attr->max_qp_sges;
 172         ib_attr->max_sge_rd = dev_attr->max_qp_sges;
 173         ib_attr->max_cq = dev_attr->max_cq;
 174         ib_attr->max_cqe = dev_attr->max_cq_wqes;
 175         ib_attr->max_mr = dev_attr->max_mr;
 176         ib_attr->max_pd = dev_attr->max_pd;
 177         ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
 178         ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
 179         ib_attr->atomic_cap = IB_ATOMIC_NONE;
 180         ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
 181
 182         ib_attr->max_ee_rd_atom = 0;
 183         ib_attr->max_res_rd_atom = 0;
 184         ib_attr->max_ee_init_rd_atom = 0;
 185         ib_attr->max_ee = 0;
 186         ib_attr->max_rdd = 0;
 187         ib_attr->max_mw = dev_attr->max_mw;
 188         ib_attr->max_raw_ipv6_qp = 0;
 189         ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
 190         ib_attr->max_mcast_grp = 0;
 191         ib_attr->max_mcast_qp_attach = 0;
 192         ib_attr->max_total_mcast_qp_attach = 0;
 193         ib_attr->max_ah = dev_attr->max_ah;
 194
 195         ib_attr->max_fmr = 0;
 196         ib_attr->max_map_per_fmr = 0;
 197
 198         ib_attr->max_srq = dev_attr->max_srq;
 199         ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
 200         ib_attr->max_srq_sge = dev_attr->max_srq_sges;
 201
 202         ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
 203
 204         ib_attr->max_pkeys = 1;
 205         ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
 206         return 0;
 207 }
 208
 209 int bnxt_re_modify_device(struct ib_device *ibdev,
 210                           int device_modify_mask,
 211                           struct ib_device_modify *device_modify)
 212 {
 213         switch (device_modify_mask) {
 214         case IB_DEVICE_MODIFY_SYS_IMAGE_GUID:
 215                 /* Modify the GUID requires the modification of the GID table */
 216                 /* GUID should be made as READ-ONLY */
 217                 break;
 218         case IB_DEVICE_MODIFY_NODE_DESC:
 219                 /* Node Desc should be made as READ-ONLY */
 220                 break;
 221         default:
 222                 break;
 223         }
 224         return 0;
 225 }
 226
 227 /* Port */
 228 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
 229                        struct ib_port_attr *port_attr)
 230 {
 231         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 232         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
 233
 234         memset(port_attr, 0, sizeof(*port_attr));
 235
 236         if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
 237                 port_attr->state = IB_PORT_ACTIVE;
 238                 port_attr->phys_state = 5;
 239         } else {
 240                 port_attr->state = IB_PORT_DOWN;
 241                 port_attr->phys_state = 3;
 242         }
 243         port_attr->max_mtu = IB_MTU_4096;
 244         port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
 245         port_attr->gid_tbl_len = dev_attr->max_sgid;
 246         port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 247                                     IB_PORT_DEVICE_MGMT_SUP |
 248                                     IB_PORT_VENDOR_CLASS_SUP;
 249         port_attr->ip_gids = true;
 250
 251         port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
 252         port_attr->bad_pkey_cntr = 0;
 253         port_attr->qkey_viol_cntr = 0;
 254         port_attr->pkey_tbl_len = dev_attr->max_pkey;
 255         port_attr->lid = 0;
 256         port_attr->sm_lid = 0;
 257         port_attr->lmc = 0;
 258         port_attr->max_vl_num = 4;
 259         port_attr->sm_sl = 0;
 260         port_attr->subnet_timeout = 0;
 261         port_attr->init_type_reply = 0;
 262         port_attr->active_speed = rdev->active_speed;
 263         port_attr->active_width = rdev->active_width;
 264
 265         return 0;
 266 }
 267
 268 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
 269                                struct ib_port_immutable *immutable)
 270 {
 271         struct ib_port_attr port_attr;
 272
 273         if (bnxt_re_query_port(ibdev, port_num, &port_attr))
 274                 return -EINVAL;
 275
 276         immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
 277         immutable->gid_tbl_len = port_attr.gid_tbl_len;
 278         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 279         immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
 280         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 281         return 0;
 282 }
 283
 284 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
 285 {
 286         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 287
 288         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
 289                  rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
 290                  rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
 291 }
 292
 293 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
 294                        u16 index, u16 *pkey)
 295 {
 296         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 297
 298         /* Ignore port_num */
 299
 300         memset(pkey, 0, sizeof(*pkey));
 301         return bnxt_qplib_get_pkey(&rdev->qplib_res,
 302                                    &rdev->qplib_res.pkey_tbl, index, pkey);
 303 }
 304
 305 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
 306                       int index, union ib_gid *gid)
 307 {
 308         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 309         int rc = 0;
 310
 311         /* Ignore port_num */
 312         memset(gid, 0, sizeof(*gid));
 313         rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
 314                                  &rdev->qplib_res.sgid_tbl, index,
 315                                  (struct bnxt_qplib_gid *)gid);
 316         return rc;
 317 }
 318
 319 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
 320 {
 321         int rc = 0;
 322         struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
 323         struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
 324         struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
 325         struct bnxt_qplib_gid *gid_to_del;
 326
 327         /* Delete the entry from the hardware */
 328         ctx = *context;
 329         if (!ctx)
 330                 return -EINVAL;
 331
 332         if (sgid_tbl && sgid_tbl->active) {
 333                 if (ctx->idx >= sgid_tbl->max)
 334                         return -EINVAL;
 335                 gid_to_del = &sgid_tbl->tbl[ctx->idx];
 336                 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
 337                  * or via the ib_unregister_device path. In the former case QP1
 338                  * may not be destroyed yet, in which case just return as FW
 339                  * needs that entry to be present and will fail it's deletion.
 340                  * We could get invoked again after QP1 is destroyed OR get an
 341                  * ADD_GID call with a different GID value for the same index
 342                  * where we issue MODIFY_GID cmd to update the GID entry -- TBD
 343                  */
 344                 if (ctx->idx == 0 &&
 345                     rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
 346                     ctx->refcnt == 1 && rdev->qp1_sqp) {
 347                         dev_dbg(rdev_to_dev(rdev),
 348                                 "Trying to delete GID0 while QP1 is alive\n");
 349                         return -EFAULT;
 350                 }
 351                 ctx->refcnt--;
 352                 if (!ctx->refcnt) {
 353                         rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true);
 354                         if (rc) {
 355                                 dev_err(rdev_to_dev(rdev),
 356                                         "Failed to remove GID: %#x", rc);
 357                         } else {
 358                                 ctx_tbl = sgid_tbl->ctx;
 359                                 ctx_tbl[ctx->idx] = NULL;
 360                                 kfree(ctx);
 361                         }
 362                 }
 363         } else {
 364                 return -EINVAL;
 365         }
 366         return rc;
 367 }
 368
 369 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
 370 {
 371         int rc;
 372         u32 tbl_idx = 0;
 373         u16 vlan_id = 0xFFFF;
 374         struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
 375         struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
 376         struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
 377
 378         if ((attr->ndev) && is_vlan_dev(attr->ndev))
 379                 vlan_id = vlan_dev_vlan_id(attr->ndev);
 380
 381         rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
 382                                  rdev->qplib_res.netdev->dev_addr,
 383                                  vlan_id, true, &tbl_idx);
 384         if (rc == -EALREADY) {
 385                 ctx_tbl = sgid_tbl->ctx;
 386                 ctx_tbl[tbl_idx]->refcnt++;
 387                 *context = ctx_tbl[tbl_idx];
 388                 return 0;
 389         }
 390
 391         if (rc < 0) {
 392                 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc);
 393                 return rc;
 394         }
 395
 396         ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
 397         if (!ctx)
 398                 return -ENOMEM;
 399         ctx_tbl = sgid_tbl->ctx;
 400         ctx->idx = tbl_idx;
 401         ctx->refcnt = 1;
 402         ctx_tbl[tbl_idx] = ctx;
 403         *context = ctx;
 404
 405         return rc;
 406 }
 407
 408 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
 409                                             u8 port_num)
 410 {
 411         return IB_LINK_LAYER_ETHERNET;
 412 }
 413
 414 #define BNXT_RE_FENCE_PBL_SIZE  DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
 415
 416 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
 417 {
 418         struct bnxt_re_fence_data *fence = &pd->fence;
 419         struct ib_mr *ib_mr = &fence->mr->ib_mr;
 420         struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
 421
 422         memset(wqe, 0, sizeof(*wqe));
 423         wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
 424         wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
 425         wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
 426         wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
 427         wqe->bind.zero_based = false;
 428         wqe->bind.parent_l_key = ib_mr->lkey;
 429         wqe->bind.va = (u64)(unsigned long)fence->va;
 430         wqe->bind.length = fence->size;
 431         wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
 432         wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
 433
 434         /* Save the initial rkey in fence structure for now;
 435          * wqe->bind.r_key will be set at (re)bind time.
 436          */
 437         fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
 438 }
 439
 440 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
 441 {
 442         struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
 443                                              qplib_qp);
 444         struct ib_pd *ib_pd = qp->ib_qp.pd;
 445         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 446         struct bnxt_re_fence_data *fence = &pd->fence;
 447         struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
 448         struct bnxt_qplib_swqe wqe;
 449         int rc;
 450
 451         memcpy(&wqe, fence_wqe, sizeof(wqe));
 452         wqe.bind.r_key = fence->bind_rkey;
 453         fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
 454
 455         dev_dbg(rdev_to_dev(qp->rdev),
 456                 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
 457                 wqe.bind.r_key, qp->qplib_qp.id, pd);
 458         rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
 459         if (rc) {
 460                 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n");
 461                 return rc;
 462         }
 463         bnxt_qplib_post_send_db(&qp->qplib_qp);
 464
 465         return rc;
 466 }
 467
 468 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
 469 {
 470         struct bnxt_re_fence_data *fence = &pd->fence;
 471         struct bnxt_re_dev *rdev = pd->rdev;
 472         struct device *dev = &rdev->en_dev->pdev->dev;
 473         struct bnxt_re_mr *mr = fence->mr;
 474
 475         if (fence->mw) {
 476                 bnxt_re_dealloc_mw(fence->mw);
 477                 fence->mw = NULL;
 478         }
 479         if (mr) {
 480                 if (mr->ib_mr.rkey)
 481                         bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
 482                                              true);
 483                 if (mr->ib_mr.lkey)
 484                         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
 485                 kfree(mr);
 486                 fence->mr = NULL;
 487         }
 488         if (fence->dma_addr) {
 489                 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
 490                                  DMA_BIDIRECTIONAL);
 491                 fence->dma_addr = 0;
 492         }
 493 }
 494
 495 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
 496 {
 497         int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
 498         struct bnxt_re_fence_data *fence = &pd->fence;
 499         struct bnxt_re_dev *rdev = pd->rdev;
 500         struct device *dev = &rdev->en_dev->pdev->dev;
 501         struct bnxt_re_mr *mr = NULL;
 502         dma_addr_t dma_addr = 0;
 503         struct ib_mw *mw;
 504         u64 pbl_tbl;
 505         int rc;
 506
 507         dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
 508                                   DMA_BIDIRECTIONAL);
 509         rc = dma_mapping_error(dev, dma_addr);
 510         if (rc) {
 511                 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n");
 512                 rc = -EIO;
 513                 fence->dma_addr = 0;
 514                 goto fail;
 515         }
 516         fence->dma_addr = dma_addr;
 517
 518         /* Allocate a MR */
 519         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
 520         if (!mr) {
 521                 rc = -ENOMEM;
 522                 goto fail;
 523         }
 524         fence->mr = mr;
 525         mr->rdev = rdev;
 526         mr->qplib_mr.pd = &pd->qplib_pd;
 527         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
 528         mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
 529         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
 530         if (rc) {
 531                 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n");
 532                 goto fail;
 533         }
 534
 535         /* Register MR */
 536         mr->ib_mr.lkey = mr->qplib_mr.lkey;
 537         mr->qplib_mr.va = (u64)(unsigned long)fence->va;
 538         mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
 539         pbl_tbl = dma_addr;
 540         rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
 541                                BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE);
 542         if (rc) {
 543                 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n");
 544                 goto fail;
 545         }
 546         mr->ib_mr.rkey = mr->qplib_mr.rkey;
 547
 548         /* Create a fence MW only for kernel consumers */
 549         mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
 550         if (IS_ERR(mw)) {
 551                 dev_err(rdev_to_dev(rdev),
 552                         "Failed to create fence-MW for PD: %p\n", pd);
 553                 rc = PTR_ERR(mw);
 554                 goto fail;
 555         }
 556         fence->mw = mw;
 557
 558         bnxt_re_create_fence_wqe(pd);
 559         return 0;
 560
 561 fail:
 562         bnxt_re_destroy_fence_mr(pd);
 563         return rc;
 564 }
 565
 566 /* Protection Domains */
 567 void bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
 568 {
 569         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 570         struct bnxt_re_dev *rdev = pd->rdev;
 571
 572         bnxt_re_destroy_fence_mr(pd);
 573
 574         if (pd->qplib_pd.id)
 575                 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
 576                                       &pd->qplib_pd);
 577 }
 578
 579 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
 580 {
 581         struct ib_device *ibdev = ibpd->device;
 582         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 583         struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
 584                 udata, struct bnxt_re_ucontext, ib_uctx);
 585         struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
 586         int rc;
 587
 588         pd->rdev = rdev;
 589         if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
 590                 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD");
 591                 rc = -ENOMEM;
 592                 goto fail;
 593         }
 594
 595         if (udata) {
 596                 struct bnxt_re_pd_resp resp;
 597
 598                 if (!ucntx->dpi.dbr) {
 599                         /* Allocate DPI in alloc_pd to avoid failing of
 600                          * ibv_devinfo and family of application when DPIs
 601                          * are depleted.
 602                          */
 603                         if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
 604                                                  &ucntx->dpi, ucntx)) {
 605                                 rc = -ENOMEM;
 606                                 goto dbfail;
 607                         }
 608                 }
 609
 610                 resp.pdid = pd->qplib_pd.id;
 611                 /* Still allow mapping this DBR to the new user PD. */
 612                 resp.dpi = ucntx->dpi.dpi;
 613                 resp.dbr = (u64)ucntx->dpi.umdbr;
 614
 615                 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
 616                 if (rc) {
 617                         dev_err(rdev_to_dev(rdev),
 618                                 "Failed to copy user response\n");
 619                         goto dbfail;
 620                 }
 621         }
 622
 623         if (!udata)
 624                 if (bnxt_re_create_fence_mr(pd))
 625                         dev_warn(rdev_to_dev(rdev),
 626                                  "Failed to create Fence-MR\n");
 627         return 0;
 628 dbfail:
 629         bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
 630                               &pd->qplib_pd);
 631 fail:
 632         return rc;
 633 }
 634
 635 /* Address Handles */
 636 void bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
 637 {
 638         struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 639         struct bnxt_re_dev *rdev = ah->rdev;
 640
 641         bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah,
 642                               !(flags & RDMA_DESTROY_AH_SLEEPABLE));
 643 }
 644
 645 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
 646 {
 647         u8 nw_type;
 648
 649         switch (ntype) {
 650         case RDMA_NETWORK_IPV4:
 651                 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
 652                 break;
 653         case RDMA_NETWORK_IPV6:
 654                 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
 655                 break;
 656         default:
 657                 nw_type = CMDQ_CREATE_AH_TYPE_V1;
 658                 break;
 659         }
 660         return nw_type;
 661 }
 662
 663 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr,
 664                       u32 flags, struct ib_udata *udata)
 665 {
 666         struct ib_pd *ib_pd = ib_ah->pd;
 667         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 668         const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
 669         struct bnxt_re_dev *rdev = pd->rdev;
 670         const struct ib_gid_attr *sgid_attr;
 671         struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 672         u8 nw_type;
 673         int rc;
 674
 675         if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
 676                 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
 677                 return -EINVAL;
 678         }
 679
 680         ah->rdev = rdev;
 681         ah->qplib_ah.pd = &pd->qplib_pd;
 682
 683         /* Supply the configuration for the HW */
 684         memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
 685                sizeof(union ib_gid));
 686         /*
 687          * If RoCE V2 is enabled, stack will have two entries for
 688          * each GID entry. Avoiding this duplicte entry in HW. Dividing
 689          * the GID index by 2 for RoCE V2
 690          */
 691         ah->qplib_ah.sgid_index = grh->sgid_index / 2;
 692         ah->qplib_ah.host_sgid_index = grh->sgid_index;
 693         ah->qplib_ah.traffic_class = grh->traffic_class;
 694         ah->qplib_ah.flow_label = grh->flow_label;
 695         ah->qplib_ah.hop_limit = grh->hop_limit;
 696         ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
 697
 698         sgid_attr = grh->sgid_attr;
 699         /* Get network header type for this GID */
 700         nw_type = rdma_gid_attr_network_type(sgid_attr);
 701         ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
 702
 703         memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
 704         rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
 705                                   !(flags & RDMA_CREATE_AH_SLEEPABLE));
 706         if (rc) {
 707                 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH");
 708                 return rc;
 709         }
 710
 711         /* Write AVID to shared page. */
 712         if (udata) {
 713                 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
 714                         udata, struct bnxt_re_ucontext, ib_uctx);
 715                 unsigned long flag;
 716                 u32 *wrptr;
 717
 718                 spin_lock_irqsave(&uctx->sh_lock, flag);
 719                 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
 720                 *wrptr = ah->qplib_ah.id;
 721                 wmb(); /* make sure cache is updated. */
 722                 spin_unlock_irqrestore(&uctx->sh_lock, flag);
 723         }
 724
 725         return 0;
 726 }
 727
 728 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
 729 {
 730         return 0;
 731 }
 732
 733 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
 734 {
 735         struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 736
 737         ah_attr->type = ib_ah->type;
 738         rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
 739         memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
 740         rdma_ah_set_grh(ah_attr, NULL, 0,
 741                         ah->qplib_ah.host_sgid_index,
 742                         0, ah->qplib_ah.traffic_class);
 743         rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
 744         rdma_ah_set_port_num(ah_attr, 1);
 745         rdma_ah_set_static_rate(ah_attr, 0);
 746         return 0;
 747 }
 748
 749 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
 750         __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
 751 {
 752         unsigned long flags;
 753
 754         spin_lock_irqsave(&qp->scq->cq_lock, flags);
 755         if (qp->rcq != qp->scq)
 756                 spin_lock(&qp->rcq->cq_lock);
 757         else
 758                 __acquire(&qp->rcq->cq_lock);
 759
 760         return flags;
 761 }
 762
 763 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
 764                         unsigned long flags)
 765         __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
 766 {
 767         if (qp->rcq != qp->scq)
 768                 spin_unlock(&qp->rcq->cq_lock);
 769         else
 770                 __release(&qp->rcq->cq_lock);
 771         spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
 772 }
 773
 774 /* Queue Pairs */
 775 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
 776 {
 777         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
 778         struct bnxt_re_dev *rdev = qp->rdev;
 779         unsigned int flags;
 780         int rc;
 781
 782         bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
 783         rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
 784         if (rc) {
 785                 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
 786                 return rc;
 787         }
 788
 789         if (rdma_is_kernel_res(&qp->ib_qp.res)) {
 790                 flags = bnxt_re_lock_cqs(qp);
 791                 bnxt_qplib_clean_qp(&qp->qplib_qp);
 792                 bnxt_re_unlock_cqs(qp, flags);
 793         }
 794
 795         bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
 796
 797         if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
 798                 bnxt_qplib_destroy_ah(&rdev->qplib_res, &rdev->sqp_ah->qplib_ah,
 799                                       false);
 800
 801                 bnxt_qplib_clean_qp(&qp->qplib_qp);
 802                 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
 803                                            &rdev->qp1_sqp->qplib_qp);
 804                 if (rc) {
 805                         dev_err(rdev_to_dev(rdev),
 806                                 "Failed to destroy Shadow QP");
 807                         return rc;
 808                 }
 809                 bnxt_qplib_free_qp_res(&rdev->qplib_res,
 810                                        &rdev->qp1_sqp->qplib_qp);
 811                 mutex_lock(&rdev->qp_lock);
 812                 list_del(&rdev->qp1_sqp->list);
 813                 atomic_dec(&rdev->qp_count);
 814                 mutex_unlock(&rdev->qp_lock);
 815
 816                 kfree(rdev->sqp_ah);
 817                 kfree(rdev->qp1_sqp);
 818                 rdev->qp1_sqp = NULL;
 819                 rdev->sqp_ah = NULL;
 820         }
 821
 822         if (!IS_ERR_OR_NULL(qp->rumem))
 823                 ib_umem_release(qp->rumem);
 824         if (!IS_ERR_OR_NULL(qp->sumem))
 825                 ib_umem_release(qp->sumem);
 826
 827         mutex_lock(&rdev->qp_lock);
 828         list_del(&qp->list);
 829         atomic_dec(&rdev->qp_count);
 830         mutex_unlock(&rdev->qp_lock);
 831         kfree(qp);
 832         return 0;
 833 }
 834
 835 static u8 __from_ib_qp_type(enum ib_qp_type type)
 836 {
 837         switch (type) {
 838         case IB_QPT_GSI:
 839                 return CMDQ_CREATE_QP1_TYPE_GSI;
 840         case IB_QPT_RC:
 841                 return CMDQ_CREATE_QP_TYPE_RC;
 842         case IB_QPT_UD:
 843                 return CMDQ_CREATE_QP_TYPE_UD;
 844         default:
 845                 return IB_QPT_MAX;
 846         }
 847 }
 848
 849 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
 850                                 struct bnxt_re_qp *qp, struct ib_udata *udata)
 851 {
 852         struct bnxt_re_qp_req ureq;
 853         struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
 854         struct ib_umem *umem;
 855         int bytes = 0, psn_sz;
 856         struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
 857                 udata, struct bnxt_re_ucontext, ib_uctx);
 858
 859         if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
 860                 return -EFAULT;
 861
 862         bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
 863         /* Consider mapping PSN search memory only for RC QPs. */
 864         if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
 865                 psn_sz = bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx) ?
 866                                         sizeof(struct sq_psn_search_ext) :
 867                                         sizeof(struct sq_psn_search);
 868                 bytes += (qplib_qp->sq.max_wqe * psn_sz);
 869         }
 870         bytes = PAGE_ALIGN(bytes);
 871         umem = ib_umem_get(udata, ureq.qpsva, bytes, IB_ACCESS_LOCAL_WRITE, 1);
 872         if (IS_ERR(umem))
 873                 return PTR_ERR(umem);
 874
 875         qp->sumem = umem;
 876         qplib_qp->sq.sg_info.sglist = umem->sg_head.sgl;
 877         qplib_qp->sq.sg_info.npages = ib_umem_num_pages(umem);
 878         qplib_qp->sq.sg_info.nmap = umem->nmap;
 879         qplib_qp->qp_handle = ureq.qp_handle;
 880
 881         if (!qp->qplib_qp.srq) {
 882                 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
 883                 bytes = PAGE_ALIGN(bytes);
 884                 umem = ib_umem_get(udata, ureq.qprva, bytes,
 885                                    IB_ACCESS_LOCAL_WRITE, 1);
 886                 if (IS_ERR(umem))
 887                         goto rqfail;
 888                 qp->rumem = umem;
 889                 qplib_qp->rq.sg_info.sglist = umem->sg_head.sgl;
 890                 qplib_qp->rq.sg_info.npages = ib_umem_num_pages(umem);
 891                 qplib_qp->rq.sg_info.nmap = umem->nmap;
 892         }
 893
 894         qplib_qp->dpi = &cntx->dpi;
 895         return 0;
 896 rqfail:
 897         ib_umem_release(qp->sumem);
 898         qp->sumem = NULL;
 899         memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
 900
 901         return PTR_ERR(umem);
 902 }
 903
 904 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
 905                                 (struct bnxt_re_pd *pd,
 906                                  struct bnxt_qplib_res *qp1_res,
 907                                  struct bnxt_qplib_qp *qp1_qp)
 908 {
 909         struct bnxt_re_dev *rdev = pd->rdev;
 910         struct bnxt_re_ah *ah;
 911         union ib_gid sgid;
 912         int rc;
 913
 914         ah = kzalloc(sizeof(*ah), GFP_KERNEL);
 915         if (!ah)
 916                 return NULL;
 917
 918         ah->rdev = rdev;
 919         ah->qplib_ah.pd = &pd->qplib_pd;
 920
 921         rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
 922         if (rc)
 923                 goto fail;
 924
 925         /* supply the dgid data same as sgid */
 926         memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
 927                sizeof(union ib_gid));
 928         ah->qplib_ah.sgid_index = 0;
 929
 930         ah->qplib_ah.traffic_class = 0;
 931         ah->qplib_ah.flow_label = 0;
 932         ah->qplib_ah.hop_limit = 1;
 933         ah->qplib_ah.sl = 0;
 934         /* Have DMAC same as SMAC */
 935         ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
 936
 937         rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
 938         if (rc) {
 939                 dev_err(rdev_to_dev(rdev),
 940                         "Failed to allocate HW AH for Shadow QP");
 941                 goto fail;
 942         }
 943
 944         return ah;
 945
 946 fail:
 947         kfree(ah);
 948         return NULL;
 949 }
 950
 951 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
 952                                 (struct bnxt_re_pd *pd,
 953                                  struct bnxt_qplib_res *qp1_res,
 954                                  struct bnxt_qplib_qp *qp1_qp)
 955 {
 956         struct bnxt_re_dev *rdev = pd->rdev;
 957         struct bnxt_re_qp *qp;
 958         int rc;
 959
 960         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
 961         if (!qp)
 962                 return NULL;
 963
 964         qp->rdev = rdev;
 965
 966         /* Initialize the shadow QP structure from the QP1 values */
 967         ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
 968
 969         qp->qplib_qp.pd = &pd->qplib_pd;
 970         qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
 971         qp->qplib_qp.type = IB_QPT_UD;
 972
 973         qp->qplib_qp.max_inline_data = 0;
 974         qp->qplib_qp.sig_type = true;
 975
 976         /* Shadow QP SQ depth should be same as QP1 RQ depth */
 977         qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
 978         qp->qplib_qp.sq.max_sge = 2;
 979         /* Q full delta can be 1 since it is internal QP */
 980         qp->qplib_qp.sq.q_full_delta = 1;
 981
 982         qp->qplib_qp.scq = qp1_qp->scq;
 983         qp->qplib_qp.rcq = qp1_qp->rcq;
 984
 985         qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
 986         qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
 987         /* Q full delta can be 1 since it is internal QP */
 988         qp->qplib_qp.rq.q_full_delta = 1;
 989
 990         qp->qplib_qp.mtu = qp1_qp->mtu;
 991
 992         qp->qplib_qp.sq_hdr_buf_size = 0;
 993         qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
 994         qp->qplib_qp.dpi = &rdev->dpi_privileged;
 995
 996         rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
 997         if (rc)
 998                 goto fail;
 999
1000         rdev->sqp_id = qp->qplib_qp.id;
1001
1002         spin_lock_init(&qp->sq_lock);
1003         INIT_LIST_HEAD(&qp->list);
1004         mutex_lock(&rdev->qp_lock);
1005         list_add_tail(&qp->list, &rdev->qp_list);
1006         atomic_inc(&rdev->qp_count);
1007         mutex_unlock(&rdev->qp_lock);
1008         return qp;
1009 fail:
1010         kfree(qp);
1011         return NULL;
1012 }
1013
1014 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1015                                 struct ib_qp_init_attr *qp_init_attr,
1016                                 struct ib_udata *udata)
1017 {
1018         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1019         struct bnxt_re_dev *rdev = pd->rdev;
1020         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1021         struct bnxt_re_qp *qp;
1022         struct bnxt_re_cq *cq;
1023         struct bnxt_re_srq *srq;
1024         int rc, entries;
1025
1026         if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) ||
1027             (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) ||
1028             (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) ||
1029             (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) ||
1030             (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data))
1031                 return ERR_PTR(-EINVAL);
1032
1033         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1034         if (!qp)
1035                 return ERR_PTR(-ENOMEM);
1036
1037         qp->rdev = rdev;
1038         ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1039         qp->qplib_qp.pd = &pd->qplib_pd;
1040         qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1041         qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
1042
1043         if (qp_init_attr->qp_type == IB_QPT_GSI &&
1044             bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx))
1045                 qp->qplib_qp.type = CMDQ_CREATE_QP_TYPE_GSI;
1046         if (qp->qplib_qp.type == IB_QPT_MAX) {
1047                 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
1048                         qp->qplib_qp.type);
1049                 rc = -EINVAL;
1050                 goto fail;
1051         }
1052
1053         qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
1054         qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
1055                                   IB_SIGNAL_ALL_WR) ? true : false);
1056
1057         qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
1058         if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1059                 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1060
1061         if (qp_init_attr->send_cq) {
1062                 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq,
1063                                   ib_cq);
1064                 if (!cq) {
1065                         dev_err(rdev_to_dev(rdev), "Send CQ not found");
1066                         rc = -EINVAL;
1067                         goto fail;
1068                 }
1069                 qp->qplib_qp.scq = &cq->qplib_cq;
1070                 qp->scq = cq;
1071         }
1072
1073         if (qp_init_attr->recv_cq) {
1074                 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq,
1075                                   ib_cq);
1076                 if (!cq) {
1077                         dev_err(rdev_to_dev(rdev), "Receive CQ not found");
1078                         rc = -EINVAL;
1079                         goto fail;
1080                 }
1081                 qp->qplib_qp.rcq = &cq->qplib_cq;
1082                 qp->rcq = cq;
1083         }
1084
1085         if (qp_init_attr->srq) {
1086                 srq = container_of(qp_init_attr->srq, struct bnxt_re_srq,
1087                                    ib_srq);
1088                 if (!srq) {
1089                         dev_err(rdev_to_dev(rdev), "SRQ not found");
1090                         rc = -EINVAL;
1091                         goto fail;
1092                 }
1093                 qp->qplib_qp.srq = &srq->qplib_srq;
1094                 qp->qplib_qp.rq.max_wqe = 0;
1095         } else {
1096                 /* Allocate 1 more than what's provided so posting max doesn't
1097                  * mean empty
1098                  */
1099                 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1);
1100                 qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
1101                                                 dev_attr->max_qp_wqes + 1);
1102
1103                 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1104                                                 qp_init_attr->cap.max_recv_wr;
1105
1106                 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
1107                 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1108                         qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1109         }
1110
1111         qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1112
1113         if (qp_init_attr->qp_type == IB_QPT_GSI &&
1114             !(bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx))) {
1115                 /* Allocate 1 more than what's provided */
1116                 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
1117                 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1118                                                 dev_attr->max_qp_wqes + 1);
1119                 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1120                                                 qp_init_attr->cap.max_send_wr;
1121                 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1122                 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1123                         qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1124                 qp->qplib_qp.sq.max_sge++;
1125                 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1126                         qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1127
1128                 qp->qplib_qp.rq_hdr_buf_size =
1129                                         BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1130
1131                 qp->qplib_qp.sq_hdr_buf_size =
1132                                         BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1133                 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1134                 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp);
1135                 if (rc) {
1136                         dev_err(rdev_to_dev(rdev), "Failed to create HW QP1");
1137                         goto fail;
1138                 }
1139                 /* Create a shadow QP to handle the QP1 traffic */
1140                 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res,
1141                                                          &qp->qplib_qp);
1142                 if (!rdev->qp1_sqp) {
1143                         rc = -EINVAL;
1144                         dev_err(rdev_to_dev(rdev),
1145                                 "Failed to create Shadow QP for QP1");
1146                         goto qp_destroy;
1147                 }
1148                 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1149                                                            &qp->qplib_qp);
1150                 if (!rdev->sqp_ah) {
1151                         bnxt_qplib_destroy_qp(&rdev->qplib_res,
1152                                               &rdev->qp1_sqp->qplib_qp);
1153                         rc = -EINVAL;
1154                         dev_err(rdev_to_dev(rdev),
1155                                 "Failed to create AH entry for ShadowQP");
1156                         goto qp_destroy;
1157                 }
1158
1159         } else {
1160                 /* Allocate 128 + 1 more than what's provided */
1161                 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr +
1162                                              BNXT_QPLIB_RESERVED_QP_WRS + 1);
1163                 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1164                                                 dev_attr->max_qp_wqes +
1165                                                 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1166                 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
1167
1168                 /*
1169                  * Reserving one slot for Phantom WQE. Application can
1170                  * post one extra entry in this case. But allowing this to avoid
1171                  * unexpected Queue full condition
1172                  */
1173
1174                 qp->qplib_qp.sq.q_full_delta -= 1;
1175
1176                 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
1177                 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1178                 if (udata) {
1179                         rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1180                         if (rc)
1181                                 goto fail;
1182                 } else {
1183                         qp->qplib_qp.dpi = &rdev->dpi_privileged;
1184                 }
1185
1186                 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1187                 if (rc) {
1188                         dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
1189                         goto free_umem;
1190                 }
1191         }
1192
1193         qp->ib_qp.qp_num = qp->qplib_qp.id;
1194         spin_lock_init(&qp->sq_lock);
1195         spin_lock_init(&qp->rq_lock);
1196
1197         if (udata) {
1198                 struct bnxt_re_qp_resp resp;
1199
1200                 resp.qpid = qp->ib_qp.qp_num;
1201                 resp.rsvd = 0;
1202                 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1203                 if (rc) {
1204                         dev_err(rdev_to_dev(rdev), "Failed to copy QP udata");
1205                         goto qp_destroy;
1206                 }
1207         }
1208         INIT_LIST_HEAD(&qp->list);
1209         mutex_lock(&rdev->qp_lock);
1210         list_add_tail(&qp->list, &rdev->qp_list);
1211         atomic_inc(&rdev->qp_count);
1212         mutex_unlock(&rdev->qp_lock);
1213
1214         return &qp->ib_qp;
1215 qp_destroy:
1216         bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1217 free_umem:
1218         if (udata) {
1219                 if (qp->rumem)
1220                         ib_umem_release(qp->rumem);
1221                 if (qp->sumem)
1222                         ib_umem_release(qp->sumem);
1223         }
1224 fail:
1225         kfree(qp);
1226         return ERR_PTR(rc);
1227 }
1228
1229 static u8 __from_ib_qp_state(enum ib_qp_state state)
1230 {
1231         switch (state) {
1232         case IB_QPS_RESET:
1233                 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1234         case IB_QPS_INIT:
1235                 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1236         case IB_QPS_RTR:
1237                 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1238         case IB_QPS_RTS:
1239                 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1240         case IB_QPS_SQD:
1241                 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1242         case IB_QPS_SQE:
1243                 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1244         case IB_QPS_ERR:
1245         default:
1246                 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1247         }
1248 }
1249
1250 static enum ib_qp_state __to_ib_qp_state(u8 state)
1251 {
1252         switch (state) {
1253         case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1254                 return IB_QPS_RESET;
1255         case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1256                 return IB_QPS_INIT;
1257         case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1258                 return IB_QPS_RTR;
1259         case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1260                 return IB_QPS_RTS;
1261         case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1262                 return IB_QPS_SQD;
1263         case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1264                 return IB_QPS_SQE;
1265         case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1266         default:
1267                 return IB_QPS_ERR;
1268         }
1269 }
1270
1271 static u32 __from_ib_mtu(enum ib_mtu mtu)
1272 {
1273         switch (mtu) {
1274         case IB_MTU_256:
1275                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1276         case IB_MTU_512:
1277                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1278         case IB_MTU_1024:
1279                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1280         case IB_MTU_2048:
1281                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1282         case IB_MTU_4096:
1283                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1284         default:
1285                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1286         }
1287 }
1288
1289 static enum ib_mtu __to_ib_mtu(u32 mtu)
1290 {
1291         switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1292         case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1293                 return IB_MTU_256;
1294         case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1295                 return IB_MTU_512;
1296         case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1297                 return IB_MTU_1024;
1298         case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1299                 return IB_MTU_2048;
1300         case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1301                 return IB_MTU_4096;
1302         default:
1303                 return IB_MTU_2048;
1304         }
1305 }
1306
1307 /* Shared Receive Queues */
1308 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1309 {
1310         struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1311                                                ib_srq);
1312         struct bnxt_re_dev *rdev = srq->rdev;
1313         struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1314         struct bnxt_qplib_nq *nq = NULL;
1315         int rc;
1316
1317         if (qplib_srq->cq)
1318                 nq = qplib_srq->cq->nq;
1319         rc = bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1320         if (rc) {
1321                 dev_err(rdev_to_dev(rdev), "Destroy HW SRQ failed!");
1322                 return rc;
1323         }
1324
1325         if (srq->umem)
1326                 ib_umem_release(srq->umem);
1327         kfree(srq);
1328         atomic_dec(&rdev->srq_count);
1329         if (nq)
1330                 nq->budget--;
1331         return 0;
1332 }
1333
1334 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1335                                  struct bnxt_re_pd *pd,
1336                                  struct bnxt_re_srq *srq,
1337                                  struct ib_udata *udata)
1338 {
1339         struct bnxt_re_srq_req ureq;
1340         struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1341         struct ib_umem *umem;
1342         int bytes = 0;
1343         struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1344                 udata, struct bnxt_re_ucontext, ib_uctx);
1345
1346         if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1347                 return -EFAULT;
1348
1349         bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
1350         bytes = PAGE_ALIGN(bytes);
1351         umem = ib_umem_get(udata, ureq.srqva, bytes, IB_ACCESS_LOCAL_WRITE, 1);
1352         if (IS_ERR(umem))
1353                 return PTR_ERR(umem);
1354
1355         srq->umem = umem;
1356         qplib_srq->sg_info.sglist = umem->sg_head.sgl;
1357         qplib_srq->sg_info.npages = ib_umem_num_pages(umem);
1358         qplib_srq->sg_info.nmap = umem->nmap;
1359         qplib_srq->srq_handle = ureq.srq_handle;
1360         qplib_srq->dpi = &cntx->dpi;
1361
1362         return 0;
1363 }
1364
1365 struct ib_srq *bnxt_re_create_srq(struct ib_pd *ib_pd,
1366                                   struct ib_srq_init_attr *srq_init_attr,
1367                                   struct ib_udata *udata)
1368 {
1369         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1370         struct bnxt_re_dev *rdev = pd->rdev;
1371         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1372         struct bnxt_re_srq *srq;
1373         struct bnxt_qplib_nq *nq = NULL;
1374         int rc, entries;
1375
1376         if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1377                 dev_err(rdev_to_dev(rdev), "Create CQ failed - max exceeded");
1378                 rc = -EINVAL;
1379                 goto exit;
1380         }
1381
1382         if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1383                 rc = -EOPNOTSUPP;
1384                 goto exit;
1385         }
1386
1387         srq = kzalloc(sizeof(*srq), GFP_KERNEL);
1388         if (!srq) {
1389                 rc = -ENOMEM;
1390                 goto exit;
1391         }
1392         srq->rdev = rdev;
1393         srq->qplib_srq.pd = &pd->qplib_pd;
1394         srq->qplib_srq.dpi = &rdev->dpi_privileged;
1395         /* Allocate 1 more than what's provided so posting max doesn't
1396          * mean empty
1397          */
1398         entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1399         if (entries > dev_attr->max_srq_wqes + 1)
1400                 entries = dev_attr->max_srq_wqes + 1;
1401
1402         srq->qplib_srq.max_wqe = entries;
1403         srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1404         srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1405         srq->srq_limit = srq_init_attr->attr.srq_limit;
1406         srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1407         nq = &rdev->nq[0];
1408
1409         if (udata) {
1410                 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1411                 if (rc)
1412                         goto fail;
1413         }
1414
1415         rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1416         if (rc) {
1417                 dev_err(rdev_to_dev(rdev), "Create HW SRQ failed!");
1418                 goto fail;
1419         }
1420
1421         if (udata) {
1422                 struct bnxt_re_srq_resp resp;
1423
1424                 resp.srqid = srq->qplib_srq.id;
1425                 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1426                 if (rc) {
1427                         dev_err(rdev_to_dev(rdev), "SRQ copy to udata failed!");
1428                         bnxt_qplib_destroy_srq(&rdev->qplib_res,
1429                                                &srq->qplib_srq);
1430                         goto exit;
1431                 }
1432         }
1433         if (nq)
1434                 nq->budget++;
1435         atomic_inc(&rdev->srq_count);
1436
1437         return &srq->ib_srq;
1438
1439 fail:
1440         if (srq->umem)
1441                 ib_umem_release(srq->umem);
1442         kfree(srq);
1443 exit:
1444         return ERR_PTR(rc);
1445 }
1446
1447 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1448                        enum ib_srq_attr_mask srq_attr_mask,
1449                        struct ib_udata *udata)
1450 {
1451         struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1452                                                ib_srq);
1453         struct bnxt_re_dev *rdev = srq->rdev;
1454         int rc;
1455
1456         switch (srq_attr_mask) {
1457         case IB_SRQ_MAX_WR:
1458                 /* SRQ resize is not supported */
1459                 break;
1460         case IB_SRQ_LIMIT:
1461                 /* Change the SRQ threshold */
1462                 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1463                         return -EINVAL;
1464
1465                 srq->qplib_srq.threshold = srq_attr->srq_limit;
1466                 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1467                 if (rc) {
1468                         dev_err(rdev_to_dev(rdev), "Modify HW SRQ failed!");
1469                         return rc;
1470                 }
1471                 /* On success, update the shadow */
1472                 srq->srq_limit = srq_attr->srq_limit;
1473                 /* No need to Build and send response back to udata */
1474                 break;
1475         default:
1476                 dev_err(rdev_to_dev(rdev),
1477                         "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1478                 return -EINVAL;
1479         }
1480         return 0;
1481 }
1482
1483 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1484 {
1485         struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1486                                                ib_srq);
1487         struct bnxt_re_srq tsrq;
1488         struct bnxt_re_dev *rdev = srq->rdev;
1489         int rc;
1490
1491         /* Get live SRQ attr */
1492         tsrq.qplib_srq.id = srq->qplib_srq.id;
1493         rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1494         if (rc) {
1495                 dev_err(rdev_to_dev(rdev), "Query HW SRQ failed!");
1496                 return rc;
1497         }
1498         srq_attr->max_wr = srq->qplib_srq.max_wqe;
1499         srq_attr->max_sge = srq->qplib_srq.max_sge;
1500         srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1501
1502         return 0;
1503 }
1504
1505 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1506                           const struct ib_recv_wr **bad_wr)
1507 {
1508         struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1509                                                ib_srq);
1510         struct bnxt_qplib_swqe wqe;
1511         unsigned long flags;
1512         int rc = 0;
1513
1514         spin_lock_irqsave(&srq->lock, flags);
1515         while (wr) {
1516                 /* Transcribe each ib_recv_wr to qplib_swqe */
1517                 wqe.num_sge = wr->num_sge;
1518                 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1519                 wqe.wr_id = wr->wr_id;
1520                 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1521
1522                 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1523                 if (rc) {
1524                         *bad_wr = wr;
1525                         break;
1526                 }
1527                 wr = wr->next;
1528         }
1529         spin_unlock_irqrestore(&srq->lock, flags);
1530
1531         return rc;
1532 }
1533 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1534                                     struct bnxt_re_qp *qp1_qp,
1535                                     int qp_attr_mask)
1536 {
1537         struct bnxt_re_qp *qp = rdev->qp1_sqp;
1538         int rc = 0;
1539
1540         if (qp_attr_mask & IB_QP_STATE) {
1541                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1542                 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1543         }
1544         if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1545                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1546                 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1547         }
1548
1549         if (qp_attr_mask & IB_QP_QKEY) {
1550                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1551                 /* Using a Random  QKEY */
1552                 qp->qplib_qp.qkey = 0x81818181;
1553         }
1554         if (qp_attr_mask & IB_QP_SQ_PSN) {
1555                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1556                 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1557         }
1558
1559         rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1560         if (rc)
1561                 dev_err(rdev_to_dev(rdev),
1562                         "Failed to modify Shadow QP for QP1");
1563         return rc;
1564 }
1565
1566 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1567                       int qp_attr_mask, struct ib_udata *udata)
1568 {
1569         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1570         struct bnxt_re_dev *rdev = qp->rdev;
1571         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1572         enum ib_qp_state curr_qp_state, new_qp_state;
1573         int rc, entries;
1574         unsigned int flags;
1575         u8 nw_type;
1576
1577         qp->qplib_qp.modify_flags = 0;
1578         if (qp_attr_mask & IB_QP_STATE) {
1579                 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1580                 new_qp_state = qp_attr->qp_state;
1581                 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1582                                         ib_qp->qp_type, qp_attr_mask)) {
1583                         dev_err(rdev_to_dev(rdev),
1584                                 "Invalid attribute mask: %#x specified ",
1585                                 qp_attr_mask);
1586                         dev_err(rdev_to_dev(rdev),
1587                                 "for qpn: %#x type: %#x",
1588                                 ib_qp->qp_num, ib_qp->qp_type);
1589                         dev_err(rdev_to_dev(rdev),
1590                                 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1591                                 curr_qp_state, new_qp_state);
1592                         return -EINVAL;
1593                 }
1594                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1595                 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1596
1597                 if (!qp->sumem &&
1598                     qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1599                         dev_dbg(rdev_to_dev(rdev),
1600                                 "Move QP = %p to flush list\n",
1601                                 qp);
1602                         flags = bnxt_re_lock_cqs(qp);
1603                         bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1604                         bnxt_re_unlock_cqs(qp, flags);
1605                 }
1606                 if (!qp->sumem &&
1607                     qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1608                         dev_dbg(rdev_to_dev(rdev),
1609                                 "Move QP = %p out of flush list\n",
1610                                 qp);
1611                         flags = bnxt_re_lock_cqs(qp);
1612                         bnxt_qplib_clean_qp(&qp->qplib_qp);
1613                         bnxt_re_unlock_cqs(qp, flags);
1614                 }
1615         }
1616         if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1617                 qp->qplib_qp.modify_flags |=
1618                                 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1619                 qp->qplib_qp.en_sqd_async_notify = true;
1620         }
1621         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1622                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1623                 qp->qplib_qp.access =
1624                         __from_ib_access_flags(qp_attr->qp_access_flags);
1625                 /* LOCAL_WRITE access must be set to allow RC receive */
1626                 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1627                 /* Temp: Set all params on QP as of now */
1628                 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1629                 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1630         }
1631         if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1632                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1633                 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1634         }
1635         if (qp_attr_mask & IB_QP_QKEY) {
1636                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1637                 qp->qplib_qp.qkey = qp_attr->qkey;
1638         }
1639         if (qp_attr_mask & IB_QP_AV) {
1640                 const struct ib_global_route *grh =
1641                         rdma_ah_read_grh(&qp_attr->ah_attr);
1642                 const struct ib_gid_attr *sgid_attr;
1643
1644                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1645                                      CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1646                                      CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1647                                      CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1648                                      CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1649                                      CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1650                                      CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1651                 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1652                        sizeof(qp->qplib_qp.ah.dgid.data));
1653                 qp->qplib_qp.ah.flow_label = grh->flow_label;
1654                 /* If RoCE V2 is enabled, stack will have two entries for
1655                  * each GID entry. Avoiding this duplicte entry in HW. Dividing
1656                  * the GID index by 2 for RoCE V2
1657                  */
1658                 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2;
1659                 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1660                 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1661                 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1662                 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1663                 ether_addr_copy(qp->qplib_qp.ah.dmac,
1664                                 qp_attr->ah_attr.roce.dmac);
1665
1666                 sgid_attr = qp_attr->ah_attr.grh.sgid_attr;
1667                 memcpy(qp->qplib_qp.smac, sgid_attr->ndev->dev_addr,
1668                        ETH_ALEN);
1669                 nw_type = rdma_gid_attr_network_type(sgid_attr);
1670                 switch (nw_type) {
1671                 case RDMA_NETWORK_IPV4:
1672                         qp->qplib_qp.nw_type =
1673                                 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1674                         break;
1675                 case RDMA_NETWORK_IPV6:
1676                         qp->qplib_qp.nw_type =
1677                                 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1678                         break;
1679                 default:
1680                         qp->qplib_qp.nw_type =
1681                                 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1682                         break;
1683                 }
1684         }
1685
1686         if (qp_attr_mask & IB_QP_PATH_MTU) {
1687                 qp->qplib_qp.modify_flags |=
1688                                 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1689                 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1690                 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1691         } else if (qp_attr->qp_state == IB_QPS_RTR) {
1692                 qp->qplib_qp.modify_flags |=
1693                         CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1694                 qp->qplib_qp.path_mtu =
1695                         __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1696                 qp->qplib_qp.mtu =
1697                         ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1698         }
1699
1700         if (qp_attr_mask & IB_QP_TIMEOUT) {
1701                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1702                 qp->qplib_qp.timeout = qp_attr->timeout;
1703         }
1704         if (qp_attr_mask & IB_QP_RETRY_CNT) {
1705                 qp->qplib_qp.modify_flags |=
1706                                 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1707                 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1708         }
1709         if (qp_attr_mask & IB_QP_RNR_RETRY) {
1710                 qp->qplib_qp.modify_flags |=
1711                                 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1712                 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1713         }
1714         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1715                 qp->qplib_qp.modify_flags |=
1716                                 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1717                 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1718         }
1719         if (qp_attr_mask & IB_QP_RQ_PSN) {
1720                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1721                 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1722         }
1723         if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1724                 qp->qplib_qp.modify_flags |=
1725                                 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1726                 /* Cap the max_rd_atomic to device max */
1727                 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1728                                                    dev_attr->max_qp_rd_atom);
1729         }
1730         if (qp_attr_mask & IB_QP_SQ_PSN) {
1731                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1732                 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1733         }
1734         if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1735                 if (qp_attr->max_dest_rd_atomic >
1736                     dev_attr->max_qp_init_rd_atom) {
1737                         dev_err(rdev_to_dev(rdev),
1738                                 "max_dest_rd_atomic requested%d is > dev_max%d",
1739                                 qp_attr->max_dest_rd_atomic,
1740                                 dev_attr->max_qp_init_rd_atom);
1741                         return -EINVAL;
1742                 }
1743
1744                 qp->qplib_qp.modify_flags |=
1745                                 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1746                 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1747         }
1748         if (qp_attr_mask & IB_QP_CAP) {
1749                 qp->qplib_qp.modify_flags |=
1750                                 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1751                                 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1752                                 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
1753                                 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
1754                                 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
1755                 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
1756                     (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
1757                     (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
1758                     (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
1759                     (qp_attr->cap.max_inline_data >=
1760                                                 dev_attr->max_inline_data)) {
1761                         dev_err(rdev_to_dev(rdev),
1762                                 "Create QP failed - max exceeded");
1763                         return -EINVAL;
1764                 }
1765                 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1766                 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1767                                                 dev_attr->max_qp_wqes + 1);
1768                 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1769                                                 qp_attr->cap.max_send_wr;
1770                 /*
1771                  * Reserving one slot for Phantom WQE. Some application can
1772                  * post one extra entry in this case. Allowing this to avoid
1773                  * unexpected Queue full condition
1774                  */
1775                 qp->qplib_qp.sq.q_full_delta -= 1;
1776                 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1777                 if (qp->qplib_qp.rq.max_wqe) {
1778                         entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1779                         qp->qplib_qp.rq.max_wqe =
1780                                 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1781                         qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1782                                                        qp_attr->cap.max_recv_wr;
1783                         qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1784                 } else {
1785                         /* SRQ was used prior, just ignore the RQ caps */
1786                 }
1787         }
1788         if (qp_attr_mask & IB_QP_DEST_QPN) {
1789                 qp->qplib_qp.modify_flags |=
1790                                 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
1791                 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
1792         }
1793         rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1794         if (rc) {
1795                 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP");
1796                 return rc;
1797         }
1798         if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp)
1799                 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
1800         return rc;
1801 }
1802
1803 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1804                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1805 {
1806         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1807         struct bnxt_re_dev *rdev = qp->rdev;
1808         struct bnxt_qplib_qp *qplib_qp;
1809         int rc;
1810
1811         qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
1812         if (!qplib_qp)
1813                 return -ENOMEM;
1814
1815         qplib_qp->id = qp->qplib_qp.id;
1816         qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1817
1818         rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
1819         if (rc) {
1820                 dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
1821                 goto out;
1822         }
1823         qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
1824         qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
1825         qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
1826         qp_attr->pkey_index = qplib_qp->pkey_index;
1827         qp_attr->qkey = qplib_qp->qkey;
1828         qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
1829         rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
1830                         qplib_qp->ah.host_sgid_index,
1831                         qplib_qp->ah.hop_limit,
1832                         qplib_qp->ah.traffic_class);
1833         rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
1834         rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
1835         ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
1836         qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
1837         qp_attr->timeout = qplib_qp->timeout;
1838         qp_attr->retry_cnt = qplib_qp->retry_cnt;
1839         qp_attr->rnr_retry = qplib_qp->rnr_retry;
1840         qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
1841         qp_attr->rq_psn = qplib_qp->rq.psn;
1842         qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
1843         qp_attr->sq_psn = qplib_qp->sq.psn;
1844         qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
1845         qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
1846                                                          IB_SIGNAL_REQ_WR;
1847         qp_attr->dest_qp_num = qplib_qp->dest_qpn;
1848
1849         qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
1850         qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
1851         qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
1852         qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
1853         qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
1854         qp_init_attr->cap = qp_attr->cap;
1855
1856 out:
1857         kfree(qplib_qp);
1858         return rc;
1859 }
1860
1861 /* Routine for sending QP1 packets for RoCE V1 an V2
1862  */
1863 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
1864                                      const struct ib_send_wr *wr,
1865                                      struct bnxt_qplib_swqe *wqe,
1866                                      int payload_size)
1867 {
1868         struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
1869                                              ib_ah);
1870         struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
1871         const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
1872         struct bnxt_qplib_sge sge;
1873         u8 nw_type;
1874         u16 ether_type;
1875         union ib_gid dgid;
1876         bool is_eth = false;
1877         bool is_vlan = false;
1878         bool is_grh = false;
1879         bool is_udp = false;
1880         u8 ip_version = 0;
1881         u16 vlan_id = 0xFFFF;
1882         void *buf;
1883         int i, rc = 0;
1884
1885         memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
1886
1887         if (is_vlan_dev(sgid_attr->ndev))
1888                 vlan_id = vlan_dev_vlan_id(sgid_attr->ndev);
1889         /* Get network header type for this GID */
1890         nw_type = rdma_gid_attr_network_type(sgid_attr);
1891         switch (nw_type) {
1892         case RDMA_NETWORK_IPV4:
1893                 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
1894                 break;
1895         case RDMA_NETWORK_IPV6:
1896                 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
1897                 break;
1898         default:
1899                 nw_type = BNXT_RE_ROCE_V1_PACKET;
1900                 break;
1901         }
1902         memcpy(&dgid.raw, &qplib_ah->dgid, 16);
1903         is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
1904         if (is_udp) {
1905                 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
1906                         ip_version = 4;
1907                         ether_type = ETH_P_IP;
1908                 } else {
1909                         ip_version = 6;
1910                         ether_type = ETH_P_IPV6;
1911                 }
1912                 is_grh = false;
1913         } else {
1914                 ether_type = ETH_P_IBOE;
1915                 is_grh = true;
1916         }
1917
1918         is_eth = true;
1919         is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
1920
1921         ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
1922                           ip_version, is_udp, 0, &qp->qp1_hdr);
1923
1924         /* ETH */
1925         ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
1926         ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
1927
1928         /* For vlan, check the sgid for vlan existence */
1929
1930         if (!is_vlan) {
1931                 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
1932         } else {
1933                 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
1934                 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
1935         }
1936
1937         if (is_grh || (ip_version == 6)) {
1938                 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
1939                        sizeof(sgid_attr->gid));
1940                 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
1941                        sizeof(sgid_attr->gid));
1942                 qp->qp1_hdr.grh.hop_limit     = qplib_ah->hop_limit;
1943         }
1944
1945         if (ip_version == 4) {
1946                 qp->qp1_hdr.ip4.tos = 0;
1947                 qp->qp1_hdr.ip4.id = 0;
1948                 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
1949                 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
1950
1951                 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
1952                 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
1953                 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
1954         }
1955
1956         if (is_udp) {
1957                 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
1958                 qp->qp1_hdr.udp.sport = htons(0x8CD1);
1959                 qp->qp1_hdr.udp.csum = 0;
1960         }
1961
1962         /* BTH */
1963         if (wr->opcode == IB_WR_SEND_WITH_IMM) {
1964                 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1965                 qp->qp1_hdr.immediate_present = 1;
1966         } else {
1967                 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1968         }
1969         if (wr->send_flags & IB_SEND_SOLICITED)
1970                 qp->qp1_hdr.bth.solicited_event = 1;
1971         /* pad_count */
1972         qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
1973
1974         /* P_key for QP1 is for all members */
1975         qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
1976         qp->qp1_hdr.bth.destination_qpn = IB_QP1;
1977         qp->qp1_hdr.bth.ack_req = 0;
1978         qp->send_psn++;
1979         qp->send_psn &= BTH_PSN_MASK;
1980         qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
1981         /* DETH */
1982         /* Use the priviledged Q_Key for QP1 */
1983         qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
1984         qp->qp1_hdr.deth.source_qpn = IB_QP1;
1985
1986         /* Pack the QP1 to the transmit buffer */
1987         buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
1988         if (buf) {
1989                 ib_ud_header_pack(&qp->qp1_hdr, buf);
1990                 for (i = wqe->num_sge; i; i--) {
1991                         wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
1992                         wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
1993                         wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
1994                 }
1995
1996                 /*
1997                  * Max Header buf size for IPV6 RoCE V2 is 86,
1998                  * which is same as the QP1 SQ header buffer.
1999                  * Header buf size for IPV4 RoCE V2 can be 66.
2000                  * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2001                  * Subtract 20 bytes from QP1 SQ header buf size
2002                  */
2003                 if (is_udp && ip_version == 4)
2004                         sge.size -= 20;
2005                 /*
2006                  * Max Header buf size for RoCE V1 is 78.
2007                  * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2008                  * Subtract 8 bytes from QP1 SQ header buf size
2009                  */
2010                 if (!is_udp)
2011                         sge.size -= 8;
2012
2013                 /* Subtract 4 bytes for non vlan packets */
2014                 if (!is_vlan)
2015                         sge.size -= 4;
2016
2017                 wqe->sg_list[0].addr = sge.addr;
2018                 wqe->sg_list[0].lkey = sge.lkey;
2019                 wqe->sg_list[0].size = sge.size;
2020                 wqe->num_sge++;
2021
2022         } else {
2023                 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!");
2024                 rc = -ENOMEM;
2025         }
2026         return rc;
2027 }
2028
2029 /* For the MAD layer, it only provides the recv SGE the size of
2030  * ib_grh + MAD datagram.  No Ethernet headers, Ethertype, BTH, DETH,
2031  * nor RoCE iCRC.  The Cu+ solution must provide buffer for the entire
2032  * receive packet (334 bytes) with no VLAN and then copy the GRH
2033  * and the MAD datagram out to the provided SGE.
2034  */
2035 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2036                                             const struct ib_recv_wr *wr,
2037                                             struct bnxt_qplib_swqe *wqe,
2038                                             int payload_size)
2039 {
2040         struct bnxt_qplib_sge ref, sge;
2041         u32 rq_prod_index;
2042         struct bnxt_re_sqp_entries *sqp_entry;
2043
2044         rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2045
2046         if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2047                 return -ENOMEM;
2048
2049         /* Create 1 SGE to receive the entire
2050          * ethernet packet
2051          */
2052         /* Save the reference from ULP */
2053         ref.addr = wqe->sg_list[0].addr;
2054         ref.lkey = wqe->sg_list[0].lkey;
2055         ref.size = wqe->sg_list[0].size;
2056
2057         sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index];
2058
2059         /* SGE 1 */
2060         wqe->sg_list[0].addr = sge.addr;
2061         wqe->sg_list[0].lkey = sge.lkey;
2062         wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2063         sge.size -= wqe->sg_list[0].size;
2064
2065         sqp_entry->sge.addr = ref.addr;
2066         sqp_entry->sge.lkey = ref.lkey;
2067         sqp_entry->sge.size = ref.size;
2068         /* Store the wrid for reporting completion */
2069         sqp_entry->wrid = wqe->wr_id;
2070         /* change the wqe->wrid to table index */
2071         wqe->wr_id = rq_prod_index;
2072         return 0;
2073 }
2074
2075 static int is_ud_qp(struct bnxt_re_qp *qp)
2076 {
2077         return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2078                 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2079 }
2080
2081 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2082                                   const struct ib_send_wr *wr,
2083                                   struct bnxt_qplib_swqe *wqe)
2084 {
2085         struct bnxt_re_ah *ah = NULL;
2086
2087         if (is_ud_qp(qp)) {
2088                 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2089                 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2090                 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2091                 wqe->send.avid = ah->qplib_ah.id;
2092         }
2093         switch (wr->opcode) {
2094         case IB_WR_SEND:
2095                 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2096                 break;
2097         case IB_WR_SEND_WITH_IMM:
2098                 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2099                 wqe->send.imm_data = wr->ex.imm_data;
2100                 break;
2101         case IB_WR_SEND_WITH_INV:
2102                 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2103                 wqe->send.inv_key = wr->ex.invalidate_rkey;
2104                 break;
2105         default:
2106                 return -EINVAL;
2107         }
2108         if (wr->send_flags & IB_SEND_SIGNALED)
2109                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2110         if (wr->send_flags & IB_SEND_FENCE)
2111                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2112         if (wr->send_flags & IB_SEND_SOLICITED)
2113                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2114         if (wr->send_flags & IB_SEND_INLINE)
2115                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2116
2117         return 0;
2118 }
2119
2120 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2121                                   struct bnxt_qplib_swqe *wqe)
2122 {
2123         switch (wr->opcode) {
2124         case IB_WR_RDMA_WRITE:
2125                 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2126                 break;
2127         case IB_WR_RDMA_WRITE_WITH_IMM:
2128                 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2129                 wqe->rdma.imm_data = wr->ex.imm_data;
2130                 break;
2131         case IB_WR_RDMA_READ:
2132                 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2133                 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2134                 break;
2135         default:
2136                 return -EINVAL;
2137         }
2138         wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2139         wqe->rdma.r_key = rdma_wr(wr)->rkey;
2140         if (wr->send_flags & IB_SEND_SIGNALED)
2141                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2142         if (wr->send_flags & IB_SEND_FENCE)
2143                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2144         if (wr->send_flags & IB_SEND_SOLICITED)
2145                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2146         if (wr->send_flags & IB_SEND_INLINE)
2147                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2148
2149         return 0;
2150 }
2151
2152 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2153                                     struct bnxt_qplib_swqe *wqe)
2154 {
2155         switch (wr->opcode) {
2156         case IB_WR_ATOMIC_CMP_AND_SWP:
2157                 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2158                 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2159                 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2160                 break;
2161         case IB_WR_ATOMIC_FETCH_AND_ADD:
2162                 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2163                 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2164                 break;
2165         default:
2166                 return -EINVAL;
2167         }
2168         wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2169         wqe->atomic.r_key = atomic_wr(wr)->rkey;
2170         if (wr->send_flags & IB_SEND_SIGNALED)
2171                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2172         if (wr->send_flags & IB_SEND_FENCE)
2173                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2174         if (wr->send_flags & IB_SEND_SOLICITED)
2175                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2176         return 0;
2177 }
2178
2179 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2180                                  struct bnxt_qplib_swqe *wqe)
2181 {
2182         wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2183         wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2184
2185         /* Need unconditional fence for local invalidate
2186          * opcode to work as expected.
2187          */
2188         wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2189
2190         if (wr->send_flags & IB_SEND_SIGNALED)
2191                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2192         if (wr->send_flags & IB_SEND_SOLICITED)
2193                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2194
2195         return 0;
2196 }
2197
2198 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2199                                  struct bnxt_qplib_swqe *wqe)
2200 {
2201         struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2202         struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2203         int access = wr->access;
2204
2205         wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2206         wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2207         wqe->frmr.page_list = mr->pages;
2208         wqe->frmr.page_list_len = mr->npages;
2209         wqe->frmr.levels = qplib_frpl->hwq.level + 1;
2210         wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2211
2212         /* Need unconditional fence for reg_mr
2213          * opcode to function as expected.
2214          */
2215
2216         wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2217
2218         if (wr->wr.send_flags & IB_SEND_SIGNALED)
2219                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2220
2221         if (access & IB_ACCESS_LOCAL_WRITE)
2222                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2223         if (access & IB_ACCESS_REMOTE_READ)
2224                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2225         if (access & IB_ACCESS_REMOTE_WRITE)
2226                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2227         if (access & IB_ACCESS_REMOTE_ATOMIC)
2228                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2229         if (access & IB_ACCESS_MW_BIND)
2230                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2231
2232         wqe->frmr.l_key = wr->key;
2233         wqe->frmr.length = wr->mr->length;
2234         wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2235         wqe->frmr.va = wr->mr->iova;
2236         return 0;
2237 }
2238
2239 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2240                                     const struct ib_send_wr *wr,
2241                                     struct bnxt_qplib_swqe *wqe)
2242 {
2243         /*  Copy the inline data to the data  field */
2244         u8 *in_data;
2245         u32 i, sge_len;
2246         void *sge_addr;
2247
2248         in_data = wqe->inline_data;
2249         for (i = 0; i < wr->num_sge; i++) {
2250                 sge_addr = (void *)(unsigned long)
2251                                 wr->sg_list[i].addr;
2252                 sge_len = wr->sg_list[i].length;
2253
2254                 if ((sge_len + wqe->inline_len) >
2255                     BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2256                         dev_err(rdev_to_dev(rdev),
2257                                 "Inline data size requested > supported value");
2258                         return -EINVAL;
2259                 }
2260                 sge_len = wr->sg_list[i].length;
2261
2262                 memcpy(in_data, sge_addr, sge_len);
2263                 in_data += wr->sg_list[i].length;
2264                 wqe->inline_len += wr->sg_list[i].length;
2265         }
2266         return wqe->inline_len;
2267 }
2268
2269 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2270                                    const struct ib_send_wr *wr,
2271                                    struct bnxt_qplib_swqe *wqe)
2272 {
2273         int payload_sz = 0;
2274
2275         if (wr->send_flags & IB_SEND_INLINE)
2276                 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2277         else
2278                 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2279                                                wqe->num_sge);
2280
2281         return payload_sz;
2282 }
2283
2284 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2285 {
2286         if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2287              qp->ib_qp.qp_type == IB_QPT_GSI ||
2288              qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2289              qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2290                 int qp_attr_mask;
2291                 struct ib_qp_attr qp_attr;
2292
2293                 qp_attr_mask = IB_QP_STATE;
2294                 qp_attr.qp_state = IB_QPS_RTS;
2295                 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2296                 qp->qplib_qp.wqe_cnt = 0;
2297         }
2298 }
2299
2300 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2301                                        struct bnxt_re_qp *qp,
2302                                        const struct ib_send_wr *wr)
2303 {
2304         struct bnxt_qplib_swqe wqe;
2305         int rc = 0, payload_sz = 0;
2306         unsigned long flags;
2307
2308         spin_lock_irqsave(&qp->sq_lock, flags);
2309         memset(&wqe, 0, sizeof(wqe));
2310         while (wr) {
2311                 /* House keeping */
2312                 memset(&wqe, 0, sizeof(wqe));
2313
2314                 /* Common */
2315                 wqe.num_sge = wr->num_sge;
2316                 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2317                         dev_err(rdev_to_dev(rdev),
2318                                 "Limit exceeded for Send SGEs");
2319                         rc = -EINVAL;
2320                         goto bad;
2321                 }
2322
2323                 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2324                 if (payload_sz < 0) {
2325                         rc = -EINVAL;
2326                         goto bad;
2327                 }
2328                 wqe.wr_id = wr->wr_id;
2329
2330                 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2331
2332                 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2333                 if (!rc)
2334                         rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2335 bad:
2336                 if (rc) {
2337                         dev_err(rdev_to_dev(rdev),
2338                                 "Post send failed opcode = %#x rc = %d",
2339                                 wr->opcode, rc);
2340                         break;
2341                 }
2342                 wr = wr->next;
2343         }
2344         bnxt_qplib_post_send_db(&qp->qplib_qp);
2345         bnxt_ud_qp_hw_stall_workaround(qp);
2346         spin_unlock_irqrestore(&qp->sq_lock, flags);
2347         return rc;
2348 }
2349
2350 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2351                       const struct ib_send_wr **bad_wr)
2352 {
2353         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2354         struct bnxt_qplib_swqe wqe;
2355         int rc = 0, payload_sz = 0;
2356         unsigned long flags;
2357
2358         spin_lock_irqsave(&qp->sq_lock, flags);
2359         while (wr) {
2360                 /* House keeping */
2361                 memset(&wqe, 0, sizeof(wqe));
2362
2363                 /* Common */
2364                 wqe.num_sge = wr->num_sge;
2365                 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2366                         dev_err(rdev_to_dev(qp->rdev),
2367                                 "Limit exceeded for Send SGEs");
2368                         rc = -EINVAL;
2369                         goto bad;
2370                 }
2371
2372                 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2373                 if (payload_sz < 0) {
2374                         rc = -EINVAL;
2375                         goto bad;
2376                 }
2377                 wqe.wr_id = wr->wr_id;
2378
2379                 switch (wr->opcode) {
2380                 case IB_WR_SEND:
2381                 case IB_WR_SEND_WITH_IMM:
2382                         if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2383                                 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2384                                                                payload_sz);
2385                                 if (rc)
2386                                         goto bad;
2387                                 wqe.rawqp1.lflags |=
2388                                         SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2389                         }
2390                         switch (wr->send_flags) {
2391                         case IB_SEND_IP_CSUM:
2392                                 wqe.rawqp1.lflags |=
2393                                         SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2394                                 break;
2395                         default:
2396                                 break;
2397                         }
2398                         /* fall through */
2399                 case IB_WR_SEND_WITH_INV:
2400                         rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2401                         break;
2402                 case IB_WR_RDMA_WRITE:
2403                 case IB_WR_RDMA_WRITE_WITH_IMM:
2404                 case IB_WR_RDMA_READ:
2405                         rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2406                         break;
2407                 case IB_WR_ATOMIC_CMP_AND_SWP:
2408                 case IB_WR_ATOMIC_FETCH_AND_ADD:
2409                         rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2410                         break;
2411                 case IB_WR_RDMA_READ_WITH_INV:
2412                         dev_err(rdev_to_dev(qp->rdev),
2413                                 "RDMA Read with Invalidate is not supported");
2414                         rc = -EINVAL;
2415                         goto bad;
2416                 case IB_WR_LOCAL_INV:
2417                         rc = bnxt_re_build_inv_wqe(wr, &wqe);
2418                         break;
2419                 case IB_WR_REG_MR:
2420                         rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2421                         break;
2422                 default:
2423                         /* Unsupported WRs */
2424                         dev_err(rdev_to_dev(qp->rdev),
2425                                 "WR (%#x) is not supported", wr->opcode);
2426                         rc = -EINVAL;
2427                         goto bad;
2428                 }
2429                 if (!rc)
2430                         rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2431 bad:
2432                 if (rc) {
2433                         dev_err(rdev_to_dev(qp->rdev),
2434                                 "post_send failed op:%#x qps = %#x rc = %d\n",
2435                                 wr->opcode, qp->qplib_qp.state, rc);
2436                         *bad_wr = wr;
2437                         break;
2438                 }
2439                 wr = wr->next;
2440         }
2441         bnxt_qplib_post_send_db(&qp->qplib_qp);
2442         bnxt_ud_qp_hw_stall_workaround(qp);
2443         spin_unlock_irqrestore(&qp->sq_lock, flags);
2444
2445         return rc;
2446 }
2447
2448 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2449                                        struct bnxt_re_qp *qp,
2450                                        const struct ib_recv_wr *wr)
2451 {
2452         struct bnxt_qplib_swqe wqe;
2453         int rc = 0;
2454
2455         memset(&wqe, 0, sizeof(wqe));
2456         while (wr) {
2457                 /* House keeping */
2458                 memset(&wqe, 0, sizeof(wqe));
2459
2460                 /* Common */
2461                 wqe.num_sge = wr->num_sge;
2462                 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2463                         dev_err(rdev_to_dev(rdev),
2464                                 "Limit exceeded for Receive SGEs");
2465                         rc = -EINVAL;
2466                         break;
2467                 }
2468                 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2469                 wqe.wr_id = wr->wr_id;
2470                 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2471
2472                 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2473                 if (rc)
2474                         break;
2475
2476                 wr = wr->next;
2477         }
2478         if (!rc)
2479                 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2480         return rc;
2481 }
2482
2483 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2484                       const struct ib_recv_wr **bad_wr)
2485 {
2486         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2487         struct bnxt_qplib_swqe wqe;
2488         int rc = 0, payload_sz = 0;
2489         unsigned long flags;
2490         u32 count = 0;
2491
2492         spin_lock_irqsave(&qp->rq_lock, flags);
2493         while (wr) {
2494                 /* House keeping */
2495                 memset(&wqe, 0, sizeof(wqe));
2496
2497                 /* Common */
2498                 wqe.num_sge = wr->num_sge;
2499                 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2500                         dev_err(rdev_to_dev(qp->rdev),
2501                                 "Limit exceeded for Receive SGEs");
2502                         rc = -EINVAL;
2503                         *bad_wr = wr;
2504                         break;
2505                 }
2506
2507                 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2508                                                wr->num_sge);
2509                 wqe.wr_id = wr->wr_id;
2510                 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2511
2512                 if (ib_qp->qp_type == IB_QPT_GSI &&
2513                     qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2514                         rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2515                                                               payload_sz);
2516                 if (!rc)
2517                         rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2518                 if (rc) {
2519                         *bad_wr = wr;
2520                         break;
2521                 }
2522
2523                 /* Ring DB if the RQEs posted reaches a threshold value */
2524                 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2525                         bnxt_qplib_post_recv_db(&qp->qplib_qp);
2526                         count = 0;
2527                 }
2528
2529                 wr = wr->next;
2530         }
2531
2532         if (count)
2533                 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2534
2535         spin_unlock_irqrestore(&qp->rq_lock, flags);
2536
2537         return rc;
2538 }
2539
2540 /* Completion Queues */
2541 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2542 {
2543         int rc;
2544         struct bnxt_re_cq *cq;
2545         struct bnxt_qplib_nq *nq;
2546         struct bnxt_re_dev *rdev;
2547
2548         cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2549         rdev = cq->rdev;
2550         nq = cq->qplib_cq.nq;
2551
2552         rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2553         if (rc) {
2554                 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ");
2555                 return rc;
2556         }
2557         if (!IS_ERR_OR_NULL(cq->umem))
2558                 ib_umem_release(cq->umem);
2559
2560         atomic_dec(&rdev->cq_count);
2561         nq->budget--;
2562         kfree(cq->cql);
2563         kfree(cq);
2564
2565         return 0;
2566 }
2567
2568 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev,
2569                                 const struct ib_cq_init_attr *attr,
2570                                 struct ib_udata *udata)
2571 {
2572         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
2573         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2574         struct bnxt_re_cq *cq = NULL;
2575         int rc, entries;
2576         int cqe = attr->cqe;
2577         struct bnxt_qplib_nq *nq = NULL;
2578         unsigned int nq_alloc_cnt;
2579
2580         /* Validate CQ fields */
2581         if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2582                 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded");
2583                 return ERR_PTR(-EINVAL);
2584         }
2585         cq = kzalloc(sizeof(*cq), GFP_KERNEL);
2586         if (!cq)
2587                 return ERR_PTR(-ENOMEM);
2588
2589         cq->rdev = rdev;
2590         cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2591
2592         entries = roundup_pow_of_two(cqe + 1);
2593         if (entries > dev_attr->max_cq_wqes + 1)
2594                 entries = dev_attr->max_cq_wqes + 1;
2595
2596         if (udata) {
2597                 struct bnxt_re_cq_req req;
2598                 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
2599                         udata, struct bnxt_re_ucontext, ib_uctx);
2600                 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2601                         rc = -EFAULT;
2602                         goto fail;
2603                 }
2604
2605                 cq->umem = ib_umem_get(udata, req.cq_va,
2606                                        entries * sizeof(struct cq_base),
2607                                        IB_ACCESS_LOCAL_WRITE, 1);
2608                 if (IS_ERR(cq->umem)) {
2609                         rc = PTR_ERR(cq->umem);
2610                         goto fail;
2611                 }
2612                 cq->qplib_cq.sg_info.sglist = cq->umem->sg_head.sgl;
2613                 cq->qplib_cq.sg_info.npages = ib_umem_num_pages(cq->umem);
2614                 cq->qplib_cq.sg_info.nmap = cq->umem->nmap;
2615                 cq->qplib_cq.dpi = &uctx->dpi;
2616         } else {
2617                 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2618                 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2619                                   GFP_KERNEL);
2620                 if (!cq->cql) {
2621                         rc = -ENOMEM;
2622                         goto fail;
2623                 }
2624
2625                 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2626         }
2627         /*
2628          * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2629          * used for getting the NQ index.
2630          */
2631         nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2632         nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2633         cq->qplib_cq.max_wqe = entries;
2634         cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2635         cq->qplib_cq.nq = nq;
2636
2637         rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2638         if (rc) {
2639                 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ");
2640                 goto fail;
2641         }
2642
2643         cq->ib_cq.cqe = entries;
2644         cq->cq_period = cq->qplib_cq.period;
2645         nq->budget++;
2646
2647         atomic_inc(&rdev->cq_count);
2648         spin_lock_init(&cq->cq_lock);
2649
2650         if (udata) {
2651                 struct bnxt_re_cq_resp resp;
2652
2653                 resp.cqid = cq->qplib_cq.id;
2654                 resp.tail = cq->qplib_cq.hwq.cons;
2655                 resp.phase = cq->qplib_cq.period;
2656                 resp.rsvd = 0;
2657                 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2658                 if (rc) {
2659                         dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata");
2660                         bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2661                         goto c2fail;
2662                 }
2663         }
2664
2665         return &cq->ib_cq;
2666
2667 c2fail:
2668         if (udata)
2669                 ib_umem_release(cq->umem);
2670 fail:
2671         kfree(cq->cql);
2672         kfree(cq);
2673         return ERR_PTR(rc);
2674 }
2675
2676 static u8 __req_to_ib_wc_status(u8 qstatus)
2677 {
2678         switch (qstatus) {
2679         case CQ_REQ_STATUS_OK:
2680                 return IB_WC_SUCCESS;
2681         case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2682                 return IB_WC_BAD_RESP_ERR;
2683         case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2684                 return IB_WC_LOC_LEN_ERR;
2685         case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2686                 return IB_WC_LOC_QP_OP_ERR;
2687         case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2688                 return IB_WC_LOC_PROT_ERR;
2689         case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2690                 return IB_WC_GENERAL_ERR;
2691         case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2692                 return IB_WC_REM_INV_REQ_ERR;
2693         case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2694                 return IB_WC_REM_ACCESS_ERR;
2695         case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2696                 return IB_WC_REM_OP_ERR;
2697         case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2698                 return IB_WC_RNR_RETRY_EXC_ERR;
2699         case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2700                 return IB_WC_RETRY_EXC_ERR;
2701         case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2702                 return IB_WC_WR_FLUSH_ERR;
2703         default:
2704                 return IB_WC_GENERAL_ERR;
2705         }
2706         return 0;
2707 }
2708
2709 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2710 {
2711         switch (qstatus) {
2712         case CQ_RES_RAWETH_QP1_STATUS_OK:
2713                 return IB_WC_SUCCESS;
2714         case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2715                 return IB_WC_LOC_ACCESS_ERR;
2716         case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2717                 return IB_WC_LOC_LEN_ERR;
2718         case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2719                 return IB_WC_LOC_PROT_ERR;
2720         case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2721                 return IB_WC_LOC_QP_OP_ERR;
2722         case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2723                 return IB_WC_GENERAL_ERR;
2724         case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2725                 return IB_WC_WR_FLUSH_ERR;
2726         case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2727                 return IB_WC_WR_FLUSH_ERR;
2728         default:
2729                 return IB_WC_GENERAL_ERR;
2730         }
2731 }
2732
2733 static u8 __rc_to_ib_wc_status(u8 qstatus)
2734 {
2735         switch (qstatus) {
2736         case CQ_RES_RC_STATUS_OK:
2737                 return IB_WC_SUCCESS;
2738         case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2739                 return IB_WC_LOC_ACCESS_ERR;
2740         case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2741                 return IB_WC_LOC_LEN_ERR;
2742         case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2743                 return IB_WC_LOC_PROT_ERR;
2744         case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2745                 return IB_WC_LOC_QP_OP_ERR;
2746         case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2747                 return IB_WC_GENERAL_ERR;
2748         case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2749                 return IB_WC_REM_INV_REQ_ERR;
2750         case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2751                 return IB_WC_WR_FLUSH_ERR;
2752         case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2753                 return IB_WC_WR_FLUSH_ERR;
2754         default:
2755                 return IB_WC_GENERAL_ERR;
2756         }
2757 }
2758
2759 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2760 {
2761         switch (cqe->type) {
2762         case BNXT_QPLIB_SWQE_TYPE_SEND:
2763                 wc->opcode = IB_WC_SEND;
2764                 break;
2765         case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
2766                 wc->opcode = IB_WC_SEND;
2767                 wc->wc_flags |= IB_WC_WITH_IMM;
2768                 break;
2769         case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
2770                 wc->opcode = IB_WC_SEND;
2771                 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2772                 break;
2773         case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
2774                 wc->opcode = IB_WC_RDMA_WRITE;
2775                 break;
2776         case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
2777                 wc->opcode = IB_WC_RDMA_WRITE;
2778                 wc->wc_flags |= IB_WC_WITH_IMM;
2779                 break;
2780         case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
2781                 wc->opcode = IB_WC_RDMA_READ;
2782                 break;
2783         case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
2784                 wc->opcode = IB_WC_COMP_SWAP;
2785                 break;
2786         case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
2787                 wc->opcode = IB_WC_FETCH_ADD;
2788                 break;
2789         case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
2790                 wc->opcode = IB_WC_LOCAL_INV;
2791                 break;
2792         case BNXT_QPLIB_SWQE_TYPE_REG_MR:
2793                 wc->opcode = IB_WC_REG_MR;
2794                 break;
2795         default:
2796                 wc->opcode = IB_WC_SEND;
2797                 break;
2798         }
2799
2800         wc->status = __req_to_ib_wc_status(cqe->status);
2801 }
2802
2803 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2804                                      u16 raweth_qp1_flags2)
2805 {
2806         bool is_ipv6 = false, is_ipv4 = false;
2807
2808         /* raweth_qp1_flags Bit 9-6 indicates itype */
2809         if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2810             != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2811                 return -1;
2812
2813         if (raweth_qp1_flags2 &
2814             CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2815             raweth_qp1_flags2 &
2816             CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2817                 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2818                 (raweth_qp1_flags2 &
2819                  CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
2820                         (is_ipv6 = true) : (is_ipv4 = true);
2821                 return ((is_ipv6) ?
2822                          BNXT_RE_ROCEV2_IPV6_PACKET :
2823                          BNXT_RE_ROCEV2_IPV4_PACKET);
2824         } else {
2825                 return BNXT_RE_ROCE_V1_PACKET;
2826         }
2827 }
2828
2829 static int bnxt_re_to_ib_nw_type(int nw_type)
2830 {
2831         u8 nw_hdr_type = 0xFF;
2832
2833         switch (nw_type) {
2834         case BNXT_RE_ROCE_V1_PACKET:
2835                 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
2836                 break;
2837         case BNXT_RE_ROCEV2_IPV4_PACKET:
2838                 nw_hdr_type = RDMA_NETWORK_IPV4;
2839                 break;
2840         case BNXT_RE_ROCEV2_IPV6_PACKET:
2841                 nw_hdr_type = RDMA_NETWORK_IPV6;
2842                 break;
2843         }
2844         return nw_hdr_type;
2845 }
2846
2847 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
2848                                        void *rq_hdr_buf)
2849 {
2850         u8 *tmp_buf = NULL;
2851         struct ethhdr *eth_hdr;
2852         u16 eth_type;
2853         bool rc = false;
2854
2855         tmp_buf = (u8 *)rq_hdr_buf;
2856         /*
2857          * If dest mac is not same as I/F mac, this could be a
2858          * loopback address or multicast address, check whether
2859          * it is a loopback packet
2860          */
2861         if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
2862                 tmp_buf += 4;
2863                 /* Check the  ether type */
2864                 eth_hdr = (struct ethhdr *)tmp_buf;
2865                 eth_type = ntohs(eth_hdr->h_proto);
2866                 switch (eth_type) {
2867                 case ETH_P_IBOE:
2868                         rc = true;
2869                         break;
2870                 case ETH_P_IP:
2871                 case ETH_P_IPV6: {
2872                         u32 len;
2873                         struct udphdr *udp_hdr;
2874
2875                         len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
2876                                                       sizeof(struct ipv6hdr));
2877                         tmp_buf += sizeof(struct ethhdr) + len;
2878                         udp_hdr = (struct udphdr *)tmp_buf;
2879                         if (ntohs(udp_hdr->dest) ==
2880                                     ROCE_V2_UDP_DPORT)
2881                                 rc = true;
2882                         break;
2883                         }
2884                 default:
2885                         break;
2886                 }
2887         }
2888
2889         return rc;
2890 }
2891
2892 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp,
2893                                          struct bnxt_qplib_cqe *cqe)
2894 {
2895         struct bnxt_re_dev *rdev = qp1_qp->rdev;
2896         struct bnxt_re_sqp_entries *sqp_entry = NULL;
2897         struct bnxt_re_qp *qp = rdev->qp1_sqp;
2898         struct ib_send_wr *swr;
2899         struct ib_ud_wr udwr;
2900         struct ib_recv_wr rwr;
2901         int pkt_type = 0;
2902         u32 tbl_idx;
2903         void *rq_hdr_buf;
2904         dma_addr_t rq_hdr_buf_map;
2905         dma_addr_t shrq_hdr_buf_map;
2906         u32 offset = 0;
2907         u32 skip_bytes = 0;
2908         struct ib_sge s_sge[2];
2909         struct ib_sge r_sge[2];
2910         int rc;
2911
2912         memset(&udwr, 0, sizeof(udwr));
2913         memset(&rwr, 0, sizeof(rwr));
2914         memset(&s_sge, 0, sizeof(s_sge));
2915         memset(&r_sge, 0, sizeof(r_sge));
2916
2917         swr = &udwr.wr;
2918         tbl_idx = cqe->wr_id;
2919
2920         rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf +
2921                         (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size);
2922         rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp,
2923                                                           tbl_idx);
2924
2925         /* Shadow QP header buffer */
2926         shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp,
2927                                                             tbl_idx);
2928         sqp_entry = &rdev->sqp_tbl[tbl_idx];
2929
2930         /* Store this cqe */
2931         memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
2932         sqp_entry->qp1_qp = qp1_qp;
2933
2934         /* Find packet type from the cqe */
2935
2936         pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
2937                                              cqe->raweth_qp1_flags2);
2938         if (pkt_type < 0) {
2939                 dev_err(rdev_to_dev(rdev), "Invalid packet\n");
2940                 return -EINVAL;
2941         }
2942
2943         /* Adjust the offset for the user buffer and post in the rq */
2944
2945         if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
2946                 offset = 20;
2947
2948         /*
2949          * QP1 loopback packet has 4 bytes of internal header before
2950          * ether header. Skip these four bytes.
2951          */
2952         if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
2953                 skip_bytes = 4;
2954
2955         /* First send SGE . Skip the ether header*/
2956         s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
2957                         + skip_bytes;
2958         s_sge[0].lkey = 0xFFFFFFFF;
2959         s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
2960                                 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
2961
2962         /* Second Send SGE */
2963         s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
2964                         BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
2965         if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
2966                 s_sge[1].addr += 8;
2967         s_sge[1].lkey = 0xFFFFFFFF;
2968         s_sge[1].length = 256;
2969
2970         /* First recv SGE */
2971
2972         r_sge[0].addr = shrq_hdr_buf_map;
2973         r_sge[0].lkey = 0xFFFFFFFF;
2974         r_sge[0].length = 40;
2975
2976         r_sge[1].addr = sqp_entry->sge.addr + offset;
2977         r_sge[1].lkey = sqp_entry->sge.lkey;
2978         r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
2979
2980         /* Create receive work request */
2981         rwr.num_sge = 2;
2982         rwr.sg_list = r_sge;
2983         rwr.wr_id = tbl_idx;
2984         rwr.next = NULL;
2985
2986         rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr);
2987         if (rc) {
2988                 dev_err(rdev_to_dev(rdev),
2989                         "Failed to post Rx buffers to shadow QP");
2990                 return -ENOMEM;
2991         }
2992
2993         swr->num_sge = 2;
2994         swr->sg_list = s_sge;
2995         swr->wr_id = tbl_idx;
2996         swr->opcode = IB_WR_SEND;
2997         swr->next = NULL;
2998
2999         udwr.ah = &rdev->sqp_ah->ib_ah;
3000         udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id;
3001         udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey;
3002
3003         /* post data received  in the send queue */
3004         rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr);
3005
3006         return 0;
3007 }
3008
3009 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3010                                           struct bnxt_qplib_cqe *cqe)
3011 {
3012         wc->opcode = IB_WC_RECV;
3013         wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3014         wc->wc_flags |= IB_WC_GRH;
3015 }
3016
3017 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3018                                 u16 *vid, u8 *sl)
3019 {
3020         bool ret = false;
3021         u32 metadata;
3022         u16 tpid;
3023
3024         metadata = orig_cqe->raweth_qp1_metadata;
3025         if (orig_cqe->raweth_qp1_flags2 &
3026                 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3027                 tpid = ((metadata &
3028                          CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3029                          CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3030                 if (tpid == ETH_P_8021Q) {
3031                         *vid = metadata &
3032                                CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3033                         *sl = (metadata &
3034                                CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3035                                CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3036                         ret = true;
3037                 }
3038         }
3039
3040         return ret;
3041 }
3042
3043 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3044                                       struct bnxt_qplib_cqe *cqe)
3045 {
3046         wc->opcode = IB_WC_RECV;
3047         wc->status = __rc_to_ib_wc_status(cqe->status);
3048
3049         if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3050                 wc->wc_flags |= IB_WC_WITH_IMM;
3051         if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3052                 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3053         if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3054             (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3055                 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3056 }
3057
3058 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
3059                                              struct ib_wc *wc,
3060                                              struct bnxt_qplib_cqe *cqe)
3061 {
3062         struct bnxt_re_dev *rdev = qp->rdev;
3063         struct bnxt_re_qp *qp1_qp = NULL;
3064         struct bnxt_qplib_cqe *orig_cqe = NULL;
3065         struct bnxt_re_sqp_entries *sqp_entry = NULL;
3066         int nw_type;
3067         u32 tbl_idx;
3068         u16 vlan_id;
3069         u8 sl;
3070
3071         tbl_idx = cqe->wr_id;
3072
3073         sqp_entry = &rdev->sqp_tbl[tbl_idx];
3074         qp1_qp = sqp_entry->qp1_qp;
3075         orig_cqe = &sqp_entry->cqe;
3076
3077         wc->wr_id = sqp_entry->wrid;
3078         wc->byte_len = orig_cqe->length;
3079         wc->qp = &qp1_qp->ib_qp;
3080
3081         wc->ex.imm_data = orig_cqe->immdata;
3082         wc->src_qp = orig_cqe->src_qp;
3083         memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3084         if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3085                 wc->vlan_id = vlan_id;
3086                 wc->sl = sl;
3087                 wc->wc_flags |= IB_WC_WITH_VLAN;
3088         }
3089         wc->port_num = 1;
3090         wc->vendor_err = orig_cqe->status;
3091
3092         wc->opcode = IB_WC_RECV;
3093         wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3094         wc->wc_flags |= IB_WC_GRH;
3095
3096         nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3097                                             orig_cqe->raweth_qp1_flags2);
3098         if (nw_type >= 0) {
3099                 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3100                 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3101         }
3102 }
3103
3104 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3105                                       struct ib_wc *wc,
3106                                       struct bnxt_qplib_cqe *cqe)
3107 {
3108         u8 nw_type;
3109
3110         wc->opcode = IB_WC_RECV;
3111         wc->status = __rc_to_ib_wc_status(cqe->status);
3112
3113         if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3114                 wc->wc_flags |= IB_WC_WITH_IMM;
3115         /* report only on GSI QP for Thor */
3116         if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3117                 wc->wc_flags |= IB_WC_GRH;
3118                 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3119                 wc->wc_flags |= IB_WC_WITH_SMAC;
3120                 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3121                         wc->vlan_id = (cqe->cfa_meta & 0xFFF);
3122                         if (wc->vlan_id < 0x1000)
3123                                 wc->wc_flags |= IB_WC_WITH_VLAN;
3124                 }
3125                 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3126                            CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3127                 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3128                 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3129         }
3130
3131 }
3132
3133 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3134 {
3135         struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3136         unsigned long flags;
3137         int rc = 0;
3138
3139         spin_lock_irqsave(&qp->sq_lock, flags);
3140
3141         rc = bnxt_re_bind_fence_mw(lib_qp);
3142         if (!rc) {
3143                 lib_qp->sq.phantom_wqe_cnt++;
3144                 dev_dbg(&lib_qp->sq.hwq.pdev->dev,
3145                         "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3146                         lib_qp->id, lib_qp->sq.hwq.prod,
3147                         HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3148                         lib_qp->sq.phantom_wqe_cnt);
3149         }
3150
3151         spin_unlock_irqrestore(&qp->sq_lock, flags);
3152         return rc;
3153 }
3154
3155 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3156 {
3157         struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3158         struct bnxt_re_qp *qp;
3159         struct bnxt_qplib_cqe *cqe;
3160         int i, ncqe, budget;
3161         struct bnxt_qplib_q *sq;
3162         struct bnxt_qplib_qp *lib_qp;
3163         u32 tbl_idx;
3164         struct bnxt_re_sqp_entries *sqp_entry = NULL;
3165         unsigned long flags;
3166
3167         spin_lock_irqsave(&cq->cq_lock, flags);
3168         budget = min_t(u32, num_entries, cq->max_cql);
3169         num_entries = budget;
3170         if (!cq->cql) {
3171                 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use");
3172                 goto exit;
3173         }
3174         cqe = &cq->cql[0];
3175         while (budget) {
3176                 lib_qp = NULL;
3177                 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3178                 if (lib_qp) {
3179                         sq = &lib_qp->sq;
3180                         if (sq->send_phantom) {
3181                                 qp = container_of(lib_qp,
3182                                                   struct bnxt_re_qp, qplib_qp);
3183                                 if (send_phantom_wqe(qp) == -ENOMEM)
3184                                         dev_err(rdev_to_dev(cq->rdev),
3185                                                 "Phantom failed! Scheduled to send again\n");
3186                                 else
3187                                         sq->send_phantom = false;
3188                         }
3189                 }
3190                 if (ncqe < budget)
3191                         ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3192                                                               cqe + ncqe,
3193                                                               budget - ncqe);
3194
3195                 if (!ncqe)
3196                         break;
3197
3198                 for (i = 0; i < ncqe; i++, cqe++) {
3199                         /* Transcribe each qplib_wqe back to ib_wc */
3200                         memset(wc, 0, sizeof(*wc));
3201
3202                         wc->wr_id = cqe->wr_id;
3203                         wc->byte_len = cqe->length;
3204                         qp = container_of
3205                                 ((struct bnxt_qplib_qp *)
3206                                  (unsigned long)(cqe->qp_handle),
3207                                  struct bnxt_re_qp, qplib_qp);
3208                         if (!qp) {
3209                                 dev_err(rdev_to_dev(cq->rdev),
3210                                         "POLL CQ : bad QP handle");
3211                                 continue;
3212                         }
3213                         wc->qp = &qp->ib_qp;
3214                         wc->ex.imm_data = cqe->immdata;
3215                         wc->src_qp = cqe->src_qp;
3216                         memcpy(wc->smac, cqe->smac, ETH_ALEN);
3217                         wc->port_num = 1;
3218                         wc->vendor_err = cqe->status;
3219
3220                         switch (cqe->opcode) {
3221                         case CQ_BASE_CQE_TYPE_REQ:
3222                                 if (qp->rdev->qp1_sqp && qp->qplib_qp.id ==
3223                                     qp->rdev->qp1_sqp->qplib_qp.id) {
3224                                         /* Handle this completion with
3225                                          * the stored completion
3226                                          */
3227                                         memset(wc, 0, sizeof(*wc));
3228                                         continue;
3229                                 }
3230                                 bnxt_re_process_req_wc(wc, cqe);
3231                                 break;
3232                         case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3233                                 if (!cqe->status) {
3234                                         int rc = 0;
3235
3236                                         rc = bnxt_re_process_raw_qp_pkt_rx
3237                                                                 (qp, cqe);
3238                                         if (!rc) {
3239                                                 memset(wc, 0, sizeof(*wc));
3240                                                 continue;
3241                                         }
3242                                         cqe->status = -1;
3243                                 }
3244                                 /* Errors need not be looped back.
3245                                  * But change the wr_id to the one
3246                                  * stored in the table
3247                                  */
3248                                 tbl_idx = cqe->wr_id;
3249                                 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx];
3250                                 wc->wr_id = sqp_entry->wrid;
3251                                 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3252                                 break;
3253                         case CQ_BASE_CQE_TYPE_RES_RC:
3254                                 bnxt_re_process_res_rc_wc(wc, cqe);
3255                                 break;
3256                         case CQ_BASE_CQE_TYPE_RES_UD:
3257                                 if (qp->rdev->qp1_sqp && qp->qplib_qp.id ==
3258                                     qp->rdev->qp1_sqp->qplib_qp.id) {
3259                                         /* Handle this completion with
3260                                          * the stored completion
3261                                          */
3262                                         if (cqe->status) {
3263                                                 continue;
3264                                         } else {
3265                                                 bnxt_re_process_res_shadow_qp_wc
3266                                                                 (qp, wc, cqe);
3267                                                 break;
3268                                         }
3269                                 }
3270                                 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3271                                 break;
3272                         default:
3273                                 dev_err(rdev_to_dev(cq->rdev),
3274                                         "POLL CQ : type 0x%x not handled",
3275                                         cqe->opcode);
3276                                 continue;
3277                         }
3278                         wc++;
3279                         budget--;
3280                 }
3281         }
3282 exit:
3283         spin_unlock_irqrestore(&cq->cq_lock, flags);
3284         return num_entries - budget;
3285 }
3286
3287 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3288                           enum ib_cq_notify_flags ib_cqn_flags)
3289 {
3290         struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3291         int type = 0, rc = 0;
3292         unsigned long flags;
3293
3294         spin_lock_irqsave(&cq->cq_lock, flags);
3295         /* Trigger on the very next completion */
3296         if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3297                 type = DBC_DBC_TYPE_CQ_ARMALL;
3298         /* Trigger on the next solicited completion */
3299         else if (ib_cqn_flags & IB_CQ_SOLICITED)
3300                 type = DBC_DBC_TYPE_CQ_ARMSE;
3301
3302         /* Poll to see if there are missed events */
3303         if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3304             !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3305                 rc = 1;
3306                 goto exit;
3307         }
3308         bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3309
3310 exit:
3311         spin_unlock_irqrestore(&cq->cq_lock, flags);
3312         return rc;
3313 }
3314
3315 /* Memory Regions */
3316 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3317 {
3318         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3319         struct bnxt_re_dev *rdev = pd->rdev;
3320         struct bnxt_re_mr *mr;
3321         u64 pbl = 0;
3322         int rc;
3323
3324         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3325         if (!mr)
3326                 return ERR_PTR(-ENOMEM);
3327
3328         mr->rdev = rdev;
3329         mr->qplib_mr.pd = &pd->qplib_pd;
3330         mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3331         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3332
3333         /* Allocate and register 0 as the address */
3334         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3335         if (rc)
3336                 goto fail;
3337
3338         mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3339         mr->qplib_mr.total_size = -1; /* Infinte length */
3340         rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false,
3341                                PAGE_SIZE);
3342         if (rc)
3343                 goto fail_mr;
3344
3345         mr->ib_mr.lkey = mr->qplib_mr.lkey;
3346         if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3347                                IB_ACCESS_REMOTE_ATOMIC))
3348                 mr->ib_mr.rkey = mr->ib_mr.lkey;
3349         atomic_inc(&rdev->mr_count);
3350
3351         return &mr->ib_mr;
3352
3353 fail_mr:
3354         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3355 fail:
3356         kfree(mr);
3357         return ERR_PTR(rc);
3358 }
3359
3360 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3361 {
3362         struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3363         struct bnxt_re_dev *rdev = mr->rdev;
3364         int rc;
3365
3366         rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3367         if (rc)
3368                 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
3369
3370         if (mr->pages) {
3371                 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3372                                                         &mr->qplib_frpl);
3373                 kfree(mr->pages);
3374                 mr->npages = 0;
3375                 mr->pages = NULL;
3376         }
3377         if (!IS_ERR_OR_NULL(mr->ib_umem))
3378                 ib_umem_release(mr->ib_umem);
3379
3380         kfree(mr);
3381         atomic_dec(&rdev->mr_count);
3382         return rc;
3383 }
3384
3385 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3386 {
3387         struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3388
3389         if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3390                 return -ENOMEM;
3391
3392         mr->pages[mr->npages++] = addr;
3393         return 0;
3394 }
3395
3396 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3397                       unsigned int *sg_offset)
3398 {
3399         struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3400
3401         mr->npages = 0;
3402         return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3403 }
3404
3405 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3406                                u32 max_num_sg, struct ib_udata *udata)
3407 {
3408         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3409         struct bnxt_re_dev *rdev = pd->rdev;
3410         struct bnxt_re_mr *mr = NULL;
3411         int rc;
3412
3413         if (type != IB_MR_TYPE_MEM_REG) {
3414                 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type);
3415                 return ERR_PTR(-EINVAL);
3416         }
3417         if (max_num_sg > MAX_PBL_LVL_1_PGS)
3418                 return ERR_PTR(-EINVAL);
3419
3420         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3421         if (!mr)
3422                 return ERR_PTR(-ENOMEM);
3423
3424         mr->rdev = rdev;
3425         mr->qplib_mr.pd = &pd->qplib_pd;
3426         mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3427         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3428
3429         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3430         if (rc)
3431                 goto bail;
3432
3433         mr->ib_mr.lkey = mr->qplib_mr.lkey;
3434         mr->ib_mr.rkey = mr->ib_mr.lkey;
3435
3436         mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3437         if (!mr->pages) {
3438                 rc = -ENOMEM;
3439                 goto fail;
3440         }
3441         rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3442                                                  &mr->qplib_frpl, max_num_sg);
3443         if (rc) {
3444                 dev_err(rdev_to_dev(rdev),
3445                         "Failed to allocate HW FR page list");
3446                 goto fail_mr;
3447         }
3448
3449         atomic_inc(&rdev->mr_count);
3450         return &mr->ib_mr;
3451
3452 fail_mr:
3453         kfree(mr->pages);
3454 fail:
3455         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3456 bail:
3457         kfree(mr);
3458         return ERR_PTR(rc);
3459 }
3460
3461 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3462                                struct ib_udata *udata)
3463 {
3464         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3465         struct bnxt_re_dev *rdev = pd->rdev;
3466         struct bnxt_re_mw *mw;
3467         int rc;
3468
3469         mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3470         if (!mw)
3471                 return ERR_PTR(-ENOMEM);
3472         mw->rdev = rdev;
3473         mw->qplib_mw.pd = &pd->qplib_pd;
3474
3475         mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3476                                CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3477                                CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3478         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3479         if (rc) {
3480                 dev_err(rdev_to_dev(rdev), "Allocate MW failed!");
3481                 goto fail;
3482         }
3483         mw->ib_mw.rkey = mw->qplib_mw.rkey;
3484
3485         atomic_inc(&rdev->mw_count);
3486         return &mw->ib_mw;
3487
3488 fail:
3489         kfree(mw);
3490         return ERR_PTR(rc);
3491 }
3492
3493 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3494 {
3495         struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3496         struct bnxt_re_dev *rdev = mw->rdev;
3497         int rc;
3498
3499         rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3500         if (rc) {
3501                 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc);
3502                 return rc;
3503         }
3504
3505         kfree(mw);
3506         atomic_dec(&rdev->mw_count);
3507         return rc;
3508 }
3509
3510 static int bnxt_re_page_size_ok(int page_shift)
3511 {
3512         switch (page_shift) {
3513         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K:
3514         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K:
3515         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K:
3516         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M:
3517         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K:
3518         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M:
3519         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M:
3520         case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G:
3521                 return 1;
3522         default:
3523                 return 0;
3524         }
3525 }
3526
3527 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig,
3528                              int page_shift)
3529 {
3530         u64 *pbl_tbl = pbl_tbl_orig;
3531         u64 paddr;
3532         u64 page_mask = (1ULL << page_shift) - 1;
3533         struct sg_dma_page_iter sg_iter;
3534
3535         for_each_sg_dma_page (umem->sg_head.sgl, &sg_iter, umem->nmap, 0) {
3536                 paddr = sg_page_iter_dma_address(&sg_iter);
3537                 if (pbl_tbl == pbl_tbl_orig)
3538                         *pbl_tbl++ = paddr & ~page_mask;
3539                 else if ((paddr & page_mask) == 0)
3540                         *pbl_tbl++ = paddr;
3541         }
3542         return pbl_tbl - pbl_tbl_orig;
3543 }
3544
3545 /* uverbs */
3546 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3547                                   u64 virt_addr, int mr_access_flags,
3548                                   struct ib_udata *udata)
3549 {
3550         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3551         struct bnxt_re_dev *rdev = pd->rdev;
3552         struct bnxt_re_mr *mr;
3553         struct ib_umem *umem;
3554         u64 *pbl_tbl = NULL;
3555         int umem_pgs, page_shift, rc;
3556
3557         if (length > BNXT_RE_MAX_MR_SIZE) {
3558                 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%lld\n",
3559                         length, BNXT_RE_MAX_MR_SIZE);
3560                 return ERR_PTR(-ENOMEM);
3561         }
3562
3563         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3564         if (!mr)
3565                 return ERR_PTR(-ENOMEM);
3566
3567         mr->rdev = rdev;
3568         mr->qplib_mr.pd = &pd->qplib_pd;
3569         mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3570         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3571
3572         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3573         if (rc) {
3574                 dev_err(rdev_to_dev(rdev), "Failed to allocate MR");
3575                 goto free_mr;
3576         }
3577         /* The fixed portion of the rkey is the same as the lkey */
3578         mr->ib_mr.rkey = mr->qplib_mr.rkey;
3579
3580         umem = ib_umem_get(udata, start, length, mr_access_flags, 0);
3581         if (IS_ERR(umem)) {
3582                 dev_err(rdev_to_dev(rdev), "Failed to get umem");
3583                 rc = -EFAULT;
3584                 goto free_mrw;
3585         }
3586         mr->ib_umem = umem;
3587
3588         mr->qplib_mr.va = virt_addr;
3589         umem_pgs = ib_umem_page_count(umem);
3590         if (!umem_pgs) {
3591                 dev_err(rdev_to_dev(rdev), "umem is invalid!");
3592                 rc = -EINVAL;
3593                 goto free_umem;
3594         }
3595         mr->qplib_mr.total_size = length;
3596
3597         pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
3598         if (!pbl_tbl) {
3599                 rc = -ENOMEM;
3600                 goto free_umem;
3601         }
3602
3603         page_shift = PAGE_SHIFT;
3604
3605         if (!bnxt_re_page_size_ok(page_shift)) {
3606                 dev_err(rdev_to_dev(rdev), "umem page size unsupported!");
3607                 rc = -EFAULT;
3608                 goto fail;
3609         }
3610
3611         if (!umem->hugetlb && length > BNXT_RE_MAX_MR_SIZE_LOW) {
3612                 dev_err(rdev_to_dev(rdev), "Requested MR Sz:%llu Max sup:%llu",
3613                         length, (u64)BNXT_RE_MAX_MR_SIZE_LOW);
3614                 rc = -EINVAL;
3615                 goto fail;
3616         }
3617         if (umem->hugetlb && length > BNXT_RE_PAGE_SIZE_2M) {
3618                 page_shift = BNXT_RE_PAGE_SHIFT_2M;
3619                 dev_warn(rdev_to_dev(rdev), "umem hugetlb set page_size %x",
3620                          1 << page_shift);
3621         }
3622
3623         /* Map umem buf ptrs to the PBL */
3624         umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift);
3625         rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl,
3626                                umem_pgs, false, 1 << page_shift);
3627         if (rc) {
3628                 dev_err(rdev_to_dev(rdev), "Failed to register user MR");
3629                 goto fail;
3630         }
3631
3632         kfree(pbl_tbl);
3633
3634         mr->ib_mr.lkey = mr->qplib_mr.lkey;
3635         mr->ib_mr.rkey = mr->qplib_mr.lkey;
3636         atomic_inc(&rdev->mr_count);
3637
3638         return &mr->ib_mr;
3639 fail:
3640         kfree(pbl_tbl);
3641 free_umem:
3642         ib_umem_release(umem);
3643 free_mrw:
3644         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3645 free_mr:
3646         kfree(mr);
3647         return ERR_PTR(rc);
3648 }
3649
3650 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
3651 {
3652         struct ib_device *ibdev = ctx->device;
3653         struct bnxt_re_ucontext *uctx =
3654                 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
3655         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3656         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3657         struct bnxt_re_uctx_resp resp;
3658         u32 chip_met_rev_num = 0;
3659         int rc;
3660
3661         dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
3662                 ibdev->uverbs_abi_ver);
3663
3664         if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3665                 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ",
3666                         BNXT_RE_ABI_VERSION);
3667                 return -EPERM;
3668         }
3669
3670         uctx->rdev = rdev;
3671
3672         uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3673         if (!uctx->shpg) {
3674                 rc = -ENOMEM;
3675                 goto fail;
3676         }
3677         spin_lock_init(&uctx->sh_lock);
3678
3679         resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
3680         chip_met_rev_num = rdev->chip_ctx.chip_num;
3681         chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_rev & 0xFF) <<
3682                              BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
3683         chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_metal & 0xFF) <<
3684                              BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
3685         resp.chip_id0 = chip_met_rev_num;
3686         /* Future extension of chip info */
3687         resp.chip_id1 = 0;
3688         /*Temp, Use idr_alloc instead */
3689         resp.dev_id = rdev->en_dev->pdev->devfn;
3690         resp.max_qp = rdev->qplib_ctx.qpc_count;
3691         resp.pg_size = PAGE_SIZE;
3692         resp.cqe_sz = sizeof(struct cq_base);
3693         resp.max_cqd = dev_attr->max_cq_wqes;
3694         resp.rsvd    = 0;
3695
3696         rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
3697         if (rc) {
3698                 dev_err(rdev_to_dev(rdev), "Failed to copy user context");
3699                 rc = -EFAULT;
3700                 goto cfail;
3701         }
3702
3703         return 0;
3704 cfail:
3705         free_page((unsigned long)uctx->shpg);
3706         uctx->shpg = NULL;
3707 fail:
3708         return rc;
3709 }
3710
3711 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3712 {
3713         struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3714                                                    struct bnxt_re_ucontext,
3715                                                    ib_uctx);
3716
3717         struct bnxt_re_dev *rdev = uctx->rdev;
3718
3719         if (uctx->shpg)
3720                 free_page((unsigned long)uctx->shpg);
3721
3722         if (uctx->dpi.dbr) {
3723                 /* Free DPI only if this is the first PD allocated by the
3724                  * application and mark the context dpi as NULL
3725                  */
3726                 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3727                                        &rdev->qplib_res.dpi_tbl, &uctx->dpi);
3728                 uctx->dpi.dbr = NULL;
3729         }
3730 }
3731
3732 /* Helper function to mmap the virtual memory from user app */
3733 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3734 {
3735         struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3736                                                    struct bnxt_re_ucontext,
3737                                                    ib_uctx);
3738         struct bnxt_re_dev *rdev = uctx->rdev;
3739         u64 pfn;
3740
3741         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3742                 return -EINVAL;
3743
3744         if (vma->vm_pgoff) {
3745                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3746                 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3747                                        PAGE_SIZE, vma->vm_page_prot)) {
3748                         dev_err(rdev_to_dev(rdev), "Failed to map DPI");
3749                         return -EAGAIN;
3750                 }
3751         } else {
3752                 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3753                 if (remap_pfn_range(vma, vma->vm_start,
3754                                     pfn, PAGE_SIZE, vma->vm_page_prot)) {
3755                         dev_err(rdev_to_dev(rdev),
3756                                 "Failed to map shared page");
3757                         return -EAGAIN;
3758                 }
3759         }
3760
3761         return 0;
3762 }