drivers/iio/frequency/adf4350.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ADF4350/ADF4351 SPI Wideband Synthesizer driver
   4  *
   5  * Copyright 2012-2013 Analog Devices Inc.
   6  */
   7
   8 #include <linux/device.h>
   9 #include <linux/kernel.h>
  10 #include <linux/slab.h>
  11 #include <linux/sysfs.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/regulator/consumer.h>
  14 #include <linux/err.h>
  15 #include <linux/module.h>
  16 #include <linux/gcd.h>
  17 #include <linux/gpio/consumer.h>
  18 #include <asm/div64.h>
  19 #include <linux/clk.h>
  20 #include <linux/of.h>
  21
  22 #include <linux/iio/iio.h>
  23 #include <linux/iio/sysfs.h>
  24 #include <linux/iio/frequency/adf4350.h>
  25
  26 enum {
  27         ADF4350_FREQ,
  28         ADF4350_FREQ_REFIN,
  29         ADF4350_FREQ_RESOLUTION,
  30         ADF4350_PWRDOWN,
  31 };
  32
  33 struct adf4350_state {
  34         struct spi_device               *spi;
  35         struct regulator                *reg;
  36         struct gpio_desc                *lock_detect_gpiod;
  37         struct adf4350_platform_data    *pdata;
  38         struct clk                      *clk;
  39         unsigned long                   clkin;
  40         unsigned long                   chspc; /* Channel Spacing */
  41         unsigned long                   fpfd; /* Phase Frequency Detector */
  42         unsigned long                   min_out_freq;
  43         unsigned                        r0_fract;
  44         unsigned                        r0_int;
  45         unsigned                        r1_mod;
  46         unsigned                        r4_rf_div_sel;
  47         unsigned long                   regs[6];
  48         unsigned long                   regs_hw[6];
  49         unsigned long long              freq_req;
  50         /*
  51          * Lock to protect the state of the device from potential concurrent
  52          * writes. The device is configured via a sequence of SPI writes,
  53          * and this lock is meant to prevent the start of another sequence
  54          * before another one has finished.
  55          */
  56         struct mutex                    lock;
  57         /*
  58          * DMA (thus cache coherency maintenance) requires the
  59          * transfer buffers to live in their own cache lines.
  60          */
  61         __be32                          val ____cacheline_aligned;
  62 };
  63
  64 static struct adf4350_platform_data default_pdata = {
  65         .channel_spacing = 10000,
  66         .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
  67                             ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
  68         .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
  69         .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
  70                             ADF4350_REG4_MUTE_TILL_LOCK_EN,
  71 };
  72
  73 static int adf4350_sync_config(struct adf4350_state *st)
  74 {
  75         int ret, i, doublebuf = 0;
  76
  77         for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
  78                 if ((st->regs_hw[i] != st->regs[i]) ||
  79                         ((i == ADF4350_REG0) && doublebuf)) {
  80                         switch (i) {
  81                         case ADF4350_REG1:
  82                         case ADF4350_REG4:
  83                                 doublebuf = 1;
  84                                 break;
  85                         }
  86
  87                         st->val  = cpu_to_be32(st->regs[i] | i);
  88                         ret = spi_write(st->spi, &st->val, 4);
  89                         if (ret < 0)
  90                                 return ret;
  91                         st->regs_hw[i] = st->regs[i];
  92                         dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
  93                                 i, (u32)st->regs[i] | i);
  94                 }
  95         }
  96         return 0;
  97 }
  98
  99 static int adf4350_reg_access(struct iio_dev *indio_dev,
 100                               unsigned reg, unsigned writeval,
 101                               unsigned *readval)
 102 {
 103         struct adf4350_state *st = iio_priv(indio_dev);
 104         int ret;
 105
 106         if (reg > ADF4350_REG5)
 107                 return -EINVAL;
 108
 109         mutex_lock(&st->lock);
 110         if (readval == NULL) {
 111                 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
 112                 ret = adf4350_sync_config(st);
 113         } else {
 114                 *readval =  st->regs_hw[reg];
 115                 ret = 0;
 116         }
 117         mutex_unlock(&st->lock);
 118
 119         return ret;
 120 }
 121
 122 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
 123 {
 124         struct adf4350_platform_data *pdata = st->pdata;
 125
 126         do {
 127                 r_cnt++;
 128                 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
 129                            (r_cnt * (pdata->ref_div2_en ? 2 : 1));
 130         } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
 131
 132         return r_cnt;
 133 }
 134
 135 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
 136 {
 137         struct adf4350_platform_data *pdata = st->pdata;
 138         u64 tmp;
 139         u32 div_gcd, prescaler, chspc;
 140         u16 mdiv, r_cnt = 0;
 141         u8 band_sel_div;
 142
 143         if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
 144                 return -EINVAL;
 145
 146         if (freq > ADF4350_MAX_FREQ_45_PRESC) {
 147                 prescaler = ADF4350_REG1_PRESCALER;
 148                 mdiv = 75;
 149         } else {
 150                 prescaler = 0;
 151                 mdiv = 23;
 152         }
 153
 154         st->r4_rf_div_sel = 0;
 155
 156         while (freq < ADF4350_MIN_VCO_FREQ) {
 157                 freq <<= 1;
 158                 st->r4_rf_div_sel++;
 159         }
 160
 161         /*
 162          * Allow a predefined reference division factor
 163          * if not set, compute our own
 164          */
 165         if (pdata->ref_div_factor)
 166                 r_cnt = pdata->ref_div_factor - 1;
 167
 168         chspc = st->chspc;
 169
 170         do  {
 171                 do {
 172                         do {
 173                                 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
 174                                 st->r1_mod = st->fpfd / chspc;
 175                                 if (r_cnt > ADF4350_MAX_R_CNT) {
 176                                         /* try higher spacing values */
 177                                         chspc++;
 178                                         r_cnt = 0;
 179                                 }
 180                         } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
 181                 } while (r_cnt == 0);
 182
 183                 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
 184                 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
 185                 st->r0_fract = do_div(tmp, st->r1_mod);
 186                 st->r0_int = tmp;
 187         } while (mdiv > st->r0_int);
 188
 189         band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
 190
 191         if (st->r0_fract && st->r1_mod) {
 192                 div_gcd = gcd(st->r1_mod, st->r0_fract);
 193                 st->r1_mod /= div_gcd;
 194                 st->r0_fract /= div_gcd;
 195         } else {
 196                 st->r0_fract = 0;
 197                 st->r1_mod = 1;
 198         }
 199
 200         dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
 201                 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
 202                 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
 203                 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
 204                 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
 205                 band_sel_div);
 206
 207         st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
 208                                  ADF4350_REG0_FRACT(st->r0_fract);
 209
 210         st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
 211                                  ADF4350_REG1_MOD(st->r1_mod) |
 212                                  prescaler;
 213
 214         st->regs[ADF4350_REG2] =
 215                 ADF4350_REG2_10BIT_R_CNT(r_cnt) |
 216                 ADF4350_REG2_DOUBLE_BUFF_EN |
 217                 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
 218                 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
 219                 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
 220                 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
 221                 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
 222                 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
 223
 224         st->regs[ADF4350_REG3] = pdata->r3_user_settings &
 225                                  (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
 226                                  ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
 227                                  ADF4350_REG3_12BIT_CSR_EN |
 228                                  ADF4351_REG3_CHARGE_CANCELLATION_EN |
 229                                  ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
 230                                  ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
 231
 232         st->regs[ADF4350_REG4] =
 233                 ADF4350_REG4_FEEDBACK_FUND |
 234                 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
 235                 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
 236                 ADF4350_REG4_RF_OUT_EN |
 237                 (pdata->r4_user_settings &
 238                 (ADF4350_REG4_OUTPUT_PWR(0x3) |
 239                 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
 240                 ADF4350_REG4_AUX_OUTPUT_EN |
 241                 ADF4350_REG4_AUX_OUTPUT_FUND |
 242                 ADF4350_REG4_MUTE_TILL_LOCK_EN));
 243
 244         st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
 245         st->freq_req = freq;
 246
 247         return adf4350_sync_config(st);
 248 }
 249
 250 static ssize_t adf4350_write(struct iio_dev *indio_dev,
 251                                     uintptr_t private,
 252                                     const struct iio_chan_spec *chan,
 253                                     const char *buf, size_t len)
 254 {
 255         struct adf4350_state *st = iio_priv(indio_dev);
 256         unsigned long long readin;
 257         unsigned long tmp;
 258         int ret;
 259
 260         ret = kstrtoull(buf, 10, &readin);
 261         if (ret)
 262                 return ret;
 263
 264         mutex_lock(&st->lock);
 265         switch ((u32)private) {
 266         case ADF4350_FREQ:
 267                 ret = adf4350_set_freq(st, readin);
 268                 break;
 269         case ADF4350_FREQ_REFIN:
 270                 if (readin > ADF4350_MAX_FREQ_REFIN) {
 271                         ret = -EINVAL;
 272                         break;
 273                 }
 274
 275                 if (st->clk) {
 276                         tmp = clk_round_rate(st->clk, readin);
 277                         if (tmp != readin) {
 278                                 ret = -EINVAL;
 279                                 break;
 280                         }
 281                         ret = clk_set_rate(st->clk, tmp);
 282                         if (ret < 0)
 283                                 break;
 284                 }
 285                 st->clkin = readin;
 286                 ret = adf4350_set_freq(st, st->freq_req);
 287                 break;
 288         case ADF4350_FREQ_RESOLUTION:
 289                 if (readin == 0)
 290                         ret = -EINVAL;
 291                 else
 292                         st->chspc = readin;
 293                 break;
 294         case ADF4350_PWRDOWN:
 295                 if (readin)
 296                         st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
 297                 else
 298                         st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
 299
 300                 adf4350_sync_config(st);
 301                 break;
 302         default:
 303                 ret = -EINVAL;
 304         }
 305         mutex_unlock(&st->lock);
 306
 307         return ret ? ret : len;
 308 }
 309
 310 static ssize_t adf4350_read(struct iio_dev *indio_dev,
 311                                    uintptr_t private,
 312                                    const struct iio_chan_spec *chan,
 313                                    char *buf)
 314 {
 315         struct adf4350_state *st = iio_priv(indio_dev);
 316         unsigned long long val;
 317         int ret = 0;
 318
 319         mutex_lock(&st->lock);
 320         switch ((u32)private) {
 321         case ADF4350_FREQ:
 322                 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
 323                         (u64)st->fpfd;
 324                 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
 325                 /* PLL unlocked? return error */
 326                 if (st->lock_detect_gpiod)
 327                         if (!gpiod_get_value(st->lock_detect_gpiod)) {
 328                                 dev_dbg(&st->spi->dev, "PLL un-locked\n");
 329                                 ret = -EBUSY;
 330                         }
 331                 break;
 332         case ADF4350_FREQ_REFIN:
 333                 if (st->clk)
 334                         st->clkin = clk_get_rate(st->clk);
 335
 336                 val = st->clkin;
 337                 break;
 338         case ADF4350_FREQ_RESOLUTION:
 339                 val = st->chspc;
 340                 break;
 341         case ADF4350_PWRDOWN:
 342                 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
 343                 break;
 344         default:
 345                 ret = -EINVAL;
 346                 val = 0;
 347         }
 348         mutex_unlock(&st->lock);
 349
 350         return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
 351 }
 352
 353 #define _ADF4350_EXT_INFO(_name, _ident) { \
 354         .name = _name, \
 355         .read = adf4350_read, \
 356         .write = adf4350_write, \
 357         .private = _ident, \
 358         .shared = IIO_SEPARATE, \
 359 }
 360
 361 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
 362         /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
 363          * values > 2^32 in order to support the entire frequency range
 364          * in Hz. Using scale is a bit ugly.
 365          */
 366         _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
 367         _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
 368         _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
 369         _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
 370         { },
 371 };
 372
 373 static const struct iio_chan_spec adf4350_chan = {
 374         .type = IIO_ALTVOLTAGE,
 375         .indexed = 1,
 376         .output = 1,
 377         .ext_info = adf4350_ext_info,
 378 };
 379
 380 static const struct iio_info adf4350_info = {
 381         .debugfs_reg_access = &adf4350_reg_access,
 382 };
 383
 384 #ifdef CONFIG_OF
 385 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
 386 {
 387         struct device_node *np = dev->of_node;
 388         struct adf4350_platform_data *pdata;
 389         unsigned int tmp;
 390
 391         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 392         if (!pdata)
 393                 return NULL;
 394
 395         snprintf(&pdata->name[0], SPI_NAME_SIZE - 1, "%pOFn", np);
 396
 397         tmp = 10000;
 398         of_property_read_u32(np, "adi,channel-spacing", &tmp);
 399         pdata->channel_spacing = tmp;
 400
 401         tmp = 0;
 402         of_property_read_u32(np, "adi,power-up-frequency", &tmp);
 403         pdata->power_up_frequency = tmp;
 404
 405         tmp = 0;
 406         of_property_read_u32(np, "adi,reference-div-factor", &tmp);
 407         pdata->ref_div_factor = tmp;
 408
 409         pdata->ref_doubler_en = of_property_read_bool(np,
 410                         "adi,reference-doubler-enable");
 411         pdata->ref_div2_en = of_property_read_bool(np,
 412                         "adi,reference-div2-enable");
 413
 414         /* r2_user_settings */
 415         pdata->r2_user_settings = of_property_read_bool(np,
 416                         "adi,phase-detector-polarity-positive-enable") ?
 417                         ADF4350_REG2_PD_POLARITY_POS : 0;
 418         pdata->r2_user_settings |= of_property_read_bool(np,
 419                         "adi,lock-detect-precision-6ns-enable") ?
 420                         ADF4350_REG2_LDP_6ns : 0;
 421         pdata->r2_user_settings |= of_property_read_bool(np,
 422                         "adi,lock-detect-function-integer-n-enable") ?
 423                         ADF4350_REG2_LDF_INT_N : 0;
 424
 425         tmp = 2500;
 426         of_property_read_u32(np, "adi,charge-pump-current", &tmp);
 427         pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
 428
 429         tmp = 0;
 430         of_property_read_u32(np, "adi,muxout-select", &tmp);
 431         pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);
 432
 433         pdata->r2_user_settings |= of_property_read_bool(np,
 434                         "adi,low-spur-mode-enable") ?
 435                         ADF4350_REG2_NOISE_MODE(0x3) : 0;
 436
 437         /* r3_user_settings */
 438
 439         pdata->r3_user_settings = of_property_read_bool(np,
 440                         "adi,cycle-slip-reduction-enable") ?
 441                         ADF4350_REG3_12BIT_CSR_EN : 0;
 442         pdata->r3_user_settings |= of_property_read_bool(np,
 443                         "adi,charge-cancellation-enable") ?
 444                         ADF4351_REG3_CHARGE_CANCELLATION_EN : 0;
 445
 446         pdata->r3_user_settings |= of_property_read_bool(np,
 447                         "adi,anti-backlash-3ns-enable") ?
 448                         ADF4351_REG3_ANTI_BACKLASH_3ns_EN : 0;
 449         pdata->r3_user_settings |= of_property_read_bool(np,
 450                         "adi,band-select-clock-mode-high-enable") ?
 451                         ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH : 0;
 452
 453         tmp = 0;
 454         of_property_read_u32(np, "adi,12bit-clk-divider", &tmp);
 455         pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);
 456
 457         tmp = 0;
 458         of_property_read_u32(np, "adi,clk-divider-mode", &tmp);
 459         pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
 460
 461         /* r4_user_settings */
 462
 463         pdata->r4_user_settings = of_property_read_bool(np,
 464                         "adi,aux-output-enable") ?
 465                         ADF4350_REG4_AUX_OUTPUT_EN : 0;
 466         pdata->r4_user_settings |= of_property_read_bool(np,
 467                         "adi,aux-output-fundamental-enable") ?
 468                         ADF4350_REG4_AUX_OUTPUT_FUND : 0;
 469         pdata->r4_user_settings |= of_property_read_bool(np,
 470                         "adi,mute-till-lock-enable") ?
 471                         ADF4350_REG4_MUTE_TILL_LOCK_EN : 0;
 472
 473         tmp = 0;
 474         of_property_read_u32(np, "adi,output-power", &tmp);
 475         pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);
 476
 477         tmp = 0;
 478         of_property_read_u32(np, "adi,aux-output-power", &tmp);
 479         pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
 480
 481         return pdata;
 482 }
 483 #else
 484 static
 485 struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
 486 {
 487         return NULL;
 488 }
 489 #endif
 490
 491 static int adf4350_probe(struct spi_device *spi)
 492 {
 493         struct adf4350_platform_data *pdata;
 494         struct iio_dev *indio_dev;
 495         struct adf4350_state *st;
 496         struct clk *clk = NULL;
 497         int ret;
 498
 499         if (spi->dev.of_node) {
 500                 pdata = adf4350_parse_dt(&spi->dev);
 501                 if (pdata == NULL)
 502                         return -EINVAL;
 503         } else {
 504                 pdata = spi->dev.platform_data;
 505         }
 506
 507         if (!pdata) {
 508                 dev_warn(&spi->dev, "no platform data? using default\n");
 509                 pdata = &default_pdata;
 510         }
 511
 512         if (!pdata->clkin) {
 513                 clk = devm_clk_get(&spi->dev, "clkin");
 514                 if (IS_ERR(clk))
 515                         return -EPROBE_DEFER;
 516
 517                 ret = clk_prepare_enable(clk);
 518                 if (ret < 0)
 519                         return ret;
 520         }
 521
 522         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 523         if (indio_dev == NULL) {
 524                 ret =  -ENOMEM;
 525                 goto error_disable_clk;
 526         }
 527
 528         st = iio_priv(indio_dev);
 529
 530         st->reg = devm_regulator_get(&spi->dev, "vcc");
 531         if (!IS_ERR(st->reg)) {
 532                 ret = regulator_enable(st->reg);
 533                 if (ret)
 534                         goto error_disable_clk;
 535         }
 536
 537         spi_set_drvdata(spi, indio_dev);
 538         st->spi = spi;
 539         st->pdata = pdata;
 540
 541         indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
 542                 spi_get_device_id(spi)->name;
 543
 544         indio_dev->info = &adf4350_info;
 545         indio_dev->modes = INDIO_DIRECT_MODE;
 546         indio_dev->channels = &adf4350_chan;
 547         indio_dev->num_channels = 1;
 548
 549         mutex_init(&st->lock);
 550
 551         st->chspc = pdata->channel_spacing;
 552         if (clk) {
 553                 st->clk = clk;
 554                 st->clkin = clk_get_rate(clk);
 555         } else {
 556                 st->clkin = pdata->clkin;
 557         }
 558
 559         st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
 560                 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
 561
 562         memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
 563
 564         st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
 565                                                         GPIOD_IN);
 566         if (IS_ERR(st->lock_detect_gpiod)) {
 567                 ret = PTR_ERR(st->lock_detect_gpiod);
 568                 goto error_disable_reg;
 569         }
 570
 571         if (pdata->power_up_frequency) {
 572                 ret = adf4350_set_freq(st, pdata->power_up_frequency);
 573                 if (ret)
 574                         goto error_disable_reg;
 575         }
 576
 577         ret = iio_device_register(indio_dev);
 578         if (ret)
 579                 goto error_disable_reg;
 580
 581         return 0;
 582
 583 error_disable_reg:
 584         if (!IS_ERR(st->reg))
 585                 regulator_disable(st->reg);
 586 error_disable_clk:
 587         clk_disable_unprepare(clk);
 588
 589         return ret;
 590 }
 591
 592 static void adf4350_remove(struct spi_device *spi)
 593 {
 594         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 595         struct adf4350_state *st = iio_priv(indio_dev);
 596         struct regulator *reg = st->reg;
 597
 598         st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
 599         adf4350_sync_config(st);
 600
 601         iio_device_unregister(indio_dev);
 602
 603         clk_disable_unprepare(st->clk);
 604
 605         if (!IS_ERR(reg))
 606                 regulator_disable(reg);
 607 }
 608
 609 static const struct of_device_id adf4350_of_match[] = {
 610         { .compatible = "adi,adf4350", },
 611         { .compatible = "adi,adf4351", },
 612         { /* sentinel */ },
 613 };
 614 MODULE_DEVICE_TABLE(of, adf4350_of_match);
 615
 616 static const struct spi_device_id adf4350_id[] = {
 617         {"adf4350", 4350},
 618         {"adf4351", 4351},
 619         {}
 620 };
 621 MODULE_DEVICE_TABLE(spi, adf4350_id);
 622
 623 static struct spi_driver adf4350_driver = {
 624         .driver = {
 625                 .name   = "adf4350",
 626                 .of_match_table = of_match_ptr(adf4350_of_match),
 627         },
 628         .probe          = adf4350_probe,
 629         .remove         = adf4350_remove,
 630         .id_table       = adf4350_id,
 631 };
 632 module_spi_driver(adf4350_driver);
 633
 634 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
 635 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
 636 MODULE_LICENSE("GPL v2");