2 * Driver for the Renesas R-Car I2C unit
4 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
5 * Copyright (C) 2011-2015 Renesas Electronics Corporation
7 * Copyright (C) 2012-14 Renesas Solutions Corp.
8 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
11 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/of_device.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/slab.h>
37 /* register offsets */
38 #define ICSCR 0x00 /* slave ctrl */
39 #define ICMCR 0x04 /* master ctrl */
40 #define ICSSR 0x08 /* slave status */
41 #define ICMSR 0x0C /* master status */
42 #define ICSIER 0x10 /* slave irq enable */
43 #define ICMIER 0x14 /* master irq enable */
44 #define ICCCR 0x18 /* clock dividers */
45 #define ICSAR 0x1C /* slave address */
46 #define ICMAR 0x20 /* master address */
47 #define ICRXTX 0x24 /* data port */
48 #define ICDMAER 0x3c /* DMA enable */
49 #define ICFBSCR 0x38 /* first bit setup cycle */
52 #define SDBS (1 << 3) /* slave data buffer select */
53 #define SIE (1 << 2) /* slave interface enable */
54 #define GCAE (1 << 1) /* general call address enable */
55 #define FNA (1 << 0) /* forced non acknowledgment */
58 #define MDBS (1 << 7) /* non-fifo mode switch */
59 #define FSCL (1 << 6) /* override SCL pin */
60 #define FSDA (1 << 5) /* override SDA pin */
61 #define OBPC (1 << 4) /* override pins */
62 #define MIE (1 << 3) /* master if enable */
64 #define FSB (1 << 1) /* force stop bit */
65 #define ESG (1 << 0) /* enable start bit gen */
67 /* ICSSR (also for ICSIER) */
68 #define GCAR (1 << 6) /* general call received */
69 #define STM (1 << 5) /* slave transmit mode */
70 #define SSR (1 << 4) /* stop received */
71 #define SDE (1 << 3) /* slave data empty */
72 #define SDT (1 << 2) /* slave data transmitted */
73 #define SDR (1 << 1) /* slave data received */
74 #define SAR (1 << 0) /* slave addr received */
76 /* ICMSR (also for ICMIE) */
77 #define MNR (1 << 6) /* nack received */
78 #define MAL (1 << 5) /* arbitration lost */
79 #define MST (1 << 4) /* sent a stop */
83 #define MAT (1 << 0) /* slave addr xfer done */
86 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */
87 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
88 #define RMDMAE (1 << 1) /* DMA Master Received Enable */
89 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
92 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
93 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
96 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
97 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
98 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
99 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
101 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
102 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
103 #define RCAR_IRQ_STOP (MST)
105 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F)
106 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F)
108 #define ID_LAST_MSG (1 << 0)
109 #define ID_FIRST_MSG (1 << 1)
110 #define ID_DONE (1 << 2)
111 #define ID_ARBLOST (1 << 3)
112 #define ID_NACK (1 << 4)
113 /* persistent flags */
114 #define ID_P_PM_BLOCKED (1 << 31)
115 #define ID_P_MASK ID_P_PM_BLOCKED
123 struct rcar_i2c_priv {
125 struct i2c_adapter adap;
130 wait_queue_head_t wait;
135 u8 recovery_icmcr; /* protected by adapter lock */
136 enum rcar_i2c_type devtype;
137 struct i2c_client *slave;
139 struct resource *res;
140 struct dma_chan *dma_tx;
141 struct dma_chan *dma_rx;
142 struct scatterlist sg;
143 enum dma_data_direction dma_direction;
146 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
147 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
149 #define LOOP_TIMEOUT 1024
152 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
154 writel(val, priv->io + reg);
157 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
159 return readl(priv->io + reg);
162 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
164 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
166 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
170 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
172 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
175 priv->recovery_icmcr |= FSCL;
177 priv->recovery_icmcr &= ~FSCL;
179 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
182 /* No get_sda, because the HW only reports its bus free logic, not SDA itself */
184 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
186 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
189 priv->recovery_icmcr |= FSDA;
191 priv->recovery_icmcr &= ~FSDA;
193 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
196 static struct i2c_bus_recovery_info rcar_i2c_bri = {
197 .get_scl = rcar_i2c_get_scl,
198 .set_scl = rcar_i2c_set_scl,
199 .set_sda = rcar_i2c_set_sda,
200 .recover_bus = i2c_generic_scl_recovery,
202 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
204 /* reset master mode */
205 rcar_i2c_write(priv, ICMIER, 0);
206 rcar_i2c_write(priv, ICMCR, MDBS);
207 rcar_i2c_write(priv, ICMSR, 0);
209 rcar_i2c_write(priv, ICCCR, priv->icccr);
212 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
216 for (i = 0; i < LOOP_TIMEOUT; i++) {
217 /* make sure that bus is not busy */
218 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
223 /* Waiting did not help, try to recover */
224 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
225 ret = i2c_recover_bus(&priv->adap);
227 /* No failure when recovering, so check bus busy bit again */
229 ret = (rcar_i2c_read(priv, ICMCR) & FSDA) ? -EBUSY : 0;
234 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
236 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
238 struct device *dev = rcar_i2c_priv_to_dev(priv);
240 /* Fall back to previously used values if not supplied */
241 t->bus_freq_hz = t->bus_freq_hz ?: 100000;
242 t->scl_fall_ns = t->scl_fall_ns ?: 35;
243 t->scl_rise_ns = t->scl_rise_ns ?: 200;
244 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
246 switch (priv->devtype) {
255 dev_err(dev, "device type error\n");
260 * calculate SCL clock
264 * ick = clkp / (1 + CDF)
265 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
267 * ick : I2C internal clock < 20 MHz
268 * ticf : I2C SCL falling time
269 * tr : I2C SCL rising time
270 * intd : LSI internal delay
271 * clkp : peripheral_clk
272 * F[] : integer up-valuation
274 rate = clk_get_rate(priv->clk);
275 cdf = rate / 20000000;
276 if (cdf >= 1U << cdf_width) {
277 dev_err(dev, "Input clock %lu too high\n", rate);
280 ick = rate / (cdf + 1);
283 * it is impossible to calculate large scale
284 * number on u32. separate it
286 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
287 * = F[sum * ick / 1000000000]
288 * = F[(ick / 1000000) * sum / 1000]
290 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
291 round = (ick + 500000) / 1000000 * sum;
292 round = (round + 500) / 1000;
295 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
297 * Calculation result (= SCL) should be less than
298 * bus_speed for hardware safety
300 * We could use something along the lines of
301 * div = ick / (bus_speed + 1) + 1;
302 * scgd = (div - 20 - round + 7) / 8;
303 * scl = ick / (20 + (scgd * 8) + round);
304 * (not fully verified) but that would get pretty involved
306 for (scgd = 0; scgd < 0x40; scgd++) {
307 scl = ick / (20 + (scgd * 8) + round);
308 if (scl <= t->bus_freq_hz)
311 dev_err(dev, "it is impossible to calculate best SCL\n");
315 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
316 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
318 /* keep icccr value */
319 priv->icccr = scgd << cdf_width | cdf;
324 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
326 int read = !!rcar_i2c_is_recv(priv);
329 if (priv->msgs_left == 1)
330 priv->flags |= ID_LAST_MSG;
332 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
334 * We don't have a test case but the HW engineers say that the write order
335 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
336 * it didn't cause a drawback for me, let's rather be safe than sorry.
338 if (priv->flags & ID_FIRST_MSG) {
339 rcar_i2c_write(priv, ICMSR, 0);
340 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
342 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
343 rcar_i2c_write(priv, ICMSR, 0);
345 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
348 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
352 priv->flags &= ID_P_MASK;
353 rcar_i2c_prepare_msg(priv);
357 * interrupt functions
359 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
361 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
362 ? priv->dma_rx : priv->dma_tx;
364 /* Disable DMA Master Received/Transmitted */
365 rcar_i2c_write(priv, ICDMAER, 0);
367 /* Reset default delay */
368 rcar_i2c_write(priv, ICFBSCR, TCYC06);
370 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
371 sg_dma_len(&priv->sg), priv->dma_direction);
373 priv->dma_direction = DMA_NONE;
376 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
378 if (priv->dma_direction == DMA_NONE)
380 else if (priv->dma_direction == DMA_FROM_DEVICE)
381 dmaengine_terminate_all(priv->dma_rx);
382 else if (priv->dma_direction == DMA_TO_DEVICE)
383 dmaengine_terminate_all(priv->dma_tx);
385 rcar_i2c_dma_unmap(priv);
388 static void rcar_i2c_dma_callback(void *data)
390 struct rcar_i2c_priv *priv = data;
392 priv->pos += sg_dma_len(&priv->sg);
394 rcar_i2c_dma_unmap(priv);
397 static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
399 struct device *dev = rcar_i2c_priv_to_dev(priv);
400 struct i2c_msg *msg = priv->msg;
401 bool read = msg->flags & I2C_M_RD;
402 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
403 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
404 struct dma_async_tx_descriptor *txdesc;
410 /* Do not use DMA if it's not available or for messages < 8 bytes */
411 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE))
416 * The last two bytes needs to be fetched using PIO in
417 * order for the STOP phase to work.
419 buf = priv->msg->buf;
420 len = priv->msg->len - 2;
423 * First byte in message was sent using PIO.
425 buf = priv->msg->buf + 1;
426 len = priv->msg->len - 1;
429 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
430 if (dma_mapping_error(chan->device->dev, dma_addr)) {
431 dev_dbg(dev, "dma map failed, using PIO\n");
435 sg_dma_len(&priv->sg) = len;
436 sg_dma_address(&priv->sg) = dma_addr;
438 priv->dma_direction = dir;
440 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
441 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
442 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
444 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
445 rcar_i2c_cleanup_dma(priv);
449 txdesc->callback = rcar_i2c_dma_callback;
450 txdesc->callback_param = priv;
452 cookie = dmaengine_submit(txdesc);
453 if (dma_submit_error(cookie)) {
454 dev_dbg(dev, "submitting dma failed, using PIO\n");
455 rcar_i2c_cleanup_dma(priv);
459 /* Set delay for DMA operations */
460 rcar_i2c_write(priv, ICFBSCR, TCYC17);
462 /* Enable DMA Master Received/Transmitted */
464 rcar_i2c_write(priv, ICDMAER, RMDMAE);
466 rcar_i2c_write(priv, ICDMAER, TMDMAE);
468 dma_async_issue_pending(chan);
471 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
473 struct i2c_msg *msg = priv->msg;
475 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
479 if (priv->pos < msg->len) {
481 * Prepare next data to ICRXTX register.
482 * This data will go to _SHIFT_ register.
485 * [ICRXTX] -> [SHIFT] -> [I2C bus]
487 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
491 * Try to use DMA to transmit the rest of the data if
492 * address transfer phase just finished.
498 * The last data was pushed to ICRXTX on _PREV_ empty irq.
499 * It is on _SHIFT_ register, and will sent to I2C bus.
502 * [ICRXTX] -> [SHIFT] -> [I2C bus]
505 if (priv->flags & ID_LAST_MSG) {
507 * If current msg is the _LAST_ msg,
508 * prepare stop condition here.
509 * ID_DONE will be set on STOP irq.
511 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
513 rcar_i2c_next_msg(priv);
518 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
521 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
523 struct i2c_msg *msg = priv->msg;
525 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
531 * Address transfer phase finished, but no data at this point.
532 * Try to use DMA to receive data.
535 } else if (priv->pos < msg->len) {
536 /* get received data */
537 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
542 * If next received data is the _LAST_, go to STOP phase. Might be
543 * overwritten by REP START when setting up a new msg. Not elegant
544 * but the only stable sequence for REP START I have found so far.
545 * If you want to change this code, make sure sending one transfer with
546 * four messages (WR-RD-WR-RD) works!
548 if (priv->pos + 1 >= msg->len)
549 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
551 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
552 rcar_i2c_next_msg(priv);
554 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
557 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
559 u32 ssr_raw, ssr_filtered;
562 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
563 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
568 /* address detected */
569 if (ssr_filtered & SAR) {
570 /* read or write request */
572 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
573 rcar_i2c_write(priv, ICRXTX, value);
574 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
576 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
577 rcar_i2c_read(priv, ICRXTX); /* dummy read */
578 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
581 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
584 /* master sent stop */
585 if (ssr_filtered & SSR) {
586 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
587 rcar_i2c_write(priv, ICSIER, SAR | SSR);
588 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
591 /* master wants to write to us */
592 if (ssr_filtered & SDR) {
595 value = rcar_i2c_read(priv, ICRXTX);
596 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
597 /* Send NACK in case of error */
598 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
599 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
602 /* master wants to read from us */
603 if (ssr_filtered & SDE) {
604 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
605 rcar_i2c_write(priv, ICRXTX, value);
606 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
612 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
614 struct rcar_i2c_priv *priv = ptr;
617 /* Clear START or STOP as soon as we can */
618 val = rcar_i2c_read(priv, ICMCR);
619 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
621 msr = rcar_i2c_read(priv, ICMSR);
623 /* Only handle interrupts that are currently enabled */
624 msr &= rcar_i2c_read(priv, ICMIER);
626 if (rcar_i2c_slave_irq(priv))
632 /* Arbitration lost */
634 priv->flags |= ID_DONE | ID_ARBLOST;
640 /* HW automatically sends STOP after received NACK */
641 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
642 priv->flags |= ID_NACK;
648 priv->msgs_left--; /* The last message also made it */
649 priv->flags |= ID_DONE;
653 if (rcar_i2c_is_recv(priv))
654 rcar_i2c_irq_recv(priv, msr);
656 rcar_i2c_irq_send(priv, msr);
659 if (priv->flags & ID_DONE) {
660 rcar_i2c_write(priv, ICMIER, 0);
661 rcar_i2c_write(priv, ICMSR, 0);
662 wake_up(&priv->wait);
668 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
669 enum dma_transfer_direction dir,
670 dma_addr_t port_addr)
672 struct dma_chan *chan;
673 struct dma_slave_config cfg;
674 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
677 chan = dma_request_chan(dev, chan_name);
679 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
680 chan_name, PTR_ERR(chan));
684 memset(&cfg, 0, sizeof(cfg));
686 if (dir == DMA_MEM_TO_DEV) {
687 cfg.dst_addr = port_addr;
688 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
690 cfg.src_addr = port_addr;
691 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
694 ret = dmaengine_slave_config(chan, &cfg);
696 dev_dbg(dev, "slave_config failed for %s (%d)\n",
698 dma_release_channel(chan);
702 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
706 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
709 struct device *dev = rcar_i2c_priv_to_dev(priv);
711 struct dma_chan *chan;
712 enum dma_transfer_direction dir;
714 read = msg->flags & I2C_M_RD;
716 chan = read ? priv->dma_rx : priv->dma_tx;
717 if (PTR_ERR(chan) != -EPROBE_DEFER)
720 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
721 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
729 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
731 if (!IS_ERR(priv->dma_tx)) {
732 dma_release_channel(priv->dma_tx);
733 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
736 if (!IS_ERR(priv->dma_rx)) {
737 dma_release_channel(priv->dma_rx);
738 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
742 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
743 struct i2c_msg *msgs,
746 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
747 struct device *dev = rcar_i2c_priv_to_dev(priv);
751 pm_runtime_get_sync(dev);
755 ret = rcar_i2c_bus_barrier(priv);
759 for (i = 0; i < num; i++) {
760 /* This HW can't send STOP after address phase */
761 if (msgs[i].len == 0) {
765 rcar_i2c_request_dma(priv, msgs + i);
768 /* init first message */
770 priv->msgs_left = num;
771 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
772 rcar_i2c_prepare_msg(priv);
774 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
775 num * adap->timeout);
777 rcar_i2c_cleanup_dma(priv);
780 } else if (priv->flags & ID_NACK) {
782 } else if (priv->flags & ID_ARBLOST) {
785 ret = num - priv->msgs_left; /* The number of transfer */
790 if (ret < 0 && ret != -ENXIO)
791 dev_err(dev, "error %d : %x\n", ret, priv->flags);
796 static int rcar_reg_slave(struct i2c_client *slave)
798 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
803 if (slave->flags & I2C_CLIENT_TEN)
804 return -EAFNOSUPPORT;
806 /* Keep device active for slave address detection logic */
807 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
810 rcar_i2c_write(priv, ICSAR, slave->addr);
811 rcar_i2c_write(priv, ICSSR, 0);
812 rcar_i2c_write(priv, ICSIER, SAR | SSR);
813 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
818 static int rcar_unreg_slave(struct i2c_client *slave)
820 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
822 WARN_ON(!priv->slave);
824 rcar_i2c_write(priv, ICSIER, 0);
825 rcar_i2c_write(priv, ICSCR, 0);
829 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
834 static u32 rcar_i2c_func(struct i2c_adapter *adap)
838 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
839 * I2C_M_NOSTART (automatically sends address after START)
840 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
842 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
843 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
846 static const struct i2c_algorithm rcar_i2c_algo = {
847 .master_xfer = rcar_i2c_master_xfer,
848 .functionality = rcar_i2c_func,
849 .reg_slave = rcar_reg_slave,
850 .unreg_slave = rcar_unreg_slave,
853 static const struct of_device_id rcar_i2c_dt_ids[] = {
854 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
855 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
856 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
857 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
858 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
859 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
860 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
861 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
862 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
863 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */
864 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
865 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
866 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
869 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
871 static int rcar_i2c_probe(struct platform_device *pdev)
873 struct rcar_i2c_priv *priv;
874 struct i2c_adapter *adap;
875 struct device *dev = &pdev->dev;
876 struct i2c_timings i2c_t;
879 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
883 priv->clk = devm_clk_get(dev, NULL);
884 if (IS_ERR(priv->clk)) {
885 dev_err(dev, "cannot get clock\n");
886 return PTR_ERR(priv->clk);
889 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
891 priv->io = devm_ioremap_resource(dev, priv->res);
892 if (IS_ERR(priv->io))
893 return PTR_ERR(priv->io);
895 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
896 init_waitqueue_head(&priv->wait);
900 adap->algo = &rcar_i2c_algo;
901 adap->class = I2C_CLASS_DEPRECATED;
903 adap->dev.parent = dev;
904 adap->dev.of_node = dev->of_node;
905 adap->bus_recovery_info = &rcar_i2c_bri;
906 i2c_set_adapdata(adap, priv);
907 strlcpy(adap->name, pdev->name, sizeof(adap->name));
909 i2c_parse_fw_timings(dev, &i2c_t, false);
912 sg_init_table(&priv->sg, 1);
913 priv->dma_direction = DMA_NONE;
914 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
916 /* Activate device for clock calculation */
917 pm_runtime_enable(dev);
918 pm_runtime_get_sync(dev);
919 ret = rcar_i2c_clock_calculate(priv, &i2c_t);
923 /* Stay always active when multi-master to keep arbitration working */
924 if (of_property_read_bool(dev->of_node, "multi-master"))
925 priv->flags |= ID_P_PM_BLOCKED;
930 irq = platform_get_irq(pdev, 0);
931 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv);
933 dev_err(dev, "cannot get irq %d\n", irq);
937 platform_set_drvdata(pdev, priv);
939 ret = i2c_add_numbered_adapter(adap);
943 dev_info(dev, "probed\n");
950 pm_runtime_disable(dev);
954 static int rcar_i2c_remove(struct platform_device *pdev)
956 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
957 struct device *dev = &pdev->dev;
959 i2c_del_adapter(&priv->adap);
960 rcar_i2c_release_dma(priv);
961 if (priv->flags & ID_P_PM_BLOCKED)
963 pm_runtime_disable(dev);
968 static struct platform_driver rcar_i2c_driver = {
971 .of_match_table = rcar_i2c_dt_ids,
973 .probe = rcar_i2c_probe,
974 .remove = rcar_i2c_remove,
977 module_platform_driver(rcar_i2c_driver);
979 MODULE_LICENSE("GPL v2");
980 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
981 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");