2 * Driver for the Renesas R-Car I2C unit
4 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
5 * Copyright (C) 2011-2015 Renesas Electronics Corporation
7 * Copyright (C) 2012-14 Renesas Solutions Corp.
8 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
11 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/of_device.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
38 /* register offsets */
39 #define ICSCR 0x00 /* slave ctrl */
40 #define ICMCR 0x04 /* master ctrl */
41 #define ICSSR 0x08 /* slave status */
42 #define ICMSR 0x0C /* master status */
43 #define ICSIER 0x10 /* slave irq enable */
44 #define ICMIER 0x14 /* master irq enable */
45 #define ICCCR 0x18 /* clock dividers */
46 #define ICSAR 0x1C /* slave address */
47 #define ICMAR 0x20 /* master address */
48 #define ICRXTX 0x24 /* data port */
49 #define ICDMAER 0x3c /* DMA enable */
50 #define ICFBSCR 0x38 /* first bit setup cycle */
53 #define SDBS (1 << 3) /* slave data buffer select */
54 #define SIE (1 << 2) /* slave interface enable */
55 #define GCAE (1 << 1) /* general call address enable */
56 #define FNA (1 << 0) /* forced non acknowledgment */
59 #define MDBS (1 << 7) /* non-fifo mode switch */
60 #define FSCL (1 << 6) /* override SCL pin */
61 #define FSDA (1 << 5) /* override SDA pin */
62 #define OBPC (1 << 4) /* override pins */
63 #define MIE (1 << 3) /* master if enable */
65 #define FSB (1 << 1) /* force stop bit */
66 #define ESG (1 << 0) /* enable start bit gen */
68 /* ICSSR (also for ICSIER) */
69 #define GCAR (1 << 6) /* general call received */
70 #define STM (1 << 5) /* slave transmit mode */
71 #define SSR (1 << 4) /* stop received */
72 #define SDE (1 << 3) /* slave data empty */
73 #define SDT (1 << 2) /* slave data transmitted */
74 #define SDR (1 << 1) /* slave data received */
75 #define SAR (1 << 0) /* slave addr received */
77 /* ICMSR (also for ICMIE) */
78 #define MNR (1 << 6) /* nack received */
79 #define MAL (1 << 5) /* arbitration lost */
80 #define MST (1 << 4) /* sent a stop */
84 #define MAT (1 << 0) /* slave addr xfer done */
87 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */
88 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
89 #define RMDMAE (1 << 1) /* DMA Master Received Enable */
90 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
93 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
94 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
97 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
98 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
99 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
100 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
102 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
103 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
104 #define RCAR_IRQ_STOP (MST)
106 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F)
107 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F)
109 #define ID_LAST_MSG (1 << 0)
110 #define ID_FIRST_MSG (1 << 1)
111 #define ID_DONE (1 << 2)
112 #define ID_ARBLOST (1 << 3)
113 #define ID_NACK (1 << 4)
114 /* persistent flags */
115 #define ID_P_NO_RXDMA (1 << 30) /* HW forbids RXDMA sometimes */
116 #define ID_P_PM_BLOCKED (1 << 31)
117 #define ID_P_MASK (ID_P_PM_BLOCKED | ID_P_NO_RXDMA)
125 struct rcar_i2c_priv {
127 struct i2c_adapter adap;
132 wait_queue_head_t wait;
137 u8 recovery_icmcr; /* protected by adapter lock */
138 enum rcar_i2c_type devtype;
139 struct i2c_client *slave;
141 struct resource *res;
142 struct dma_chan *dma_tx;
143 struct dma_chan *dma_rx;
144 struct scatterlist sg;
145 enum dma_data_direction dma_direction;
147 struct reset_control *rstc;
150 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
151 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
153 #define LOOP_TIMEOUT 1024
156 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
158 writel(val, priv->io + reg);
161 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
163 return readl(priv->io + reg);
166 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
168 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
170 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
174 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
176 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
179 priv->recovery_icmcr |= FSCL;
181 priv->recovery_icmcr &= ~FSCL;
183 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
186 /* No get_sda, because the HW only reports its bus free logic, not SDA itself */
188 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
190 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
193 priv->recovery_icmcr |= FSDA;
195 priv->recovery_icmcr &= ~FSDA;
197 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
200 static struct i2c_bus_recovery_info rcar_i2c_bri = {
201 .get_scl = rcar_i2c_get_scl,
202 .set_scl = rcar_i2c_set_scl,
203 .set_sda = rcar_i2c_set_sda,
204 .recover_bus = i2c_generic_scl_recovery,
206 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
208 /* reset master mode */
209 rcar_i2c_write(priv, ICMIER, 0);
210 rcar_i2c_write(priv, ICMCR, MDBS);
211 rcar_i2c_write(priv, ICMSR, 0);
213 rcar_i2c_write(priv, ICCCR, priv->icccr);
216 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
220 for (i = 0; i < LOOP_TIMEOUT; i++) {
221 /* make sure that bus is not busy */
222 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
227 /* Waiting did not help, try to recover */
228 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
229 ret = i2c_recover_bus(&priv->adap);
231 /* No failure when recovering, so check bus busy bit again */
233 ret = (rcar_i2c_read(priv, ICMCR) & FSDA) ? -EBUSY : 0;
238 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
240 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
242 struct device *dev = rcar_i2c_priv_to_dev(priv);
244 /* Fall back to previously used values if not supplied */
245 t->bus_freq_hz = t->bus_freq_hz ?: 100000;
246 t->scl_fall_ns = t->scl_fall_ns ?: 35;
247 t->scl_rise_ns = t->scl_rise_ns ?: 200;
248 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
250 switch (priv->devtype) {
259 dev_err(dev, "device type error\n");
264 * calculate SCL clock
268 * ick = clkp / (1 + CDF)
269 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
271 * ick : I2C internal clock < 20 MHz
272 * ticf : I2C SCL falling time
273 * tr : I2C SCL rising time
274 * intd : LSI internal delay
275 * clkp : peripheral_clk
276 * F[] : integer up-valuation
278 rate = clk_get_rate(priv->clk);
279 cdf = rate / 20000000;
280 if (cdf >= 1U << cdf_width) {
281 dev_err(dev, "Input clock %lu too high\n", rate);
284 ick = rate / (cdf + 1);
287 * it is impossible to calculate large scale
288 * number on u32. separate it
290 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
291 * = F[sum * ick / 1000000000]
292 * = F[(ick / 1000000) * sum / 1000]
294 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
295 round = (ick + 500000) / 1000000 * sum;
296 round = (round + 500) / 1000;
299 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
301 * Calculation result (= SCL) should be less than
302 * bus_speed for hardware safety
304 * We could use something along the lines of
305 * div = ick / (bus_speed + 1) + 1;
306 * scgd = (div - 20 - round + 7) / 8;
307 * scl = ick / (20 + (scgd * 8) + round);
308 * (not fully verified) but that would get pretty involved
310 for (scgd = 0; scgd < 0x40; scgd++) {
311 scl = ick / (20 + (scgd * 8) + round);
312 if (scl <= t->bus_freq_hz)
315 dev_err(dev, "it is impossible to calculate best SCL\n");
319 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
320 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
322 /* keep icccr value */
323 priv->icccr = scgd << cdf_width | cdf;
328 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
330 int read = !!rcar_i2c_is_recv(priv);
333 if (priv->msgs_left == 1)
334 priv->flags |= ID_LAST_MSG;
336 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
338 * We don't have a test case but the HW engineers say that the write order
339 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
340 * it didn't cause a drawback for me, let's rather be safe than sorry.
342 if (priv->flags & ID_FIRST_MSG) {
343 rcar_i2c_write(priv, ICMSR, 0);
344 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
346 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
347 rcar_i2c_write(priv, ICMSR, 0);
349 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
352 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
356 priv->flags &= ID_P_MASK;
357 rcar_i2c_prepare_msg(priv);
361 * interrupt functions
363 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
365 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
366 ? priv->dma_rx : priv->dma_tx;
368 /* Disable DMA Master Received/Transmitted */
369 rcar_i2c_write(priv, ICDMAER, 0);
371 /* Reset default delay */
372 rcar_i2c_write(priv, ICFBSCR, TCYC06);
374 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
375 sg_dma_len(&priv->sg), priv->dma_direction);
377 /* Gen3 can only do one RXDMA per transfer and we just completed it */
378 if (priv->devtype == I2C_RCAR_GEN3 &&
379 priv->dma_direction == DMA_FROM_DEVICE)
380 priv->flags |= ID_P_NO_RXDMA;
382 priv->dma_direction = DMA_NONE;
385 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
387 if (priv->dma_direction == DMA_NONE)
389 else if (priv->dma_direction == DMA_FROM_DEVICE)
390 dmaengine_terminate_all(priv->dma_rx);
391 else if (priv->dma_direction == DMA_TO_DEVICE)
392 dmaengine_terminate_all(priv->dma_tx);
394 rcar_i2c_dma_unmap(priv);
397 static void rcar_i2c_dma_callback(void *data)
399 struct rcar_i2c_priv *priv = data;
401 priv->pos += sg_dma_len(&priv->sg);
403 rcar_i2c_dma_unmap(priv);
406 static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
408 struct device *dev = rcar_i2c_priv_to_dev(priv);
409 struct i2c_msg *msg = priv->msg;
410 bool read = msg->flags & I2C_M_RD;
411 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
412 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
413 struct dma_async_tx_descriptor *txdesc;
419 /* Do various checks to see if DMA is feasible at all */
420 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) ||
421 (read && priv->flags & ID_P_NO_RXDMA))
426 * The last two bytes needs to be fetched using PIO in
427 * order for the STOP phase to work.
429 buf = priv->msg->buf;
430 len = priv->msg->len - 2;
433 * First byte in message was sent using PIO.
435 buf = priv->msg->buf + 1;
436 len = priv->msg->len - 1;
439 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
440 if (dma_mapping_error(chan->device->dev, dma_addr)) {
441 dev_dbg(dev, "dma map failed, using PIO\n");
445 sg_dma_len(&priv->sg) = len;
446 sg_dma_address(&priv->sg) = dma_addr;
448 priv->dma_direction = dir;
450 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
451 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
452 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
454 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
455 rcar_i2c_cleanup_dma(priv);
459 txdesc->callback = rcar_i2c_dma_callback;
460 txdesc->callback_param = priv;
462 cookie = dmaengine_submit(txdesc);
463 if (dma_submit_error(cookie)) {
464 dev_dbg(dev, "submitting dma failed, using PIO\n");
465 rcar_i2c_cleanup_dma(priv);
469 /* Set delay for DMA operations */
470 rcar_i2c_write(priv, ICFBSCR, TCYC17);
472 /* Enable DMA Master Received/Transmitted */
474 rcar_i2c_write(priv, ICDMAER, RMDMAE);
476 rcar_i2c_write(priv, ICDMAER, TMDMAE);
478 dma_async_issue_pending(chan);
481 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
483 struct i2c_msg *msg = priv->msg;
485 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
489 if (priv->pos < msg->len) {
491 * Prepare next data to ICRXTX register.
492 * This data will go to _SHIFT_ register.
495 * [ICRXTX] -> [SHIFT] -> [I2C bus]
497 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
501 * Try to use DMA to transmit the rest of the data if
502 * address transfer phase just finished.
508 * The last data was pushed to ICRXTX on _PREV_ empty irq.
509 * It is on _SHIFT_ register, and will sent to I2C bus.
512 * [ICRXTX] -> [SHIFT] -> [I2C bus]
515 if (priv->flags & ID_LAST_MSG) {
517 * If current msg is the _LAST_ msg,
518 * prepare stop condition here.
519 * ID_DONE will be set on STOP irq.
521 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
523 rcar_i2c_next_msg(priv);
528 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
531 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
533 struct i2c_msg *msg = priv->msg;
535 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
541 * Address transfer phase finished, but no data at this point.
542 * Try to use DMA to receive data.
545 } else if (priv->pos < msg->len) {
546 /* get received data */
547 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
552 * If next received data is the _LAST_, go to STOP phase. Might be
553 * overwritten by REP START when setting up a new msg. Not elegant
554 * but the only stable sequence for REP START I have found so far.
555 * If you want to change this code, make sure sending one transfer with
556 * four messages (WR-RD-WR-RD) works!
558 if (priv->pos + 1 >= msg->len)
559 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
561 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
562 rcar_i2c_next_msg(priv);
564 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
567 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
569 u32 ssr_raw, ssr_filtered;
572 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
573 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
578 /* address detected */
579 if (ssr_filtered & SAR) {
580 /* read or write request */
582 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
583 rcar_i2c_write(priv, ICRXTX, value);
584 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
586 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
587 rcar_i2c_read(priv, ICRXTX); /* dummy read */
588 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
591 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
594 /* master sent stop */
595 if (ssr_filtered & SSR) {
596 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
597 rcar_i2c_write(priv, ICSIER, SAR | SSR);
598 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
601 /* master wants to write to us */
602 if (ssr_filtered & SDR) {
605 value = rcar_i2c_read(priv, ICRXTX);
606 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
607 /* Send NACK in case of error */
608 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
609 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
612 /* master wants to read from us */
613 if (ssr_filtered & SDE) {
614 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
615 rcar_i2c_write(priv, ICRXTX, value);
616 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
622 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
624 struct rcar_i2c_priv *priv = ptr;
627 /* Clear START or STOP as soon as we can */
628 val = rcar_i2c_read(priv, ICMCR);
629 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
631 msr = rcar_i2c_read(priv, ICMSR);
633 /* Only handle interrupts that are currently enabled */
634 msr &= rcar_i2c_read(priv, ICMIER);
636 if (rcar_i2c_slave_irq(priv))
642 /* Arbitration lost */
644 priv->flags |= ID_DONE | ID_ARBLOST;
650 /* HW automatically sends STOP after received NACK */
651 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
652 priv->flags |= ID_NACK;
658 priv->msgs_left--; /* The last message also made it */
659 priv->flags |= ID_DONE;
663 if (rcar_i2c_is_recv(priv))
664 rcar_i2c_irq_recv(priv, msr);
666 rcar_i2c_irq_send(priv, msr);
669 if (priv->flags & ID_DONE) {
670 rcar_i2c_write(priv, ICMIER, 0);
671 rcar_i2c_write(priv, ICMSR, 0);
672 wake_up(&priv->wait);
678 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
679 enum dma_transfer_direction dir,
680 dma_addr_t port_addr)
682 struct dma_chan *chan;
683 struct dma_slave_config cfg;
684 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
687 chan = dma_request_chan(dev, chan_name);
689 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
690 chan_name, PTR_ERR(chan));
694 memset(&cfg, 0, sizeof(cfg));
696 if (dir == DMA_MEM_TO_DEV) {
697 cfg.dst_addr = port_addr;
698 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
700 cfg.src_addr = port_addr;
701 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
704 ret = dmaengine_slave_config(chan, &cfg);
706 dev_dbg(dev, "slave_config failed for %s (%d)\n",
708 dma_release_channel(chan);
712 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
716 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
719 struct device *dev = rcar_i2c_priv_to_dev(priv);
721 struct dma_chan *chan;
722 enum dma_transfer_direction dir;
724 read = msg->flags & I2C_M_RD;
726 chan = read ? priv->dma_rx : priv->dma_tx;
727 if (PTR_ERR(chan) != -EPROBE_DEFER)
730 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
731 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
739 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
741 if (!IS_ERR(priv->dma_tx)) {
742 dma_release_channel(priv->dma_tx);
743 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
746 if (!IS_ERR(priv->dma_rx)) {
747 dma_release_channel(priv->dma_rx);
748 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
752 /* I2C is a special case, we need to poll the status of a reset */
753 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
757 ret = reset_control_reset(priv->rstc);
761 for (i = 0; i < LOOP_TIMEOUT; i++) {
762 ret = reset_control_status(priv->rstc);
771 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
772 struct i2c_msg *msgs,
775 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
776 struct device *dev = rcar_i2c_priv_to_dev(priv);
780 pm_runtime_get_sync(dev);
782 /* Gen3 needs a reset before allowing RXDMA once */
783 if (priv->devtype == I2C_RCAR_GEN3) {
784 priv->flags |= ID_P_NO_RXDMA;
785 if (!IS_ERR(priv->rstc)) {
786 ret = rcar_i2c_do_reset(priv);
788 priv->flags &= ~ID_P_NO_RXDMA;
794 ret = rcar_i2c_bus_barrier(priv);
798 for (i = 0; i < num; i++) {
799 /* This HW can't send STOP after address phase */
800 if (msgs[i].len == 0) {
804 rcar_i2c_request_dma(priv, msgs + i);
807 /* init first message */
809 priv->msgs_left = num;
810 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
811 rcar_i2c_prepare_msg(priv);
813 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
814 num * adap->timeout);
816 rcar_i2c_cleanup_dma(priv);
819 } else if (priv->flags & ID_NACK) {
821 } else if (priv->flags & ID_ARBLOST) {
824 ret = num - priv->msgs_left; /* The number of transfer */
829 if (ret < 0 && ret != -ENXIO)
830 dev_err(dev, "error %d : %x\n", ret, priv->flags);
835 static int rcar_reg_slave(struct i2c_client *slave)
837 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
842 if (slave->flags & I2C_CLIENT_TEN)
843 return -EAFNOSUPPORT;
845 /* Keep device active for slave address detection logic */
846 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
849 rcar_i2c_write(priv, ICSAR, slave->addr);
850 rcar_i2c_write(priv, ICSSR, 0);
851 rcar_i2c_write(priv, ICSIER, SAR | SSR);
852 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
857 static int rcar_unreg_slave(struct i2c_client *slave)
859 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
861 WARN_ON(!priv->slave);
863 rcar_i2c_write(priv, ICSIER, 0);
864 rcar_i2c_write(priv, ICSCR, 0);
868 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
873 static u32 rcar_i2c_func(struct i2c_adapter *adap)
877 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
878 * I2C_M_NOSTART (automatically sends address after START)
879 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
881 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
882 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
885 static const struct i2c_algorithm rcar_i2c_algo = {
886 .master_xfer = rcar_i2c_master_xfer,
887 .functionality = rcar_i2c_func,
888 .reg_slave = rcar_reg_slave,
889 .unreg_slave = rcar_unreg_slave,
892 static const struct of_device_id rcar_i2c_dt_ids[] = {
893 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
894 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
895 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
896 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
897 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
898 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
899 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
900 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
901 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
902 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */
903 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
904 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
905 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
908 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
910 static int rcar_i2c_probe(struct platform_device *pdev)
912 struct rcar_i2c_priv *priv;
913 struct i2c_adapter *adap;
914 struct device *dev = &pdev->dev;
915 struct i2c_timings i2c_t;
918 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
922 priv->clk = devm_clk_get(dev, NULL);
923 if (IS_ERR(priv->clk)) {
924 dev_err(dev, "cannot get clock\n");
925 return PTR_ERR(priv->clk);
928 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
930 priv->io = devm_ioremap_resource(dev, priv->res);
931 if (IS_ERR(priv->io))
932 return PTR_ERR(priv->io);
934 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
935 init_waitqueue_head(&priv->wait);
939 adap->algo = &rcar_i2c_algo;
940 adap->class = I2C_CLASS_DEPRECATED;
942 adap->dev.parent = dev;
943 adap->dev.of_node = dev->of_node;
944 adap->bus_recovery_info = &rcar_i2c_bri;
945 i2c_set_adapdata(adap, priv);
946 strlcpy(adap->name, pdev->name, sizeof(adap->name));
948 i2c_parse_fw_timings(dev, &i2c_t, false);
951 sg_init_table(&priv->sg, 1);
952 priv->dma_direction = DMA_NONE;
953 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
955 /* Activate device for clock calculation */
956 pm_runtime_enable(dev);
957 pm_runtime_get_sync(dev);
958 ret = rcar_i2c_clock_calculate(priv, &i2c_t);
962 if (priv->devtype == I2C_RCAR_GEN3) {
963 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
964 if (!IS_ERR(priv->rstc)) {
965 ret = reset_control_status(priv->rstc);
967 priv->rstc = ERR_PTR(-ENOTSUPP);
971 /* Stay always active when multi-master to keep arbitration working */
972 if (of_property_read_bool(dev->of_node, "multi-master"))
973 priv->flags |= ID_P_PM_BLOCKED;
978 irq = platform_get_irq(pdev, 0);
979 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv);
981 dev_err(dev, "cannot get irq %d\n", irq);
985 platform_set_drvdata(pdev, priv);
987 ret = i2c_add_numbered_adapter(adap);
991 dev_info(dev, "probed\n");
998 pm_runtime_disable(dev);
1002 static int rcar_i2c_remove(struct platform_device *pdev)
1004 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1005 struct device *dev = &pdev->dev;
1007 i2c_del_adapter(&priv->adap);
1008 rcar_i2c_release_dma(priv);
1009 if (priv->flags & ID_P_PM_BLOCKED)
1010 pm_runtime_put(dev);
1011 pm_runtime_disable(dev);
1016 static struct platform_driver rcar_i2c_driver = {
1019 .of_match_table = rcar_i2c_dt_ids,
1021 .probe = rcar_i2c_probe,
1022 .remove = rcar_i2c_remove,
1025 module_platform_driver(rcar_i2c_driver);
1027 MODULE_LICENSE("GPL v2");
1028 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1029 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");